version 1.155.2.1, 2009/05/13 17:20:24 |
version 1.155.2.2, 2009/07/23 23:31:57 |
Line 499 static const struct bge_product { |
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Line 499 static const struct bge_product { |
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(BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || \ |
(BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || \ |
(BGE_IS_5750_OR_BEYOND(sc))) |
(BGE_IS_5750_OR_BEYOND(sc))) |
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#define BGE_IS_JUMBO_CAPABLE(sc) \ |
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(BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || \ |
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BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || \ |
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BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || \ |
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BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) |
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static const struct bge_revision { |
static const struct bge_revision { |
uint32_t br_chipid; |
uint32_t br_chipid; |
const char *br_name; |
const char *br_name; |
Line 576 static const struct bge_revision bge_maj |
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Line 583 static const struct bge_revision bge_maj |
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{ BGE_ASICREV_BCM5755, "unknown BCM5755" }, |
{ BGE_ASICREV_BCM5755, "unknown BCM5755" }, |
{ BGE_ASICREV_BCM5780, "unknown BCM5780" }, |
{ BGE_ASICREV_BCM5780, "unknown BCM5780" }, |
/* 5754 and 5787 share the same ASIC ID */ |
/* 5754 and 5787 share the same ASIC ID */ |
{ BGE_ASICREV_BCM5787, "unknown BCM5787/5787" }, |
{ BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, |
{ BGE_ASICREV_BCM5906, "unknown BCM5906" }, |
{ BGE_ASICREV_BCM5906, "unknown BCM5906" }, |
{ 0, NULL } |
{ 0, NULL } |
}; |
}; |
Line 1559 bge_chipinit(struct bge_softc *sc) |
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Line 1566 bge_chipinit(struct bge_softc *sc) |
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BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); |
BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); |
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/* Set up the PCI DMA control register. */ |
/* Set up the PCI DMA control register. */ |
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dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; |
if (sc->bge_flags & BGE_PCIE) { |
if (sc->bge_flags & BGE_PCIE) { |
u_int32_t device_ctl; |
/* Read watermark not used, 128 bytes for write. */ |
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/* From FreeBSD */ |
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DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", |
DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", |
device_xname(sc->bge_dev))); |
device_xname(sc->bge_dev))); |
dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | |
dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); |
(0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | |
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(0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); |
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/* jonathan: alternative from Linux driver */ |
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#define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000 |
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#define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000 |
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dma_rw_ctl = 0x76000000; /* XXX XXX XXX */; |
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device_ctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, |
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BGE_PCI_CONF_DEV_CTRL); |
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aprint_debug_dev(sc->bge_dev, "pcie mode=0x%x\n", device_ctl); |
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if ((device_ctl & 0x00e0) && 0) { |
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/* |
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* XXX jonathan@NetBSD.org: |
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* This clause is exactly what the Broadcom-supplied |
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* Linux does; but given overall register programming |
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* by if_bge(4), this larger DMA-write watermark |
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* value causes bcm5721 chips to totally wedge. |
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*/ |
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dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256; |
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} else { |
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dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128; |
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} |
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} else if (sc->bge_flags & BGE_PCIX){ |
} else if (sc->bge_flags & BGE_PCIX){ |
DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", |
DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", |
device_xname(sc->bge_dev))); |
device_xname(sc->bge_dev))); |
/* PCI-X bus */ |
/* PCI-X bus */ |
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | |
dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | |
(0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | |
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(0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | |
(0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | |
(0x0F); |
(0x0F); |
/* |
/* |
Line 1629 bge_chipinit(struct bge_softc *sc) |
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Line 1610 bge_chipinit(struct bge_softc *sc) |
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/* Conventional PCI bus */ |
/* Conventional PCI bus */ |
DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", |
DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", |
device_xname(sc->bge_dev))); |
device_xname(sc->bge_dev))); |
dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | |
dma_rw_ctl = (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | |
(0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | |
(0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); |
(0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); |
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if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && |
if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) |
dma_rw_ctl |= 0x0F; |
dma_rw_ctl |= 0x0F; |
Line 1829 bge_blockinit(struct bge_softc *sc) |
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Line 1809 bge_blockinit(struct bge_softc *sc) |
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* using this ring (i.e. once we set the MTU |
* using this ring (i.e. once we set the MTU |
* high enough to require it). |
* high enough to require it). |
*/ |
*/ |
if (!BGE_IS_5705_OR_BEYOND(sc)) { |
if (BGE_IS_JUMBO_CAPABLE(sc)) { |
rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; |
rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; |
bge_set_hostaddr(&rcb->bge_hostaddr, |
bge_set_hostaddr(&rcb->bge_hostaddr, |
BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); |
BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); |
Line 2495 bge_attach(device_t parent, device_t sel |
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Line 2475 bge_attach(device_t parent, device_t sel |
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memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); |
memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); |
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/* Try to allocate memory for jumbo buffers. */ |
/* Try to allocate memory for jumbo buffers. */ |
if (!(BGE_IS_5705_OR_BEYOND(sc))) { |
if (BGE_IS_JUMBO_CAPABLE(sc)) { |
if (bge_alloc_jumbo_mem(sc)) { |
if (bge_alloc_jumbo_mem(sc)) { |
aprint_error_dev(sc->bge_dev, |
aprint_error_dev(sc->bge_dev, |
"jumbo buffer allocation failed\n"); |
"jumbo buffer allocation failed\n"); |