Annotation of src/sys/dev/pci/if_aq.c, Revision 1.42
1.42 ! ryo 1: /* $NetBSD: if_aq.c,v 1.41 2023/01/14 13:17:20 ryo Exp $ */
1.1 ryo 2:
3: /**
4: * aQuantia Corporation Network Driver
5: * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: *
11: * (1) Redistributions of source code must retain the above
12: * copyright notice, this list of conditions and the following
13: * disclaimer.
14: *
15: * (2) Redistributions in binary form must reproduce the above
16: * copyright notice, this list of conditions and the following
17: * disclaimer in the documentation and/or other materials provided
18: * with the distribution.
19: *
20: * (3) The name of the author may not be used to endorse or promote
21: * products derived from this software without specific prior
22: * written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
25: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
28: * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
30: * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33: * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34: * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35: *
36: */
37:
38: /*-
39: * Copyright (c) 2020 Ryo Shimizu <ryo@nerv.org>
40: * All rights reserved.
41: *
42: * Redistribution and use in source and binary forms, with or without
43: * modification, are permitted provided that the following conditions
44: * are met:
45: * 1. Redistributions of source code must retain the above copyright
46: * notice, this list of conditions and the following disclaimer.
47: * 2. Redistributions in binary form must reproduce the above copyright
48: * notice, this list of conditions and the following disclaimer in the
49: * documentation and/or other materials provided with the distribution.
50: *
51: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
52: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
53: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
54: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
55: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
56: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
57: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
58: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
59: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
60: * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
61: * POSSIBILITY OF SUCH DAMAGE.
62: */
63:
64: #include <sys/cdefs.h>
1.42 ! ryo 65: __KERNEL_RCSID(0, "$NetBSD: if_aq.c,v 1.41 2023/01/14 13:17:20 ryo Exp $");
1.1 ryo 66:
67: #ifdef _KERNEL_OPT
68: #include "opt_if_aq.h"
1.4 ryo 69: #include "sysmon_envsys.h"
1.1 ryo 70: #endif
71:
72: #include <sys/param.h>
73: #include <sys/types.h>
74: #include <sys/bitops.h>
75: #include <sys/cprng.h>
76: #include <sys/cpu.h>
77: #include <sys/interrupt.h>
78: #include <sys/module.h>
79: #include <sys/pcq.h>
80:
81: #include <net/bpf.h>
82: #include <net/if.h>
83: #include <net/if_dl.h>
84: #include <net/if_media.h>
85: #include <net/if_ether.h>
86: #include <net/rss_config.h>
87:
88: #include <dev/pci/pcivar.h>
89: #include <dev/pci/pcireg.h>
90: #include <dev/pci/pcidevs.h>
1.4 ryo 91: #include <dev/sysmon/sysmonvar.h>
1.1 ryo 92:
93: /* driver configuration */
94: #define CONFIG_INTR_MODERATION_ENABLE true /* delayed interrupt */
1.39 andvar 95: #undef CONFIG_LRO_SUPPORT /* no LRO not supported */
1.1 ryo 96: #undef CONFIG_NO_TXRX_INDEPENDENT /* share TX/RX interrupts */
97:
98: #define AQ_NINTR_MAX (AQ_RSSQUEUE_MAX + AQ_RSSQUEUE_MAX + 1)
99: /* TX + RX + LINK. must be <= 32 */
100: #define AQ_LINKSTAT_IRQ 31 /* for legacy mode */
101:
102: #define AQ_TXD_NUM 2048 /* per ring. 8*n && 32~8184 */
103: #define AQ_RXD_NUM 2048 /* per ring. 8*n && 32~8184 */
104: /* minimum required to send a packet (vlan needs additional TX descriptor) */
105: #define AQ_TXD_MIN (1 + 1)
106:
107:
108: /* hardware specification */
109: #define AQ_RINGS_NUM 32
110: #define AQ_RSSQUEUE_MAX 8
111: #define AQ_RX_DESCRIPTOR_MIN 32
112: #define AQ_TX_DESCRIPTOR_MIN 32
113: #define AQ_RX_DESCRIPTOR_MAX 8184
114: #define AQ_TX_DESCRIPTOR_MAX 8184
115: #define AQ_TRAFFICCLASS_NUM 8
116: #define AQ_RSS_HASHKEY_SIZE 40
117: #define AQ_RSS_INDIRECTION_TABLE_MAX 64
118:
1.23 ryo 119: #define AQ_JUMBO_MTU_REV_A 9000
120: #define AQ_JUMBO_MTU_REV_B 16338
121:
1.1 ryo 122: /*
123: * TERMINOLOGY
124: * MPI = MAC PHY INTERFACE?
125: * RPO = RX Protocol Offloading
126: * TPO = TX Protocol Offloading
127: * RPF = RX Packet Filter
128: * TPB = TX Packet buffer
129: * RPB = RX Packet buffer
130: */
131:
132: /* registers */
133: #define AQ_FW_SOFTRESET_REG 0x0000
134: #define AQ_FW_SOFTRESET_RESET __BIT(15) /* soft reset bit */
135: #define AQ_FW_SOFTRESET_DIS __BIT(14) /* reset disable */
136:
137: #define AQ_FW_VERSION_REG 0x0018
138: #define AQ_HW_REVISION_REG 0x001c
139: #define AQ_GLB_NVR_INTERFACE1_REG 0x0100
140:
141: #define AQ_FW_MBOX_CMD_REG 0x0200
142: #define AQ_FW_MBOX_CMD_EXECUTE 0x00008000
143: #define AQ_FW_MBOX_CMD_BUSY 0x00000100
144: #define AQ_FW_MBOX_ADDR_REG 0x0208
145: #define AQ_FW_MBOX_VAL_REG 0x020c
146:
147: #define FW2X_LED_MIN_VERSION 0x03010026 /* >= 3.1.38 */
148: #define FW2X_LED_REG 0x031c
149: #define FW2X_LED_DEFAULT 0x00000000
150: #define FW2X_LED_NONE 0x0000003f
151: #define FW2X_LINKLED __BITS(0,1)
152: #define FW2X_LINKLED_ACTIVE 0
153: #define FW2X_LINKLED_ON 1
154: #define FW2X_LINKLED_BLINK 2
155: #define FW2X_LINKLED_OFF 3
156: #define FW2X_STATUSLED __BITS(2,5)
157: #define FW2X_STATUSLED_ORANGE 0
158: #define FW2X_STATUSLED_ORANGE_BLINK 2
159: #define FW2X_STATUSLED_OFF 3
160: #define FW2X_STATUSLED_GREEN 4
161: #define FW2X_STATUSLED_ORANGE_GREEN_BLINK 8
162: #define FW2X_STATUSLED_GREEN_BLINK 10
163:
164: #define FW_MPI_MBOX_ADDR_REG 0x0360
165: #define FW1X_MPI_INIT1_REG 0x0364
166: #define FW1X_MPI_CONTROL_REG 0x0368
167: #define FW1X_MPI_STATE_REG 0x036c
168: #define FW1X_MPI_STATE_MODE __BITS(7,0)
169: #define FW1X_MPI_STATE_SPEED __BITS(32,16)
170: #define FW1X_MPI_STATE_DISABLE_DIRTYWAKE __BITS(25)
171: #define FW1X_MPI_STATE_DOWNSHIFT __BITS(31,28)
172: #define FW1X_MPI_INIT2_REG 0x0370
173: #define FW1X_MPI_EFUSEADDR_REG 0x0374
174:
175: #define FW2X_MPI_EFUSEADDR_REG 0x0364
176: #define FW2X_MPI_CONTROL_REG 0x0368 /* 64bit */
177: #define FW2X_MPI_STATE_REG 0x0370 /* 64bit */
178: #define FW_BOOT_EXIT_CODE_REG 0x0388
179: #define RBL_STATUS_DEAD 0x0000dead
180: #define RBL_STATUS_SUCCESS 0x0000abba
181: #define RBL_STATUS_FAILURE 0x00000bad
182: #define RBL_STATUS_HOST_BOOT 0x0000f1a7
183:
184: #define AQ_FW_GLB_CPU_SEM_REG(i) (0x03a0 + (i) * 4)
185: #define AQ_FW_SEM_RAM_REG AQ_FW_GLB_CPU_SEM_REG(2)
186:
187: #define AQ_FW_GLB_CTL2_REG 0x0404
188: #define AQ_FW_GLB_CTL2_MCP_UP_FORCE_INTERRUPT __BIT(1)
189:
190: #define AQ_GLB_GENERAL_PROVISIONING9_REG 0x0520
191: #define AQ_GLB_NVR_PROVISIONING2_REG 0x0534
192:
193: #define FW_MPI_DAISY_CHAIN_STATUS_REG 0x0704
194:
195: #define AQ_PCI_REG_CONTROL_6_REG 0x1014
196:
197: // msix bitmap */
198: #define AQ_INTR_STATUS_REG 0x2000 /* intr status */
199: #define AQ_INTR_STATUS_CLR_REG 0x2050 /* intr status clear */
200: #define AQ_INTR_MASK_REG 0x2060 /* intr mask set */
201: #define AQ_INTR_MASK_CLR_REG 0x2070 /* intr mask clear */
202: #define AQ_INTR_AUTOMASK_REG 0x2090
203:
204: /* AQ_INTR_IRQ_MAP_TXRX_REG[AQ_RINGS_NUM] 0x2100-0x2140 */
205: #define AQ_INTR_IRQ_MAP_TXRX_REG(i) (0x2100 + ((i) / 2) * 4)
206: #define AQ_INTR_IRQ_MAP_TX_REG(i) AQ_INTR_IRQ_MAP_TXRX_REG(i)
207: #define AQ_INTR_IRQ_MAP_TX_IRQMAP(i) (__BITS(28,24) >> (((i) & 1)*8))
208: #define AQ_INTR_IRQ_MAP_TX_EN(i) (__BIT(31) >> (((i) & 1)*8))
209: #define AQ_INTR_IRQ_MAP_RX_REG(i) AQ_INTR_IRQ_MAP_TXRX_REG(i)
210: #define AQ_INTR_IRQ_MAP_RX_IRQMAP(i) (__BITS(12,8) >> (((i) & 1)*8))
211: #define AQ_INTR_IRQ_MAP_RX_EN(i) (__BIT(15) >> (((i) & 1)*8))
212:
213: /* AQ_GEN_INTR_MAP_REG[AQ_RINGS_NUM] 0x2180-0x2200 */
214: #define AQ_GEN_INTR_MAP_REG(i) (0x2180 + (i) * 4)
1.5 msaitoh 215: #define AQ_B0_ERR_INT 8U
1.1 ryo 216:
217: #define AQ_INTR_CTRL_REG 0x2300
218: #define AQ_INTR_CTRL_IRQMODE __BITS(1,0)
219: #define AQ_INTR_CTRL_IRQMODE_LEGACY 0
220: #define AQ_INTR_CTRL_IRQMODE_MSI 1
221: #define AQ_INTR_CTRL_IRQMODE_MSIX 2
222: #define AQ_INTR_CTRL_MULTIVEC __BIT(2)
223: #define AQ_INTR_CTRL_AUTO_MASK __BIT(5)
224: #define AQ_INTR_CTRL_CLR_ON_READ __BIT(7)
225: #define AQ_INTR_CTRL_RESET_DIS __BIT(29)
226: #define AQ_INTR_CTRL_RESET_IRQ __BIT(31)
227:
228: #define AQ_MBOXIF_POWER_GATING_CONTROL_REG 0x32a8
229:
230: #define FW_MPI_RESETCTRL_REG 0x4000
231: #define FW_MPI_RESETCTRL_RESET_DIS __BIT(29)
232:
233: #define RX_SYSCONTROL_REG 0x5000
234: #define RX_SYSCONTROL_RPB_DMA_LOOPBACK __BIT(6)
235: #define RX_SYSCONTROL_RPF_TPO_LOOPBACK __BIT(8)
236: #define RX_SYSCONTROL_RESET_DIS __BIT(29)
237:
238: #define RX_TCP_RSS_HASH_REG 0x5040
239: #define RX_TCP_RSS_HASH_RPF2 __BITS(19,16)
240: #define RX_TCP_RSS_HASH_TYPE __BITS(15,0)
241:
242: /* for RPF_*_REG.ACTION */
243: #define RPF_ACTION_DISCARD 0
244: #define RPF_ACTION_HOST 1
245: #define RPF_ACTION_MANAGEMENT 2
246: #define RPF_ACTION_HOST_MANAGEMENT 3
247: #define RPF_ACTION_WOL 4
248:
249: #define RPF_L2BC_REG 0x5100
250: #define RPF_L2BC_EN __BIT(0)
251: #define RPF_L2BC_PROMISC __BIT(3)
252: #define RPF_L2BC_ACTION __BITS(12,14)
253: #define RPF_L2BC_THRESHOLD __BITS(31,16)
254:
255: /* RPF_L2UC_*_REG[34] (actual [38]?) */
256: #define RPF_L2UC_LSW_REG(i) (0x5110 + (i) * 8)
257: #define RPF_L2UC_MSW_REG(i) (0x5114 + (i) * 8)
258: #define RPF_L2UC_MSW_MACADDR_HI __BITS(15,0)
259: #define RPF_L2UC_MSW_ACTION __BITS(18,16)
260: #define RPF_L2UC_MSW_EN __BIT(31)
261: #define AQ_HW_MAC_OWN 0 /* index of own address */
262: #define AQ_HW_MAC_NUM 34
263:
1.9 ryo 264: /* RPF_MCAST_FILTER_REG[8] 0x5250-0x5270 */
1.1 ryo 265: #define RPF_MCAST_FILTER_REG(i) (0x5250 + (i) * 4)
266: #define RPF_MCAST_FILTER_EN __BIT(31)
267: #define RPF_MCAST_FILTER_MASK_REG 0x5270
268: #define RPF_MCAST_FILTER_MASK_ALLMULTI __BIT(14)
269:
270: #define RPF_VLAN_MODE_REG 0x5280
271: #define RPF_VLAN_MODE_PROMISC __BIT(1)
272: #define RPF_VLAN_MODE_ACCEPT_UNTAGGED __BIT(2)
273: #define RPF_VLAN_MODE_UNTAGGED_ACTION __BITS(5,3)
274:
275: #define RPF_VLAN_TPID_REG 0x5284
276: #define RPF_VLAN_TPID_OUTER __BITS(31,16)
277: #define RPF_VLAN_TPID_INNER __BITS(15,0)
278:
1.9 ryo 279: /* RPF_VLAN_FILTER_REG[RPF_VLAN_MAX_FILTERS] 0x5290-0x52d0 */
1.1 ryo 280: #define RPF_VLAN_MAX_FILTERS 16
281: #define RPF_VLAN_FILTER_REG(i) (0x5290 + (i) * 4)
282: #define RPF_VLAN_FILTER_EN __BIT(31)
283: #define RPF_VLAN_FILTER_RXQ_EN __BIT(28)
284: #define RPF_VLAN_FILTER_RXQ __BITS(24,20)
285: #define RPF_VLAN_FILTER_ACTION __BITS(18,16)
286: #define RPF_VLAN_FILTER_ID __BITS(11,0)
287:
288: /* RPF_ETHERTYPE_FILTER_REG[AQ_RINGS_NUM] 0x5300-0x5380 */
289: #define RPF_ETHERTYPE_FILTER_REG(i) (0x5300 + (i) * 4)
290: #define RPF_ETHERTYPE_FILTER_EN __BIT(31)
291: #define RPF_ETHERTYPE_FILTER_PRIO_EN __BIT(30)
292: #define RPF_ETHERTYPE_FILTER_RXQF_EN __BIT(29)
293: #define RPF_ETHERTYPE_FILTER_PRIO __BITS(28,26)
294: #define RPF_ETHERTYPE_FILTER_RXQF __BITS(24,20)
295: #define RPF_ETHERTYPE_FILTER_MNG_RXQF __BIT(19)
296: #define RPF_ETHERTYPE_FILTER_ACTION __BITS(18,16)
297: #define RPF_ETHERTYPE_FILTER_VAL __BITS(15,0)
298:
299: /* RPF_L3_FILTER_REG[8] 0x5380-0x53a0 */
300: #define RPF_L3_FILTER_REG(i) (0x5380 + (i) * 4)
301: #define RPF_L3_FILTER_L4_EN __BIT(31)
302: #define RPF_L3_FILTER_IPV6_EN __BIT(30)
303: #define RPF_L3_FILTER_SRCADDR_EN __BIT(29)
304: #define RPF_L3_FILTER_DSTADDR_EN __BIT(28)
305: #define RPF_L3_FILTER_L4_SRCPORT_EN __BIT(27)
306: #define RPF_L3_FILTER_L4_DSTPORT_EN __BIT(26)
307: #define RPF_L3_FILTER_L4_PROTO_EN __BIT(25)
308: #define RPF_L3_FILTER_ARP_EN __BIT(24)
309: #define RPF_L3_FILTER_L4_RXQUEUE_EN __BIT(23)
310: #define RPF_L3_FILTER_L4_RXQUEUE_MANAGEMENT_EN __BIT(22)
311: #define RPF_L3_FILTER_L4_ACTION __BITS(16,18)
312: #define RPF_L3_FILTER_L4_RXQUEUE __BITS(12,8)
313: #define RPF_L3_FILTER_L4_PROTO __BITS(2,0)
314: #define RPF_L3_FILTER_L4_PROTO_TCP 0
315: #define RPF_L3_FILTER_L4_PROTO_UDP 1
316: #define RPF_L3_FILTER_L4_PROTO_SCTP 2
317: #define RPF_L3_FILTER_L4_PROTO_ICMP 3
318: /* parameters of RPF_L3_FILTER_REG[8] */
319: #define RPF_L3_FILTER_SRCADDR_REG(i) (0x53b0 + (i) * 4)
320: #define RPF_L3_FILTER_DSTADDR_REG(i) (0x53d0 + (i) * 4)
321: #define RPF_L3_FILTER_L4_SRCPORT_REG(i) (0x5400 + (i) * 4)
322: #define RPF_L3_FILTER_L4_DSTPORT_REG(i) (0x5420 + (i) * 4)
323:
324: #define RX_FLR_RSS_CONTROL1_REG 0x54c0
325: #define RX_FLR_RSS_CONTROL1_EN __BIT(31)
326:
327: #define RPF_RPB_RX_TC_UPT_REG 0x54c4
328: #define RPF_RPB_RX_TC_UPT_MASK(i) (0x00000007 << ((i) * 4))
329:
330: #define RPF_RSS_KEY_ADDR_REG 0x54d0
331: #define RPF_RSS_KEY_ADDR __BITS(4,0)
332: #define RPF_RSS_KEY_WR_EN __BIT(5)
333: #define RPF_RSS_KEY_WR_DATA_REG 0x54d4
334: #define RPF_RSS_KEY_RD_DATA_REG 0x54d8
335:
336: #define RPF_RSS_REDIR_ADDR_REG 0x54e0
337: #define RPF_RSS_REDIR_ADDR __BITS(3,0)
338: #define RPF_RSS_REDIR_WR_EN __BIT(4)
339:
340: #define RPF_RSS_REDIR_WR_DATA_REG 0x54e4
341: #define RPF_RSS_REDIR_WR_DATA __BITS(15,0)
342:
343: #define RPO_HWCSUM_REG 0x5580
344: #define RPO_HWCSUM_IP4CSUM_EN __BIT(1)
345: #define RPO_HWCSUM_L4CSUM_EN __BIT(0) /* TCP/UDP/SCTP */
346:
347: #define RPO_LRO_ENABLE_REG 0x5590
348:
349: #define RPO_LRO_CONF_REG 0x5594
350: #define RPO_LRO_CONF_QSESSION_LIMIT __BITS(13,12)
351: #define RPO_LRO_CONF_TOTAL_DESC_LIMIT __BITS(6,5)
352: #define RPO_LRO_CONF_PATCHOPTIMIZATION_EN __BIT(15)
353: #define RPO_LRO_CONF_MIN_PAYLOAD_OF_FIRST_PKT __BITS(4,0)
354: #define RPO_LRO_RSC_MAX_REG 0x5598
355:
356: /* RPO_LRO_LDES_MAX_REG[32/8] 0x55a0-0x55b0 */
357: #define RPO_LRO_LDES_MAX_REG(i) (0x55a0 + (i / 8) * 4)
358: #define RPO_LRO_LDES_MAX_MASK(i) (0x00000003 << ((i & 7) * 4))
359: #define RPO_LRO_TB_DIV_REG 0x5620
360: #define RPO_LRO_TB_DIV __BITS(20,31)
361: #define RPO_LRO_INACTIVE_IVAL_REG 0x5620
362: #define RPO_LRO_INACTIVE_IVAL __BITS(10,19)
363: #define RPO_LRO_MAX_COALESCING_IVAL_REG 0x5620
364: #define RPO_LRO_MAX_COALESCING_IVAL __BITS(9,0)
365:
366: #define RPB_RPF_RX_REG 0x5700
367: #define RPB_RPF_RX_TC_MODE __BIT(8)
368: #define RPB_RPF_RX_FC_MODE __BITS(5,4)
369: #define RPB_RPF_RX_BUF_EN __BIT(0)
370:
371: /* RPB_RXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x5710-0x5790 */
372: #define RPB_RXB_BUFSIZE_REG(i) (0x5710 + (i) * 0x10)
373: #define RPB_RXB_BUFSIZE __BITS(8,0)
374: #define RPB_RXB_XOFF_REG(i) (0x5714 + (i) * 0x10)
375: #define RPB_RXB_XOFF_EN __BIT(31)
376: #define RPB_RXB_XOFF_THRESH_HI __BITS(29,16)
377: #define RPB_RXB_XOFF_THRESH_LO __BITS(13,0)
378:
379: #define RX_DMA_DESC_CACHE_INIT_REG 0x5a00
380: #define RX_DMA_DESC_CACHE_INIT __BIT(0)
381:
382: #define RX_DMA_INT_DESC_WRWB_EN_REG 0x05a30
383: #define RX_DMA_INT_DESC_WRWB_EN __BIT(2)
384: #define RX_DMA_INT_DESC_MODERATE_EN __BIT(3)
385:
386: /* RX_INTR_MODERATION_CTL_REG[AQ_RINGS_NUM] 0x5a40-0x5ac0 */
387: #define RX_INTR_MODERATION_CTL_REG(i) (0x5a40 + (i) * 4)
388: #define RX_INTR_MODERATION_CTL_EN __BIT(1)
389: #define RX_INTR_MODERATION_CTL_MIN __BITS(15,8)
390: #define RX_INTR_MODERATION_CTL_MAX __BITS(24,16)
391:
392: /* RX_DMA_DESC_*[AQ_RINGS_NUM] 0x5b00-0x5f00 */
393: #define RX_DMA_DESC_BASE_ADDRLSW_REG(i) (0x5b00 + (i) * 0x20)
394: #define RX_DMA_DESC_BASE_ADDRMSW_REG(i) (0x5b04 + (i) * 0x20)
395: #define RX_DMA_DESC_REG(i) (0x5b08 + (i) * 0x20)
396: #define RX_DMA_DESC_LEN __BITS(12,3) /* RXD_NUM/8 */
397: #define RX_DMA_DESC_RESET __BIT(25)
398: #define RX_DMA_DESC_HEADER_SPLIT __BIT(28)
399: #define RX_DMA_DESC_VLAN_STRIP __BIT(29)
400: #define RX_DMA_DESC_EN __BIT(31)
401: #define RX_DMA_DESC_HEAD_PTR_REG(i) (0x5b0c + (i) * 0x20)
402: #define RX_DMA_DESC_HEAD_PTR __BITS(12,0)
403: #define RX_DMA_DESC_TAIL_PTR_REG(i) (0x5b10 + (i) * 0x20)
404: #define RX_DMA_DESC_BUFSIZE_REG(i) (0x5b18 + (i) * 0x20)
405: #define RX_DMA_DESC_BUFSIZE_DATA __BITS(4,0)
406: #define RX_DMA_DESC_BUFSIZE_HDR __BITS(12,8)
407:
408: /* RX_DMA_DCAD_REG[AQ_RINGS_NUM] 0x6100-0x6180 */
409: #define RX_DMA_DCAD_REG(i) (0x6100 + (i) * 4)
410: #define RX_DMA_DCAD_CPUID __BITS(7,0)
411: #define RX_DMA_DCAD_PAYLOAD_EN __BIT(29)
412: #define RX_DMA_DCAD_HEADER_EN __BIT(30)
413: #define RX_DMA_DCAD_DESC_EN __BIT(31)
414:
415: #define RX_DMA_DCA_REG 0x6180
416: #define RX_DMA_DCA_EN __BIT(31)
417: #define RX_DMA_DCA_MODE __BITS(3,0)
418:
419: /* counters */
420: #define RX_DMA_GOOD_PKT_COUNTERLSW 0x6800
421: #define RX_DMA_GOOD_OCTET_COUNTERLSW 0x6808
422: #define RX_DMA_DROP_PKT_CNT_REG 0x6818
423: #define RX_DMA_COALESCED_PKT_CNT_REG 0x6820
424:
425: #define TX_SYSCONTROL_REG 0x7000
426: #define TX_SYSCONTROL_TPB_DMA_LOOPBACK __BIT(6)
427: #define TX_SYSCONTROL_TPO_PKT_LOOPBACK __BIT(7)
428: #define TX_SYSCONTROL_RESET_DIS __BIT(29)
429:
430: #define TX_TPO2_REG 0x7040
431: #define TX_TPO2_EN __BIT(16)
432:
433: #define TPS_DESC_VM_ARB_MODE_REG 0x7300
434: #define TPS_DESC_VM_ARB_MODE __BIT(0)
435: #define TPS_DESC_RATE_REG 0x7310
436: #define TPS_DESC_RATE_TA_RST __BIT(31)
437: #define TPS_DESC_RATE_LIM __BITS(10,0)
438: #define TPS_DESC_TC_ARB_MODE_REG 0x7200
439: #define TPS_DESC_TC_ARB_MODE __BITS(1,0)
440: #define TPS_DATA_TC_ARB_MODE_REG 0x7100
441: #define TPS_DATA_TC_ARB_MODE __BIT(0)
442:
443: /* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7110-0x7130 */
444: #define TPS_DATA_TCT_REG(i) (0x7110 + (i) * 4)
445: #define TPS_DATA_TCT_CREDIT_MAX __BITS(16,27)
446: #define TPS_DATA_TCT_WEIGHT __BITS(8,0)
447: /* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7210-0x7230 */
448: #define TPS_DESC_TCT_REG(i) (0x7210 + (i) * 4)
449: #define TPS_DESC_TCT_CREDIT_MAX __BITS(16,27)
450: #define TPS_DESC_TCT_WEIGHT __BITS(8,0)
451:
452: #define AQ_HW_TXBUF_MAX 160
453: #define AQ_HW_RXBUF_MAX 320
454:
455: #define TPO_HWCSUM_REG 0x7800
456: #define TPO_HWCSUM_IP4CSUM_EN __BIT(1)
457: #define TPO_HWCSUM_L4CSUM_EN __BIT(0) /* TCP/UDP/SCTP */
458:
459: #define TDM_LSO_EN_REG 0x7810
460:
461: #define THM_LSO_TCP_FLAG1_REG 0x7820
462: #define THM_LSO_TCP_FLAG1_FIRST __BITS(11,0)
463: #define THM_LSO_TCP_FLAG1_MID __BITS(27,16)
464: #define THM_LSO_TCP_FLAG2_REG 0x7824
465: #define THM_LSO_TCP_FLAG2_LAST __BITS(11,0)
466:
467: #define TPB_TX_BUF_REG 0x7900
468: #define TPB_TX_BUF_EN __BIT(0)
469: #define TPB_TX_BUF_SCP_INS_EN __BIT(2)
470: #define TPB_TX_BUF_TC_MODE_EN __BIT(8)
471:
472: /* TPB_TXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x7910-7990 */
473: #define TPB_TXB_BUFSIZE_REG(i) (0x7910 + (i) * 0x10)
474: #define TPB_TXB_BUFSIZE __BITS(7,0)
475: #define TPB_TXB_THRESH_REG(i) (0x7914 + (i) * 0x10)
476: #define TPB_TXB_THRESH_HI __BITS(16,28)
477: #define TPB_TXB_THRESH_LO __BITS(12,0)
478:
479: #define AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG 0x7b20
480: #define TX_DMA_INT_DESC_WRWB_EN_REG 0x7b40
481: #define TX_DMA_INT_DESC_WRWB_EN __BIT(1)
482: #define TX_DMA_INT_DESC_MODERATE_EN __BIT(4)
483:
484: /* TX_DMA_DESC_*[AQ_RINGS_NUM] 0x7c00-0x8400 */
485: #define TX_DMA_DESC_BASE_ADDRLSW_REG(i) (0x7c00 + (i) * 0x40)
486: #define TX_DMA_DESC_BASE_ADDRMSW_REG(i) (0x7c04 + (i) * 0x40)
487: #define TX_DMA_DESC_REG(i) (0x7c08 + (i) * 0x40)
488: #define TX_DMA_DESC_LEN __BITS(12, 3) /* TXD_NUM/8 */
489: #define TX_DMA_DESC_EN __BIT(31)
490: #define TX_DMA_DESC_HEAD_PTR_REG(i) (0x7c0c + (i) * 0x40)
491: #define TX_DMA_DESC_HEAD_PTR __BITS(12,0)
492: #define TX_DMA_DESC_TAIL_PTR_REG(i) (0x7c10 + (i) * 0x40)
493: #define TX_DMA_DESC_WRWB_THRESH_REG(i) (0x7c18 + (i) * 0x40)
494: #define TX_DMA_DESC_WRWB_THRESH __BITS(14,8)
495:
496: /* TDM_DCAD_REG[AQ_RINGS_NUM] 0x8400-0x8480 */
497: #define TDM_DCAD_REG(i) (0x8400 + (i) * 4)
498: #define TDM_DCAD_CPUID __BITS(7,0)
499: #define TDM_DCAD_CPUID_EN __BIT(31)
500:
501: #define TDM_DCA_REG 0x8480
502: #define TDM_DCA_EN __BIT(31)
503: #define TDM_DCA_MODE __BITS(3,0)
504:
505: /* TX_INTR_MODERATION_CTL_REG[AQ_RINGS_NUM] 0x8980-0x8a00 */
506: #define TX_INTR_MODERATION_CTL_REG(i) (0x8980 + (i) * 4)
507: #define TX_INTR_MODERATION_CTL_EN __BIT(1)
508: #define TX_INTR_MODERATION_CTL_MIN __BITS(15,8)
509: #define TX_INTR_MODERATION_CTL_MAX __BITS(24,16)
510:
511: #define FW1X_CTRL_10G __BIT(0)
512: #define FW1X_CTRL_5G __BIT(1)
513: #define FW1X_CTRL_5GSR __BIT(2)
514: #define FW1X_CTRL_2G5 __BIT(3)
515: #define FW1X_CTRL_1G __BIT(4)
516: #define FW1X_CTRL_100M __BIT(5)
517:
518: #define FW2X_CTRL_10BASET_HD __BIT(0)
519: #define FW2X_CTRL_10BASET_FD __BIT(1)
520: #define FW2X_CTRL_100BASETX_HD __BIT(2)
521: #define FW2X_CTRL_100BASET4_HD __BIT(3)
522: #define FW2X_CTRL_100BASET2_HD __BIT(4)
523: #define FW2X_CTRL_100BASETX_FD __BIT(5)
524: #define FW2X_CTRL_100BASET2_FD __BIT(6)
525: #define FW2X_CTRL_1000BASET_HD __BIT(7)
526: #define FW2X_CTRL_1000BASET_FD __BIT(8)
527: #define FW2X_CTRL_2P5GBASET_FD __BIT(9)
528: #define FW2X_CTRL_5GBASET_FD __BIT(10)
529: #define FW2X_CTRL_10GBASET_FD __BIT(11)
530: #define FW2X_CTRL_RESERVED1 __BIT(32)
531: #define FW2X_CTRL_10BASET_EEE __BIT(33)
532: #define FW2X_CTRL_RESERVED2 __BIT(34)
533: #define FW2X_CTRL_PAUSE __BIT(35)
534: #define FW2X_CTRL_ASYMMETRIC_PAUSE __BIT(36)
535: #define FW2X_CTRL_100BASETX_EEE __BIT(37)
536: #define FW2X_CTRL_RESERVED3 __BIT(38)
537: #define FW2X_CTRL_RESERVED4 __BIT(39)
538: #define FW2X_CTRL_1000BASET_FD_EEE __BIT(40)
539: #define FW2X_CTRL_2P5GBASET_FD_EEE __BIT(41)
540: #define FW2X_CTRL_5GBASET_FD_EEE __BIT(42)
541: #define FW2X_CTRL_10GBASET_FD_EEE __BIT(43)
542: #define FW2X_CTRL_RESERVED5 __BIT(44)
543: #define FW2X_CTRL_RESERVED6 __BIT(45)
544: #define FW2X_CTRL_RESERVED7 __BIT(46)
545: #define FW2X_CTRL_RESERVED8 __BIT(47)
546: #define FW2X_CTRL_RESERVED9 __BIT(48)
547: #define FW2X_CTRL_CABLE_DIAG __BIT(49)
548: #define FW2X_CTRL_TEMPERATURE __BIT(50)
549: #define FW2X_CTRL_DOWNSHIFT __BIT(51)
550: #define FW2X_CTRL_PTP_AVB_EN __BIT(52)
551: #define FW2X_CTRL_MEDIA_DETECT __BIT(53)
552: #define FW2X_CTRL_LINK_DROP __BIT(54)
553: #define FW2X_CTRL_SLEEP_PROXY __BIT(55)
554: #define FW2X_CTRL_WOL __BIT(56)
555: #define FW2X_CTRL_MAC_STOP __BIT(57)
556: #define FW2X_CTRL_EXT_LOOPBACK __BIT(58)
557: #define FW2X_CTRL_INT_LOOPBACK __BIT(59)
558: #define FW2X_CTRL_EFUSE_AGENT __BIT(60)
559: #define FW2X_CTRL_WOL_TIMER __BIT(61)
560: #define FW2X_CTRL_STATISTICS __BIT(62)
561: #define FW2X_CTRL_TRANSACTION_ID __BIT(63)
562:
563: #define FW2X_SNPRINTB \
564: "\177\020" \
565: "b\x23" "PAUSE\0" \
566: "b\x24" "ASYMMETRIC-PAUSE\0" \
567: "b\x31" "CABLE-DIAG\0" \
568: "b\x32" "TEMPERATURE\0" \
569: "b\x33" "DOWNSHIFT\0" \
570: "b\x34" "PTP-AVB\0" \
571: "b\x35" "MEDIA-DETECT\0" \
572: "b\x36" "LINK-DROP\0" \
573: "b\x37" "SLEEP-PROXY\0" \
574: "b\x38" "WOL\0" \
575: "b\x39" "MAC-STOP\0" \
576: "b\x3a" "EXT-LOOPBACK\0" \
577: "b\x3b" "INT-LOOPBACK\0" \
578: "b\x3c" "EFUSE-AGENT\0" \
579: "b\x3d" "WOL-TIMER\0" \
580: "b\x3e" "STATISTICS\0" \
581: "b\x3f" "TRANSACTION-ID\0" \
582: "\0"
583:
584: #define FW2X_CTRL_RATE_100M FW2X_CTRL_100BASETX_FD
585: #define FW2X_CTRL_RATE_1G FW2X_CTRL_1000BASET_FD
586: #define FW2X_CTRL_RATE_2G5 FW2X_CTRL_2P5GBASET_FD
587: #define FW2X_CTRL_RATE_5G FW2X_CTRL_5GBASET_FD
588: #define FW2X_CTRL_RATE_10G FW2X_CTRL_10GBASET_FD
589: #define FW2X_CTRL_RATE_MASK \
590: (FW2X_CTRL_RATE_100M | \
591: FW2X_CTRL_RATE_1G | \
592: FW2X_CTRL_RATE_2G5 | \
593: FW2X_CTRL_RATE_5G | \
594: FW2X_CTRL_RATE_10G)
595: #define FW2X_CTRL_EEE_MASK \
596: (FW2X_CTRL_10BASET_EEE | \
597: FW2X_CTRL_100BASETX_EEE | \
598: FW2X_CTRL_1000BASET_FD_EEE | \
599: FW2X_CTRL_2P5GBASET_FD_EEE | \
600: FW2X_CTRL_5GBASET_FD_EEE | \
601: FW2X_CTRL_10GBASET_FD_EEE)
602:
603: typedef enum aq_fw_bootloader_mode {
604: FW_BOOT_MODE_UNKNOWN = 0,
605: FW_BOOT_MODE_FLB,
606: FW_BOOT_MODE_RBL_FLASH,
607: FW_BOOT_MODE_RBL_HOST_BOOTLOAD
608: } aq_fw_bootloader_mode_t;
609:
610: #define AQ_WRITE_REG(sc, reg, val) \
611: bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
612:
613: #define AQ_READ_REG(sc, reg) \
614: bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
615:
616: #define AQ_READ64_REG(sc, reg) \
617: ((uint64_t)AQ_READ_REG(sc, reg) | \
618: (((uint64_t)AQ_READ_REG(sc, (reg) + 4)) << 32))
619:
620: #define AQ_WRITE64_REG(sc, reg, val) \
621: do { \
622: AQ_WRITE_REG(sc, reg, (uint32_t)val); \
623: AQ_WRITE_REG(sc, reg + 4, (uint32_t)(val >> 32)); \
624: } while (/* CONSTCOND */0)
625:
626: #define AQ_READ_REG_BIT(sc, reg, mask) \
627: __SHIFTOUT(AQ_READ_REG(sc, reg), mask)
628:
629: #define AQ_WRITE_REG_BIT(sc, reg, mask, val) \
630: do { \
631: uint32_t _v; \
632: _v = AQ_READ_REG((sc), (reg)); \
633: _v &= ~(mask); \
634: if ((val) != 0) \
635: _v |= __SHIFTIN((val), (mask)); \
636: AQ_WRITE_REG((sc), (reg), _v); \
637: } while (/* CONSTCOND */ 0)
638:
639: #define WAIT_FOR(expr, us, n, errp) \
640: do { \
641: unsigned int _n; \
642: for (_n = n; (!(expr)) && _n != 0; --_n) { \
643: delay((us)); \
644: } \
645: if ((errp != NULL)) { \
646: if (_n == 0) \
647: *(errp) = ETIMEDOUT; \
648: else \
649: *(errp) = 0; \
650: } \
651: } while (/* CONSTCOND */ 0)
652:
653: #define msec_delay(x) DELAY(1000 * (x))
654:
655: typedef struct aq_mailbox_header {
656: uint32_t version;
657: uint32_t transaction_id;
658: int32_t error;
1.19 ryo 659: } __packed __aligned(4) aq_mailbox_header_t;
1.1 ryo 660:
661: typedef struct aq_hw_stats_s {
662: uint32_t uprc;
663: uint32_t mprc;
664: uint32_t bprc;
665: uint32_t erpt;
666: uint32_t uptc;
667: uint32_t mptc;
668: uint32_t bptc;
669: uint32_t erpr;
670: uint32_t mbtc;
671: uint32_t bbtc;
672: uint32_t mbrc;
673: uint32_t bbrc;
674: uint32_t ubrc;
675: uint32_t ubtc;
676: uint32_t ptc;
677: uint32_t prc;
678: uint32_t dpc; /* not exists in fw2x_msm_statistics */
679: uint32_t cprc; /* not exists in fw2x_msm_statistics */
1.19 ryo 680: } __packed __aligned(4) aq_hw_stats_s_t;
1.1 ryo 681:
682: typedef struct fw1x_mailbox {
683: aq_mailbox_header_t header;
684: aq_hw_stats_s_t msm;
1.19 ryo 685: } __packed __aligned(4) fw1x_mailbox_t;
1.1 ryo 686:
687: typedef struct fw2x_msm_statistics {
688: uint32_t uprc;
689: uint32_t mprc;
690: uint32_t bprc;
691: uint32_t erpt;
692: uint32_t uptc;
693: uint32_t mptc;
694: uint32_t bptc;
695: uint32_t erpr;
696: uint32_t mbtc;
697: uint32_t bbtc;
698: uint32_t mbrc;
699: uint32_t bbrc;
700: uint32_t ubrc;
701: uint32_t ubtc;
702: uint32_t ptc;
703: uint32_t prc;
1.19 ryo 704: } __packed __aligned(4) fw2x_msm_statistics_t;
1.1 ryo 705:
706: typedef struct fw2x_phy_cable_diag_data {
707: uint32_t lane_data[4];
1.19 ryo 708: } __packed __aligned(4) fw2x_phy_cable_diag_data_t;
1.1 ryo 709:
710: typedef struct fw2x_capabilities {
711: uint32_t caps_lo;
712: uint32_t caps_hi;
1.19 ryo 713: } __packed __aligned(4) fw2x_capabilities_t;
1.1 ryo 714:
715: typedef struct fw2x_mailbox { /* struct fwHostInterface */
716: aq_mailbox_header_t header;
717: fw2x_msm_statistics_t msm; /* msmStatistics_t msm; */
1.4 ryo 718:
719: uint32_t phy_info1;
720: #define PHYINFO1_FAULT_CODE __BITS(31,16)
721: #define PHYINFO1_PHY_H_BIT __BITS(0,15)
722: uint32_t phy_info2;
723: #define PHYINFO2_TEMPERATURE __BITS(15,0)
724: #define PHYINFO2_CABLE_LEN __BITS(23,16)
725:
1.1 ryo 726: fw2x_phy_cable_diag_data_t diag_data;
727: uint32_t reserved[8];
728:
729: fw2x_capabilities_t caps;
730:
731: /* ... */
1.19 ryo 732: } __packed __aligned(4) fw2x_mailbox_t;
1.1 ryo 733:
734: typedef enum aq_link_speed {
735: AQ_LINK_NONE = 0,
736: AQ_LINK_100M = (1 << 0),
737: AQ_LINK_1G = (1 << 1),
738: AQ_LINK_2G5 = (1 << 2),
739: AQ_LINK_5G = (1 << 3),
740: AQ_LINK_10G = (1 << 4)
741: } aq_link_speed_t;
742: #define AQ_LINK_ALL (AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | \
743: AQ_LINK_5G | AQ_LINK_10G )
744: #define AQ_LINK_AUTO AQ_LINK_ALL
745:
746: typedef enum aq_link_fc {
747: AQ_FC_NONE = 0,
748: AQ_FC_RX = __BIT(0),
749: AQ_FC_TX = __BIT(1),
750: AQ_FC_ALL = (AQ_FC_RX | AQ_FC_TX)
751: } aq_link_fc_t;
752:
753: typedef enum aq_link_eee {
754: AQ_EEE_DISABLE = 0,
755: AQ_EEE_ENABLE = 1
756: } aq_link_eee_t;
757:
758: typedef enum aq_hw_fw_mpi_state {
759: MPI_DEINIT = 0,
760: MPI_RESET = 1,
761: MPI_INIT = 2,
762: MPI_POWER = 4
763: } aq_hw_fw_mpi_state_t;
764:
765: enum aq_media_type {
766: AQ_MEDIA_TYPE_UNKNOWN = 0,
767: AQ_MEDIA_TYPE_FIBRE,
768: AQ_MEDIA_TYPE_TP
769: };
770:
771: struct aq_rx_desc_read {
772: uint64_t buf_addr;
773: uint64_t hdr_addr;
1.19 ryo 774: } __packed __aligned(8);
1.1 ryo 775:
776: struct aq_rx_desc_wb {
777: uint32_t type;
778: #define RXDESC_TYPE_RSSTYPE __BITS(3,0)
779: #define RXDESC_TYPE_RSSTYPE_NONE 0
780: #define RXDESC_TYPE_RSSTYPE_IPV4 2
781: #define RXDESC_TYPE_RSSTYPE_IPV6 3
782: #define RXDESC_TYPE_RSSTYPE_IPV4_TCP 4
783: #define RXDESC_TYPE_RSSTYPE_IPV6_TCP 5
784: #define RXDESC_TYPE_RSSTYPE_IPV4_UDP 6
785: #define RXDESC_TYPE_RSSTYPE_IPV6_UDP 7
786: #define RXDESC_TYPE_PKTTYPE_ETHER __BITS(5,4)
787: #define RXDESC_TYPE_PKTTYPE_ETHER_IPV4 0
788: #define RXDESC_TYPE_PKTTYPE_ETHER_IPV6 1
789: #define RXDESC_TYPE_PKTTYPE_ETHER_OTHERS 2
790: #define RXDESC_TYPE_PKTTYPE_ETHER_ARP 3
791: #define RXDESC_TYPE_PKTTYPE_PROTO __BITS(8,6)
792: #define RXDESC_TYPE_PKTTYPE_PROTO_TCP 0
793: #define RXDESC_TYPE_PKTTYPE_PROTO_UDP 1
794: #define RXDESC_TYPE_PKTTYPE_PROTO_SCTP 2
795: #define RXDESC_TYPE_PKTTYPE_PROTO_ICMP 3
796: #define RXDESC_TYPE_PKTTYPE_PROTO_OTHERS 4
797: #define RXDESC_TYPE_PKTTYPE_VLAN __BIT(9)
798: #define RXDESC_TYPE_PKTTYPE_VLAN_DOUBLE __BIT(10)
799: #define RXDESC_TYPE_MAC_DMA_ERR __BIT(12)
800: #define RXDESC_TYPE_RESERVED __BITS(18,13)
801: #define RXDESC_TYPE_IPV4_CSUM_CHECKED __BIT(19) /* PKTTYPE_ETHER_IPV4 */
802: #define RXDESC_TYPE_TCPUDP_CSUM_CHECKED __BIT(20)
803: #define RXDESC_TYPE_SPH __BIT(21)
804: #define RXDESC_TYPE_HDR_LEN __BITS(31,22)
805: uint32_t rss_hash;
806: uint16_t status;
807: #define RXDESC_STATUS_DD __BIT(0)
808: #define RXDESC_STATUS_EOP __BIT(1)
809: #define RXDESC_STATUS_MACERR __BIT(2)
810: #define RXDESC_STATUS_IPV4_CSUM_NG __BIT(3)
811: #define RXDESC_STATUS_TCPUDP_CSUM_ERROR __BIT(4)
812: #define RXDESC_STATUS_TCPUDP_CSUM_OK __BIT(5)
813:
814: #define RXDESC_STATUS_STAT __BITS(2,5)
815: #define RXDESC_STATUS_ESTAT __BITS(6,11)
816: #define RXDESC_STATUS_RSC_CNT __BITS(12,15)
817: uint16_t pkt_len;
818: uint16_t next_desc_ptr;
819: uint16_t vlan;
1.19 ryo 820: } __packed __aligned(4);
1.1 ryo 821:
822: typedef union aq_rx_desc {
823: struct aq_rx_desc_read read;
824: struct aq_rx_desc_wb wb;
1.19 ryo 825: } __packed __aligned(8) aq_rx_desc_t;
1.1 ryo 826:
827: typedef struct aq_tx_desc {
828: uint64_t buf_addr;
829: uint32_t ctl1;
830: #define AQ_TXDESC_CTL1_TYPE_MASK 0x00000003
831: #define AQ_TXDESC_CTL1_TYPE_TXD 0x00000001
832: #define AQ_TXDESC_CTL1_TYPE_TXC 0x00000002
833: #define AQ_TXDESC_CTL1_BLEN __BITS(19,4) /* TXD */
834: #define AQ_TXDESC_CTL1_DD __BIT(20) /* TXD */
835: #define AQ_TXDESC_CTL1_EOP __BIT(21) /* TXD */
836: #define AQ_TXDESC_CTL1_CMD_VLAN __BIT(22) /* TXD */
837: #define AQ_TXDESC_CTL1_CMD_FCS __BIT(23) /* TXD */
838: #define AQ_TXDESC_CTL1_CMD_IP4CSUM __BIT(24) /* TXD */
839: #define AQ_TXDESC_CTL1_CMD_L4CSUM __BIT(25) /* TXD */
840: #define AQ_TXDESC_CTL1_CMD_LSO __BIT(26) /* TXD */
841: #define AQ_TXDESC_CTL1_CMD_WB __BIT(27) /* TXD */
842: #define AQ_TXDESC_CTL1_CMD_VXLAN __BIT(28) /* TXD */
843: #define AQ_TXDESC_CTL1_VID __BITS(15,4) /* TXC */
844: #define AQ_TXDESC_CTL1_LSO_IPV6 __BIT(21) /* TXC */
845: #define AQ_TXDESC_CTL1_LSO_TCP __BIT(22) /* TXC */
846: uint32_t ctl2;
847: #define AQ_TXDESC_CTL2_LEN __BITS(31,14)
848: #define AQ_TXDESC_CTL2_CTX_EN __BIT(13)
849: #define AQ_TXDESC_CTL2_CTX_IDX __BIT(12)
1.19 ryo 850: } __packed __aligned(8) aq_tx_desc_t;
1.1 ryo 851:
852: struct aq_txring {
853: struct aq_softc *txr_sc;
854: int txr_index;
855: kmutex_t txr_mutex;
856: bool txr_active;
1.33 skrll 857: bool txr_stopping;
858: bool txr_sending;
859: time_t txr_lastsent;
1.1 ryo 860:
861: pcq_t *txr_pcq;
862: void *txr_softint;
863:
864: aq_tx_desc_t *txr_txdesc; /* aq_tx_desc_t[AQ_TXD_NUM] */
865: bus_dmamap_t txr_txdesc_dmamap;
866: bus_dma_segment_t txr_txdesc_seg[1];
867: bus_size_t txr_txdesc_size;
868:
869: struct {
870: struct mbuf *m;
871: bus_dmamap_t dmamap;
872: } txr_mbufs[AQ_TXD_NUM];
873: unsigned int txr_prodidx;
874: unsigned int txr_considx;
875: int txr_nfree;
876: };
877:
878: struct aq_rxring {
879: struct aq_softc *rxr_sc;
880: int rxr_index;
881: kmutex_t rxr_mutex;
882: bool rxr_active;
1.28 ryo 883: bool rxr_discarding;
1.33 skrll 884: bool rxr_stopping;
1.28 ryo 885: struct mbuf *rxr_receiving_m; /* receiving jumboframe */
886: struct mbuf *rxr_receiving_m_last; /* last mbuf of jumboframe */
1.1 ryo 887:
888: aq_rx_desc_t *rxr_rxdesc; /* aq_rx_desc_t[AQ_RXD_NUM] */
889: bus_dmamap_t rxr_rxdesc_dmamap;
890: bus_dma_segment_t rxr_rxdesc_seg[1];
891: bus_size_t rxr_rxdesc_size;
892: struct {
893: struct mbuf *m;
894: bus_dmamap_t dmamap;
895: } rxr_mbufs[AQ_RXD_NUM];
896: unsigned int rxr_readidx;
897: };
898:
899: struct aq_queue {
900: struct aq_softc *sc;
901: struct aq_txring txring;
902: struct aq_rxring rxring;
903: };
904:
905: struct aq_softc;
906: struct aq_firmware_ops {
907: int (*reset)(struct aq_softc *);
908: int (*set_mode)(struct aq_softc *, aq_hw_fw_mpi_state_t,
909: aq_link_speed_t, aq_link_fc_t, aq_link_eee_t);
910: int (*get_mode)(struct aq_softc *, aq_hw_fw_mpi_state_t *,
911: aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *);
912: int (*get_stats)(struct aq_softc *, aq_hw_stats_s_t *);
1.4 ryo 913: #if NSYSMON_ENVSYS > 0
914: int (*get_temperature)(struct aq_softc *, uint32_t *);
915: #endif
1.1 ryo 916: };
917:
918: #ifdef AQ_EVENT_COUNTERS
919: #define AQ_EVCNT_DECL(name) \
920: char sc_evcount_##name##_name[32]; \
921: struct evcnt sc_evcount_##name##_ev;
922: #define AQ_EVCNT_ATTACH(sc, name, desc, evtype) \
923: do { \
924: snprintf((sc)->sc_evcount_##name##_name, \
925: sizeof((sc)->sc_evcount_##name##_name), \
926: "%s", desc); \
927: evcnt_attach_dynamic(&(sc)->sc_evcount_##name##_ev, \
928: (evtype), NULL, device_xname((sc)->sc_dev), \
929: (sc)->sc_evcount_##name##_name); \
930: } while (/*CONSTCOND*/0)
931: #define AQ_EVCNT_ATTACH_MISC(sc, name, desc) \
932: AQ_EVCNT_ATTACH(sc, name, desc, EVCNT_TYPE_MISC)
933: #define AQ_EVCNT_DETACH(sc, name) \
1.41 ryo 934: if ((sc)->sc_evcount_##name##_name[0] != '\0') \
935: evcnt_detach(&(sc)->sc_evcount_##name##_ev)
1.1 ryo 936: #define AQ_EVCNT_ADD(sc, name, val) \
937: ((sc)->sc_evcount_##name##_ev.ev_count += (val))
938: #endif /* AQ_EVENT_COUNTERS */
939:
940: #define AQ_LOCK(sc) mutex_enter(&(sc)->sc_mutex);
941: #define AQ_UNLOCK(sc) mutex_exit(&(sc)->sc_mutex);
1.33 skrll 942: #define AQ_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_mutex));
1.1 ryo 943:
1.4 ryo 944: /* lock for FW2X_MPI_{CONTROL,STATE]_REG read-modify-write */
945: #define AQ_MPI_LOCK(sc) mutex_enter(&(sc)->sc_mpi_mutex);
946: #define AQ_MPI_UNLOCK(sc) mutex_exit(&(sc)->sc_mpi_mutex);
1.33 skrll 947: #define AQ_MPI_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_mpi_mutex));
1.4 ryo 948:
949:
1.1 ryo 950: struct aq_softc {
951: device_t sc_dev;
952:
953: bus_space_tag_t sc_iot;
954: bus_space_handle_t sc_ioh;
955: bus_size_t sc_iosize;
1.17 msaitoh 956: bus_dma_tag_t sc_dmat;
1.1 ryo 957:
958: void *sc_ihs[AQ_NINTR_MAX];
959: pci_intr_handle_t *sc_intrs;
960:
961: int sc_tx_irq[AQ_RSSQUEUE_MAX];
962: int sc_rx_irq[AQ_RSSQUEUE_MAX];
963: int sc_linkstat_irq;
964: bool sc_use_txrx_independent_intr;
965: bool sc_poll_linkstat;
966: bool sc_detect_linkstat;
967:
1.4 ryo 968: #if NSYSMON_ENVSYS > 0
969: struct sysmon_envsys *sc_sme;
970: envsys_data_t sc_sensor_temp;
971: #endif
972:
1.1 ryo 973: callout_t sc_tick_ch;
974:
975: int sc_nintrs;
976: bool sc_msix;
977:
978: struct aq_queue sc_queue[AQ_RSSQUEUE_MAX];
979: int sc_nqueues;
980:
981: pci_chipset_tag_t sc_pc;
982: pcitag_t sc_pcitag;
983: uint16_t sc_product;
984: uint16_t sc_revision;
985:
986: kmutex_t sc_mutex;
1.4 ryo 987: kmutex_t sc_mpi_mutex;
1.1 ryo 988:
1.8 maxv 989: const struct aq_firmware_ops *sc_fw_ops;
1.1 ryo 990: uint64_t sc_fw_caps;
991: enum aq_media_type sc_media_type;
992: aq_link_speed_t sc_available_rates;
993:
994: aq_link_speed_t sc_link_rate;
995: aq_link_fc_t sc_link_fc;
996: aq_link_eee_t sc_link_eee;
997:
998: uint32_t sc_fw_version;
999: #define FW_VERSION_MAJOR(sc) (((sc)->sc_fw_version >> 24) & 0xff)
1000: #define FW_VERSION_MINOR(sc) (((sc)->sc_fw_version >> 16) & 0xff)
1001: #define FW_VERSION_BUILD(sc) ((sc)->sc_fw_version & 0xffff)
1002: uint32_t sc_features;
1003: #define FEATURES_MIPS 0x00000001
1004: #define FEATURES_TPO2 0x00000002
1005: #define FEATURES_RPF2 0x00000004
1006: #define FEATURES_MPI_AQ 0x00000008
1007: #define FEATURES_REV_A0 0x10000000
1008: #define FEATURES_REV_A (FEATURES_REV_A0)
1009: #define FEATURES_REV_B0 0x20000000
1010: #define FEATURES_REV_B1 0x40000000
1011: #define FEATURES_REV_B (FEATURES_REV_B0|FEATURES_REV_B1)
1.40 ryo 1012: int sc_max_mtu;
1.1 ryo 1013: uint32_t sc_mbox_addr;
1014:
1015: bool sc_rbl_enabled;
1016: bool sc_fast_start_enabled;
1017: bool sc_flash_present;
1018:
1019: bool sc_intr_moderation_enable;
1020: bool sc_rss_enable;
1021:
1022: struct ethercom sc_ethercom;
1023: struct ether_addr sc_enaddr;
1024: struct ifmedia sc_media;
1025: int sc_ec_capenable; /* last ec_capenable */
1026: unsigned short sc_if_flags; /* last if_flags */
1027:
1.33 skrll 1028: bool sc_tx_sending;
1029: bool sc_stopping;
1030:
1031: struct workqueue *sc_reset_wq;
1032: struct work sc_reset_work;
1033: volatile unsigned sc_reset_pending;
1034:
1035: bool sc_trigger_reset;
1036:
1.1 ryo 1037: #ifdef AQ_EVENT_COUNTERS
1038: aq_hw_stats_s_t sc_statistics[2];
1039: int sc_statistics_idx;
1040: bool sc_poll_statistics;
1041:
1042: AQ_EVCNT_DECL(uprc);
1043: AQ_EVCNT_DECL(mprc);
1044: AQ_EVCNT_DECL(bprc);
1045: AQ_EVCNT_DECL(erpt);
1046: AQ_EVCNT_DECL(uptc);
1047: AQ_EVCNT_DECL(mptc);
1048: AQ_EVCNT_DECL(bptc);
1049: AQ_EVCNT_DECL(erpr);
1050: AQ_EVCNT_DECL(mbtc);
1051: AQ_EVCNT_DECL(bbtc);
1052: AQ_EVCNT_DECL(mbrc);
1053: AQ_EVCNT_DECL(bbrc);
1054: AQ_EVCNT_DECL(ubrc);
1055: AQ_EVCNT_DECL(ubtc);
1056: AQ_EVCNT_DECL(ptc);
1057: AQ_EVCNT_DECL(prc);
1058: AQ_EVCNT_DECL(dpc);
1059: AQ_EVCNT_DECL(cprc);
1060: #endif
1061: };
1062:
1063: static int aq_match(device_t, cfdata_t, void *);
1064: static void aq_attach(device_t, device_t, void *);
1065: static int aq_detach(device_t, int);
1066:
1067: static int aq_setup_msix(struct aq_softc *, struct pci_attach_args *, int,
1068: bool, bool);
1069: static int aq_setup_legacy(struct aq_softc *, struct pci_attach_args *,
1070: pci_intr_type_t);
1071: static int aq_establish_msix_intr(struct aq_softc *, bool, bool);
1072:
1073: static int aq_ifmedia_change(struct ifnet * const);
1074: static void aq_ifmedia_status(struct ifnet * const, struct ifmediareq *);
1.10 ryo 1075: static int aq_vlan_cb(struct ethercom *ec, uint16_t vid, bool set);
1.1 ryo 1076: static int aq_ifflags_cb(struct ethercom *);
1077: static int aq_init(struct ifnet *);
1.33 skrll 1078: static int aq_init_locked(struct ifnet *);
1.1 ryo 1079: static void aq_send_common_locked(struct ifnet *, struct aq_softc *,
1080: struct aq_txring *, bool);
1081: static int aq_transmit(struct ifnet *, struct mbuf *);
1082: static void aq_deferred_transmit(void *);
1083: static void aq_start(struct ifnet *);
1084: static void aq_stop(struct ifnet *, int);
1.33 skrll 1085: static void aq_stop_locked(struct ifnet *, bool);
1.1 ryo 1086: static int aq_ioctl(struct ifnet *, unsigned long, void *);
1087:
1088: static int aq_txrx_rings_alloc(struct aq_softc *);
1089: static void aq_txrx_rings_free(struct aq_softc *);
1090: static int aq_tx_pcq_alloc(struct aq_softc *, struct aq_txring *);
1091: static void aq_tx_pcq_free(struct aq_softc *, struct aq_txring *);
1092:
1093: static void aq_initmedia(struct aq_softc *);
1094: static void aq_enable_intr(struct aq_softc *, bool, bool);
1095:
1.33 skrll 1096: static void aq_handle_reset_work(struct work *, void *);
1097: static void aq_unset_stopping_flags(struct aq_softc *);
1098: static void aq_set_stopping_flags(struct aq_softc *);
1099:
1.4 ryo 1100: #if NSYSMON_ENVSYS > 0
1101: static void aq_temp_refresh(struct sysmon_envsys *, envsys_data_t *);
1102: #endif
1.1 ryo 1103: static void aq_tick(void *);
1104: static int aq_legacy_intr(void *);
1105: static int aq_link_intr(void *);
1106: static int aq_txrx_intr(void *);
1107: static int aq_tx_intr(void *);
1108: static int aq_rx_intr(void *);
1109:
1110: static int aq_set_linkmode(struct aq_softc *, aq_link_speed_t, aq_link_fc_t,
1111: aq_link_eee_t);
1112: static int aq_get_linkmode(struct aq_softc *, aq_link_speed_t *, aq_link_fc_t *,
1113: aq_link_eee_t *);
1114:
1115: static int aq_fw_reset(struct aq_softc *);
1116: static int aq_fw_version_init(struct aq_softc *);
1117: static int aq_hw_init(struct aq_softc *);
1118: static int aq_hw_init_ucp(struct aq_softc *);
1119: static int aq_hw_reset(struct aq_softc *);
1120: static int aq_fw_downld_dwords(struct aq_softc *, uint32_t, uint32_t *,
1121: uint32_t);
1122: static int aq_get_mac_addr(struct aq_softc *);
1123: static int aq_init_rss(struct aq_softc *);
1124: static int aq_set_capability(struct aq_softc *);
1125:
1126: static int fw1x_reset(struct aq_softc *);
1127: static int fw1x_set_mode(struct aq_softc *, aq_hw_fw_mpi_state_t,
1128: aq_link_speed_t, aq_link_fc_t, aq_link_eee_t);
1129: static int fw1x_get_mode(struct aq_softc *, aq_hw_fw_mpi_state_t *,
1130: aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *);
1131: static int fw1x_get_stats(struct aq_softc *, aq_hw_stats_s_t *);
1132:
1133: static int fw2x_reset(struct aq_softc *);
1134: static int fw2x_set_mode(struct aq_softc *, aq_hw_fw_mpi_state_t,
1135: aq_link_speed_t, aq_link_fc_t, aq_link_eee_t);
1136: static int fw2x_get_mode(struct aq_softc *, aq_hw_fw_mpi_state_t *,
1137: aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *);
1138: static int fw2x_get_stats(struct aq_softc *, aq_hw_stats_s_t *);
1.4 ryo 1139: #if NSYSMON_ENVSYS > 0
1140: static int fw2x_get_temperature(struct aq_softc *, uint32_t *);
1141: #endif
1.1 ryo 1142:
1.33 skrll 1143: #ifndef AQ_WATCHDOG_TIMEOUT
1144: #define AQ_WATCHDOG_TIMEOUT 5
1145: #endif
1146: static int aq_watchdog_timeout = AQ_WATCHDOG_TIMEOUT;
1147:
1148:
1.8 maxv 1149: static const struct aq_firmware_ops aq_fw1x_ops = {
1.1 ryo 1150: .reset = fw1x_reset,
1151: .set_mode = fw1x_set_mode,
1152: .get_mode = fw1x_get_mode,
1.4 ryo 1153: .get_stats = fw1x_get_stats,
1154: #if NSYSMON_ENVSYS > 0
1155: .get_temperature = NULL
1156: #endif
1.1 ryo 1157: };
1158:
1.8 maxv 1159: static const struct aq_firmware_ops aq_fw2x_ops = {
1.1 ryo 1160: .reset = fw2x_reset,
1161: .set_mode = fw2x_set_mode,
1162: .get_mode = fw2x_get_mode,
1.4 ryo 1163: .get_stats = fw2x_get_stats,
1164: #if NSYSMON_ENVSYS > 0
1165: .get_temperature = fw2x_get_temperature
1166: #endif
1.1 ryo 1167: };
1168:
1169: CFATTACH_DECL3_NEW(aq, sizeof(struct aq_softc),
1170: aq_match, aq_attach, aq_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
1171:
1172: static const struct aq_product {
1173: pci_vendor_id_t aq_vendor;
1174: pci_product_id_t aq_product;
1175: const char *aq_name;
1176: enum aq_media_type aq_media_type;
1177: aq_link_speed_t aq_available_rates;
1178: } aq_products[] = {
1.14 ryo 1179: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100,
1180: "Aquantia AQC100 10 Gigabit Network Adapter",
1181: AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL
1182: },
1.1 ryo 1183: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107,
1184: "Aquantia AQC107 10 Gigabit Network Adapter",
1185: AQ_MEDIA_TYPE_TP, AQ_LINK_ALL
1186: },
1187: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108,
1188: "Aquantia AQC108 5 Gigabit Network Adapter",
1189: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1190: },
1191: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109,
1192: "Aquantia AQC109 2.5 Gigabit Network Adapter",
1193: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1194: },
1195: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111,
1196: "Aquantia AQC111 5 Gigabit Network Adapter",
1197: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1198: },
1199: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112,
1200: "Aquantia AQC112 2.5 Gigabit Network Adapter",
1201: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1202: },
1.15 ryo 1203: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100S,
1.16 ryo 1204: "Aquantia AQC100S 10 Gigabit Network Adapter",
1.15 ryo 1205: AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL
1206: },
1.1 ryo 1207: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107S,
1208: "Aquantia AQC107S 10 Gigabit Network Adapter",
1209: AQ_MEDIA_TYPE_TP, AQ_LINK_ALL
1210: },
1211: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108S,
1212: "Aquantia AQC108S 5 Gigabit Network Adapter",
1213: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1214: },
1215: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109S,
1216: "Aquantia AQC109S 2.5 Gigabit Network Adapter",
1217: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1218: },
1219: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111S,
1220: "Aquantia AQC111S 5 Gigabit Network Adapter",
1221: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1222: },
1223: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112S,
1224: "Aquantia AQC112S 2.5 Gigabit Network Adapter",
1225: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1226: },
1.15 ryo 1227: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D100,
1228: "Aquantia D100 10 Gigabit Network Adapter",
1229: AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL
1230: },
1.1 ryo 1231: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D107,
1232: "Aquantia D107 10 Gigabit Network Adapter",
1233: AQ_MEDIA_TYPE_TP, AQ_LINK_ALL
1234: },
1235: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D108,
1236: "Aquantia D108 5 Gigabit Network Adapter",
1237: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1238: },
1239: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D109,
1240: "Aquantia D109 2.5 Gigabit Network Adapter",
1241: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1242: }
1243: };
1244:
1245: static const struct aq_product *
1246: aq_lookup(const struct pci_attach_args *pa)
1247: {
1248: unsigned int i;
1249:
1250: for (i = 0; i < __arraycount(aq_products); i++) {
1251: if (PCI_VENDOR(pa->pa_id) == aq_products[i].aq_vendor &&
1252: PCI_PRODUCT(pa->pa_id) == aq_products[i].aq_product)
1253: return &aq_products[i];
1254: }
1255: return NULL;
1256: }
1257:
1258: static int
1259: aq_match(device_t parent, cfdata_t cf, void *aux)
1260: {
1.32 skrll 1261: struct pci_attach_args * const pa = aux;
1.1 ryo 1262:
1263: if (aq_lookup(pa) != NULL)
1264: return 1;
1265:
1266: return 0;
1267: }
1268:
1269: static void
1270: aq_attach(device_t parent, device_t self, void *aux)
1271: {
1.32 skrll 1272: struct aq_softc * const sc = device_private(self);
1273: struct pci_attach_args * const pa = aux;
1274: struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
1.1 ryo 1275: pci_chipset_tag_t pc;
1276: pcitag_t tag;
1277: pcireg_t command, memtype, bar;
1278: const struct aq_product *aqp;
1279: int error;
1280:
1281: sc->sc_dev = self;
1282: mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_NET);
1.4 ryo 1283: mutex_init(&sc->sc_mpi_mutex, MUTEX_DEFAULT, IPL_NET);
1.1 ryo 1284:
1285: sc->sc_pc = pc = pa->pa_pc;
1286: sc->sc_pcitag = tag = pa->pa_tag;
1287: sc->sc_dmat = pci_dma64_available(pa) ? pa->pa_dmat64 : pa->pa_dmat;
1288:
1289: command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1290: command |= PCI_COMMAND_MASTER_ENABLE;
1291: pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
1292:
1293: sc->sc_product = PCI_PRODUCT(pa->pa_id);
1294: sc->sc_revision = PCI_REVISION(pa->pa_class);
1295:
1296: aqp = aq_lookup(pa);
1297: KASSERT(aqp != NULL);
1298:
1299: pci_aprint_devinfo_fancy(pa, "Ethernet controller", aqp->aq_name, 1);
1300:
1301: bar = pci_conf_read(pc, tag, PCI_BAR(0));
1302: if ((PCI_MAPREG_MEM_ADDR(bar) == 0) ||
1303: (PCI_MAPREG_TYPE(bar) != PCI_MAPREG_TYPE_MEM)) {
1304: aprint_error_dev(sc->sc_dev, "wrong BAR type\n");
1305: return;
1306: }
1307: memtype = pci_mapreg_type(pc, tag, PCI_BAR(0));
1308: if (pci_mapreg_map(pa, PCI_BAR(0), memtype, 0, &sc->sc_iot, &sc->sc_ioh,
1309: NULL, &sc->sc_iosize) != 0) {
1310: aprint_error_dev(sc->sc_dev, "unable to map register\n");
1311: return;
1312: }
1313:
1.31 ryo 1314: error = aq_fw_reset(sc);
1315: if (error != 0)
1316: goto attach_failure;
1317:
1.1 ryo 1318: sc->sc_nqueues = MIN(ncpu, AQ_RSSQUEUE_MAX);
1319:
1320: /* max queue num is 8, and must be 2^n */
1321: if (ncpu >= 8)
1322: sc->sc_nqueues = 8;
1323: else if (ncpu >= 4)
1324: sc->sc_nqueues = 4;
1325: else if (ncpu >= 2)
1326: sc->sc_nqueues = 2;
1327: else
1328: sc->sc_nqueues = 1;
1329:
1330: int msixcount = pci_msix_count(pa->pa_pc, pa->pa_tag);
1331: #ifndef CONFIG_NO_TXRX_INDEPENDENT
1332: if (msixcount >= (sc->sc_nqueues * 2 + 1)) {
1333: /* TX intrs + RX intrs + LINKSTAT intrs */
1334: sc->sc_use_txrx_independent_intr = true;
1335: sc->sc_poll_linkstat = false;
1336: sc->sc_msix = true;
1337: } else if (msixcount >= (sc->sc_nqueues * 2)) {
1338: /* TX intrs + RX intrs */
1339: sc->sc_use_txrx_independent_intr = true;
1340: sc->sc_poll_linkstat = true;
1341: sc->sc_msix = true;
1342: } else
1343: #endif
1344: if (msixcount >= (sc->sc_nqueues + 1)) {
1345: /* TX/RX intrs LINKSTAT intrs */
1346: sc->sc_use_txrx_independent_intr = false;
1347: sc->sc_poll_linkstat = false;
1348: sc->sc_msix = true;
1349: } else if (msixcount >= sc->sc_nqueues) {
1350: /* TX/RX intrs */
1351: sc->sc_use_txrx_independent_intr = false;
1352: sc->sc_poll_linkstat = true;
1353: sc->sc_msix = true;
1354: } else {
1355: /* giving up using MSI-X */
1356: sc->sc_msix = false;
1357: }
1358:
1.31 ryo 1359: /* on FW Ver1 or FIBRE, linkstat interrupt does not occur on boot? */
1360: if (aqp->aq_media_type == AQ_MEDIA_TYPE_FIBRE ||
1361: FW_VERSION_MAJOR(sc) == 1)
1.13 ryo 1362: sc->sc_poll_linkstat = true;
1363:
1364: #ifdef AQ_FORCE_POLL_LINKSTAT
1365: sc->sc_poll_linkstat = true;
1366: #endif
1367:
1.1 ryo 1368: aprint_debug_dev(sc->sc_dev,
1369: "ncpu=%d, pci_msix_count=%d."
1370: " allocate %d interrupts for %d%s queues%s\n",
1371: ncpu, msixcount,
1372: (sc->sc_use_txrx_independent_intr ?
1373: (sc->sc_nqueues * 2) : sc->sc_nqueues) +
1374: (sc->sc_poll_linkstat ? 0 : 1),
1375: sc->sc_nqueues,
1376: sc->sc_use_txrx_independent_intr ? "*2" : "",
1377: sc->sc_poll_linkstat ? "" : ", and link status");
1378:
1379: if (sc->sc_msix)
1380: error = aq_setup_msix(sc, pa, sc->sc_nqueues,
1381: sc->sc_use_txrx_independent_intr, !sc->sc_poll_linkstat);
1382: else
1383: error = ENODEV;
1384:
1385: if (error != 0) {
1386: /* if MSI-X failed, fallback to MSI with single queue */
1387: sc->sc_use_txrx_independent_intr = false;
1388: sc->sc_poll_linkstat = false;
1389: sc->sc_msix = false;
1390: sc->sc_nqueues = 1;
1391: error = aq_setup_legacy(sc, pa, PCI_INTR_TYPE_MSI);
1392: }
1393: if (error != 0) {
1394: /* if MSI failed, fallback to INTx */
1395: error = aq_setup_legacy(sc, pa, PCI_INTR_TYPE_INTX);
1396: }
1397: if (error != 0)
1.31 ryo 1398: goto attach_failure;
1.1 ryo 1399:
1.33 skrll 1400: callout_init(&sc->sc_tick_ch, CALLOUT_MPSAFE);
1.1 ryo 1401: callout_setfunc(&sc->sc_tick_ch, aq_tick, sc);
1402:
1.33 skrll 1403: char wqname[MAXCOMLEN];
1404: snprintf(wqname, sizeof(wqname), "%sReset", device_xname(sc->sc_dev));
1405: error = workqueue_create(&sc->sc_reset_wq, wqname,
1406: aq_handle_reset_work, sc, PRI_SOFTNET, IPL_SOFTCLOCK,
1407: WQ_MPSAFE);
1408: if (error) {
1409: aprint_error_dev(sc->sc_dev,
1410: "unable to create reset workqueue\n");
1411: goto attach_failure;
1412: }
1413:
1.1 ryo 1414: sc->sc_intr_moderation_enable = CONFIG_INTR_MODERATION_ENABLE;
1415:
1416: if (sc->sc_msix && (sc->sc_nqueues > 1))
1417: sc->sc_rss_enable = true;
1418: else
1419: sc->sc_rss_enable = false;
1420:
1421: error = aq_txrx_rings_alloc(sc);
1422: if (error != 0)
1423: goto attach_failure;
1424:
1425: error = aq_fw_version_init(sc);
1426: if (error != 0)
1427: goto attach_failure;
1428:
1429: error = aq_hw_init_ucp(sc);
1430: if (error < 0)
1431: goto attach_failure;
1432:
1433: KASSERT(sc->sc_mbox_addr != 0);
1434: error = aq_hw_reset(sc);
1435: if (error != 0)
1436: goto attach_failure;
1437:
1438: aq_get_mac_addr(sc);
1439: aq_init_rss(sc);
1440:
1441: error = aq_hw_init(sc); /* initialize and interrupts */
1442: if (error != 0)
1443: goto attach_failure;
1444:
1445: sc->sc_media_type = aqp->aq_media_type;
1446: sc->sc_available_rates = aqp->aq_available_rates;
1447:
1448: sc->sc_ethercom.ec_ifmedia = &sc->sc_media;
1449: ifmedia_init(&sc->sc_media, IFM_IMASK,
1450: aq_ifmedia_change, aq_ifmedia_status);
1451: aq_initmedia(sc);
1452:
1453: strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
1454: ifp->if_softc = sc;
1455: ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1.20 ryo 1456: ifp->if_extflags = IFEF_MPSAFE;
1.1 ryo 1457: ifp->if_baudrate = IF_Gbps(10);
1458: ifp->if_init = aq_init;
1459: ifp->if_ioctl = aq_ioctl;
1460: if (sc->sc_msix && (sc->sc_nqueues > 1))
1461: ifp->if_transmit = aq_transmit;
1462: ifp->if_start = aq_start;
1463: ifp->if_stop = aq_stop;
1.33 skrll 1464: ifp->if_watchdog = NULL;
1.1 ryo 1465: IFQ_SET_READY(&ifp->if_snd);
1466:
1467: /* initialize capabilities */
1468: sc->sc_ethercom.ec_capabilities = 0;
1469: sc->sc_ethercom.ec_capenable = 0;
1470: #if notyet
1471: /* TODO */
1472: sc->sc_ethercom.ec_capabilities |= ETHERCAP_EEE;
1473: #endif
1474: sc->sc_ethercom.ec_capabilities |=
1475: ETHERCAP_JUMBO_MTU |
1476: ETHERCAP_VLAN_MTU |
1.10 ryo 1477: ETHERCAP_VLAN_HWTAGGING |
1478: ETHERCAP_VLAN_HWFILTER;
1.1 ryo 1479: sc->sc_ethercom.ec_capenable |=
1.10 ryo 1480: ETHERCAP_VLAN_HWTAGGING |
1481: ETHERCAP_VLAN_HWFILTER;
1.1 ryo 1482:
1483: ifp->if_capabilities = 0;
1484: ifp->if_capenable = 0;
1485: #ifdef CONFIG_LRO_SUPPORT
1486: ifp->if_capabilities |= IFCAP_LRO;
1487: ifp->if_capenable |= IFCAP_LRO;
1488: #endif
1489: #if notyet
1490: /* TSO */
1491: ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
1492: #endif
1493:
1.25 ryo 1494: /* TX hardware checksum offloading */
1.1 ryo 1495: ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx;
1496: ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv6_Tx;
1497: ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv6_Tx;
1.25 ryo 1498: /* RX hardware checksum offloading */
1.1 ryo 1499: ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx;
1.21 ryo 1500: ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_TCPv6_Rx;
1501: ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Rx | IFCAP_CSUM_UDPv6_Rx;
1.1 ryo 1502:
1.27 riastrad 1503: if_initialize(ifp);
1.20 ryo 1504: ifp->if_percpuq = if_percpuq_create(ifp);
1.1 ryo 1505: if_deferred_start_init(ifp, NULL);
1506: ether_ifattach(ifp, sc->sc_enaddr.ether_addr_octet);
1.10 ryo 1507: ether_set_vlan_cb(&sc->sc_ethercom, aq_vlan_cb);
1.1 ryo 1508: ether_set_ifflags_cb(&sc->sc_ethercom, aq_ifflags_cb);
1.20 ryo 1509: if_register(ifp);
1.1 ryo 1510:
1.37 riastrad 1511: /* only intr about link */
1512: aq_enable_intr(sc, /*link*/true, /*txrx*/false);
1.1 ryo 1513:
1514: /* update media */
1515: aq_ifmedia_change(ifp);
1516:
1.4 ryo 1517: #if NSYSMON_ENVSYS > 0
1518: /* temperature monitoring */
1519: if (sc->sc_fw_ops != NULL && sc->sc_fw_ops->get_temperature != NULL &&
1520: (sc->sc_fw_caps & FW2X_CTRL_TEMPERATURE) != 0) {
1521:
1522: sc->sc_sme = sysmon_envsys_create();
1523: sc->sc_sme->sme_name = device_xname(self);
1524: sc->sc_sme->sme_cookie = sc;
1525: sc->sc_sme->sme_flags = 0;
1526: sc->sc_sme->sme_refresh = aq_temp_refresh;
1527: sc->sc_sensor_temp.units = ENVSYS_STEMP;
1528: sc->sc_sensor_temp.state = ENVSYS_SINVALID;
1529: snprintf(sc->sc_sensor_temp.desc, ENVSYS_DESCLEN, "PHY");
1530:
1531: sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor_temp);
1.26 mlelstv 1532: if (sysmon_envsys_register(sc->sc_sme)) {
1533: sysmon_envsys_destroy(sc->sc_sme);
1534: sc->sc_sme = NULL;
1535: goto attach_failure;
1536: }
1.4 ryo 1537:
1538: /*
1539: * for unknown reasons, the first call of fw2x_get_temperature()
1540: * will always fail (firmware matter?), so run once now.
1541: */
1542: aq_temp_refresh(sc->sc_sme, &sc->sc_sensor_temp);
1543: }
1544: #endif
1545:
1.1 ryo 1546: #ifdef AQ_EVENT_COUNTERS
1547: /* get starting statistics values */
1548: if (sc->sc_fw_ops != NULL && sc->sc_fw_ops->get_stats != NULL &&
1549: sc->sc_fw_ops->get_stats(sc, &sc->sc_statistics[0]) == 0) {
1550: sc->sc_poll_statistics = true;
1551: }
1552:
1553: AQ_EVCNT_ATTACH_MISC(sc, uprc, "RX unicast packet");
1554: AQ_EVCNT_ATTACH_MISC(sc, bprc, "RX broadcast packet");
1555: AQ_EVCNT_ATTACH_MISC(sc, mprc, "RX multicast packet");
1556: AQ_EVCNT_ATTACH_MISC(sc, erpr, "RX error packet");
1557: AQ_EVCNT_ATTACH_MISC(sc, ubrc, "RX unicast bytes");
1558: AQ_EVCNT_ATTACH_MISC(sc, bbrc, "RX broadcast bytes");
1559: AQ_EVCNT_ATTACH_MISC(sc, mbrc, "RX multicast bytes");
1560: AQ_EVCNT_ATTACH_MISC(sc, prc, "RX good packet");
1561: AQ_EVCNT_ATTACH_MISC(sc, uptc, "TX unicast packet");
1562: AQ_EVCNT_ATTACH_MISC(sc, bptc, "TX broadcast packet");
1563: AQ_EVCNT_ATTACH_MISC(sc, mptc, "TX multicast packet");
1564: AQ_EVCNT_ATTACH_MISC(sc, erpt, "TX error packet");
1565: AQ_EVCNT_ATTACH_MISC(sc, ubtc, "TX unicast bytes");
1566: AQ_EVCNT_ATTACH_MISC(sc, bbtc, "TX broadcast bytes");
1567: AQ_EVCNT_ATTACH_MISC(sc, mbtc, "TX multicast bytes");
1568: AQ_EVCNT_ATTACH_MISC(sc, ptc, "TX good packet");
1569: AQ_EVCNT_ATTACH_MISC(sc, dpc, "DMA drop packet");
1570: AQ_EVCNT_ATTACH_MISC(sc, cprc, "RX coalesced packet");
1571: #endif
1572:
1.29 msaitoh 1573: if (pmf_device_register(self, NULL, NULL))
1574: pmf_class_network_register(self, ifp);
1575: else
1576: aprint_error_dev(self, "couldn't establish power handler\n");
1577:
1.1 ryo 1578: return;
1579:
1580: attach_failure:
1581: aq_detach(self, 0);
1582: }
1583:
1584: static int
1585: aq_detach(device_t self, int flags __unused)
1586: {
1.32 skrll 1587: struct aq_softc * const sc = device_private(self);
1588: struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
1589: int i;
1.1 ryo 1590:
1.41 ryo 1591: if (sc->sc_dev == NULL)
1592: return 0;
1593:
1.1 ryo 1594: if (sc->sc_iosize != 0) {
1595: if (ifp->if_softc != NULL) {
1.35 skrll 1596: IFNET_LOCK(ifp);
1597: aq_stop(ifp, 1);
1598: IFNET_UNLOCK(ifp);
1.1 ryo 1599: }
1600:
1601: for (i = 0; i < AQ_NINTR_MAX; i++) {
1602: if (sc->sc_ihs[i] != NULL) {
1603: pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
1604: sc->sc_ihs[i] = NULL;
1605: }
1606: }
1607: if (sc->sc_nintrs > 0) {
1.41 ryo 1608: callout_stop(&sc->sc_tick_ch);
1609:
1.1 ryo 1610: pci_intr_release(sc->sc_pc, sc->sc_intrs,
1611: sc->sc_nintrs);
1612: sc->sc_intrs = NULL;
1613: sc->sc_nintrs = 0;
1614: }
1615:
1.41 ryo 1616: if (sc->sc_reset_wq != NULL) {
1617: workqueue_destroy(sc->sc_reset_wq);
1618: sc->sc_reset_wq = NULL;
1619: }
1620:
1.1 ryo 1621: aq_txrx_rings_free(sc);
1622:
1623: if (ifp->if_softc != NULL) {
1624: ether_ifdetach(ifp);
1625: if_detach(ifp);
1626: }
1627:
1628: bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize);
1629: sc->sc_iosize = 0;
1630: }
1631:
1.4 ryo 1632: #if NSYSMON_ENVSYS > 0
1633: if (sc->sc_sme != NULL) {
1634: /* all sensors associated with this will also be detached */
1635: sysmon_envsys_unregister(sc->sc_sme);
1636: }
1637: #endif
1638:
1.1 ryo 1639: #ifdef AQ_EVENT_COUNTERS
1640: AQ_EVCNT_DETACH(sc, uprc);
1641: AQ_EVCNT_DETACH(sc, mprc);
1642: AQ_EVCNT_DETACH(sc, bprc);
1643: AQ_EVCNT_DETACH(sc, erpt);
1644: AQ_EVCNT_DETACH(sc, uptc);
1645: AQ_EVCNT_DETACH(sc, mptc);
1646: AQ_EVCNT_DETACH(sc, bptc);
1647: AQ_EVCNT_DETACH(sc, erpr);
1648: AQ_EVCNT_DETACH(sc, mbtc);
1649: AQ_EVCNT_DETACH(sc, bbtc);
1650: AQ_EVCNT_DETACH(sc, mbrc);
1651: AQ_EVCNT_DETACH(sc, bbrc);
1652: AQ_EVCNT_DETACH(sc, ubrc);
1653: AQ_EVCNT_DETACH(sc, ubtc);
1654: AQ_EVCNT_DETACH(sc, ptc);
1655: AQ_EVCNT_DETACH(sc, prc);
1656: AQ_EVCNT_DETACH(sc, dpc);
1657: AQ_EVCNT_DETACH(sc, cprc);
1658: #endif
1659:
1.41 ryo 1660: if (sc->sc_ethercom.ec_ifmedia != NULL) {
1661: ifmedia_fini(&sc->sc_media);
1662: sc->sc_ethercom.ec_ifmedia = NULL;
1663: }
1.7 thorpej 1664:
1.4 ryo 1665: mutex_destroy(&sc->sc_mpi_mutex);
1.1 ryo 1666: mutex_destroy(&sc->sc_mutex);
1.41 ryo 1667: sc->sc_dev = NULL;
1.1 ryo 1668:
1669: return 0;
1670: }
1671:
1672: static int
1673: aq_establish_intr(struct aq_softc *sc, int intno, kcpuset_t *affinity,
1674: int (*func)(void *), void *arg, const char *xname)
1675: {
1676: char intrbuf[PCI_INTRSTR_LEN];
1677: pci_chipset_tag_t pc = sc->sc_pc;
1678: void *vih;
1679: const char *intrstr = NULL;
1680:
1681: intrstr = pci_intr_string(pc, sc->sc_intrs[intno], intrbuf,
1682: sizeof(intrbuf));
1683:
1684: pci_intr_setattr(pc, &sc->sc_intrs[intno], PCI_INTR_MPSAFE, true);
1685:
1686: vih = pci_intr_establish_xname(pc, sc->sc_intrs[intno],
1687: IPL_NET, func, arg, xname);
1688: if (vih == NULL) {
1689: aprint_error_dev(sc->sc_dev,
1690: "unable to establish MSI-X%s%s for %s\n",
1691: intrstr ? " at " : "",
1692: intrstr ? intrstr : "", xname);
1693: return EIO;
1694: }
1695: sc->sc_ihs[intno] = vih;
1696:
1697: if (affinity != NULL) {
1698: /* Round-robin affinity */
1699: kcpuset_zero(affinity);
1700: kcpuset_set(affinity, intno % ncpu);
1701: interrupt_distribute(vih, affinity, NULL);
1702: }
1703:
1704: return 0;
1705: }
1706:
1707: static int
1708: aq_establish_msix_intr(struct aq_softc *sc, bool txrx_independent,
1709: bool linkintr)
1710: {
1711: kcpuset_t *affinity;
1712: int error, intno, i;
1713: char intr_xname[INTRDEVNAMEBUF];
1714:
1715: kcpuset_create(&affinity, false);
1716:
1717: intno = 0;
1718:
1719: if (txrx_independent) {
1720: for (i = 0; i < sc->sc_nqueues; i++) {
1721: snprintf(intr_xname, sizeof(intr_xname), "%s RX%d",
1722: device_xname(sc->sc_dev), i);
1723: sc->sc_rx_irq[i] = intno;
1724: error = aq_establish_intr(sc, intno++, affinity,
1725: aq_rx_intr, &sc->sc_queue[i].rxring, intr_xname);
1726: if (error != 0)
1727: goto fail;
1728: }
1729: for (i = 0; i < sc->sc_nqueues; i++) {
1730: snprintf(intr_xname, sizeof(intr_xname), "%s TX%d",
1731: device_xname(sc->sc_dev), i);
1732: sc->sc_tx_irq[i] = intno;
1733: error = aq_establish_intr(sc, intno++, affinity,
1734: aq_tx_intr, &sc->sc_queue[i].txring, intr_xname);
1735: if (error != 0)
1736: goto fail;
1737: }
1738: } else {
1739: for (i = 0; i < sc->sc_nqueues; i++) {
1740: snprintf(intr_xname, sizeof(intr_xname), "%s TXRX%d",
1741: device_xname(sc->sc_dev), i);
1742: sc->sc_rx_irq[i] = intno;
1743: sc->sc_tx_irq[i] = intno;
1744: error = aq_establish_intr(sc, intno++, affinity,
1745: aq_txrx_intr, &sc->sc_queue[i], intr_xname);
1746: if (error != 0)
1747: goto fail;
1748: }
1749: }
1750:
1751: if (linkintr) {
1752: snprintf(intr_xname, sizeof(intr_xname), "%s LINK",
1753: device_xname(sc->sc_dev));
1754: sc->sc_linkstat_irq = intno;
1755: error = aq_establish_intr(sc, intno++, affinity,
1756: aq_link_intr, sc, intr_xname);
1757: if (error != 0)
1758: goto fail;
1759: }
1760:
1761: kcpuset_destroy(affinity);
1762: return 0;
1763:
1764: fail:
1765: for (i = 0; i < AQ_NINTR_MAX; i++) {
1766: if (sc->sc_ihs[i] != NULL) {
1767: pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
1768: sc->sc_ihs[i] = NULL;
1769: }
1770: }
1771:
1772: kcpuset_destroy(affinity);
1773: return ENOMEM;
1774: }
1775:
1776: static int
1777: aq_setup_msix(struct aq_softc *sc, struct pci_attach_args *pa, int nqueue,
1778: bool txrx_independent, bool linkintr)
1779: {
1780: int error, nintr;
1781:
1782: if (txrx_independent)
1783: nintr = nqueue * 2;
1784: else
1785: nintr = nqueue;
1786:
1787: if (linkintr)
1788: nintr++;
1789:
1790: error = pci_msix_alloc_exact(pa, &sc->sc_intrs, nintr);
1791: if (error != 0) {
1792: aprint_error_dev(sc->sc_dev,
1793: "failed to allocate MSI-X interrupts\n");
1794: goto fail;
1795: }
1796:
1797: error = aq_establish_msix_intr(sc, txrx_independent, linkintr);
1798: if (error == 0) {
1799: sc->sc_nintrs = nintr;
1800: } else {
1801: pci_intr_release(sc->sc_pc, sc->sc_intrs, nintr);
1802: sc->sc_nintrs = 0;
1803: }
1804: fail:
1805: return error;
1806:
1807: }
1808:
1809: static int
1810: aq_setup_legacy(struct aq_softc *sc, struct pci_attach_args *pa,
1811: pci_intr_type_t inttype)
1812: {
1813: int counts[PCI_INTR_TYPE_SIZE];
1814: int error, nintr;
1815:
1816: nintr = 1;
1817:
1818: memset(counts, 0, sizeof(counts));
1819: counts[inttype] = nintr;
1820:
1821: error = pci_intr_alloc(pa, &sc->sc_intrs, counts, inttype);
1822: if (error != 0) {
1823: aprint_error_dev(sc->sc_dev,
1824: "failed to allocate%s interrupts\n",
1825: (inttype == PCI_INTR_TYPE_MSI) ? " MSI" : "");
1826: return error;
1827: }
1828: error = aq_establish_intr(sc, 0, NULL, aq_legacy_intr, sc,
1829: device_xname(sc->sc_dev));
1830: if (error == 0) {
1831: sc->sc_nintrs = nintr;
1832: } else {
1833: pci_intr_release(sc->sc_pc, sc->sc_intrs, nintr);
1834: sc->sc_nintrs = 0;
1835: }
1836: return error;
1837: }
1838:
1839: static void
1840: global_software_reset(struct aq_softc *sc)
1841: {
1842: uint32_t v;
1843:
1844: AQ_WRITE_REG_BIT(sc, RX_SYSCONTROL_REG, RX_SYSCONTROL_RESET_DIS, 0);
1845: AQ_WRITE_REG_BIT(sc, TX_SYSCONTROL_REG, TX_SYSCONTROL_RESET_DIS, 0);
1846: AQ_WRITE_REG_BIT(sc, FW_MPI_RESETCTRL_REG,
1847: FW_MPI_RESETCTRL_RESET_DIS, 0);
1848:
1849: v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG);
1850: v &= ~AQ_FW_SOFTRESET_DIS;
1851: v |= AQ_FW_SOFTRESET_RESET;
1852: AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v);
1853: }
1854:
1855: static int
1856: mac_soft_reset_rbl(struct aq_softc *sc, aq_fw_bootloader_mode_t *mode)
1857: {
1858: int timo;
1859:
1860: aprint_debug_dev(sc->sc_dev, "RBL> MAC reset STARTED!\n");
1861:
1862: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1);
1863: AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1);
1864: AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0);
1865:
1866: /* MAC FW will reload PHY FW if 1E.1000.3 was cleaned - #undone */
1867: AQ_WRITE_REG(sc, FW_BOOT_EXIT_CODE_REG, RBL_STATUS_DEAD);
1868:
1869: global_software_reset(sc);
1870:
1871: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e0);
1872:
1873: /* Wait for RBL to finish boot process. */
1874: #define RBL_TIMEOUT_MS 10000
1875: uint16_t rbl_status;
1876: for (timo = RBL_TIMEOUT_MS; timo > 0; timo--) {
1877: rbl_status = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG) & 0xffff;
1878: if (rbl_status != 0 && rbl_status != RBL_STATUS_DEAD)
1879: break;
1880: msec_delay(1);
1881: }
1882: if (timo <= 0) {
1883: aprint_error_dev(sc->sc_dev,
1884: "RBL> RBL restart failed: timeout\n");
1885: return EBUSY;
1886: }
1887: switch (rbl_status) {
1888: case RBL_STATUS_SUCCESS:
1889: if (mode != NULL)
1890: *mode = FW_BOOT_MODE_RBL_FLASH;
1891: aprint_debug_dev(sc->sc_dev, "RBL> reset complete! [Flash]\n");
1892: break;
1893: case RBL_STATUS_HOST_BOOT:
1894: if (mode != NULL)
1895: *mode = FW_BOOT_MODE_RBL_HOST_BOOTLOAD;
1896: aprint_debug_dev(sc->sc_dev,
1897: "RBL> reset complete! [Host Bootload]\n");
1898: break;
1899: case RBL_STATUS_FAILURE:
1900: default:
1901: aprint_error_dev(sc->sc_dev,
1902: "unknown RBL status 0x%x\n", rbl_status);
1903: return EBUSY;
1904: }
1905:
1906: return 0;
1907: }
1908:
1909: static int
1910: mac_soft_reset_flb(struct aq_softc *sc)
1911: {
1912: uint32_t v;
1913: int timo;
1914:
1915: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1);
1916: /*
1917: * Let Felicity hardware to complete SMBUS transaction before
1918: * Global software reset.
1919: */
1920: msec_delay(50);
1921:
1922: /*
1923: * If SPI burst transaction was interrupted(before running the script),
1924: * global software reset may not clear SPI interface.
1925: * Clean it up manually before global reset.
1926: */
1927: AQ_WRITE_REG(sc, AQ_GLB_NVR_PROVISIONING2_REG, 0x00a0);
1928: AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x009f);
1929: AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x809f);
1930: msec_delay(50);
1931:
1932: v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG);
1933: v &= ~AQ_FW_SOFTRESET_DIS;
1934: v |= AQ_FW_SOFTRESET_RESET;
1935: AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v);
1936:
1937: /* Kickstart. */
1938: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0);
1939: AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0);
1940: if (!sc->sc_fast_start_enabled)
1941: AQ_WRITE_REG(sc, AQ_GLB_GENERAL_PROVISIONING9_REG, 1);
1942:
1943: /*
1944: * For the case SPI burst transaction was interrupted (by MCP reset
1945: * above), wait until it is completed by hardware.
1946: */
1947: msec_delay(50);
1948:
1949: /* MAC Kickstart */
1950: if (!sc->sc_fast_start_enabled) {
1951: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x180e0);
1952:
1953: uint32_t flb_status;
1954: for (timo = 0; timo < 1000; timo++) {
1955: flb_status = AQ_READ_REG(sc,
1956: FW_MPI_DAISY_CHAIN_STATUS_REG) & 0x10;
1957: if (flb_status != 0)
1958: break;
1959: msec_delay(1);
1960: }
1961: if (flb_status == 0) {
1962: aprint_error_dev(sc->sc_dev,
1963: "FLB> MAC kickstart failed: timed out\n");
1964: return ETIMEDOUT;
1965: }
1966: aprint_debug_dev(sc->sc_dev,
1967: "FLB> MAC kickstart done, %d ms\n", timo);
1968: /* FW reset */
1969: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0);
1970: /*
1971: * Let Felicity hardware complete SMBUS transaction before
1972: * Global software reset.
1973: */
1974: msec_delay(50);
1975: sc->sc_fast_start_enabled = true;
1976: }
1977: AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1);
1978:
1979: /* PHY Kickstart: #undone */
1980: global_software_reset(sc);
1981:
1982: for (timo = 0; timo < 1000; timo++) {
1983: if (AQ_READ_REG(sc, AQ_FW_VERSION_REG) != 0)
1984: break;
1985: msec_delay(10);
1986: }
1987: if (timo >= 1000) {
1988: aprint_error_dev(sc->sc_dev, "FLB> Global Soft Reset failed\n");
1989: return ETIMEDOUT;
1990: }
1991: aprint_debug_dev(sc->sc_dev, "FLB> F/W restart: %d ms\n", timo * 10);
1992: return 0;
1993:
1994: }
1995:
1996: static int
1997: mac_soft_reset(struct aq_softc *sc, aq_fw_bootloader_mode_t *mode)
1998: {
1999: if (sc->sc_rbl_enabled)
2000: return mac_soft_reset_rbl(sc, mode);
2001:
2002: if (mode != NULL)
2003: *mode = FW_BOOT_MODE_FLB;
2004: return mac_soft_reset_flb(sc);
2005: }
2006:
2007: static int
2008: aq_fw_read_version(struct aq_softc *sc)
2009: {
2010: int i, error = EBUSY;
2011: #define MAC_FW_START_TIMEOUT_MS 10000
2012: for (i = 0; i < MAC_FW_START_TIMEOUT_MS; i++) {
2013: sc->sc_fw_version = AQ_READ_REG(sc, AQ_FW_VERSION_REG);
2014: if (sc->sc_fw_version != 0) {
2015: error = 0;
2016: break;
2017: }
2018: delay(1000);
2019: }
2020: return error;
2021: }
2022:
2023: static int
2024: aq_fw_reset(struct aq_softc *sc)
2025: {
2026: uint32_t ver, v, bootExitCode;
2027: int i, error;
2028:
2029: ver = AQ_READ_REG(sc, AQ_FW_VERSION_REG);
2030:
2031: for (i = 1000; i > 0; i--) {
2032: v = AQ_READ_REG(sc, FW_MPI_DAISY_CHAIN_STATUS_REG);
2033: bootExitCode = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG);
2034: if (v != 0x06000000 || bootExitCode != 0)
2035: break;
2036: }
2037: if (i <= 0) {
2038: aprint_error_dev(sc->sc_dev,
2039: "F/W reset failed. Neither RBL nor FLB started\n");
2040: return ETIMEDOUT;
2041: }
2042: sc->sc_rbl_enabled = (bootExitCode != 0);
2043:
2044: /*
2045: * Having FW version 0 is an indicator that cold start
2046: * is in progress. This means two things:
2047: * 1) Driver have to wait for FW/HW to finish boot (500ms giveup)
2048: * 2) Driver may skip reset sequence and save time.
2049: */
2050: if (sc->sc_fast_start_enabled && (ver != 0)) {
2051: error = aq_fw_read_version(sc);
2052: /* Skip reset as it just completed */
2053: if (error == 0)
2054: return 0;
2055: }
2056:
2057: aq_fw_bootloader_mode_t mode = FW_BOOT_MODE_UNKNOWN;
2058: error = mac_soft_reset(sc, &mode);
2059: if (error != 0) {
2060: aprint_error_dev(sc->sc_dev, "MAC reset failed: %d\n", error);
2061: return error;
2062: }
2063:
2064: switch (mode) {
2065: case FW_BOOT_MODE_FLB:
2066: aprint_debug_dev(sc->sc_dev,
2067: "FLB> F/W successfully loaded from flash.\n");
2068: sc->sc_flash_present = true;
2069: return aq_fw_read_version(sc);
2070: case FW_BOOT_MODE_RBL_FLASH:
2071: aprint_debug_dev(sc->sc_dev,
2072: "RBL> F/W loaded from flash. Host Bootload disabled.\n");
2073: sc->sc_flash_present = true;
2074: return aq_fw_read_version(sc);
2075: case FW_BOOT_MODE_UNKNOWN:
2076: aprint_error_dev(sc->sc_dev,
2077: "F/W bootload error: unknown bootloader type\n");
2078: return ENOTSUP;
2079: case FW_BOOT_MODE_RBL_HOST_BOOTLOAD:
2080: aprint_debug_dev(sc->sc_dev, "RBL> Host Bootload mode\n");
2081: break;
2082: }
2083:
2084: /*
2085: * XXX: TODO: add support Host Boot
2086: */
2087: aprint_error_dev(sc->sc_dev,
2088: "RBL> F/W Host Bootload not implemented\n");
2089: return ENOTSUP;
2090: }
2091:
2092: static int
2093: aq_hw_reset(struct aq_softc *sc)
2094: {
2095: int error;
2096:
2097: /* disable irq */
2098: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS, 0);
2099:
2100: /* apply */
2101: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_IRQ, 1);
2102:
2103: /* wait ack 10 times by 1ms */
2104: WAIT_FOR(
2105: (AQ_READ_REG(sc, AQ_INTR_CTRL_REG) & AQ_INTR_CTRL_RESET_IRQ) == 0,
2106: 1000, 10, &error);
2107: if (error != 0) {
2108: aprint_error_dev(sc->sc_dev,
2109: "atlantic: IRQ reset failed: %d\n", error);
2110: return error;
2111: }
2112:
2113: return sc->sc_fw_ops->reset(sc);
2114: }
2115:
2116: static int
2117: aq_hw_init_ucp(struct aq_softc *sc)
2118: {
2119: int timo;
2120:
2121: if (FW_VERSION_MAJOR(sc) == 1) {
1.30 ryo 2122: if (AQ_READ_REG(sc, FW1X_MPI_INIT2_REG) == 0)
2123: AQ_WRITE_REG(sc, FW1X_MPI_INIT2_REG, 0xfefefefe);
1.1 ryo 2124: AQ_WRITE_REG(sc, FW1X_MPI_INIT1_REG, 0);
2125: }
2126:
1.30 ryo 2127: /* Wait a maximum of 10sec. It usually takes about 5sec. */
2128: for (timo = 10000; timo > 0; timo--) {
1.1 ryo 2129: sc->sc_mbox_addr = AQ_READ_REG(sc, FW_MPI_MBOX_ADDR_REG);
2130: if (sc->sc_mbox_addr != 0)
2131: break;
2132: delay(1000);
2133: }
1.30 ryo 2134: if (sc->sc_mbox_addr == 0) {
2135: aprint_error_dev(sc->sc_dev, "cannot get mbox addr\n");
2136: return ETIMEDOUT;
2137: }
1.1 ryo 2138:
2139: #define AQ_FW_MIN_VERSION 0x01050006
2140: #define AQ_FW_MIN_VERSION_STR "1.5.6"
2141: if (sc->sc_fw_version < AQ_FW_MIN_VERSION) {
2142: aprint_error_dev(sc->sc_dev,
2143: "atlantic: wrong FW version: " AQ_FW_MIN_VERSION_STR
2144: " or later required, this is %d.%d.%d\n",
2145: FW_VERSION_MAJOR(sc),
2146: FW_VERSION_MINOR(sc),
2147: FW_VERSION_BUILD(sc));
2148: return ENOTSUP;
2149: }
2150:
2151: return 0;
2152: }
2153:
2154: static int
2155: aq_fw_version_init(struct aq_softc *sc)
2156: {
2157: int error = 0;
2158: char fw_vers[sizeof("F/W version xxxxx.xxxxx.xxxxx")];
2159:
2160: if (FW_VERSION_MAJOR(sc) == 1) {
2161: sc->sc_fw_ops = &aq_fw1x_ops;
2162: } else if ((FW_VERSION_MAJOR(sc) == 2) || (FW_VERSION_MAJOR(sc) == 3)) {
2163: sc->sc_fw_ops = &aq_fw2x_ops;
2164: } else {
2165: aprint_error_dev(sc->sc_dev,
2166: "Unsupported F/W version %d.%d.%d\n",
2167: FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc),
2168: FW_VERSION_BUILD(sc));
2169: return ENOTSUP;
2170: }
2171: snprintf(fw_vers, sizeof(fw_vers), "F/W version %d.%d.%d",
2172: FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc), FW_VERSION_BUILD(sc));
2173:
2174: /* detect revision */
2175: uint32_t hwrev = AQ_READ_REG(sc, AQ_HW_REVISION_REG);
2176: switch (hwrev & 0x0000000f) {
2177: case 0x01:
2178: aprint_normal_dev(sc->sc_dev, "Atlantic revision A0, %s\n",
2179: fw_vers);
2180: sc->sc_features |= FEATURES_REV_A0 |
2181: FEATURES_MPI_AQ | FEATURES_MIPS;
1.23 ryo 2182: sc->sc_max_mtu = AQ_JUMBO_MTU_REV_A;
1.1 ryo 2183: break;
2184: case 0x02:
2185: aprint_normal_dev(sc->sc_dev, "Atlantic revision B0, %s\n",
2186: fw_vers);
2187: sc->sc_features |= FEATURES_REV_B0 |
2188: FEATURES_MPI_AQ | FEATURES_MIPS |
2189: FEATURES_TPO2 | FEATURES_RPF2;
1.23 ryo 2190: sc->sc_max_mtu = AQ_JUMBO_MTU_REV_B;
1.1 ryo 2191: break;
2192: case 0x0A:
2193: aprint_normal_dev(sc->sc_dev, "Atlantic revision B1, %s\n",
2194: fw_vers);
2195: sc->sc_features |= FEATURES_REV_B1 |
2196: FEATURES_MPI_AQ | FEATURES_MIPS |
2197: FEATURES_TPO2 | FEATURES_RPF2;
1.23 ryo 2198: sc->sc_max_mtu = AQ_JUMBO_MTU_REV_B;
1.1 ryo 2199: break;
2200: default:
2201: aprint_error_dev(sc->sc_dev,
2202: "Unknown revision (0x%08x)\n", hwrev);
1.23 ryo 2203: sc->sc_features = 0;
2204: sc->sc_max_mtu = ETHERMTU;
1.1 ryo 2205: error = ENOTSUP;
2206: break;
2207: }
2208: return error;
2209: }
2210:
2211: static int
2212: fw1x_reset(struct aq_softc *sc)
2213: {
2214: struct aq_mailbox_header mbox;
2215: const int retryCount = 1000;
2216: uint32_t tid0;
2217: int i;
2218:
2219: tid0 = ~0; /*< Initial value of MBOX transactionId. */
2220:
2221: for (i = 0; i < retryCount; ++i) {
2222: /*
2223: * Read the beginning of Statistics structure to capture
2224: * the Transaction ID.
2225: */
2226: aq_fw_downld_dwords(sc, sc->sc_mbox_addr,
2227: (uint32_t *)&mbox, sizeof(mbox) / sizeof(uint32_t));
2228:
2229: /* Successfully read the stats. */
2230: if (tid0 == ~0U) {
2231: /* We have read the initial value. */
2232: tid0 = mbox.transaction_id;
2233: continue;
2234: } else if (mbox.transaction_id != tid0) {
2235: /*
2236: * Compare transaction ID to initial value.
2237: * If it's different means f/w is alive.
2238: * We're done.
2239: */
2240: return 0;
2241: }
2242:
2243: /*
2244: * Transaction ID value haven't changed since last time.
2245: * Try reading the stats again.
2246: */
2247: delay(10);
2248: }
2249: aprint_error_dev(sc->sc_dev, "F/W 1.x reset finalize timeout\n");
2250: return EBUSY;
2251: }
2252:
2253: static int
2254: fw1x_set_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t mode,
2255: aq_link_speed_t speed, aq_link_fc_t fc, aq_link_eee_t eee)
2256: {
2257: uint32_t mpictrl = 0;
2258: uint32_t mpispeed = 0;
2259:
2260: if (speed & AQ_LINK_10G)
2261: mpispeed |= FW1X_CTRL_10G;
2262: if (speed & AQ_LINK_5G)
2263: mpispeed |= (FW1X_CTRL_5G | FW1X_CTRL_5GSR);
2264: if (speed & AQ_LINK_2G5)
2265: mpispeed |= FW1X_CTRL_2G5;
2266: if (speed & AQ_LINK_1G)
2267: mpispeed |= FW1X_CTRL_1G;
2268: if (speed & AQ_LINK_100M)
2269: mpispeed |= FW1X_CTRL_100M;
2270:
2271: mpictrl |= __SHIFTIN(mode, FW1X_MPI_STATE_MODE);
2272: mpictrl |= __SHIFTIN(mpispeed, FW1X_MPI_STATE_SPEED);
2273: AQ_WRITE_REG(sc, FW1X_MPI_CONTROL_REG, mpictrl);
2274: return 0;
2275: }
2276:
2277: static int
2278: fw1x_get_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t *modep,
2279: aq_link_speed_t *speedp, aq_link_fc_t *fcp, aq_link_eee_t *eeep)
2280: {
2281: uint32_t mpistate, mpi_speed;
2282: aq_link_speed_t speed = AQ_LINK_NONE;
2283:
2284: mpistate = AQ_READ_REG(sc, FW1X_MPI_STATE_REG);
2285:
2286: if (modep != NULL)
2287: *modep = __SHIFTOUT(mpistate, FW1X_MPI_STATE_MODE);
2288:
2289: mpi_speed = __SHIFTOUT(mpistate, FW1X_MPI_STATE_SPEED);
2290: if (mpi_speed & FW1X_CTRL_10G)
2291: speed = AQ_LINK_10G;
2292: else if (mpi_speed & (FW1X_CTRL_5G|FW1X_CTRL_5GSR))
2293: speed = AQ_LINK_5G;
2294: else if (mpi_speed & FW1X_CTRL_2G5)
2295: speed = AQ_LINK_2G5;
2296: else if (mpi_speed & FW1X_CTRL_1G)
2297: speed = AQ_LINK_1G;
2298: else if (mpi_speed & FW1X_CTRL_100M)
2299: speed = AQ_LINK_100M;
2300:
2301: if (speedp != NULL)
2302: *speedp = speed;
2303:
2304: if (fcp != NULL)
2305: *fcp = AQ_FC_NONE;
2306:
2307: if (eeep != NULL)
2308: *eeep = AQ_EEE_DISABLE;
2309:
2310: return 0;
2311: }
2312:
2313: static int
2314: fw1x_get_stats(struct aq_softc *sc, aq_hw_stats_s_t *stats)
2315: {
2316: int error;
2317:
2318: error = aq_fw_downld_dwords(sc,
2319: sc->sc_mbox_addr + offsetof(fw1x_mailbox_t, msm), (uint32_t *)stats,
2320: sizeof(aq_hw_stats_s_t) / sizeof(uint32_t));
2321: if (error < 0) {
2322: device_printf(sc->sc_dev,
2323: "fw1x> download statistics data FAILED, error %d", error);
2324: return error;
2325: }
2326:
2327: stats->dpc = AQ_READ_REG(sc, RX_DMA_DROP_PKT_CNT_REG);
2328: stats->cprc = AQ_READ_REG(sc, RX_DMA_COALESCED_PKT_CNT_REG);
2329: return 0;
2330: }
2331:
2332: static int
2333: fw2x_reset(struct aq_softc *sc)
2334: {
2335: fw2x_capabilities_t caps = { 0 };
2336: int error;
2337:
2338: error = aq_fw_downld_dwords(sc,
2339: sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, caps),
2340: (uint32_t *)&caps, sizeof caps / sizeof(uint32_t));
2341: if (error != 0) {
2342: aprint_error_dev(sc->sc_dev,
2343: "fw2x> can't get F/W capabilities mask, error %d\n",
2344: error);
2345: return error;
2346: }
2347: sc->sc_fw_caps = caps.caps_lo | ((uint64_t)caps.caps_hi << 32);
2348:
2349: char buf[256];
2350: snprintb(buf, sizeof(buf), FW2X_SNPRINTB, sc->sc_fw_caps);
2351: aprint_verbose_dev(sc->sc_dev, "fw2x> F/W capabilities=%s\n", buf);
2352:
2353: return 0;
2354: }
2355:
2356: static int
2357: fw2x_set_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t mode,
2358: aq_link_speed_t speed, aq_link_fc_t fc, aq_link_eee_t eee)
2359: {
1.4 ryo 2360: uint64_t mpi_ctrl;
2361: int error = 0;
2362:
2363: AQ_MPI_LOCK(sc);
2364:
2365: mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);
1.1 ryo 2366:
2367: switch (mode) {
2368: case MPI_INIT:
2369: mpi_ctrl &= ~FW2X_CTRL_RATE_MASK;
2370: if (speed & AQ_LINK_10G)
2371: mpi_ctrl |= FW2X_CTRL_RATE_10G;
2372: if (speed & AQ_LINK_5G)
2373: mpi_ctrl |= FW2X_CTRL_RATE_5G;
2374: if (speed & AQ_LINK_2G5)
2375: mpi_ctrl |= FW2X_CTRL_RATE_2G5;
2376: if (speed & AQ_LINK_1G)
2377: mpi_ctrl |= FW2X_CTRL_RATE_1G;
2378: if (speed & AQ_LINK_100M)
2379: mpi_ctrl |= FW2X_CTRL_RATE_100M;
2380:
2381: mpi_ctrl &= ~FW2X_CTRL_LINK_DROP;
2382:
2383: mpi_ctrl &= ~FW2X_CTRL_EEE_MASK;
2384: if (eee == AQ_EEE_ENABLE)
2385: mpi_ctrl |= FW2X_CTRL_EEE_MASK;
2386:
2387: mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE);
2388: if (fc & AQ_FC_RX)
2389: mpi_ctrl |= FW2X_CTRL_PAUSE;
2390: if (fc & AQ_FC_TX)
2391: mpi_ctrl |= FW2X_CTRL_ASYMMETRIC_PAUSE;
2392: break;
2393: case MPI_DEINIT:
2394: mpi_ctrl &= ~(FW2X_CTRL_RATE_MASK | FW2X_CTRL_EEE_MASK);
2395: mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE);
2396: break;
2397: default:
2398: device_printf(sc->sc_dev, "fw2x> unknown MPI state %d\n", mode);
1.4 ryo 2399: error = EINVAL;
2400: goto failure;
1.1 ryo 2401: }
1.4 ryo 2402: AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl);
1.1 ryo 2403:
1.4 ryo 2404: failure:
2405: AQ_MPI_UNLOCK(sc);
2406: return error;
1.1 ryo 2407: }
2408:
2409: static int
2410: fw2x_get_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t *modep,
2411: aq_link_speed_t *speedp, aq_link_fc_t *fcp, aq_link_eee_t *eeep)
2412: {
2413: uint64_t mpi_state = AQ_READ64_REG(sc, FW2X_MPI_STATE_REG);
2414:
2415: if (modep != NULL) {
2416: uint64_t mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);
2417: if (mpi_ctrl & FW2X_CTRL_RATE_MASK)
2418: *modep = MPI_INIT;
2419: else
2420: *modep = MPI_DEINIT;
2421: }
2422:
2423: aq_link_speed_t speed = AQ_LINK_NONE;
2424: if (mpi_state & FW2X_CTRL_RATE_10G)
2425: speed = AQ_LINK_10G;
2426: else if (mpi_state & FW2X_CTRL_RATE_5G)
2427: speed = AQ_LINK_5G;
2428: else if (mpi_state & FW2X_CTRL_RATE_2G5)
2429: speed = AQ_LINK_2G5;
2430: else if (mpi_state & FW2X_CTRL_RATE_1G)
2431: speed = AQ_LINK_1G;
2432: else if (mpi_state & FW2X_CTRL_RATE_100M)
2433: speed = AQ_LINK_100M;
2434:
2435: if (speedp != NULL)
2436: *speedp = speed;
2437:
2438: aq_link_fc_t fc = AQ_FC_NONE;
2439: if (mpi_state & FW2X_CTRL_PAUSE)
2440: fc |= AQ_FC_RX;
2441: if (mpi_state & FW2X_CTRL_ASYMMETRIC_PAUSE)
2442: fc |= AQ_FC_TX;
2443: if (fcp != NULL)
2444: *fcp = fc;
2445:
2446: /* XXX: TODO: EEE */
2447: if (eeep != NULL)
2448: *eeep = AQ_EEE_DISABLE;
2449:
2450: return 0;
2451: }
2452:
2453: static int
2454: toggle_mpi_ctrl_and_wait(struct aq_softc *sc, uint64_t mask,
2455: uint32_t timeout_ms, uint32_t try_count)
2456: {
2457: uint64_t mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);
2458: uint64_t mpi_state = AQ_READ64_REG(sc, FW2X_MPI_STATE_REG);
2459: int error;
2460:
2461: /* First, check that control and state values are consistent */
2462: if ((mpi_ctrl & mask) != (mpi_state & mask)) {
2463: device_printf(sc->sc_dev,
2464: "fw2x> MPI control (%#llx) and state (%#llx)"
2465: " are not consistent for mask %#llx!\n",
2466: (unsigned long long)mpi_ctrl, (unsigned long long)mpi_state,
2467: (unsigned long long)mask);
2468: return EINVAL;
2469: }
2470:
2471: /* Invert bits (toggle) in control register */
2472: mpi_ctrl ^= mask;
2473: AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl);
2474:
2475: /* Clear all bits except masked */
2476: mpi_ctrl &= mask;
2477:
2478: /* Wait for FW reflecting change in state register */
2479: WAIT_FOR((AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG) & mask) == mpi_ctrl,
2480: 1000 * timeout_ms, try_count, &error);
2481: if (error != 0) {
2482: device_printf(sc->sc_dev,
2483: "f/w2x> timeout while waiting for response"
2484: " in state register for bit %#llx!",
2485: (unsigned long long)mask);
2486: return error;
2487: }
2488: return 0;
2489: }
2490:
2491: static int
2492: fw2x_get_stats(struct aq_softc *sc, aq_hw_stats_s_t *stats)
2493: {
2494: int error;
2495:
1.4 ryo 2496: AQ_MPI_LOCK(sc);
1.1 ryo 2497: /* Say to F/W to update the statistics */
2498: error = toggle_mpi_ctrl_and_wait(sc, FW2X_CTRL_STATISTICS, 1, 25);
2499: if (error != 0) {
2500: device_printf(sc->sc_dev,
2501: "fw2x> statistics update error %d\n", error);
1.4 ryo 2502: goto failure;
1.1 ryo 2503: }
2504:
2505: CTASSERT(sizeof(fw2x_msm_statistics_t) <= sizeof(struct aq_hw_stats_s));
2506: error = aq_fw_downld_dwords(sc,
2507: sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, msm), (uint32_t *)stats,
2508: sizeof(fw2x_msm_statistics_t) / sizeof(uint32_t));
2509: if (error != 0) {
2510: device_printf(sc->sc_dev,
2511: "fw2x> download statistics data FAILED, error %d", error);
1.4 ryo 2512: goto failure;
1.1 ryo 2513: }
2514: stats->dpc = AQ_READ_REG(sc, RX_DMA_DROP_PKT_CNT_REG);
2515: stats->cprc = AQ_READ_REG(sc, RX_DMA_COALESCED_PKT_CNT_REG);
2516:
1.4 ryo 2517: failure:
2518: AQ_MPI_UNLOCK(sc);
2519: return error;
2520: }
2521:
2522: #if NSYSMON_ENVSYS > 0
2523: static int
2524: fw2x_get_temperature(struct aq_softc *sc, uint32_t *temp)
2525: {
2526: int error;
2527: uint32_t value, celsius;
2528:
2529: AQ_MPI_LOCK(sc);
2530:
2531: /* Say to F/W to update the temperature */
2532: error = toggle_mpi_ctrl_and_wait(sc, FW2X_CTRL_TEMPERATURE, 1, 25);
2533: if (error != 0)
2534: goto failure;
2535:
2536: error = aq_fw_downld_dwords(sc,
2537: sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, phy_info2),
2538: &value, sizeof(value) / sizeof(uint32_t));
2539: if (error != 0)
2540: goto failure;
2541:
2542: /* 1/256 decrees C to microkelvin */
2543: celsius = __SHIFTOUT(value, PHYINFO2_TEMPERATURE);
2544: if (celsius == 0) {
2545: error = EIO;
2546: goto failure;
2547: }
2548: *temp = celsius * (1000000 / 256) + 273150000;
2549:
2550: failure:
2551: AQ_MPI_UNLOCK(sc);
1.1 ryo 2552: return 0;
2553: }
1.4 ryo 2554: #endif
1.1 ryo 2555:
2556: static int
2557: aq_fw_downld_dwords(struct aq_softc *sc, uint32_t addr, uint32_t *p,
2558: uint32_t cnt)
2559: {
2560: uint32_t v;
2561: int error = 0;
2562:
2563: WAIT_FOR(AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG) == 1, 1, 10000, &error);
2564: if (error != 0) {
2565: AQ_WRITE_REG(sc, AQ_FW_SEM_RAM_REG, 1);
2566: v = AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG);
2567: if (v == 0) {
2568: device_printf(sc->sc_dev,
2569: "%s:%d: timeout\n", __func__, __LINE__);
2570: return ETIMEDOUT;
2571: }
2572: }
2573:
2574: AQ_WRITE_REG(sc, AQ_FW_MBOX_ADDR_REG, addr);
2575:
2576: error = 0;
2577: for (; cnt > 0 && error == 0; cnt--) {
2578: /* execute mailbox interface */
2579: AQ_WRITE_REG_BIT(sc, AQ_FW_MBOX_CMD_REG,
2580: AQ_FW_MBOX_CMD_EXECUTE, 1);
2581: if (sc->sc_features & FEATURES_REV_B1) {
2582: WAIT_FOR(AQ_READ_REG(sc, AQ_FW_MBOX_ADDR_REG) != addr,
2583: 1, 1000, &error);
2584: } else {
2585: WAIT_FOR((AQ_READ_REG(sc, AQ_FW_MBOX_CMD_REG) &
2586: AQ_FW_MBOX_CMD_BUSY) == 0,
2587: 1, 1000, &error);
2588: }
2589: *p++ = AQ_READ_REG(sc, AQ_FW_MBOX_VAL_REG);
2590: addr += sizeof(uint32_t);
2591: }
2592: AQ_WRITE_REG(sc, AQ_FW_SEM_RAM_REG, 1);
2593:
2594: if (error != 0)
2595: device_printf(sc->sc_dev,
2596: "%s:%d: timeout\n", __func__, __LINE__);
2597:
2598: return error;
2599: }
2600:
2601: /* read my mac address */
2602: static int
2603: aq_get_mac_addr(struct aq_softc *sc)
2604: {
2605: uint32_t mac_addr[2];
2606: uint32_t efuse_shadow_addr;
2607: int err;
2608:
2609: efuse_shadow_addr = 0;
2610: if (FW_VERSION_MAJOR(sc) >= 2)
2611: efuse_shadow_addr = AQ_READ_REG(sc, FW2X_MPI_EFUSEADDR_REG);
2612: else
2613: efuse_shadow_addr = AQ_READ_REG(sc, FW1X_MPI_EFUSEADDR_REG);
2614:
2615: if (efuse_shadow_addr == 0) {
2616: aprint_error_dev(sc->sc_dev, "cannot get efuse addr\n");
2617: return ENXIO;
2618: }
2619:
2620: memset(mac_addr, 0, sizeof(mac_addr));
2621: err = aq_fw_downld_dwords(sc, efuse_shadow_addr + (40 * 4),
2622: mac_addr, __arraycount(mac_addr));
2623: if (err < 0)
2624: return err;
2625:
2626: if (mac_addr[0] == 0 && mac_addr[1] == 0) {
2627: aprint_error_dev(sc->sc_dev, "mac address not found\n");
2628: return ENXIO;
2629: }
2630:
1.18 ryo 2631: mac_addr[0] = htobe32(mac_addr[0]);
2632: mac_addr[1] = htobe32(mac_addr[1]);
1.1 ryo 2633:
2634: memcpy(sc->sc_enaddr.ether_addr_octet,
2635: (uint8_t *)mac_addr, ETHER_ADDR_LEN);
2636: aprint_normal_dev(sc->sc_dev, "Etheraddr: %s\n",
2637: ether_sprintf(sc->sc_enaddr.ether_addr_octet));
2638:
2639: return 0;
2640: }
2641:
2642: /* set multicast filter. index 0 for own address */
2643: static int
2644: aq_set_mac_addr(struct aq_softc *sc, int index, uint8_t *enaddr)
2645: {
2646: uint32_t h, l;
2647:
2648: if (index >= AQ_HW_MAC_NUM)
2649: return EINVAL;
2650:
2651: if (enaddr == NULL) {
2652: /* disable */
2653: AQ_WRITE_REG_BIT(sc,
2654: RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0);
2655: return 0;
2656: }
2657:
2658: h = (enaddr[0] << 8) | (enaddr[1]);
1.5 msaitoh 2659: l = ((uint32_t)enaddr[2] << 24) | (enaddr[3] << 16) |
1.1 ryo 2660: (enaddr[4] << 8) | (enaddr[5]);
2661:
2662: /* disable, set, and enable */
2663: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0);
2664: AQ_WRITE_REG(sc, RPF_L2UC_LSW_REG(index), l);
2665: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index),
2666: RPF_L2UC_MSW_MACADDR_HI, h);
2667: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_ACTION, 1);
2668: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 1);
2669:
2670: return 0;
2671: }
2672:
2673: static int
2674: aq_set_capability(struct aq_softc *sc)
2675: {
1.32 skrll 2676: struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
1.1 ryo 2677: int ip4csum_tx =
2678: ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) == 0) ? 0 : 1;
2679: int ip4csum_rx =
2680: ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) ? 0 : 1;
2681: int l4csum_tx = ((ifp->if_capenable &
2682: (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx |
2683: IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) == 0) ? 0 : 1;
2684: int l4csum_rx =
2685: ((ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
2686: IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) == 0) ? 0 : 1;
2687: uint32_t lso =
2688: ((ifp->if_capenable & (IFCAP_TSOv4 | IFCAP_TSOv6)) == 0) ?
2689: 0 : 0xffffffff;
2690: uint32_t lro = ((ifp->if_capenable & IFCAP_LRO) == 0) ?
2691: 0 : 0xffffffff;
2692: uint32_t i, v;
2693:
2694: /* TX checksums offloads*/
2695: AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_IP4CSUM_EN, ip4csum_tx);
2696: AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_L4CSUM_EN, l4csum_tx);
2697:
2698: /* RX checksums offloads*/
2699: AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_IP4CSUM_EN, ip4csum_rx);
2700: AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_L4CSUM_EN, l4csum_rx);
2701:
2702: /* LSO offloads*/
2703: AQ_WRITE_REG(sc, TDM_LSO_EN_REG, lso);
2704:
2705: #define AQ_B0_LRO_RXD_MAX 16
2706: v = (8 < AQ_B0_LRO_RXD_MAX) ? 3 :
2707: (4 < AQ_B0_LRO_RXD_MAX) ? 2 :
2708: (2 < AQ_B0_LRO_RXD_MAX) ? 1 : 0;
2709: for (i = 0; i < AQ_RINGS_NUM; i++) {
2710: AQ_WRITE_REG_BIT(sc, RPO_LRO_LDES_MAX_REG(i),
2711: RPO_LRO_LDES_MAX_MASK(i), v);
2712: }
2713:
2714: AQ_WRITE_REG_BIT(sc, RPO_LRO_TB_DIV_REG, RPO_LRO_TB_DIV, 0x61a);
2715: AQ_WRITE_REG_BIT(sc, RPO_LRO_INACTIVE_IVAL_REG,
2716: RPO_LRO_INACTIVE_IVAL, 0);
2717: /*
2718: * the LRO timebase divider is 5 uS (0x61a),
2719: * to get a maximum coalescing interval of 250 uS,
2720: * we need to multiply by 50(0x32) to get
2721: * the default value 250 uS
2722: */
2723: AQ_WRITE_REG_BIT(sc, RPO_LRO_MAX_COALESCING_IVAL_REG,
2724: RPO_LRO_MAX_COALESCING_IVAL, 50);
2725: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2726: RPO_LRO_CONF_QSESSION_LIMIT, 1);
2727: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2728: RPO_LRO_CONF_TOTAL_DESC_LIMIT, 2);
2729: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2730: RPO_LRO_CONF_PATCHOPTIMIZATION_EN, 0);
2731: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2732: RPO_LRO_CONF_MIN_PAYLOAD_OF_FIRST_PKT, 10);
2733: AQ_WRITE_REG(sc, RPO_LRO_RSC_MAX_REG, 1);
2734: AQ_WRITE_REG(sc, RPO_LRO_ENABLE_REG, lro);
2735:
2736: return 0;
2737: }
2738:
2739: static int
2740: aq_set_filter(struct aq_softc *sc)
2741: {
1.32 skrll 2742: struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
2743: struct ethercom * const ec = &sc->sc_ethercom;
1.1 ryo 2744: struct ether_multi *enm;
2745: struct ether_multistep step;
2746: int idx, error = 0;
2747:
2748: if (ifp->if_flags & IFF_PROMISC) {
2749: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_PROMISC,
2750: (ifp->if_flags & IFF_PROMISC) ? 1 : 0);
2751: ec->ec_flags |= ETHER_F_ALLMULTI;
2752: goto done;
2753: }
2754:
2755: /* clear all table */
2756: for (idx = 0; idx < AQ_HW_MAC_NUM; idx++) {
2757: if (idx == AQ_HW_MAC_OWN) /* already used for own */
2758: continue;
2759: aq_set_mac_addr(sc, idx, NULL);
2760: }
2761:
2762: /* don't accept all multicast */
2763: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG,
2764: RPF_MCAST_FILTER_MASK_ALLMULTI, 0);
2765: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0),
2766: RPF_MCAST_FILTER_EN, 0);
2767:
2768: idx = 0;
2769: ETHER_LOCK(ec);
2770: ETHER_FIRST_MULTI(step, ec, enm);
2771: while (enm != NULL) {
2772: if (idx == AQ_HW_MAC_OWN)
2773: idx++;
2774:
2775: if ((idx >= AQ_HW_MAC_NUM) ||
2776: memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
2777: /*
2778: * too many filters.
2779: * fallback to accept all multicast addresses.
2780: */
2781: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG,
2782: RPF_MCAST_FILTER_MASK_ALLMULTI, 1);
2783: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0),
2784: RPF_MCAST_FILTER_EN, 1);
2785: ec->ec_flags |= ETHER_F_ALLMULTI;
2786: ETHER_UNLOCK(ec);
2787: goto done;
2788: }
2789:
2790: /* add a filter */
2791: aq_set_mac_addr(sc, idx++, enm->enm_addrlo);
2792:
2793: ETHER_NEXT_MULTI(step, enm);
2794: }
2795: ec->ec_flags &= ~ETHER_F_ALLMULTI;
2796: ETHER_UNLOCK(ec);
2797:
2798: done:
2799: return error;
2800: }
2801:
2802: static int
2803: aq_ifmedia_change(struct ifnet * const ifp)
2804: {
1.32 skrll 2805: struct aq_softc * const sc = ifp->if_softc;
1.33 skrll 2806:
1.1 ryo 2807: aq_link_speed_t rate = AQ_LINK_NONE;
2808: aq_link_fc_t fc = AQ_FC_NONE;
2809: aq_link_eee_t eee = AQ_EEE_DISABLE;
2810:
2811: if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER)
2812: return EINVAL;
2813:
2814: switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) {
2815: case IFM_AUTO:
2816: rate = AQ_LINK_AUTO;
2817: break;
2818: case IFM_NONE:
2819: rate = AQ_LINK_NONE;
2820: break;
2821: case IFM_100_TX:
2822: rate = AQ_LINK_100M;
2823: break;
2824: case IFM_1000_T:
2825: rate = AQ_LINK_1G;
2826: break;
2827: case IFM_2500_T:
2828: rate = AQ_LINK_2G5;
2829: break;
2830: case IFM_5000_T:
2831: rate = AQ_LINK_5G;
2832: break;
2833: case IFM_10G_T:
2834: rate = AQ_LINK_10G;
2835: break;
2836: default:
2837: device_printf(sc->sc_dev, "unknown media: 0x%X\n",
2838: IFM_SUBTYPE(sc->sc_media.ifm_media));
2839: return ENODEV;
2840: }
2841:
2842: if (sc->sc_media.ifm_media & IFM_FLOW)
2843: fc = AQ_FC_ALL;
2844:
2845: /* XXX: todo EEE */
2846:
2847: /* re-initialize hardware with new parameters */
2848: aq_set_linkmode(sc, rate, fc, eee);
2849:
2850: return 0;
2851: }
2852:
2853: static void
2854: aq_ifmedia_status(struct ifnet * const ifp, struct ifmediareq *ifmr)
2855: {
1.32 skrll 2856: struct aq_softc * const sc = ifp->if_softc;
1.1 ryo 2857:
1.11 ryo 2858: /* update ifm_active */
1.1 ryo 2859: ifmr->ifm_active = IFM_ETHER;
1.11 ryo 2860: if (sc->sc_link_fc & AQ_FC_RX)
2861: ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2862: if (sc->sc_link_fc & AQ_FC_TX)
2863: ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2864:
2865: switch (sc->sc_link_rate) {
2866: case AQ_LINK_100M:
2867: /* XXX: need to detect fulldup or halfdup */
2868: ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
2869: break;
2870: case AQ_LINK_1G:
2871: ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
2872: break;
2873: case AQ_LINK_2G5:
2874: ifmr->ifm_active |= IFM_2500_T | IFM_FDX;
2875: break;
2876: case AQ_LINK_5G:
2877: ifmr->ifm_active |= IFM_5000_T | IFM_FDX;
2878: break;
2879: case AQ_LINK_10G:
2880: ifmr->ifm_active |= IFM_10G_T | IFM_FDX;
2881: break;
2882: default:
2883: ifmr->ifm_active |= IFM_NONE;
2884: break;
2885: }
2886:
2887: /* update ifm_status */
1.1 ryo 2888: ifmr->ifm_status = IFM_AVALID;
2889: if (sc->sc_link_rate != AQ_LINK_NONE)
2890: ifmr->ifm_status |= IFM_ACTIVE;
2891: }
2892:
2893: static void
2894: aq_initmedia(struct aq_softc *sc)
2895: {
2896: #define IFMEDIA_ETHER_ADD(sc, media) \
2897: ifmedia_add(&(sc)->sc_media, IFM_ETHER | media, 0, NULL);
2898:
2899: IFMEDIA_ETHER_ADD(sc, IFM_NONE);
2900: if (sc->sc_available_rates & AQ_LINK_100M) {
2901: IFMEDIA_ETHER_ADD(sc, IFM_100_TX);
2902: IFMEDIA_ETHER_ADD(sc, IFM_100_TX | IFM_FLOW);
2903: IFMEDIA_ETHER_ADD(sc, IFM_100_TX | IFM_FDX | IFM_FLOW);
2904: }
2905: if (sc->sc_available_rates & AQ_LINK_1G) {
2906: IFMEDIA_ETHER_ADD(sc, IFM_1000_T | IFM_FDX);
2907: IFMEDIA_ETHER_ADD(sc, IFM_1000_T | IFM_FDX | IFM_FLOW);
2908: }
2909: if (sc->sc_available_rates & AQ_LINK_2G5) {
2910: IFMEDIA_ETHER_ADD(sc, IFM_2500_T | IFM_FDX);
2911: IFMEDIA_ETHER_ADD(sc, IFM_2500_T | IFM_FDX | IFM_FLOW);
2912: }
2913: if (sc->sc_available_rates & AQ_LINK_5G) {
2914: IFMEDIA_ETHER_ADD(sc, IFM_5000_T | IFM_FDX);
2915: IFMEDIA_ETHER_ADD(sc, IFM_5000_T | IFM_FDX | IFM_FLOW);
2916: }
2917: if (sc->sc_available_rates & AQ_LINK_10G) {
2918: IFMEDIA_ETHER_ADD(sc, IFM_10G_T | IFM_FDX);
2919: IFMEDIA_ETHER_ADD(sc, IFM_10G_T | IFM_FDX | IFM_FLOW);
2920: }
2921: IFMEDIA_ETHER_ADD(sc, IFM_AUTO);
2922: IFMEDIA_ETHER_ADD(sc, IFM_AUTO | IFM_FLOW);
2923:
2924: /* default: auto without flowcontrol */
2925: ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO);
2926: aq_set_linkmode(sc, AQ_LINK_AUTO, AQ_FC_NONE, AQ_EEE_DISABLE);
2927: }
2928:
2929: static int
2930: aq_set_linkmode(struct aq_softc *sc, aq_link_speed_t speed, aq_link_fc_t fc,
2931: aq_link_eee_t eee)
2932: {
2933: return sc->sc_fw_ops->set_mode(sc, MPI_INIT, speed, fc, eee);
2934: }
2935:
2936: static int
2937: aq_get_linkmode(struct aq_softc *sc, aq_link_speed_t *speed, aq_link_fc_t *fc,
2938: aq_link_eee_t *eee)
2939: {
2940: aq_hw_fw_mpi_state_t mode;
2941: int error;
2942:
2943: error = sc->sc_fw_ops->get_mode(sc, &mode, speed, fc, eee);
2944: if (error != 0)
2945: return error;
2946: if (mode != MPI_INIT)
2947: return ENXIO;
2948:
2949: return 0;
2950: }
2951:
2952: static void
2953: aq_hw_init_tx_path(struct aq_softc *sc)
2954: {
2955: /* Tx TC/RSS number config */
2956: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_TC_MODE_EN, 1);
2957:
2958: AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG,
2959: THM_LSO_TCP_FLAG1_FIRST, 0x0ff6);
2960: AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG,
2961: THM_LSO_TCP_FLAG1_MID, 0x0ff6);
2962: AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG2_REG,
2963: THM_LSO_TCP_FLAG2_LAST, 0x0f7f);
2964:
2965: /* misc */
2966: AQ_WRITE_REG(sc, TX_TPO2_REG,
2967: (sc->sc_features & FEATURES_TPO2) ? TX_TPO2_EN : 0);
2968: AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_EN, 0);
2969: AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_MODE, 0);
2970:
2971: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_SCP_INS_EN, 1);
2972: }
2973:
2974: static void
2975: aq_hw_init_rx_path(struct aq_softc *sc)
2976: {
2977: int i;
2978:
2979: /* clear setting */
2980: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_TC_MODE, 0);
2981: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_FC_MODE, 0);
2982: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG, 0);
2983: for (i = 0; i < 32; i++) {
2984: AQ_WRITE_REG_BIT(sc, RPF_ETHERTYPE_FILTER_REG(i),
2985: RPF_ETHERTYPE_FILTER_EN, 0);
2986: }
2987:
2988: if (sc->sc_rss_enable) {
2989: /* Rx TC/RSS number config */
2990: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_TC_MODE, 1);
2991:
2992: /* Rx flow control */
2993: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_FC_MODE, 1);
2994:
2995: /* RSS Ring selection */
2996: switch (sc->sc_nqueues) {
2997: case 2:
2998: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG,
2999: RX_FLR_RSS_CONTROL1_EN | 0x11111111);
3000: break;
3001: case 4:
3002: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG,
3003: RX_FLR_RSS_CONTROL1_EN | 0x22222222);
3004: break;
3005: case 8:
3006: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG,
3007: RX_FLR_RSS_CONTROL1_EN | 0x33333333);
3008: break;
3009: }
3010: }
3011:
3012: /* L2 and Multicast filters */
3013: for (i = 0; i < AQ_HW_MAC_NUM; i++) {
3014: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_EN, 0);
3015: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_ACTION,
3016: RPF_ACTION_HOST);
3017: }
3018: AQ_WRITE_REG(sc, RPF_MCAST_FILTER_MASK_REG, 0);
3019: AQ_WRITE_REG(sc, RPF_MCAST_FILTER_REG(0), 0x00010fff);
3020:
3021: /* Vlan filters */
3022: AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_OUTER,
3023: ETHERTYPE_QINQ);
3024: AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_INNER,
3025: ETHERTYPE_VLAN);
1.10 ryo 3026: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, RPF_VLAN_MODE_PROMISC, 0);
1.1 ryo 3027:
3028: if (sc->sc_features & FEATURES_REV_B) {
3029: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG,
3030: RPF_VLAN_MODE_ACCEPT_UNTAGGED, 1);
3031: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG,
3032: RPF_VLAN_MODE_UNTAGGED_ACTION, RPF_ACTION_HOST);
3033: }
3034:
3035: /* misc */
3036: if (sc->sc_features & FEATURES_RPF2)
3037: AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG, RX_TCP_RSS_HASH_RPF2);
3038: else
3039: AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG, 0);
3040:
3041: /*
3042: * XXX: RX_TCP_RSS_HASH_REG:
3043: * linux set 0x000f0000
3044: * freebsd set 0x000f001e
3045: */
3046: /* RSS hash type set for IP/TCP */
3047: AQ_WRITE_REG_BIT(sc, RX_TCP_RSS_HASH_REG,
3048: RX_TCP_RSS_HASH_TYPE, 0x001e);
3049:
3050: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_EN, 1);
3051: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_ACTION, RPF_ACTION_HOST);
3052: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_THRESHOLD, 0xffff);
3053:
3054: AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_EN, 0);
3055: AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_MODE, 0);
3056: }
3057:
3058: static void
3059: aq_hw_interrupt_moderation_set(struct aq_softc *sc)
3060: {
3061: int i;
3062:
3063: if (sc->sc_intr_moderation_enable) {
3064: unsigned int tx_min, rx_min; /* 0-255 */
3065: unsigned int tx_max, rx_max; /* 0-511? */
3066:
3067: switch (sc->sc_link_rate) {
3068: case AQ_LINK_100M:
3069: tx_min = 0x4f;
3070: tx_max = 0xff;
3071: rx_min = 0x04;
3072: rx_max = 0x50;
3073: break;
3074: case AQ_LINK_1G:
3075: default:
3076: tx_min = 0x4f;
3077: tx_max = 0xff;
3078: rx_min = 0x30;
3079: rx_max = 0x80;
3080: break;
3081: case AQ_LINK_2G5:
3082: tx_min = 0x4f;
3083: tx_max = 0xff;
3084: rx_min = 0x18;
3085: rx_max = 0xe0;
3086: break;
3087: case AQ_LINK_5G:
3088: tx_min = 0x4f;
3089: tx_max = 0xff;
3090: rx_min = 0x0c;
3091: rx_max = 0x70;
3092: break;
3093: case AQ_LINK_10G:
3094: tx_min = 0x4f;
3095: tx_max = 0x1ff;
3096: rx_min = 0x06; /* freebsd use 80 */
3097: rx_max = 0x38; /* freebsd use 120 */
3098: break;
3099: }
3100:
3101: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3102: TX_DMA_INT_DESC_WRWB_EN, 0);
3103: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3104: TX_DMA_INT_DESC_MODERATE_EN, 1);
3105: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3106: RX_DMA_INT_DESC_WRWB_EN, 0);
3107: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3108: RX_DMA_INT_DESC_MODERATE_EN, 1);
3109:
3110: for (i = 0; i < AQ_RINGS_NUM; i++) {
3111: AQ_WRITE_REG(sc, TX_INTR_MODERATION_CTL_REG(i),
3112: __SHIFTIN(tx_min, TX_INTR_MODERATION_CTL_MIN) |
3113: __SHIFTIN(tx_max, TX_INTR_MODERATION_CTL_MAX) |
3114: TX_INTR_MODERATION_CTL_EN);
3115: }
3116: for (i = 0; i < AQ_RINGS_NUM; i++) {
3117: AQ_WRITE_REG(sc, RX_INTR_MODERATION_CTL_REG(i),
3118: __SHIFTIN(rx_min, RX_INTR_MODERATION_CTL_MIN) |
3119: __SHIFTIN(rx_max, RX_INTR_MODERATION_CTL_MAX) |
3120: RX_INTR_MODERATION_CTL_EN);
3121: }
3122:
3123: } else {
3124: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3125: TX_DMA_INT_DESC_WRWB_EN, 1);
3126: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3127: TX_DMA_INT_DESC_MODERATE_EN, 0);
3128: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3129: RX_DMA_INT_DESC_WRWB_EN, 1);
3130: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3131: RX_DMA_INT_DESC_MODERATE_EN, 0);
3132:
3133: for (i = 0; i < AQ_RINGS_NUM; i++) {
3134: AQ_WRITE_REG(sc, TX_INTR_MODERATION_CTL_REG(i), 0);
3135: }
3136: for (i = 0; i < AQ_RINGS_NUM; i++) {
3137: AQ_WRITE_REG(sc, RX_INTR_MODERATION_CTL_REG(i), 0);
3138: }
3139: }
3140: }
3141:
3142: static void
3143: aq_hw_qos_set(struct aq_softc *sc)
3144: {
3145: uint32_t tc = 0;
3146: uint32_t buff_size;
3147:
3148: /* TPS Descriptor rate init */
3149: AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_TA_RST, 0);
3150: AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_LIM, 0xa);
3151:
3152: /* TPS VM init */
3153: AQ_WRITE_REG_BIT(sc, TPS_DESC_VM_ARB_MODE_REG, TPS_DESC_VM_ARB_MODE, 0);
3154:
3155: /* TPS TC credits init */
3156: AQ_WRITE_REG_BIT(sc, TPS_DESC_TC_ARB_MODE_REG, TPS_DESC_TC_ARB_MODE, 0);
3157: AQ_WRITE_REG_BIT(sc, TPS_DATA_TC_ARB_MODE_REG, TPS_DATA_TC_ARB_MODE, 0);
3158:
3159: AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc),
3160: TPS_DATA_TCT_CREDIT_MAX, 0xfff);
3161: AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc),
3162: TPS_DATA_TCT_WEIGHT, 0x64);
3163: AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc),
3164: TPS_DESC_TCT_CREDIT_MAX, 0x50);
3165: AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc),
3166: TPS_DESC_TCT_WEIGHT, 0x1e);
3167:
3168: /* Tx buf size */
3169: tc = 0;
3170: buff_size = AQ_HW_TXBUF_MAX;
3171: AQ_WRITE_REG_BIT(sc, TPB_TXB_BUFSIZE_REG(tc), TPB_TXB_BUFSIZE,
3172: buff_size);
3173: AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_HI,
3174: (buff_size * (1024 / 32) * 66) / 100);
3175: AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_LO,
3176: (buff_size * (1024 / 32) * 50) / 100);
3177:
3178: /* QoS Rx buf size per TC */
3179: tc = 0;
3180: buff_size = AQ_HW_RXBUF_MAX;
3181: AQ_WRITE_REG_BIT(sc, RPB_RXB_BUFSIZE_REG(tc), RPB_RXB_BUFSIZE,
3182: buff_size);
3183: AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_EN, 0);
3184: AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_THRESH_HI,
3185: (buff_size * (1024 / 32) * 66) / 100);
3186: AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_THRESH_LO,
3187: (buff_size * (1024 / 32) * 50) / 100);
3188:
3189: /* QoS 802.1p priority -> TC mapping */
3190: int i_priority;
3191: for (i_priority = 0; i_priority < 8; i_priority++) {
3192: AQ_WRITE_REG_BIT(sc, RPF_RPB_RX_TC_UPT_REG,
3193: RPF_RPB_RX_TC_UPT_MASK(i_priority), 0);
3194: }
3195: }
3196:
3197: /* called once from aq_attach */
3198: static int
3199: aq_init_rss(struct aq_softc *sc)
3200: {
3201: CTASSERT(AQ_RSS_HASHKEY_SIZE == RSS_KEYSIZE);
3202: uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
3203: uint8_t rss_table[AQ_RSS_INDIRECTION_TABLE_MAX];
3204: unsigned int i;
3205: int error;
3206:
3207: /* initialize rss key */
3208: rss_getkey((uint8_t *)rss_key);
3209:
3210: /* hash to ring table */
3211: for (i = 0; i < AQ_RSS_INDIRECTION_TABLE_MAX; i++) {
3212: rss_table[i] = i % sc->sc_nqueues;
3213: }
3214:
3215: /*
3216: * set rss key
3217: */
3218: for (i = 0; i < __arraycount(rss_key); i++) {
3219: uint32_t key_data = sc->sc_rss_enable ? ntohl(rss_key[i]) : 0;
3220: AQ_WRITE_REG(sc, RPF_RSS_KEY_WR_DATA_REG, key_data);
3221: AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG,
3222: RPF_RSS_KEY_ADDR, __arraycount(rss_key) - 1 - i);
3223: AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG,
3224: RPF_RSS_KEY_WR_EN, 1);
3225: WAIT_FOR(AQ_READ_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG,
3226: RPF_RSS_KEY_WR_EN) == 0, 1000, 10, &error);
3227: if (error != 0) {
3228: device_printf(sc->sc_dev, "%s: rss key write timeout\n",
3229: __func__);
3230: goto rss_set_timeout;
3231: }
3232: }
3233:
3234: /*
3235: * set rss indirection table
3236: *
3237: * AQ's rss redirect table is consist of 3bit*64 (192bit) packed array.
3238: * we'll make it by __BITMAP(3) macros.
3239: */
3240: __BITMAP_TYPE(, uint16_t, 3 * AQ_RSS_INDIRECTION_TABLE_MAX) bit3x64;
3241: __BITMAP_ZERO(&bit3x64);
3242:
3243: #define AQ_3BIT_PACKED_ARRAY_SET(bitmap, idx, val) \
3244: do { \
3245: if (val & 1) { \
3246: __BITMAP_SET((idx) * 3, (bitmap)); \
3247: } else { \
3248: __BITMAP_CLR((idx) * 3, (bitmap)); \
3249: } \
3250: if (val & 2) { \
3251: __BITMAP_SET((idx) * 3 + 1, (bitmap)); \
3252: } else { \
3253: __BITMAP_CLR((idx) * 3 + 1, (bitmap)); \
3254: } \
3255: if (val & 4) { \
3256: __BITMAP_SET((idx) * 3 + 2, (bitmap)); \
3257: } else { \
3258: __BITMAP_CLR((idx) * 3 + 2, (bitmap)); \
3259: } \
3260: } while (0 /* CONSTCOND */)
3261:
3262: for (i = 0; i < AQ_RSS_INDIRECTION_TABLE_MAX; i++) {
3263: AQ_3BIT_PACKED_ARRAY_SET(&bit3x64, i, rss_table[i]);
3264: }
3265:
3266: /* write 192bit data in steps of 16bit */
3267: for (i = 0; i < (int)__arraycount(bit3x64._b); i++) {
3268: AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_WR_DATA_REG,
3269: RPF_RSS_REDIR_WR_DATA, bit3x64._b[i]);
3270: AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG,
3271: RPF_RSS_REDIR_ADDR, i);
3272: AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG,
3273: RPF_RSS_REDIR_WR_EN, 1);
3274:
3275: WAIT_FOR(AQ_READ_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG,
3276: RPF_RSS_REDIR_WR_EN) == 0, 1000, 10, &error);
3277: if (error != 0)
3278: break;
3279: }
3280:
3281: rss_set_timeout:
3282: return error;
3283: }
3284:
3285: static void
3286: aq_hw_l3_filter_set(struct aq_softc *sc)
3287: {
3288: int i;
3289:
3290: /* clear all filter */
3291: for (i = 0; i < 8; i++) {
3292: AQ_WRITE_REG_BIT(sc, RPF_L3_FILTER_REG(i),
3293: RPF_L3_FILTER_L4_EN, 0);
3294: }
3295: }
3296:
3297: static void
1.10 ryo 3298: aq_set_vlan_filters(struct aq_softc *sc)
1.1 ryo 3299: {
1.32 skrll 3300: struct ethercom * const ec = &sc->sc_ethercom;
3301: struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
1.10 ryo 3302: struct vlanid_list *vlanidp;
1.1 ryo 3303: int i;
3304:
1.10 ryo 3305: ETHER_LOCK(ec);
3306:
3307: /* disable all vlan filters */
3308: for (i = 0; i < RPF_VLAN_MAX_FILTERS; i++)
3309: AQ_WRITE_REG(sc, RPF_VLAN_FILTER_REG(i), 0);
3310:
3311: /* count VID */
3312: i = 0;
3313: SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list)
3314: i++;
3315:
3316: if (((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_HWFILTER) == 0) ||
3317: (ifp->if_flags & IFF_PROMISC) ||
3318: (i > RPF_VLAN_MAX_FILTERS)) {
3319: /*
3320: * no vlan hwfilter, in promiscuous mode, or too many VID?
3321: * must receive all VID
3322: */
3323: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG,
3324: RPF_VLAN_MODE_PROMISC, 1);
3325: goto done;
3326: }
3327:
3328: /* receive only selected VID */
3329: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, RPF_VLAN_MODE_PROMISC, 0);
3330: i = 0;
3331: SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) {
1.1 ryo 3332: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
1.10 ryo 3333: RPF_VLAN_FILTER_EN, 1);
1.1 ryo 3334: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3335: RPF_VLAN_FILTER_RXQ_EN, 0);
1.10 ryo 3336: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3337: RPF_VLAN_FILTER_RXQ, 0);
3338: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3339: RPF_VLAN_FILTER_ACTION, RPF_ACTION_HOST);
3340: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3341: RPF_VLAN_FILTER_ID, vlanidp->vid);
3342: i++;
1.1 ryo 3343: }
1.10 ryo 3344:
3345: done:
3346: ETHER_UNLOCK(ec);
1.1 ryo 3347: }
3348:
3349: static int
3350: aq_hw_init(struct aq_softc *sc)
3351: {
3352: uint32_t v;
3353:
3354: /* Force limit MRRS on RDM/TDM to 2K */
3355: v = AQ_READ_REG(sc, AQ_PCI_REG_CONTROL_6_REG);
3356: AQ_WRITE_REG(sc, AQ_PCI_REG_CONTROL_6_REG, (v & ~0x0707) | 0x0404);
3357:
3358: /*
3359: * TX DMA total request limit. B0 hardware is not capable to
3360: * handle more than (8K-MRRS) incoming DMA data.
3361: * Value 24 in 256byte units
3362: */
3363: AQ_WRITE_REG(sc, AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG, 24);
3364:
3365: aq_hw_init_tx_path(sc);
3366: aq_hw_init_rx_path(sc);
3367:
3368: aq_hw_interrupt_moderation_set(sc);
3369:
3370: aq_set_mac_addr(sc, AQ_HW_MAC_OWN, sc->sc_enaddr.ether_addr_octet);
3371: aq_set_linkmode(sc, AQ_LINK_NONE, AQ_FC_NONE, AQ_EEE_DISABLE);
3372:
3373: aq_hw_qos_set(sc);
3374:
3375: /* Enable interrupt */
3376: int irqmode;
3377: if (sc->sc_msix)
3378: irqmode = AQ_INTR_CTRL_IRQMODE_MSIX;
3379: else
3380: irqmode = AQ_INTR_CTRL_IRQMODE_MSI;
3381:
3382: AQ_WRITE_REG(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS);
3383: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_MULTIVEC,
3384: sc->sc_msix ? 1 : 0);
3385: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_IRQMODE, irqmode);
3386:
3387: AQ_WRITE_REG(sc, AQ_INTR_AUTOMASK_REG, 0xffffffff);
3388:
3389: AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(0),
1.5 msaitoh 3390: ((AQ_B0_ERR_INT << 24) | (1U << 31)) |
1.1 ryo 3391: ((AQ_B0_ERR_INT << 16) | (1 << 23))
3392: );
3393:
3394: /* link interrupt */
3395: if (!sc->sc_msix)
3396: sc->sc_linkstat_irq = AQ_LINKSTAT_IRQ;
3397: AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(3),
3398: __BIT(7) | sc->sc_linkstat_irq);
3399:
3400: return 0;
3401: }
3402:
3403: static int
3404: aq_update_link_status(struct aq_softc *sc)
3405: {
1.32 skrll 3406: struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
1.1 ryo 3407: aq_link_speed_t rate = AQ_LINK_NONE;
3408: aq_link_fc_t fc = AQ_FC_NONE;
3409: aq_link_eee_t eee = AQ_EEE_DISABLE;
3410: unsigned int speed;
3411: int changed = 0;
3412:
3413: aq_get_linkmode(sc, &rate, &fc, &eee);
3414:
3415: if (sc->sc_link_rate != rate)
3416: changed = 1;
3417: if (sc->sc_link_fc != fc)
3418: changed = 1;
3419: if (sc->sc_link_eee != eee)
3420: changed = 1;
3421:
3422: if (changed) {
3423: switch (rate) {
3424: case AQ_LINK_100M:
3425: speed = 100;
3426: break;
3427: case AQ_LINK_1G:
3428: speed = 1000;
3429: break;
3430: case AQ_LINK_2G5:
3431: speed = 2500;
3432: break;
3433: case AQ_LINK_5G:
3434: speed = 5000;
3435: break;
3436: case AQ_LINK_10G:
3437: speed = 10000;
3438: break;
3439: case AQ_LINK_NONE:
3440: default:
3441: speed = 0;
3442: break;
3443: }
3444:
3445: if (sc->sc_link_rate == AQ_LINK_NONE) {
3446: /* link DOWN -> UP */
3447: device_printf(sc->sc_dev, "link is UP: speed=%u\n",
3448: speed);
3449: if_link_state_change(ifp, LINK_STATE_UP);
3450: } else if (rate == AQ_LINK_NONE) {
3451: /* link UP -> DOWN */
3452: device_printf(sc->sc_dev, "link is DOWN\n");
3453: if_link_state_change(ifp, LINK_STATE_DOWN);
3454: } else {
3455: device_printf(sc->sc_dev,
3456: "link mode changed: speed=%u, fc=0x%x, eee=%x\n",
3457: speed, fc, eee);
3458: }
3459:
3460: sc->sc_link_rate = rate;
3461: sc->sc_link_fc = fc;
3462: sc->sc_link_eee = eee;
3463:
3464: /* update interrupt timing according to new link speed */
3465: aq_hw_interrupt_moderation_set(sc);
3466: }
3467:
3468: return changed;
3469: }
3470:
3471: #ifdef AQ_EVENT_COUNTERS
3472: static void
3473: aq_update_statistics(struct aq_softc *sc)
3474: {
3475: int prev = sc->sc_statistics_idx;
3476: int cur = prev ^ 1;
3477:
3478: sc->sc_fw_ops->get_stats(sc, &sc->sc_statistics[cur]);
3479:
3480: /*
3481: * aq's internal statistics counter is 32bit.
3482: * cauculate delta, and add to evcount
3483: */
3484: #define ADD_DELTA(cur, prev, name) \
3485: do { \
3486: uint32_t n; \
3487: n = (uint32_t)(sc->sc_statistics[cur].name - \
3488: sc->sc_statistics[prev].name); \
3489: if (n != 0) { \
3490: AQ_EVCNT_ADD(sc, name, n); \
3491: } \
3492: } while (/*CONSTCOND*/0);
3493:
3494: ADD_DELTA(cur, prev, uprc);
3495: ADD_DELTA(cur, prev, mprc);
3496: ADD_DELTA(cur, prev, bprc);
3497: ADD_DELTA(cur, prev, prc);
3498: ADD_DELTA(cur, prev, erpr);
3499: ADD_DELTA(cur, prev, uptc);
3500: ADD_DELTA(cur, prev, mptc);
3501: ADD_DELTA(cur, prev, bptc);
3502: ADD_DELTA(cur, prev, ptc);
3503: ADD_DELTA(cur, prev, erpt);
3504: ADD_DELTA(cur, prev, mbtc);
3505: ADD_DELTA(cur, prev, bbtc);
3506: ADD_DELTA(cur, prev, mbrc);
3507: ADD_DELTA(cur, prev, bbrc);
3508: ADD_DELTA(cur, prev, ubrc);
3509: ADD_DELTA(cur, prev, ubtc);
3510: ADD_DELTA(cur, prev, dpc);
3511: ADD_DELTA(cur, prev, cprc);
3512:
3513: sc->sc_statistics_idx = cur;
3514: }
3515: #endif /* AQ_EVENT_COUNTERS */
3516:
3517: /* allocate and map one DMA block */
3518: static int
3519: _alloc_dma(struct aq_softc *sc, bus_size_t size, bus_size_t *sizep,
3520: void **addrp, bus_dmamap_t *mapp, bus_dma_segment_t *seg)
3521: {
3522: int nsegs, error;
3523:
3524: if ((error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, seg,
3525: 1, &nsegs, 0)) != 0) {
3526: aprint_error_dev(sc->sc_dev,
3527: "unable to allocate DMA buffer, error=%d\n", error);
3528: goto fail_alloc;
3529: }
3530:
3531: if ((error = bus_dmamem_map(sc->sc_dmat, seg, 1, size, addrp,
3532: BUS_DMA_COHERENT)) != 0) {
3533: aprint_error_dev(sc->sc_dev,
3534: "unable to map DMA buffer, error=%d\n", error);
3535: goto fail_map;
3536: }
3537:
3538: if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
3539: 0, mapp)) != 0) {
3540: aprint_error_dev(sc->sc_dev,
3541: "unable to create DMA map, error=%d\n", error);
3542: goto fail_create;
3543: }
3544:
3545: if ((error = bus_dmamap_load(sc->sc_dmat, *mapp, *addrp, size, NULL,
3546: 0)) != 0) {
3547: aprint_error_dev(sc->sc_dev,
3548: "unable to load DMA map, error=%d\n", error);
3549: goto fail_load;
3550: }
3551:
3552: *sizep = size;
3553: return 0;
3554:
3555: fail_load:
3556: bus_dmamap_destroy(sc->sc_dmat, *mapp);
3557: *mapp = NULL;
3558: fail_create:
3559: bus_dmamem_unmap(sc->sc_dmat, *addrp, size);
3560: *addrp = NULL;
3561: fail_map:
3562: bus_dmamem_free(sc->sc_dmat, seg, 1);
3563: memset(seg, 0, sizeof(*seg));
3564: fail_alloc:
3565: *sizep = 0;
3566: return error;
3567: }
3568:
3569: static void
3570: _free_dma(struct aq_softc *sc, bus_size_t *sizep, void **addrp,
3571: bus_dmamap_t *mapp, bus_dma_segment_t *seg)
3572: {
3573: if (*mapp != NULL) {
3574: bus_dmamap_destroy(sc->sc_dmat, *mapp);
3575: *mapp = NULL;
3576: }
3577: if (*addrp != NULL) {
3578: bus_dmamem_unmap(sc->sc_dmat, *addrp, *sizep);
3579: *addrp = NULL;
3580: }
3581: if (*sizep != 0) {
3582: bus_dmamem_free(sc->sc_dmat, seg, 1);
3583: memset(seg, 0, sizeof(*seg));
3584: *sizep = 0;
3585: }
3586: }
3587:
3588: static int
3589: aq_txring_alloc(struct aq_softc *sc, struct aq_txring *txring)
3590: {
3591: int i, error;
3592:
3593: /* allocate tx descriptors */
3594: error = _alloc_dma(sc, sizeof(aq_tx_desc_t) * AQ_TXD_NUM,
3595: &txring->txr_txdesc_size, (void **)&txring->txr_txdesc,
3596: &txring->txr_txdesc_dmamap, txring->txr_txdesc_seg);
3597: if (error != 0)
3598: return error;
3599:
3600: memset(txring->txr_txdesc, 0, sizeof(aq_tx_desc_t) * AQ_TXD_NUM);
3601:
3602: /* fill tx ring with dmamap */
3603: for (i = 0; i < AQ_TXD_NUM; i++) {
3604: #define AQ_MAXDMASIZE (16 * 1024)
3605: #define AQ_NTXSEGS 32
3606: /* XXX: TODO: error check */
3607: bus_dmamap_create(sc->sc_dmat, AQ_MAXDMASIZE, AQ_NTXSEGS,
3608: AQ_MAXDMASIZE, 0, 0, &txring->txr_mbufs[i].dmamap);
3609: }
3610: return 0;
3611: }
3612:
3613: static void
3614: aq_txring_free(struct aq_softc *sc, struct aq_txring *txring)
3615: {
3616: int i;
3617:
3618: _free_dma(sc, &txring->txr_txdesc_size, (void **)&txring->txr_txdesc,
3619: &txring->txr_txdesc_dmamap, txring->txr_txdesc_seg);
3620:
3621: for (i = 0; i < AQ_TXD_NUM; i++) {
3622: if (txring->txr_mbufs[i].dmamap != NULL) {
3623: if (txring->txr_mbufs[i].m != NULL) {
3624: bus_dmamap_unload(sc->sc_dmat,
3625: txring->txr_mbufs[i].dmamap);
3626: m_freem(txring->txr_mbufs[i].m);
3627: txring->txr_mbufs[i].m = NULL;
3628: }
3629: bus_dmamap_destroy(sc->sc_dmat,
3630: txring->txr_mbufs[i].dmamap);
3631: txring->txr_mbufs[i].dmamap = NULL;
3632: }
3633: }
3634: }
3635:
3636: static int
3637: aq_rxring_alloc(struct aq_softc *sc, struct aq_rxring *rxring)
3638: {
3639: int i, error;
3640:
3641: /* allocate rx descriptors */
3642: error = _alloc_dma(sc, sizeof(aq_rx_desc_t) * AQ_RXD_NUM,
3643: &rxring->rxr_rxdesc_size, (void **)&rxring->rxr_rxdesc,
3644: &rxring->rxr_rxdesc_dmamap, rxring->rxr_rxdesc_seg);
3645: if (error != 0)
3646: return error;
3647:
3648: memset(rxring->rxr_rxdesc, 0, sizeof(aq_rx_desc_t) * AQ_RXD_NUM);
3649:
3650: /* fill rxring with dmamaps */
3651: for (i = 0; i < AQ_RXD_NUM; i++) {
3652: rxring->rxr_mbufs[i].m = NULL;
3653: /* XXX: TODO: error check */
3654: bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 0,
3655: &rxring->rxr_mbufs[i].dmamap);
3656: }
3657: return 0;
3658: }
3659:
3660: static void
3661: aq_rxdrain(struct aq_softc *sc, struct aq_rxring *rxring)
3662: {
3663: int i;
3664:
3665: /* free all mbufs allocated for RX */
3666: for (i = 0; i < AQ_RXD_NUM; i++) {
3667: if (rxring->rxr_mbufs[i].m != NULL) {
3668: bus_dmamap_unload(sc->sc_dmat,
3669: rxring->rxr_mbufs[i].dmamap);
3670: m_freem(rxring->rxr_mbufs[i].m);
3671: rxring->rxr_mbufs[i].m = NULL;
3672: }
3673: }
3674: }
3675:
3676: static void
3677: aq_rxring_free(struct aq_softc *sc, struct aq_rxring *rxring)
3678: {
3679: int i;
3680:
3681: /* free all mbufs and dmamaps */
3682: aq_rxdrain(sc, rxring);
3683: for (i = 0; i < AQ_RXD_NUM; i++) {
3684: if (rxring->rxr_mbufs[i].dmamap != NULL) {
3685: bus_dmamap_destroy(sc->sc_dmat,
3686: rxring->rxr_mbufs[i].dmamap);
3687: rxring->rxr_mbufs[i].dmamap = NULL;
3688: }
3689: }
3690:
3691: /* free RX descriptor */
3692: _free_dma(sc, &rxring->rxr_rxdesc_size, (void **)&rxring->rxr_rxdesc,
3693: &rxring->rxr_rxdesc_dmamap, rxring->rxr_rxdesc_seg);
3694: }
3695:
3696: static void
3697: aq_rxring_setmbuf(struct aq_softc *sc, struct aq_rxring *rxring, int idx,
3698: struct mbuf *m)
3699: {
3700: int error;
3701:
3702: /* if mbuf already exists, unload and free */
3703: if (rxring->rxr_mbufs[idx].m != NULL) {
3704: bus_dmamap_unload(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap);
3705: m_freem(rxring->rxr_mbufs[idx].m);
3706: rxring->rxr_mbufs[idx].m = NULL;
3707: }
3708:
3709: rxring->rxr_mbufs[idx].m = m;
3710:
3711: m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
3712: error = bus_dmamap_load_mbuf(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap,
3713: m, BUS_DMA_READ | BUS_DMA_NOWAIT);
3714: if (error) {
3715: device_printf(sc->sc_dev,
3716: "unable to load rx DMA map %d, error = %d\n", idx, error);
3717: panic("%s: unable to load rx DMA map. error=%d",
3718: __func__, error);
3719: }
3720: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap, 0,
3721: rxring->rxr_mbufs[idx].dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
3722: }
3723:
3724: static inline void
3725: aq_rxring_reset_desc(struct aq_softc *sc, struct aq_rxring *rxring, int idx)
3726: {
3727: /* refill rxdesc, and sync */
3728: rxring->rxr_rxdesc[idx].read.buf_addr =
3729: htole64(rxring->rxr_mbufs[idx].dmamap->dm_segs[0].ds_addr);
3730: rxring->rxr_rxdesc[idx].read.hdr_addr = 0;
3731: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_rxdesc_dmamap,
3732: sizeof(aq_rx_desc_t) * idx, sizeof(aq_rx_desc_t),
3733: BUS_DMASYNC_PREWRITE);
3734: }
3735:
3736: static struct mbuf *
3737: aq_alloc_mbuf(void)
3738: {
3739: struct mbuf *m;
3740:
3741: MGETHDR(m, M_DONTWAIT, MT_DATA);
3742: if (m == NULL)
3743: return NULL;
3744:
3745: MCLGET(m, M_DONTWAIT);
3746: if ((m->m_flags & M_EXT) == 0) {
3747: m_freem(m);
3748: return NULL;
3749: }
3750:
3751: return m;
3752: }
3753:
3754: /* allocate mbuf and unload dmamap */
3755: static int
3756: aq_rxring_add(struct aq_softc *sc, struct aq_rxring *rxring, int idx)
3757: {
3758: struct mbuf *m;
3759:
3760: m = aq_alloc_mbuf();
3761: if (m == NULL)
3762: return ENOBUFS;
3763:
3764: aq_rxring_setmbuf(sc, rxring, idx, m);
3765: return 0;
3766: }
3767:
3768: static int
3769: aq_txrx_rings_alloc(struct aq_softc *sc)
3770: {
3771: int n, error;
3772:
3773: for (n = 0; n < sc->sc_nqueues; n++) {
3774: sc->sc_queue[n].sc = sc;
3775: sc->sc_queue[n].txring.txr_sc = sc;
3776: sc->sc_queue[n].txring.txr_index = n;
3777: mutex_init(&sc->sc_queue[n].txring.txr_mutex, MUTEX_DEFAULT,
3778: IPL_NET);
3779: error = aq_txring_alloc(sc, &sc->sc_queue[n].txring);
3780: if (error != 0)
3781: goto failure;
3782:
3783: error = aq_tx_pcq_alloc(sc, &sc->sc_queue[n].txring);
3784: if (error != 0)
3785: goto failure;
3786:
3787: sc->sc_queue[n].rxring.rxr_sc = sc;
3788: sc->sc_queue[n].rxring.rxr_index = n;
3789: mutex_init(&sc->sc_queue[n].rxring.rxr_mutex, MUTEX_DEFAULT,
3790: IPL_NET);
3791: error = aq_rxring_alloc(sc, &sc->sc_queue[n].rxring);
3792: if (error != 0)
3793: break;
3794: }
3795:
3796: failure:
3797: return error;
3798: }
3799:
3800: static void
3801: aq_txrx_rings_free(struct aq_softc *sc)
3802: {
3803: int n;
3804:
3805: for (n = 0; n < sc->sc_nqueues; n++) {
3806: aq_txring_free(sc, &sc->sc_queue[n].txring);
3807: mutex_destroy(&sc->sc_queue[n].txring.txr_mutex);
3808:
3809: aq_tx_pcq_free(sc, &sc->sc_queue[n].txring);
3810:
3811: aq_rxring_free(sc, &sc->sc_queue[n].rxring);
3812: mutex_destroy(&sc->sc_queue[n].rxring.rxr_mutex);
3813: }
3814: }
3815:
3816: static int
3817: aq_tx_pcq_alloc(struct aq_softc *sc, struct aq_txring *txring)
3818: {
3819: int error = 0;
3820: txring->txr_softint = NULL;
3821:
3822: txring->txr_pcq = pcq_create(AQ_TXD_NUM, KM_NOSLEEP);
3823: if (txring->txr_pcq == NULL) {
3824: aprint_error_dev(sc->sc_dev,
3825: "unable to allocate pcq for TXring[%d]\n",
3826: txring->txr_index);
3827: error = ENOMEM;
3828: goto done;
3829: }
3830:
3831: txring->txr_softint = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
3832: aq_deferred_transmit, txring);
3833: if (txring->txr_softint == NULL) {
3834: aprint_error_dev(sc->sc_dev,
3835: "unable to establish softint for TXring[%d]\n",
3836: txring->txr_index);
3837: error = ENOENT;
3838: }
3839:
3840: done:
3841: return error;
3842: }
3843:
3844: static void
3845: aq_tx_pcq_free(struct aq_softc *sc, struct aq_txring *txring)
3846: {
3847: struct mbuf *m;
3848:
3849: if (txring->txr_softint != NULL) {
3850: softint_disestablish(txring->txr_softint);
3851: txring->txr_softint = NULL;
3852: }
3853:
3854: if (txring->txr_pcq != NULL) {
3855: while ((m = pcq_get(txring->txr_pcq)) != NULL)
3856: m_freem(m);
3857: pcq_destroy(txring->txr_pcq);
3858: txring->txr_pcq = NULL;
3859: }
3860: }
3861:
1.4 ryo 3862: #if NSYSMON_ENVSYS > 0
3863: static void
3864: aq_temp_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
3865: {
3866: struct aq_softc *sc;
3867: uint32_t temp;
3868: int error;
3869:
3870: sc = sme->sme_cookie;
3871:
3872: error = sc->sc_fw_ops->get_temperature(sc, &temp);
3873: if (error == 0) {
3874: edata->value_cur = temp;
3875: edata->state = ENVSYS_SVALID;
3876: } else {
3877: edata->state = ENVSYS_SINVALID;
3878: }
3879: }
3880: #endif
3881:
1.33 skrll 3882:
3883:
3884: static bool
3885: aq_watchdog_check(struct aq_softc * const sc)
3886: {
3887:
3888: AQ_LOCKED(sc);
3889:
3890: bool ok = true;
1.40 ryo 3891: for (int n = 0; n < sc->sc_nqueues; n++) {
1.33 skrll 3892: struct aq_txring *txring = &sc->sc_queue[n].txring;
3893:
3894: mutex_enter(&txring->txr_mutex);
3895: if (txring->txr_sending &&
3896: time_uptime - txring->txr_lastsent > aq_watchdog_timeout)
3897: ok = false;
3898:
3899: mutex_exit(&txring->txr_mutex);
3900:
3901: if (!ok)
3902: return false;
3903: }
3904:
3905: if (sc->sc_trigger_reset) {
3906: /* debug operation, no need for atomicity or reliability */
3907: sc->sc_trigger_reset = 0;
3908: return false;
3909: }
3910:
3911: return true;
3912: }
3913:
3914:
3915:
3916: static bool
3917: aq_watchdog_tick(struct ifnet *ifp)
3918: {
3919: struct aq_softc * const sc = ifp->if_softc;
3920:
3921: AQ_LOCKED(sc);
3922:
3923: if (!sc->sc_trigger_reset && aq_watchdog_check(sc))
3924: return true;
3925:
3926: if (atomic_swap_uint(&sc->sc_reset_pending, 1) == 0) {
3927: workqueue_enqueue(sc->sc_reset_wq, &sc->sc_reset_work, NULL);
3928: }
3929:
3930: return false;
3931: }
3932:
1.1 ryo 3933: static void
3934: aq_tick(void *arg)
3935: {
1.33 skrll 3936: struct aq_softc * const sc = arg;
3937:
3938: AQ_LOCK(sc);
3939: if (sc->sc_stopping) {
3940: AQ_UNLOCK(sc);
3941: return;
3942: }
1.1 ryo 3943:
3944: if (sc->sc_poll_linkstat || sc->sc_detect_linkstat) {
3945: sc->sc_detect_linkstat = false;
3946: aq_update_link_status(sc);
3947: }
3948:
3949: #ifdef AQ_EVENT_COUNTERS
3950: if (sc->sc_poll_statistics)
3951: aq_update_statistics(sc);
3952: #endif
3953:
1.33 skrll 3954: struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
3955: const bool ok = aq_watchdog_tick(ifp);
3956: if (ok)
1.1 ryo 3957: callout_schedule(&sc->sc_tick_ch, hz);
1.33 skrll 3958:
3959: AQ_UNLOCK(sc);
1.1 ryo 3960: }
3961:
3962: /* interrupt enable/disable */
3963: static void
3964: aq_enable_intr(struct aq_softc *sc, bool link, bool txrx)
3965: {
3966: uint32_t imask = 0;
3967: int i;
3968:
3969: if (txrx) {
3970: for (i = 0; i < sc->sc_nqueues; i++) {
3971: imask |= __BIT(sc->sc_tx_irq[i]);
3972: imask |= __BIT(sc->sc_rx_irq[i]);
3973: }
3974: }
3975:
3976: if (link)
3977: imask |= __BIT(sc->sc_linkstat_irq);
3978:
3979: AQ_WRITE_REG(sc, AQ_INTR_MASK_REG, imask);
3980: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff);
3981: }
3982:
3983: static int
3984: aq_legacy_intr(void *arg)
3985: {
3986: struct aq_softc *sc = arg;
3987: uint32_t status;
3988: int nintr = 0;
3989:
3990: status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
3991: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff);
3992:
3993: if (status & __BIT(sc->sc_linkstat_irq)) {
1.34 riastrad 3994: AQ_LOCK(sc);
1.1 ryo 3995: sc->sc_detect_linkstat = true;
1.34 riastrad 3996: if (!sc->sc_stopping)
3997: callout_schedule(&sc->sc_tick_ch, 0);
3998: AQ_UNLOCK(sc);
1.1 ryo 3999: nintr++;
4000: }
4001:
4002: if (status & __BIT(sc->sc_rx_irq[0])) {
4003: nintr += aq_rx_intr(&sc->sc_queue[0].rxring);
4004: }
4005:
4006: if (status & __BIT(sc->sc_tx_irq[0])) {
4007: nintr += aq_tx_intr(&sc->sc_queue[0].txring);
4008: }
4009:
4010: return nintr;
4011: }
4012:
4013: static int
4014: aq_txrx_intr(void *arg)
4015: {
4016: struct aq_queue *queue = arg;
4017: struct aq_softc *sc = queue->sc;
4018: struct aq_txring *txring = &queue->txring;
4019: struct aq_rxring *rxring = &queue->rxring;
4020: uint32_t status;
4021: int nintr = 0;
4022: int txringidx, rxringidx, txirq, rxirq;
4023:
4024: txringidx = txring->txr_index;
4025: rxringidx = rxring->rxr_index;
4026: txirq = sc->sc_tx_irq[txringidx];
4027: rxirq = sc->sc_rx_irq[rxringidx];
4028:
4029: status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
4030: if ((status & (__BIT(txirq) | __BIT(rxirq))) == 0) {
4031: /* stray interrupt? */
4032: return 0;
4033: }
4034:
4035: nintr += aq_rx_intr(rxring);
4036: nintr += aq_tx_intr(txring);
4037:
4038: return nintr;
4039: }
4040:
4041: static int
4042: aq_link_intr(void *arg)
4043: {
1.33 skrll 4044: struct aq_softc * const sc = arg;
1.1 ryo 4045: uint32_t status;
4046: int nintr = 0;
4047:
4048: status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
4049: if (status & __BIT(sc->sc_linkstat_irq)) {
1.34 riastrad 4050: AQ_LOCK(sc);
1.1 ryo 4051: sc->sc_detect_linkstat = true;
1.34 riastrad 4052: if (!sc->sc_stopping)
4053: callout_schedule(&sc->sc_tick_ch, 0);
4054: AQ_UNLOCK(sc);
1.1 ryo 4055: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG,
4056: __BIT(sc->sc_linkstat_irq));
4057: nintr++;
4058: }
4059:
4060: return nintr;
4061: }
4062:
4063: static void
4064: aq_txring_reset(struct aq_softc *sc, struct aq_txring *txring, bool start)
4065: {
4066: const int ringidx = txring->txr_index;
4067: int i;
4068:
4069: mutex_enter(&txring->txr_mutex);
4070:
4071: txring->txr_prodidx = 0;
4072: txring->txr_considx = 0;
4073: txring->txr_nfree = AQ_TXD_NUM;
4074: txring->txr_active = false;
4075:
4076: /* free mbufs untransmitted */
4077: for (i = 0; i < AQ_TXD_NUM; i++) {
4078: if (txring->txr_mbufs[i].m != NULL) {
4079: m_freem(txring->txr_mbufs[i].m);
4080: txring->txr_mbufs[i].m = NULL;
4081: }
4082: }
4083:
4084: /* disable DMA */
4085: AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx), TX_DMA_DESC_EN, 0);
4086:
4087: if (start) {
4088: /* TX descriptor physical address */
4089: paddr_t paddr = txring->txr_txdesc_dmamap->dm_segs[0].ds_addr;
4090: AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRLSW_REG(ringidx), paddr);
4091: AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRMSW_REG(ringidx),
4092: (uint32_t)((uint64_t)paddr >> 32));
4093:
4094: /* TX descriptor size */
4095: AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx), TX_DMA_DESC_LEN,
4096: AQ_TXD_NUM / 8);
4097:
4098: /* reload TAIL pointer */
4099: txring->txr_prodidx = txring->txr_considx =
4100: AQ_READ_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(ringidx));
4101: AQ_WRITE_REG(sc, TX_DMA_DESC_WRWB_THRESH_REG(ringidx), 0);
4102:
4103: /* Mapping interrupt vector */
4104: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(ringidx),
4105: AQ_INTR_IRQ_MAP_TX_IRQMAP(ringidx), sc->sc_tx_irq[ringidx]);
4106: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(ringidx),
4107: AQ_INTR_IRQ_MAP_TX_EN(ringidx), true);
4108:
4109: /* enable DMA */
4110: AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx),
4111: TX_DMA_DESC_EN, 1);
4112:
4113: const int cpuid = 0; /* XXX? */
4114: AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(ringidx),
4115: TDM_DCAD_CPUID, cpuid);
4116: AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(ringidx),
4117: TDM_DCAD_CPUID_EN, 0);
4118:
4119: txring->txr_active = true;
4120: }
4121:
4122: mutex_exit(&txring->txr_mutex);
4123: }
4124:
4125: static int
4126: aq_rxring_reset(struct aq_softc *sc, struct aq_rxring *rxring, bool start)
4127: {
4128: const int ringidx = rxring->rxr_index;
4129: int i;
4130: int error = 0;
4131:
4132: mutex_enter(&rxring->rxr_mutex);
4133: rxring->rxr_active = false;
1.28 ryo 4134: rxring->rxr_discarding = false;
4135: if (rxring->rxr_receiving_m != NULL) {
4136: m_freem(rxring->rxr_receiving_m);
4137: rxring->rxr_receiving_m = NULL;
4138: rxring->rxr_receiving_m_last = NULL;
4139: }
1.1 ryo 4140:
4141: /* disable DMA */
4142: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), RX_DMA_DESC_EN, 0);
4143:
4144: /* free all RX mbufs */
4145: aq_rxdrain(sc, rxring);
4146:
4147: if (start) {
4148: for (i = 0; i < AQ_RXD_NUM; i++) {
4149: error = aq_rxring_add(sc, rxring, i);
4150: if (error != 0) {
4151: aq_rxdrain(sc, rxring);
4152: return error;
4153: }
4154: aq_rxring_reset_desc(sc, rxring, i);
4155: }
4156:
4157: /* RX descriptor physical address */
4158: paddr_t paddr = rxring->rxr_rxdesc_dmamap->dm_segs[0].ds_addr;
4159: AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRLSW_REG(ringidx), paddr);
4160: AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRMSW_REG(ringidx),
4161: (uint32_t)((uint64_t)paddr >> 32));
4162:
4163: /* RX descriptor size */
4164: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), RX_DMA_DESC_LEN,
4165: AQ_RXD_NUM / 8);
4166:
4167: /* maximum receive frame size */
4168: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(ringidx),
4169: RX_DMA_DESC_BUFSIZE_DATA, MCLBYTES / 1024);
4170: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(ringidx),
4171: RX_DMA_DESC_BUFSIZE_HDR, 0 / 1024);
4172:
4173: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
4174: RX_DMA_DESC_HEADER_SPLIT, 0);
4175: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
4176: RX_DMA_DESC_VLAN_STRIP,
4177: (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) ?
4178: 1 : 0);
4179:
4180: /*
4181: * reload TAIL pointer, and update readidx
4182: * (HEAD pointer cannot write)
4183: */
4184: rxring->rxr_readidx = AQ_READ_REG_BIT(sc,
4185: RX_DMA_DESC_HEAD_PTR_REG(ringidx), RX_DMA_DESC_HEAD_PTR);
4186: AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(ringidx),
4187: (rxring->rxr_readidx + AQ_RXD_NUM - 1) % AQ_RXD_NUM);
4188:
4189: /* Rx ring set mode */
4190:
4191: /* Mapping interrupt vector */
4192: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(ringidx),
4193: AQ_INTR_IRQ_MAP_RX_IRQMAP(ringidx), sc->sc_rx_irq[ringidx]);
4194: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(ringidx),
4195: AQ_INTR_IRQ_MAP_RX_EN(ringidx), 1);
4196:
4197: const int cpuid = 0; /* XXX? */
4198: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4199: RX_DMA_DCAD_CPUID, cpuid);
4200: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4201: RX_DMA_DCAD_DESC_EN, 0);
4202: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4203: RX_DMA_DCAD_HEADER_EN, 0);
4204: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4205: RX_DMA_DCAD_PAYLOAD_EN, 0);
4206:
4207: /* enable DMA. start receiving */
4208: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
4209: RX_DMA_DESC_EN, 1);
4210:
4211: rxring->rxr_active = true;
4212: }
4213:
4214: mutex_exit(&rxring->rxr_mutex);
4215: return error;
4216: }
4217:
4218: #define TXRING_NEXTIDX(idx) \
4219: (((idx) >= (AQ_TXD_NUM - 1)) ? 0 : ((idx) + 1))
4220: #define RXRING_NEXTIDX(idx) \
4221: (((idx) >= (AQ_RXD_NUM - 1)) ? 0 : ((idx) + 1))
4222:
4223: static int
4224: aq_encap_txring(struct aq_softc *sc, struct aq_txring *txring, struct mbuf **mp)
4225: {
4226: bus_dmamap_t map;
4227: struct mbuf *m = *mp;
4228: uint32_t ctl1, ctl1_ctx, ctl2;
4229: int idx, i, error;
4230:
4231: idx = txring->txr_prodidx;
4232: map = txring->txr_mbufs[idx].dmamap;
4233:
4234: error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
4235: BUS_DMA_WRITE | BUS_DMA_NOWAIT);
4236: if (error == EFBIG) {
4237: struct mbuf *n;
4238: n = m_defrag(m, M_DONTWAIT);
4239: if (n == NULL)
4240: return EFBIG;
4241: /* m_defrag() preserve m */
4242: KASSERT(n == m);
4243: error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
4244: BUS_DMA_WRITE | BUS_DMA_NOWAIT);
4245: }
4246: if (error != 0)
4247: return error;
4248:
4249: /*
4250: * check spaces of free descriptors.
4251: * +1 is additional descriptor for context (vlan, etc,.)
4252: */
4253: if ((map->dm_nsegs + 1) > txring->txr_nfree) {
4254: device_printf(sc->sc_dev,
4255: "TX: not enough descriptors left %d for %d segs\n",
4256: txring->txr_nfree, map->dm_nsegs + 1);
4257: bus_dmamap_unload(sc->sc_dmat, map);
4258: return ENOBUFS;
4259: }
4260:
4261: /* sync dma for mbuf */
4262: bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
4263: BUS_DMASYNC_PREWRITE);
4264:
4265: ctl1_ctx = 0;
4266: ctl2 = __SHIFTIN(m->m_pkthdr.len, AQ_TXDESC_CTL2_LEN);
4267:
4268: if (vlan_has_tag(m)) {
4269: ctl1 = AQ_TXDESC_CTL1_TYPE_TXC;
4270: ctl1 |= __SHIFTIN(vlan_get_tag(m), AQ_TXDESC_CTL1_VID);
4271:
4272: ctl1_ctx |= AQ_TXDESC_CTL1_CMD_VLAN;
4273: ctl2 |= AQ_TXDESC_CTL2_CTX_EN;
4274:
4275: /* fill context descriptor and forward index */
4276: txring->txr_txdesc[idx].buf_addr = 0;
4277: txring->txr_txdesc[idx].ctl1 = htole32(ctl1);
4278: txring->txr_txdesc[idx].ctl2 = 0;
4279:
4280: idx = TXRING_NEXTIDX(idx);
4281: txring->txr_nfree--;
4282: }
4283:
4284: if (m->m_pkthdr.csum_flags & M_CSUM_IPv4)
4285: ctl1_ctx |= AQ_TXDESC_CTL1_CMD_IP4CSUM;
4286: if (m->m_pkthdr.csum_flags &
4287: (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv6)) {
4288: ctl1_ctx |= AQ_TXDESC_CTL1_CMD_L4CSUM;
4289: }
4290:
4291: /* fill descriptor(s) */
4292: for (i = 0; i < map->dm_nsegs; i++) {
4293: ctl1 = ctl1_ctx | AQ_TXDESC_CTL1_TYPE_TXD |
4294: __SHIFTIN(map->dm_segs[i].ds_len, AQ_TXDESC_CTL1_BLEN);
4295: ctl1 |= AQ_TXDESC_CTL1_CMD_FCS;
4296:
4297: if (i == 0) {
4298: /* remember mbuf of these descriptors */
4299: txring->txr_mbufs[idx].m = m;
4300: } else {
4301: txring->txr_mbufs[idx].m = NULL;
4302: }
4303:
4304: if (i == map->dm_nsegs - 1) {
4305: /* last segment, mark an EndOfPacket, and cause intr */
4306: ctl1 |= AQ_TXDESC_CTL1_EOP | AQ_TXDESC_CTL1_CMD_WB;
4307: }
4308:
4309: txring->txr_txdesc[idx].buf_addr =
4310: htole64(map->dm_segs[i].ds_addr);
4311: txring->txr_txdesc[idx].ctl1 = htole32(ctl1);
4312: txring->txr_txdesc[idx].ctl2 = htole32(ctl2);
4313:
4314: bus_dmamap_sync(sc->sc_dmat, txring->txr_txdesc_dmamap,
4315: sizeof(aq_tx_desc_t) * idx, sizeof(aq_tx_desc_t),
4316: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4317:
4318: idx = TXRING_NEXTIDX(idx);
4319: txring->txr_nfree--;
4320: }
4321:
4322: txring->txr_prodidx = idx;
4323:
4324: return 0;
4325: }
4326:
4327: static int
4328: aq_tx_intr(void *arg)
4329: {
1.32 skrll 4330: struct aq_txring * const txring = arg;
4331: struct aq_softc * const sc = txring->txr_sc;
4332: struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
1.3 ryo 4333: struct mbuf *m;
1.1 ryo 4334: const int ringidx = txring->txr_index;
4335: unsigned int idx, hw_head, n = 0;
4336:
4337: mutex_enter(&txring->txr_mutex);
4338:
4339: if (!txring->txr_active)
4340: goto tx_intr_done;
4341:
4342: hw_head = AQ_READ_REG_BIT(sc, TX_DMA_DESC_HEAD_PTR_REG(ringidx),
4343: TX_DMA_DESC_HEAD_PTR);
4344: if (hw_head == txring->txr_considx) {
1.33 skrll 4345: txring->txr_sending = false;
1.1 ryo 4346: goto tx_intr_done;
4347: }
4348:
1.6 thorpej 4349: net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
4350:
1.1 ryo 4351: for (idx = txring->txr_considx; idx != hw_head;
4352: idx = TXRING_NEXTIDX(idx), n++) {
4353:
1.3 ryo 4354: if ((m = txring->txr_mbufs[idx].m) != NULL) {
1.1 ryo 4355: bus_dmamap_unload(sc->sc_dmat,
4356: txring->txr_mbufs[idx].dmamap);
1.3 ryo 4357:
1.6 thorpej 4358: if_statinc_ref(nsr, if_opackets);
4359: if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len);
1.3 ryo 4360: if (m->m_flags & M_MCAST)
1.6 thorpej 4361: if_statinc_ref(nsr, if_omcasts);
1.3 ryo 4362:
4363: m_freem(m);
1.1 ryo 4364: txring->txr_mbufs[idx].m = NULL;
4365: }
4366:
4367: txring->txr_nfree++;
4368: }
4369: txring->txr_considx = idx;
4370:
1.6 thorpej 4371: IF_STAT_PUTREF(ifp);
4372:
1.1 ryo 4373: /* no more pending TX packet, cancel watchdog */
4374: if (txring->txr_nfree >= AQ_TXD_NUM)
1.33 skrll 4375: txring->txr_sending = false;
1.1 ryo 4376:
4377: tx_intr_done:
4378: mutex_exit(&txring->txr_mutex);
4379:
4380: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_tx_irq[ringidx]));
4381: return n;
4382: }
4383:
4384: static int
4385: aq_rx_intr(void *arg)
4386: {
1.32 skrll 4387: struct aq_rxring * const rxring = arg;
4388: struct aq_softc * const sc = rxring->rxr_sc;
4389: struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
1.1 ryo 4390: const int ringidx = rxring->rxr_index;
4391: aq_rx_desc_t *rxd;
4392: struct mbuf *m, *m0, *mprev, *new_m;
4393: uint32_t rxd_type, rxd_hash __unused;
4394: uint16_t rxd_status, rxd_pktlen;
4395: uint16_t rxd_nextdescptr __unused, rxd_vlan __unused;
4396: unsigned int idx, n = 0;
1.28 ryo 4397: bool discarding;
1.1 ryo 4398:
4399: mutex_enter(&rxring->rxr_mutex);
4400:
4401: if (!rxring->rxr_active)
4402: goto rx_intr_done;
4403:
4404: if (rxring->rxr_readidx == AQ_READ_REG_BIT(sc,
4405: RX_DMA_DESC_HEAD_PTR_REG(ringidx), RX_DMA_DESC_HEAD_PTR)) {
4406: goto rx_intr_done;
4407: }
4408:
1.6 thorpej 4409: net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
4410:
1.28 ryo 4411: /* restore ring context */
4412: discarding = rxring->rxr_discarding;
4413: m0 = rxring->rxr_receiving_m;
4414: mprev = rxring->rxr_receiving_m_last;
4415:
1.1 ryo 4416: for (idx = rxring->rxr_readidx;
4417: idx != AQ_READ_REG_BIT(sc, RX_DMA_DESC_HEAD_PTR_REG(ringidx),
4418: RX_DMA_DESC_HEAD_PTR); idx = RXRING_NEXTIDX(idx), n++) {
4419:
4420: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_rxdesc_dmamap,
4421: sizeof(aq_rx_desc_t) * idx, sizeof(aq_rx_desc_t),
4422: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4423:
4424: rxd = &rxring->rxr_rxdesc[idx];
4425: rxd_status = le16toh(rxd->wb.status);
4426:
4427: if ((rxd_status & RXDESC_STATUS_DD) == 0)
4428: break; /* not yet done */
4429:
4430: rxd_type = le32toh(rxd->wb.type);
4431: rxd_pktlen = le16toh(rxd->wb.pkt_len);
4432: rxd_nextdescptr = le16toh(rxd->wb.next_desc_ptr);
4433: rxd_hash = le32toh(rxd->wb.rss_hash);
4434: rxd_vlan = le16toh(rxd->wb.vlan);
4435:
1.28 ryo 4436: /*
4437: * Some segments are being dropped while receiving jumboframe.
4438: * Discard until EOP.
4439: */
4440: if (discarding)
4441: goto rx_next;
4442:
1.1 ryo 4443: if ((rxd_status & RXDESC_STATUS_MACERR) ||
4444: (rxd_type & RXDESC_TYPE_MAC_DMA_ERR)) {
1.6 thorpej 4445: if_statinc_ref(nsr, if_ierrors);
1.28 ryo 4446: if (m0 != NULL) {
4447: m_freem(m0);
4448: m0 = mprev = NULL;
4449: }
4450: discarding = true;
1.1 ryo 4451: goto rx_next;
4452: }
4453:
4454: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap, 0,
4455: rxring->rxr_mbufs[idx].dmamap->dm_mapsize,
4456: BUS_DMASYNC_POSTREAD);
4457: m = rxring->rxr_mbufs[idx].m;
4458:
4459: new_m = aq_alloc_mbuf();
4460: if (new_m == NULL) {
4461: /*
4462: * cannot allocate new mbuf.
4463: * discard this packet, and reuse mbuf for next.
4464: */
1.6 thorpej 4465: if_statinc_ref(nsr, if_iqdrops);
1.28 ryo 4466: if (m0 != NULL) {
4467: m_freem(m0);
4468: m0 = mprev = NULL;
4469: }
4470: discarding = true;
1.1 ryo 4471: goto rx_next;
4472: }
4473: rxring->rxr_mbufs[idx].m = NULL;
4474: aq_rxring_setmbuf(sc, rxring, idx, new_m);
4475:
4476: if (m0 == NULL) {
4477: m0 = m;
4478: } else {
4479: if (m->m_flags & M_PKTHDR)
4480: m_remove_pkthdr(m);
4481: mprev->m_next = m;
4482: }
4483: mprev = m;
4484:
4485: if ((rxd_status & RXDESC_STATUS_EOP) == 0) {
1.28 ryo 4486: /* to be continued in the next segment */
1.1 ryo 4487: m->m_len = MCLBYTES;
4488: } else {
1.28 ryo 4489: /* the last segment */
1.24 ryo 4490: int mlen = rxd_pktlen % MCLBYTES;
4491: if (mlen == 0)
4492: mlen = MCLBYTES;
4493: m->m_len = mlen;
1.1 ryo 4494: m0->m_pkthdr.len = rxd_pktlen;
4495: /* VLAN offloading */
4496: if ((sc->sc_ethercom.ec_capenable &
4497: ETHERCAP_VLAN_HWTAGGING) &&
4498: (__SHIFTOUT(rxd_type, RXDESC_TYPE_PKTTYPE_VLAN) ||
4499: __SHIFTOUT(rxd_type,
4500: RXDESC_TYPE_PKTTYPE_VLAN_DOUBLE))) {
4501: vlan_set_tag(m0, rxd_vlan);
4502: }
4503:
4504: /* Checksum offloading */
4505: unsigned int pkttype_eth =
4506: __SHIFTOUT(rxd_type, RXDESC_TYPE_PKTTYPE_ETHER);
4507: if ((ifp->if_capabilities & IFCAP_CSUM_IPv4_Rx) &&
4508: (pkttype_eth == RXDESC_TYPE_PKTTYPE_ETHER_IPV4) &&
4509: __SHIFTOUT(rxd_type,
4510: RXDESC_TYPE_IPV4_CSUM_CHECKED)) {
4511: m0->m_pkthdr.csum_flags |= M_CSUM_IPv4;
4512: if (__SHIFTOUT(rxd_status,
4513: RXDESC_STATUS_IPV4_CSUM_NG))
4514: m0->m_pkthdr.csum_flags |=
4515: M_CSUM_IPv4_BAD;
4516: }
1.21 ryo 4517:
1.1 ryo 4518: /*
1.21 ryo 4519: * aq will always mark BAD for fragment packets,
4520: * but this is not a problem because the IP stack
4521: * ignores the CSUM flag in fragment packets.
1.1 ryo 4522: */
4523: if (__SHIFTOUT(rxd_type,
4524: RXDESC_TYPE_TCPUDP_CSUM_CHECKED)) {
4525: bool checked = false;
4526: unsigned int pkttype_proto =
4527: __SHIFTOUT(rxd_type,
4528: RXDESC_TYPE_PKTTYPE_PROTO);
4529:
4530: if (pkttype_proto ==
4531: RXDESC_TYPE_PKTTYPE_PROTO_TCP) {
4532: if ((pkttype_eth ==
4533: RXDESC_TYPE_PKTTYPE_ETHER_IPV4) &&
4534: (ifp->if_capabilities &
4535: IFCAP_CSUM_TCPv4_Rx)) {
4536: m0->m_pkthdr.csum_flags |=
4537: M_CSUM_TCPv4;
4538: checked = true;
4539: } else if ((pkttype_eth ==
4540: RXDESC_TYPE_PKTTYPE_ETHER_IPV6) &&
4541: (ifp->if_capabilities &
4542: IFCAP_CSUM_TCPv6_Rx)) {
4543: m0->m_pkthdr.csum_flags |=
4544: M_CSUM_TCPv6;
4545: checked = true;
4546: }
4547: } else if (pkttype_proto ==
4548: RXDESC_TYPE_PKTTYPE_PROTO_UDP) {
4549: if ((pkttype_eth ==
4550: RXDESC_TYPE_PKTTYPE_ETHER_IPV4) &&
4551: (ifp->if_capabilities &
4552: IFCAP_CSUM_UDPv4_Rx)) {
4553: m0->m_pkthdr.csum_flags |=
4554: M_CSUM_UDPv4;
4555: checked = true;
4556: } else if ((pkttype_eth ==
4557: RXDESC_TYPE_PKTTYPE_ETHER_IPV6) &&
4558: (ifp->if_capabilities &
4559: IFCAP_CSUM_UDPv6_Rx)) {
4560: m0->m_pkthdr.csum_flags |=
4561: M_CSUM_UDPv6;
4562: checked = true;
4563: }
4564: }
4565: if (checked &&
4566: (__SHIFTOUT(rxd_status,
4567: RXDESC_STATUS_TCPUDP_CSUM_ERROR) ||
4568: !__SHIFTOUT(rxd_status,
4569: RXDESC_STATUS_TCPUDP_CSUM_OK))) {
4570: m0->m_pkthdr.csum_flags |=
4571: M_CSUM_TCP_UDP_BAD;
4572: }
4573: }
1.21 ryo 4574:
1.1 ryo 4575: m_set_rcvif(m0, ifp);
1.6 thorpej 4576: if_statinc_ref(nsr, if_ipackets);
4577: if_statadd_ref(nsr, if_ibytes, m0->m_pkthdr.len);
1.1 ryo 4578: if_percpuq_enqueue(ifp->if_percpuq, m0);
4579: m0 = mprev = NULL;
4580: }
4581:
4582: rx_next:
1.28 ryo 4583: if (discarding && (rxd_status & RXDESC_STATUS_EOP) != 0)
4584: discarding = false;
4585:
1.1 ryo 4586: aq_rxring_reset_desc(sc, rxring, idx);
4587: AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(ringidx), idx);
4588: }
1.28 ryo 4589: /* save ring context */
1.1 ryo 4590: rxring->rxr_readidx = idx;
1.28 ryo 4591: rxring->rxr_discarding = discarding;
4592: rxring->rxr_receiving_m = m0;
4593: rxring->rxr_receiving_m_last = mprev;
1.1 ryo 4594:
1.6 thorpej 4595: IF_STAT_PUTREF(ifp);
4596:
1.1 ryo 4597: rx_intr_done:
4598: mutex_exit(&rxring->rxr_mutex);
4599:
4600: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_rx_irq[ringidx]));
4601: return n;
4602: }
4603:
4604: static int
1.10 ryo 4605: aq_vlan_cb(struct ethercom *ec, uint16_t vid, bool set)
4606: {
4607: struct ifnet *ifp = &ec->ec_if;
1.32 skrll 4608: struct aq_softc * const sc = ifp->if_softc;
1.10 ryo 4609:
4610: aq_set_vlan_filters(sc);
4611: return 0;
4612: }
4613:
4614: static int
1.1 ryo 4615: aq_ifflags_cb(struct ethercom *ec)
4616: {
1.32 skrll 4617: struct ifnet * const ifp = &ec->ec_if;
4618: struct aq_softc * const sc = ifp->if_softc;
1.1 ryo 4619: int i, ecchange, error = 0;
4620: unsigned short iffchange;
4621:
4622: AQ_LOCK(sc);
4623:
4624: iffchange = ifp->if_flags ^ sc->sc_if_flags;
4625: if ((iffchange & IFF_PROMISC) != 0)
4626: error = aq_set_filter(sc);
4627:
4628: ecchange = ec->ec_capenable ^ sc->sc_ec_capenable;
4629: if (ecchange & ETHERCAP_VLAN_HWTAGGING) {
4630: for (i = 0; i < AQ_RINGS_NUM; i++) {
4631: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(i),
4632: RX_DMA_DESC_VLAN_STRIP,
4633: (ec->ec_capenable & ETHERCAP_VLAN_HWTAGGING) ?
4634: 1 : 0);
4635: }
4636: }
4637:
1.10 ryo 4638: /* vlan configuration depends on also interface promiscuous mode */
4639: if ((ecchange & ETHERCAP_VLAN_HWFILTER) || (iffchange & IFF_PROMISC))
4640: aq_set_vlan_filters(sc);
4641:
1.1 ryo 4642: sc->sc_ec_capenable = ec->ec_capenable;
4643: sc->sc_if_flags = ifp->if_flags;
4644:
4645: AQ_UNLOCK(sc);
4646:
4647: return error;
4648: }
4649:
1.33 skrll 4650:
1.1 ryo 4651: static int
4652: aq_init(struct ifnet *ifp)
4653: {
1.32 skrll 4654: struct aq_softc * const sc = ifp->if_softc;
1.33 skrll 4655:
4656: AQ_LOCK(sc);
4657:
4658: int ret = aq_init_locked(ifp);
4659:
4660: AQ_UNLOCK(sc);
4661:
4662: return ret;
4663: }
4664:
4665: static int
4666: aq_init_locked(struct ifnet *ifp)
4667: {
4668: struct aq_softc * const sc = ifp->if_softc;
1.1 ryo 4669: int i, error = 0;
4670:
1.33 skrll 4671: KASSERT(IFNET_LOCKED(ifp));
4672: AQ_LOCKED(sc);
1.22 ryo 4673:
1.33 skrll 4674: aq_stop_locked(ifp, false);
1.1 ryo 4675:
1.10 ryo 4676: aq_set_vlan_filters(sc);
1.1 ryo 4677: aq_set_capability(sc);
4678:
4679: for (i = 0; i < sc->sc_nqueues; i++) {
4680: aq_txring_reset(sc, &sc->sc_queue[i].txring, true);
4681: }
4682:
4683: /* invalidate RX descriptor cache */
4684: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT,
4685: AQ_READ_REG_BIT(sc,
4686: RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT) ^ 1);
4687:
4688: /* start RX */
4689: for (i = 0; i < sc->sc_nqueues; i++) {
4690: error = aq_rxring_reset(sc, &sc->sc_queue[i].rxring, true);
4691: if (error != 0) {
4692: device_printf(sc->sc_dev, "%s: cannot allocate rxbuf\n",
4693: __func__);
4694: goto aq_init_failure;
4695: }
4696: }
4697: aq_init_rss(sc);
4698: aq_hw_l3_filter_set(sc);
4699:
1.33 skrll 4700: /* ring reset? */
4701: aq_unset_stopping_flags(sc);
4702:
4703: callout_schedule(&sc->sc_tick_ch, hz);
1.1 ryo 4704:
4705: /* ready */
4706: ifp->if_flags |= IFF_RUNNING;
4707:
4708: /* start TX and RX */
1.37 riastrad 4709: aq_enable_intr(sc, /*link*/true, /*txrx*/true);
1.1 ryo 4710: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_EN, 1);
4711: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 1);
4712:
4713: aq_init_failure:
4714: sc->sc_if_flags = ifp->if_flags;
4715:
4716: return error;
4717: }
4718:
4719: static void
4720: aq_send_common_locked(struct ifnet *ifp, struct aq_softc *sc,
4721: struct aq_txring *txring, bool is_transmit)
4722: {
4723: struct mbuf *m;
4724: int npkt, error;
4725:
1.33 skrll 4726: if (txring->txr_nfree < AQ_TXD_MIN)
1.1 ryo 4727: return;
4728:
4729: for (npkt = 0; ; npkt++) {
4730: if (is_transmit)
4731: m = pcq_peek(txring->txr_pcq);
4732: else
4733: IFQ_POLL(&ifp->if_snd, m);
4734:
4735: if (m == NULL)
4736: break;
4737:
4738: if (is_transmit)
4739: pcq_get(txring->txr_pcq);
4740: else
4741: IFQ_DEQUEUE(&ifp->if_snd, m);
4742:
4743: error = aq_encap_txring(sc, txring, &m);
4744: if (error != 0) {
4745: /* too many mbuf chains? or not enough descriptors? */
4746: m_freem(m);
1.6 thorpej 4747: if_statinc(ifp, if_oerrors);
1.1 ryo 4748: break;
4749: }
4750:
4751: /* update tail ptr */
4752: AQ_WRITE_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(txring->txr_index),
4753: txring->txr_prodidx);
4754:
4755: /* Pass the packet to any BPF listeners */
4756: bpf_mtap(ifp, m, BPF_D_OUT);
4757: }
4758:
1.33 skrll 4759: if (npkt) {
4760: /* Set a watchdog timer in case the chip flakes out. */
4761: txring->txr_lastsent = time_uptime;
4762: txring->txr_sending = true;
4763: }
1.1 ryo 4764: }
4765:
4766: static void
4767: aq_start(struct ifnet *ifp)
4768: {
1.32 skrll 4769: struct aq_softc * const sc = ifp->if_softc;
4770: /* aq_start() always use TX ring[0] */
4771: struct aq_txring * const txring = &sc->sc_queue[0].txring;
1.1 ryo 4772:
4773: mutex_enter(&txring->txr_mutex);
1.33 skrll 4774: if (txring->txr_active && !txring->txr_stopping)
1.1 ryo 4775: aq_send_common_locked(ifp, sc, txring, false);
4776: mutex_exit(&txring->txr_mutex);
4777: }
4778:
4779: static inline unsigned int
4780: aq_select_txqueue(struct aq_softc *sc, struct mbuf *m)
4781: {
4782: return (cpu_index(curcpu()) % sc->sc_nqueues);
4783: }
4784:
4785: static int
4786: aq_transmit(struct ifnet *ifp, struct mbuf *m)
4787: {
1.32 skrll 4788: struct aq_softc * const sc = ifp->if_softc;
4789: const int ringidx = aq_select_txqueue(sc, m);
4790: struct aq_txring * const txring = &sc->sc_queue[ringidx].txring;
1.1 ryo 4791:
4792: if (__predict_false(!pcq_put(txring->txr_pcq, m))) {
4793: m_freem(m);
4794: return ENOBUFS;
4795: }
4796:
4797: if (mutex_tryenter(&txring->txr_mutex)) {
4798: aq_send_common_locked(ifp, sc, txring, true);
4799: mutex_exit(&txring->txr_mutex);
4800: } else {
4801: softint_schedule(txring->txr_softint);
4802: }
4803: return 0;
4804: }
4805:
4806: static void
4807: aq_deferred_transmit(void *arg)
4808: {
1.32 skrll 4809: struct aq_txring * const txring = arg;
4810: struct aq_softc * const sc = txring->txr_sc;
4811: struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
1.1 ryo 4812:
4813: mutex_enter(&txring->txr_mutex);
4814: if (pcq_peek(txring->txr_pcq) != NULL)
4815: aq_send_common_locked(ifp, sc, txring, true);
4816: mutex_exit(&txring->txr_mutex);
4817: }
4818:
1.33 skrll 4819:
4820: static void
4821: aq_unset_stopping_flags(struct aq_softc *sc)
4822: {
4823:
4824: AQ_LOCKED(sc);
4825:
4826: /* Must unset stopping flags in ascending order. */
1.40 ryo 4827: for (int i = 0; i < sc->sc_nqueues; i++) {
1.33 skrll 4828: struct aq_txring *txr = &sc->sc_queue[i].txring;
4829: struct aq_rxring *rxr = &sc->sc_queue[i].rxring;
4830:
4831: mutex_enter(&txr->txr_mutex);
4832: txr->txr_stopping = false;
4833: mutex_exit(&txr->txr_mutex);
4834:
4835: mutex_enter(&rxr->rxr_mutex);
4836: rxr->rxr_stopping = false;
4837: mutex_exit(&rxr->rxr_mutex);
4838: }
4839:
4840: sc->sc_stopping = false;
4841: }
4842:
4843: static void
4844: aq_set_stopping_flags(struct aq_softc *sc)
4845: {
4846:
4847: AQ_LOCKED(sc);
4848:
4849: /* Must unset stopping flags in ascending order. */
1.40 ryo 4850: for (int i = 0; i < sc->sc_nqueues; i++) {
1.33 skrll 4851: struct aq_txring *txr = &sc->sc_queue[i].txring;
4852: struct aq_rxring *rxr = &sc->sc_queue[i].rxring;
4853:
4854: mutex_enter(&txr->txr_mutex);
4855: txr->txr_stopping = true;
4856: mutex_exit(&txr->txr_mutex);
4857:
4858: mutex_enter(&rxr->rxr_mutex);
4859: rxr->rxr_stopping = true;
4860: mutex_exit(&rxr->rxr_mutex);
4861: }
4862:
4863: sc->sc_stopping = true;
4864: }
4865:
4866:
1.1 ryo 4867: static void
4868: aq_stop(struct ifnet *ifp, int disable)
4869: {
1.32 skrll 4870: struct aq_softc * const sc = ifp->if_softc;
1.33 skrll 4871:
4872: ASSERT_SLEEPABLE();
4873: KASSERT(IFNET_LOCKED(ifp));
4874:
4875: AQ_LOCK(sc);
4876: aq_stop_locked(ifp, disable ? true : false);
4877: AQ_UNLOCK(sc);
4878: }
4879:
4880:
4881:
4882: static void
4883: aq_stop_locked(struct ifnet *ifp, bool disable)
4884: {
4885: struct aq_softc * const sc = ifp->if_softc;
1.1 ryo 4886: int i;
4887:
1.33 skrll 4888: KASSERT(IFNET_LOCKED(ifp));
4889: AQ_LOCKED(sc);
1.1 ryo 4890:
1.33 skrll 4891: aq_set_stopping_flags(sc);
1.1 ryo 4892:
1.22 ryo 4893: if ((ifp->if_flags & IFF_RUNNING) == 0)
4894: goto already_stopped;
4895:
1.1 ryo 4896: /* disable tx/rx interrupts */
1.37 riastrad 4897: aq_enable_intr(sc, /*link*/true, /*txrx*/false);
1.1 ryo 4898:
4899: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_EN, 0);
4900: for (i = 0; i < sc->sc_nqueues; i++) {
4901: aq_txring_reset(sc, &sc->sc_queue[i].txring, false);
4902: }
4903:
4904: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 0);
4905: for (i = 0; i < sc->sc_nqueues; i++) {
4906: aq_rxring_reset(sc, &sc->sc_queue[i].rxring, false);
4907: }
4908:
4909: /* invalidate RX descriptor cache */
4910: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT,
4911: AQ_READ_REG_BIT(sc,
4912: RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT) ^ 1);
4913:
1.22 ryo 4914: already_stopped:
1.37 riastrad 4915: aq_enable_intr(sc, /*link*/false, /*txrx*/false);
1.36 riastrad 4916: callout_halt(&sc->sc_tick_ch, &sc->sc_mutex);
1.1 ryo 4917:
1.33 skrll 4918: ifp->if_flags &= ~IFF_RUNNING;
4919: sc->sc_if_flags = ifp->if_flags;
4920: }
1.1 ryo 4921:
4922:
4923: static void
1.33 skrll 4924: aq_handle_reset_work(struct work *work, void *arg)
1.1 ryo 4925: {
1.33 skrll 4926: struct aq_softc * const sc = arg;
4927: struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
4928:
4929: printf("%s: watchdog timeout -- resetting\n", ifp->if_xname);
1.1 ryo 4930:
4931: AQ_LOCK(sc);
4932:
4933: device_printf(sc->sc_dev, "%s: INTR_MASK/STATUS = %08x/%08x\n",
4934: __func__, AQ_READ_REG(sc, AQ_INTR_MASK_REG),
4935: AQ_READ_REG(sc, AQ_INTR_STATUS_REG));
4936:
1.40 ryo 4937: for (int n = 0; n < sc->sc_nqueues; n++) {
1.33 skrll 4938: struct aq_txring *txring = &sc->sc_queue[n].txring;
4939: u_int head = AQ_READ_REG_BIT(sc,
1.1 ryo 4940: TX_DMA_DESC_HEAD_PTR_REG(txring->txr_index),
1.33 skrll 4941: TX_DMA_DESC_HEAD_PTR);
4942: u_int tail = AQ_READ_REG(sc,
1.1 ryo 4943: TX_DMA_DESC_TAIL_PTR_REG(txring->txr_index));
4944:
1.33 skrll 4945: device_printf(sc->sc_dev, "%s: TXring[%u] HEAD/TAIL=%u/%u\n",
1.1 ryo 4946: __func__, txring->txr_index, head, tail);
4947:
4948: aq_tx_intr(txring);
4949: }
4950:
4951: AQ_UNLOCK(sc);
4952:
1.33 skrll 4953: /* Don't want ioctl operations to happen */
4954: IFNET_LOCK(ifp);
4955:
4956: /* reset the interface. */
1.1 ryo 4957: aq_init(ifp);
1.33 skrll 4958:
4959: IFNET_UNLOCK(ifp);
4960:
4961: atomic_store_relaxed(&sc->sc_reset_pending, 0);
1.1 ryo 4962: }
4963:
4964: static int
4965: aq_ioctl(struct ifnet *ifp, unsigned long cmd, void *data)
4966: {
1.32 skrll 4967: struct aq_softc * const sc = ifp->if_softc;
4968: struct ifreq * const ifr = data;
4969: int error = 0;
1.1 ryo 4970:
1.33 skrll 4971: switch (cmd) {
4972: case SIOCADDMULTI:
4973: case SIOCDELMULTI:
4974: break;
4975: default:
4976: KASSERT(IFNET_LOCKED(ifp));
4977: }
4978:
1.32 skrll 4979: const int s = splnet();
1.23 ryo 4980: switch (cmd) {
4981: case SIOCSIFMTU:
4982: if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > sc->sc_max_mtu) {
4983: error = EINVAL;
4984: } else {
4985: ifp->if_mtu = ifr->ifr_mtu;
4986: error = 0; /* no need to reset (no ENETRESET) */
4987: }
4988: break;
4989: default:
4990: error = ether_ioctl(ifp, cmd, data);
4991: break;
4992: }
1.1 ryo 4993: splx(s);
4994:
4995: if (error != ENETRESET)
4996: return error;
4997:
4998: switch (cmd) {
4999: case SIOCSIFCAP:
5000: error = aq_set_capability(sc);
5001: break;
5002: case SIOCADDMULTI:
5003: case SIOCDELMULTI:
1.33 skrll 5004: AQ_LOCK(sc);
5005: if ((sc->sc_if_flags & IFF_RUNNING) != 0) {
1.42 ! ryo 5006: /*
! 5007: * Multicast list has changed; set the hardware filter
! 5008: * accordingly.
! 5009: */
1.33 skrll 5010: error = aq_set_filter(sc);
5011: }
5012: AQ_UNLOCK(sc);
1.1 ryo 5013: break;
5014: }
5015:
5016: return error;
5017: }
5018:
5019:
5020: MODULE(MODULE_CLASS_DRIVER, if_aq, "pci");
5021:
5022: #ifdef _MODULE
5023: #include "ioconf.c"
5024: #endif
5025:
5026: static int
5027: if_aq_modcmd(modcmd_t cmd, void *opaque)
5028: {
5029: int error = 0;
5030:
5031: switch (cmd) {
5032: case MODULE_CMD_INIT:
5033: #ifdef _MODULE
5034: error = config_init_component(cfdriver_ioconf_if_aq,
5035: cfattach_ioconf_if_aq, cfdata_ioconf_if_aq);
5036: #endif
5037: return error;
5038: case MODULE_CMD_FINI:
5039: #ifdef _MODULE
5040: error = config_fini_component(cfdriver_ioconf_if_aq,
5041: cfattach_ioconf_if_aq, cfdata_ioconf_if_aq);
5042: #endif
5043: return error;
5044: default:
5045: return ENOTTY;
5046: }
5047: }
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