Annotation of src/sys/dev/pci/if_aq.c, Revision 1.23
1.23 ! ryo 1: /* $NetBSD: if_aq.c,v 1.22 2021/04/15 09:04:42 ryo Exp $ */
1.1 ryo 2:
3: /**
4: * aQuantia Corporation Network Driver
5: * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: *
11: * (1) Redistributions of source code must retain the above
12: * copyright notice, this list of conditions and the following
13: * disclaimer.
14: *
15: * (2) Redistributions in binary form must reproduce the above
16: * copyright notice, this list of conditions and the following
17: * disclaimer in the documentation and/or other materials provided
18: * with the distribution.
19: *
20: * (3) The name of the author may not be used to endorse or promote
21: * products derived from this software without specific prior
22: * written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
25: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
28: * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
30: * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33: * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34: * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35: *
36: */
37:
38: /*-
39: * Copyright (c) 2020 Ryo Shimizu <ryo@nerv.org>
40: * All rights reserved.
41: *
42: * Redistribution and use in source and binary forms, with or without
43: * modification, are permitted provided that the following conditions
44: * are met:
45: * 1. Redistributions of source code must retain the above copyright
46: * notice, this list of conditions and the following disclaimer.
47: * 2. Redistributions in binary form must reproduce the above copyright
48: * notice, this list of conditions and the following disclaimer in the
49: * documentation and/or other materials provided with the distribution.
50: *
51: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
52: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
53: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
54: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
55: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
56: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
57: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
58: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
59: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
60: * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
61: * POSSIBILITY OF SUCH DAMAGE.
62: */
63:
64: #include <sys/cdefs.h>
1.23 ! ryo 65: __KERNEL_RCSID(0, "$NetBSD: if_aq.c,v 1.22 2021/04/15 09:04:42 ryo Exp $");
1.1 ryo 66:
67: #ifdef _KERNEL_OPT
68: #include "opt_if_aq.h"
1.4 ryo 69: #include "sysmon_envsys.h"
1.1 ryo 70: #endif
71:
72: #include <sys/param.h>
73: #include <sys/types.h>
74: #include <sys/bitops.h>
75: #include <sys/cprng.h>
76: #include <sys/cpu.h>
77: #include <sys/interrupt.h>
78: #include <sys/module.h>
79: #include <sys/pcq.h>
80:
81: #include <net/bpf.h>
82: #include <net/if.h>
83: #include <net/if_dl.h>
84: #include <net/if_media.h>
85: #include <net/if_ether.h>
86: #include <net/rss_config.h>
87:
88: #include <dev/pci/pcivar.h>
89: #include <dev/pci/pcireg.h>
90: #include <dev/pci/pcidevs.h>
1.4 ryo 91: #include <dev/sysmon/sysmonvar.h>
1.1 ryo 92:
93: /* driver configuration */
94: #define CONFIG_INTR_MODERATION_ENABLE true /* delayed interrupt */
95: #undef CONFIG_LRO_SUPPORT /* no LRO not suppoted */
96: #undef CONFIG_NO_TXRX_INDEPENDENT /* share TX/RX interrupts */
97:
98: #define AQ_NINTR_MAX (AQ_RSSQUEUE_MAX + AQ_RSSQUEUE_MAX + 1)
99: /* TX + RX + LINK. must be <= 32 */
100: #define AQ_LINKSTAT_IRQ 31 /* for legacy mode */
101:
102: #define AQ_TXD_NUM 2048 /* per ring. 8*n && 32~8184 */
103: #define AQ_RXD_NUM 2048 /* per ring. 8*n && 32~8184 */
104: /* minimum required to send a packet (vlan needs additional TX descriptor) */
105: #define AQ_TXD_MIN (1 + 1)
106:
107:
108: /* hardware specification */
109: #define AQ_RINGS_NUM 32
110: #define AQ_RSSQUEUE_MAX 8
111: #define AQ_RX_DESCRIPTOR_MIN 32
112: #define AQ_TX_DESCRIPTOR_MIN 32
113: #define AQ_RX_DESCRIPTOR_MAX 8184
114: #define AQ_TX_DESCRIPTOR_MAX 8184
115: #define AQ_TRAFFICCLASS_NUM 8
116: #define AQ_RSS_HASHKEY_SIZE 40
117: #define AQ_RSS_INDIRECTION_TABLE_MAX 64
118:
1.23 ! ryo 119: #define AQ_JUMBO_MTU_REV_A 9000
! 120: #define AQ_JUMBO_MTU_REV_B 16338
! 121:
1.1 ryo 122: /*
123: * TERMINOLOGY
124: * MPI = MAC PHY INTERFACE?
125: * RPO = RX Protocol Offloading
126: * TPO = TX Protocol Offloading
127: * RPF = RX Packet Filter
128: * TPB = TX Packet buffer
129: * RPB = RX Packet buffer
130: */
131:
132: /* registers */
133: #define AQ_FW_SOFTRESET_REG 0x0000
134: #define AQ_FW_SOFTRESET_RESET __BIT(15) /* soft reset bit */
135: #define AQ_FW_SOFTRESET_DIS __BIT(14) /* reset disable */
136:
137: #define AQ_FW_VERSION_REG 0x0018
138: #define AQ_HW_REVISION_REG 0x001c
139: #define AQ_GLB_NVR_INTERFACE1_REG 0x0100
140:
141: #define AQ_FW_MBOX_CMD_REG 0x0200
142: #define AQ_FW_MBOX_CMD_EXECUTE 0x00008000
143: #define AQ_FW_MBOX_CMD_BUSY 0x00000100
144: #define AQ_FW_MBOX_ADDR_REG 0x0208
145: #define AQ_FW_MBOX_VAL_REG 0x020c
146:
147: #define FW2X_LED_MIN_VERSION 0x03010026 /* >= 3.1.38 */
148: #define FW2X_LED_REG 0x031c
149: #define FW2X_LED_DEFAULT 0x00000000
150: #define FW2X_LED_NONE 0x0000003f
151: #define FW2X_LINKLED __BITS(0,1)
152: #define FW2X_LINKLED_ACTIVE 0
153: #define FW2X_LINKLED_ON 1
154: #define FW2X_LINKLED_BLINK 2
155: #define FW2X_LINKLED_OFF 3
156: #define FW2X_STATUSLED __BITS(2,5)
157: #define FW2X_STATUSLED_ORANGE 0
158: #define FW2X_STATUSLED_ORANGE_BLINK 2
159: #define FW2X_STATUSLED_OFF 3
160: #define FW2X_STATUSLED_GREEN 4
161: #define FW2X_STATUSLED_ORANGE_GREEN_BLINK 8
162: #define FW2X_STATUSLED_GREEN_BLINK 10
163:
164: #define FW_MPI_MBOX_ADDR_REG 0x0360
165: #define FW1X_MPI_INIT1_REG 0x0364
166: #define FW1X_MPI_CONTROL_REG 0x0368
167: #define FW1X_MPI_STATE_REG 0x036c
168: #define FW1X_MPI_STATE_MODE __BITS(7,0)
169: #define FW1X_MPI_STATE_SPEED __BITS(32,16)
170: #define FW1X_MPI_STATE_DISABLE_DIRTYWAKE __BITS(25)
171: #define FW1X_MPI_STATE_DOWNSHIFT __BITS(31,28)
172: #define FW1X_MPI_INIT2_REG 0x0370
173: #define FW1X_MPI_EFUSEADDR_REG 0x0374
174:
175: #define FW2X_MPI_EFUSEADDR_REG 0x0364
176: #define FW2X_MPI_CONTROL_REG 0x0368 /* 64bit */
177: #define FW2X_MPI_STATE_REG 0x0370 /* 64bit */
178: #define FW_BOOT_EXIT_CODE_REG 0x0388
179: #define RBL_STATUS_DEAD 0x0000dead
180: #define RBL_STATUS_SUCCESS 0x0000abba
181: #define RBL_STATUS_FAILURE 0x00000bad
182: #define RBL_STATUS_HOST_BOOT 0x0000f1a7
183:
184: #define AQ_FW_GLB_CPU_SEM_REG(i) (0x03a0 + (i) * 4)
185: #define AQ_FW_SEM_RAM_REG AQ_FW_GLB_CPU_SEM_REG(2)
186:
187: #define AQ_FW_GLB_CTL2_REG 0x0404
188: #define AQ_FW_GLB_CTL2_MCP_UP_FORCE_INTERRUPT __BIT(1)
189:
190: #define AQ_GLB_GENERAL_PROVISIONING9_REG 0x0520
191: #define AQ_GLB_NVR_PROVISIONING2_REG 0x0534
192:
193: #define FW_MPI_DAISY_CHAIN_STATUS_REG 0x0704
194:
195: #define AQ_PCI_REG_CONTROL_6_REG 0x1014
196:
197: // msix bitmap */
198: #define AQ_INTR_STATUS_REG 0x2000 /* intr status */
199: #define AQ_INTR_STATUS_CLR_REG 0x2050 /* intr status clear */
200: #define AQ_INTR_MASK_REG 0x2060 /* intr mask set */
201: #define AQ_INTR_MASK_CLR_REG 0x2070 /* intr mask clear */
202: #define AQ_INTR_AUTOMASK_REG 0x2090
203:
204: /* AQ_INTR_IRQ_MAP_TXRX_REG[AQ_RINGS_NUM] 0x2100-0x2140 */
205: #define AQ_INTR_IRQ_MAP_TXRX_REG(i) (0x2100 + ((i) / 2) * 4)
206: #define AQ_INTR_IRQ_MAP_TX_REG(i) AQ_INTR_IRQ_MAP_TXRX_REG(i)
207: #define AQ_INTR_IRQ_MAP_TX_IRQMAP(i) (__BITS(28,24) >> (((i) & 1)*8))
208: #define AQ_INTR_IRQ_MAP_TX_EN(i) (__BIT(31) >> (((i) & 1)*8))
209: #define AQ_INTR_IRQ_MAP_RX_REG(i) AQ_INTR_IRQ_MAP_TXRX_REG(i)
210: #define AQ_INTR_IRQ_MAP_RX_IRQMAP(i) (__BITS(12,8) >> (((i) & 1)*8))
211: #define AQ_INTR_IRQ_MAP_RX_EN(i) (__BIT(15) >> (((i) & 1)*8))
212:
213: /* AQ_GEN_INTR_MAP_REG[AQ_RINGS_NUM] 0x2180-0x2200 */
214: #define AQ_GEN_INTR_MAP_REG(i) (0x2180 + (i) * 4)
1.5 msaitoh 215: #define AQ_B0_ERR_INT 8U
1.1 ryo 216:
217: #define AQ_INTR_CTRL_REG 0x2300
218: #define AQ_INTR_CTRL_IRQMODE __BITS(1,0)
219: #define AQ_INTR_CTRL_IRQMODE_LEGACY 0
220: #define AQ_INTR_CTRL_IRQMODE_MSI 1
221: #define AQ_INTR_CTRL_IRQMODE_MSIX 2
222: #define AQ_INTR_CTRL_MULTIVEC __BIT(2)
223: #define AQ_INTR_CTRL_AUTO_MASK __BIT(5)
224: #define AQ_INTR_CTRL_CLR_ON_READ __BIT(7)
225: #define AQ_INTR_CTRL_RESET_DIS __BIT(29)
226: #define AQ_INTR_CTRL_RESET_IRQ __BIT(31)
227:
228: #define AQ_MBOXIF_POWER_GATING_CONTROL_REG 0x32a8
229:
230: #define FW_MPI_RESETCTRL_REG 0x4000
231: #define FW_MPI_RESETCTRL_RESET_DIS __BIT(29)
232:
233: #define RX_SYSCONTROL_REG 0x5000
234: #define RX_SYSCONTROL_RPB_DMA_LOOPBACK __BIT(6)
235: #define RX_SYSCONTROL_RPF_TPO_LOOPBACK __BIT(8)
236: #define RX_SYSCONTROL_RESET_DIS __BIT(29)
237:
238: #define RX_TCP_RSS_HASH_REG 0x5040
239: #define RX_TCP_RSS_HASH_RPF2 __BITS(19,16)
240: #define RX_TCP_RSS_HASH_TYPE __BITS(15,0)
241:
242: /* for RPF_*_REG.ACTION */
243: #define RPF_ACTION_DISCARD 0
244: #define RPF_ACTION_HOST 1
245: #define RPF_ACTION_MANAGEMENT 2
246: #define RPF_ACTION_HOST_MANAGEMENT 3
247: #define RPF_ACTION_WOL 4
248:
249: #define RPF_L2BC_REG 0x5100
250: #define RPF_L2BC_EN __BIT(0)
251: #define RPF_L2BC_PROMISC __BIT(3)
252: #define RPF_L2BC_ACTION __BITS(12,14)
253: #define RPF_L2BC_THRESHOLD __BITS(31,16)
254:
255: /* RPF_L2UC_*_REG[34] (actual [38]?) */
256: #define RPF_L2UC_LSW_REG(i) (0x5110 + (i) * 8)
257: #define RPF_L2UC_MSW_REG(i) (0x5114 + (i) * 8)
258: #define RPF_L2UC_MSW_MACADDR_HI __BITS(15,0)
259: #define RPF_L2UC_MSW_ACTION __BITS(18,16)
260: #define RPF_L2UC_MSW_EN __BIT(31)
261: #define AQ_HW_MAC_OWN 0 /* index of own address */
262: #define AQ_HW_MAC_NUM 34
263:
1.9 ryo 264: /* RPF_MCAST_FILTER_REG[8] 0x5250-0x5270 */
1.1 ryo 265: #define RPF_MCAST_FILTER_REG(i) (0x5250 + (i) * 4)
266: #define RPF_MCAST_FILTER_EN __BIT(31)
267: #define RPF_MCAST_FILTER_MASK_REG 0x5270
268: #define RPF_MCAST_FILTER_MASK_ALLMULTI __BIT(14)
269:
270: #define RPF_VLAN_MODE_REG 0x5280
271: #define RPF_VLAN_MODE_PROMISC __BIT(1)
272: #define RPF_VLAN_MODE_ACCEPT_UNTAGGED __BIT(2)
273: #define RPF_VLAN_MODE_UNTAGGED_ACTION __BITS(5,3)
274:
275: #define RPF_VLAN_TPID_REG 0x5284
276: #define RPF_VLAN_TPID_OUTER __BITS(31,16)
277: #define RPF_VLAN_TPID_INNER __BITS(15,0)
278:
1.9 ryo 279: /* RPF_VLAN_FILTER_REG[RPF_VLAN_MAX_FILTERS] 0x5290-0x52d0 */
1.1 ryo 280: #define RPF_VLAN_MAX_FILTERS 16
281: #define RPF_VLAN_FILTER_REG(i) (0x5290 + (i) * 4)
282: #define RPF_VLAN_FILTER_EN __BIT(31)
283: #define RPF_VLAN_FILTER_RXQ_EN __BIT(28)
284: #define RPF_VLAN_FILTER_RXQ __BITS(24,20)
285: #define RPF_VLAN_FILTER_ACTION __BITS(18,16)
286: #define RPF_VLAN_FILTER_ID __BITS(11,0)
287:
288: /* RPF_ETHERTYPE_FILTER_REG[AQ_RINGS_NUM] 0x5300-0x5380 */
289: #define RPF_ETHERTYPE_FILTER_REG(i) (0x5300 + (i) * 4)
290: #define RPF_ETHERTYPE_FILTER_EN __BIT(31)
291: #define RPF_ETHERTYPE_FILTER_PRIO_EN __BIT(30)
292: #define RPF_ETHERTYPE_FILTER_RXQF_EN __BIT(29)
293: #define RPF_ETHERTYPE_FILTER_PRIO __BITS(28,26)
294: #define RPF_ETHERTYPE_FILTER_RXQF __BITS(24,20)
295: #define RPF_ETHERTYPE_FILTER_MNG_RXQF __BIT(19)
296: #define RPF_ETHERTYPE_FILTER_ACTION __BITS(18,16)
297: #define RPF_ETHERTYPE_FILTER_VAL __BITS(15,0)
298:
299: /* RPF_L3_FILTER_REG[8] 0x5380-0x53a0 */
300: #define RPF_L3_FILTER_REG(i) (0x5380 + (i) * 4)
301: #define RPF_L3_FILTER_L4_EN __BIT(31)
302: #define RPF_L3_FILTER_IPV6_EN __BIT(30)
303: #define RPF_L3_FILTER_SRCADDR_EN __BIT(29)
304: #define RPF_L3_FILTER_DSTADDR_EN __BIT(28)
305: #define RPF_L3_FILTER_L4_SRCPORT_EN __BIT(27)
306: #define RPF_L3_FILTER_L4_DSTPORT_EN __BIT(26)
307: #define RPF_L3_FILTER_L4_PROTO_EN __BIT(25)
308: #define RPF_L3_FILTER_ARP_EN __BIT(24)
309: #define RPF_L3_FILTER_L4_RXQUEUE_EN __BIT(23)
310: #define RPF_L3_FILTER_L4_RXQUEUE_MANAGEMENT_EN __BIT(22)
311: #define RPF_L3_FILTER_L4_ACTION __BITS(16,18)
312: #define RPF_L3_FILTER_L4_RXQUEUE __BITS(12,8)
313: #define RPF_L3_FILTER_L4_PROTO __BITS(2,0)
314: #define RPF_L3_FILTER_L4_PROTO_TCP 0
315: #define RPF_L3_FILTER_L4_PROTO_UDP 1
316: #define RPF_L3_FILTER_L4_PROTO_SCTP 2
317: #define RPF_L3_FILTER_L4_PROTO_ICMP 3
318: /* parameters of RPF_L3_FILTER_REG[8] */
319: #define RPF_L3_FILTER_SRCADDR_REG(i) (0x53b0 + (i) * 4)
320: #define RPF_L3_FILTER_DSTADDR_REG(i) (0x53d0 + (i) * 4)
321: #define RPF_L3_FILTER_L4_SRCPORT_REG(i) (0x5400 + (i) * 4)
322: #define RPF_L3_FILTER_L4_DSTPORT_REG(i) (0x5420 + (i) * 4)
323:
324: #define RX_FLR_RSS_CONTROL1_REG 0x54c0
325: #define RX_FLR_RSS_CONTROL1_EN __BIT(31)
326:
327: #define RPF_RPB_RX_TC_UPT_REG 0x54c4
328: #define RPF_RPB_RX_TC_UPT_MASK(i) (0x00000007 << ((i) * 4))
329:
330: #define RPF_RSS_KEY_ADDR_REG 0x54d0
331: #define RPF_RSS_KEY_ADDR __BITS(4,0)
332: #define RPF_RSS_KEY_WR_EN __BIT(5)
333: #define RPF_RSS_KEY_WR_DATA_REG 0x54d4
334: #define RPF_RSS_KEY_RD_DATA_REG 0x54d8
335:
336: #define RPF_RSS_REDIR_ADDR_REG 0x54e0
337: #define RPF_RSS_REDIR_ADDR __BITS(3,0)
338: #define RPF_RSS_REDIR_WR_EN __BIT(4)
339:
340: #define RPF_RSS_REDIR_WR_DATA_REG 0x54e4
341: #define RPF_RSS_REDIR_WR_DATA __BITS(15,0)
342:
343: #define RPO_HWCSUM_REG 0x5580
344: #define RPO_HWCSUM_IP4CSUM_EN __BIT(1)
345: #define RPO_HWCSUM_L4CSUM_EN __BIT(0) /* TCP/UDP/SCTP */
346:
347: #define RPO_LRO_ENABLE_REG 0x5590
348:
349: #define RPO_LRO_CONF_REG 0x5594
350: #define RPO_LRO_CONF_QSESSION_LIMIT __BITS(13,12)
351: #define RPO_LRO_CONF_TOTAL_DESC_LIMIT __BITS(6,5)
352: #define RPO_LRO_CONF_PATCHOPTIMIZATION_EN __BIT(15)
353: #define RPO_LRO_CONF_MIN_PAYLOAD_OF_FIRST_PKT __BITS(4,0)
354: #define RPO_LRO_RSC_MAX_REG 0x5598
355:
356: /* RPO_LRO_LDES_MAX_REG[32/8] 0x55a0-0x55b0 */
357: #define RPO_LRO_LDES_MAX_REG(i) (0x55a0 + (i / 8) * 4)
358: #define RPO_LRO_LDES_MAX_MASK(i) (0x00000003 << ((i & 7) * 4))
359: #define RPO_LRO_TB_DIV_REG 0x5620
360: #define RPO_LRO_TB_DIV __BITS(20,31)
361: #define RPO_LRO_INACTIVE_IVAL_REG 0x5620
362: #define RPO_LRO_INACTIVE_IVAL __BITS(10,19)
363: #define RPO_LRO_MAX_COALESCING_IVAL_REG 0x5620
364: #define RPO_LRO_MAX_COALESCING_IVAL __BITS(9,0)
365:
366: #define RPB_RPF_RX_REG 0x5700
367: #define RPB_RPF_RX_TC_MODE __BIT(8)
368: #define RPB_RPF_RX_FC_MODE __BITS(5,4)
369: #define RPB_RPF_RX_BUF_EN __BIT(0)
370:
371: /* RPB_RXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x5710-0x5790 */
372: #define RPB_RXB_BUFSIZE_REG(i) (0x5710 + (i) * 0x10)
373: #define RPB_RXB_BUFSIZE __BITS(8,0)
374: #define RPB_RXB_XOFF_REG(i) (0x5714 + (i) * 0x10)
375: #define RPB_RXB_XOFF_EN __BIT(31)
376: #define RPB_RXB_XOFF_THRESH_HI __BITS(29,16)
377: #define RPB_RXB_XOFF_THRESH_LO __BITS(13,0)
378:
379: #define RX_DMA_DESC_CACHE_INIT_REG 0x5a00
380: #define RX_DMA_DESC_CACHE_INIT __BIT(0)
381:
382: #define RX_DMA_INT_DESC_WRWB_EN_REG 0x05a30
383: #define RX_DMA_INT_DESC_WRWB_EN __BIT(2)
384: #define RX_DMA_INT_DESC_MODERATE_EN __BIT(3)
385:
386: /* RX_INTR_MODERATION_CTL_REG[AQ_RINGS_NUM] 0x5a40-0x5ac0 */
387: #define RX_INTR_MODERATION_CTL_REG(i) (0x5a40 + (i) * 4)
388: #define RX_INTR_MODERATION_CTL_EN __BIT(1)
389: #define RX_INTR_MODERATION_CTL_MIN __BITS(15,8)
390: #define RX_INTR_MODERATION_CTL_MAX __BITS(24,16)
391:
392: /* RX_DMA_DESC_*[AQ_RINGS_NUM] 0x5b00-0x5f00 */
393: #define RX_DMA_DESC_BASE_ADDRLSW_REG(i) (0x5b00 + (i) * 0x20)
394: #define RX_DMA_DESC_BASE_ADDRMSW_REG(i) (0x5b04 + (i) * 0x20)
395: #define RX_DMA_DESC_REG(i) (0x5b08 + (i) * 0x20)
396: #define RX_DMA_DESC_LEN __BITS(12,3) /* RXD_NUM/8 */
397: #define RX_DMA_DESC_RESET __BIT(25)
398: #define RX_DMA_DESC_HEADER_SPLIT __BIT(28)
399: #define RX_DMA_DESC_VLAN_STRIP __BIT(29)
400: #define RX_DMA_DESC_EN __BIT(31)
401: #define RX_DMA_DESC_HEAD_PTR_REG(i) (0x5b0c + (i) * 0x20)
402: #define RX_DMA_DESC_HEAD_PTR __BITS(12,0)
403: #define RX_DMA_DESC_TAIL_PTR_REG(i) (0x5b10 + (i) * 0x20)
404: #define RX_DMA_DESC_BUFSIZE_REG(i) (0x5b18 + (i) * 0x20)
405: #define RX_DMA_DESC_BUFSIZE_DATA __BITS(4,0)
406: #define RX_DMA_DESC_BUFSIZE_HDR __BITS(12,8)
407:
408: /* RX_DMA_DCAD_REG[AQ_RINGS_NUM] 0x6100-0x6180 */
409: #define RX_DMA_DCAD_REG(i) (0x6100 + (i) * 4)
410: #define RX_DMA_DCAD_CPUID __BITS(7,0)
411: #define RX_DMA_DCAD_PAYLOAD_EN __BIT(29)
412: #define RX_DMA_DCAD_HEADER_EN __BIT(30)
413: #define RX_DMA_DCAD_DESC_EN __BIT(31)
414:
415: #define RX_DMA_DCA_REG 0x6180
416: #define RX_DMA_DCA_EN __BIT(31)
417: #define RX_DMA_DCA_MODE __BITS(3,0)
418:
419: /* counters */
420: #define RX_DMA_GOOD_PKT_COUNTERLSW 0x6800
421: #define RX_DMA_GOOD_OCTET_COUNTERLSW 0x6808
422: #define RX_DMA_DROP_PKT_CNT_REG 0x6818
423: #define RX_DMA_COALESCED_PKT_CNT_REG 0x6820
424:
425: #define TX_SYSCONTROL_REG 0x7000
426: #define TX_SYSCONTROL_TPB_DMA_LOOPBACK __BIT(6)
427: #define TX_SYSCONTROL_TPO_PKT_LOOPBACK __BIT(7)
428: #define TX_SYSCONTROL_RESET_DIS __BIT(29)
429:
430: #define TX_TPO2_REG 0x7040
431: #define TX_TPO2_EN __BIT(16)
432:
433: #define TPS_DESC_VM_ARB_MODE_REG 0x7300
434: #define TPS_DESC_VM_ARB_MODE __BIT(0)
435: #define TPS_DESC_RATE_REG 0x7310
436: #define TPS_DESC_RATE_TA_RST __BIT(31)
437: #define TPS_DESC_RATE_LIM __BITS(10,0)
438: #define TPS_DESC_TC_ARB_MODE_REG 0x7200
439: #define TPS_DESC_TC_ARB_MODE __BITS(1,0)
440: #define TPS_DATA_TC_ARB_MODE_REG 0x7100
441: #define TPS_DATA_TC_ARB_MODE __BIT(0)
442:
443: /* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7110-0x7130 */
444: #define TPS_DATA_TCT_REG(i) (0x7110 + (i) * 4)
445: #define TPS_DATA_TCT_CREDIT_MAX __BITS(16,27)
446: #define TPS_DATA_TCT_WEIGHT __BITS(8,0)
447: /* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7210-0x7230 */
448: #define TPS_DESC_TCT_REG(i) (0x7210 + (i) * 4)
449: #define TPS_DESC_TCT_CREDIT_MAX __BITS(16,27)
450: #define TPS_DESC_TCT_WEIGHT __BITS(8,0)
451:
452: #define AQ_HW_TXBUF_MAX 160
453: #define AQ_HW_RXBUF_MAX 320
454:
455: #define TPO_HWCSUM_REG 0x7800
456: #define TPO_HWCSUM_IP4CSUM_EN __BIT(1)
457: #define TPO_HWCSUM_L4CSUM_EN __BIT(0) /* TCP/UDP/SCTP */
458:
459: #define TDM_LSO_EN_REG 0x7810
460:
461: #define THM_LSO_TCP_FLAG1_REG 0x7820
462: #define THM_LSO_TCP_FLAG1_FIRST __BITS(11,0)
463: #define THM_LSO_TCP_FLAG1_MID __BITS(27,16)
464: #define THM_LSO_TCP_FLAG2_REG 0x7824
465: #define THM_LSO_TCP_FLAG2_LAST __BITS(11,0)
466:
467: #define TPB_TX_BUF_REG 0x7900
468: #define TPB_TX_BUF_EN __BIT(0)
469: #define TPB_TX_BUF_SCP_INS_EN __BIT(2)
470: #define TPB_TX_BUF_TC_MODE_EN __BIT(8)
471:
472: /* TPB_TXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x7910-7990 */
473: #define TPB_TXB_BUFSIZE_REG(i) (0x7910 + (i) * 0x10)
474: #define TPB_TXB_BUFSIZE __BITS(7,0)
475: #define TPB_TXB_THRESH_REG(i) (0x7914 + (i) * 0x10)
476: #define TPB_TXB_THRESH_HI __BITS(16,28)
477: #define TPB_TXB_THRESH_LO __BITS(12,0)
478:
479: #define AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG 0x7b20
480: #define TX_DMA_INT_DESC_WRWB_EN_REG 0x7b40
481: #define TX_DMA_INT_DESC_WRWB_EN __BIT(1)
482: #define TX_DMA_INT_DESC_MODERATE_EN __BIT(4)
483:
484: /* TX_DMA_DESC_*[AQ_RINGS_NUM] 0x7c00-0x8400 */
485: #define TX_DMA_DESC_BASE_ADDRLSW_REG(i) (0x7c00 + (i) * 0x40)
486: #define TX_DMA_DESC_BASE_ADDRMSW_REG(i) (0x7c04 + (i) * 0x40)
487: #define TX_DMA_DESC_REG(i) (0x7c08 + (i) * 0x40)
488: #define TX_DMA_DESC_LEN __BITS(12, 3) /* TXD_NUM/8 */
489: #define TX_DMA_DESC_EN __BIT(31)
490: #define TX_DMA_DESC_HEAD_PTR_REG(i) (0x7c0c + (i) * 0x40)
491: #define TX_DMA_DESC_HEAD_PTR __BITS(12,0)
492: #define TX_DMA_DESC_TAIL_PTR_REG(i) (0x7c10 + (i) * 0x40)
493: #define TX_DMA_DESC_WRWB_THRESH_REG(i) (0x7c18 + (i) * 0x40)
494: #define TX_DMA_DESC_WRWB_THRESH __BITS(14,8)
495:
496: /* TDM_DCAD_REG[AQ_RINGS_NUM] 0x8400-0x8480 */
497: #define TDM_DCAD_REG(i) (0x8400 + (i) * 4)
498: #define TDM_DCAD_CPUID __BITS(7,0)
499: #define TDM_DCAD_CPUID_EN __BIT(31)
500:
501: #define TDM_DCA_REG 0x8480
502: #define TDM_DCA_EN __BIT(31)
503: #define TDM_DCA_MODE __BITS(3,0)
504:
505: /* TX_INTR_MODERATION_CTL_REG[AQ_RINGS_NUM] 0x8980-0x8a00 */
506: #define TX_INTR_MODERATION_CTL_REG(i) (0x8980 + (i) * 4)
507: #define TX_INTR_MODERATION_CTL_EN __BIT(1)
508: #define TX_INTR_MODERATION_CTL_MIN __BITS(15,8)
509: #define TX_INTR_MODERATION_CTL_MAX __BITS(24,16)
510:
511: #define FW1X_CTRL_10G __BIT(0)
512: #define FW1X_CTRL_5G __BIT(1)
513: #define FW1X_CTRL_5GSR __BIT(2)
514: #define FW1X_CTRL_2G5 __BIT(3)
515: #define FW1X_CTRL_1G __BIT(4)
516: #define FW1X_CTRL_100M __BIT(5)
517:
518: #define FW2X_CTRL_10BASET_HD __BIT(0)
519: #define FW2X_CTRL_10BASET_FD __BIT(1)
520: #define FW2X_CTRL_100BASETX_HD __BIT(2)
521: #define FW2X_CTRL_100BASET4_HD __BIT(3)
522: #define FW2X_CTRL_100BASET2_HD __BIT(4)
523: #define FW2X_CTRL_100BASETX_FD __BIT(5)
524: #define FW2X_CTRL_100BASET2_FD __BIT(6)
525: #define FW2X_CTRL_1000BASET_HD __BIT(7)
526: #define FW2X_CTRL_1000BASET_FD __BIT(8)
527: #define FW2X_CTRL_2P5GBASET_FD __BIT(9)
528: #define FW2X_CTRL_5GBASET_FD __BIT(10)
529: #define FW2X_CTRL_10GBASET_FD __BIT(11)
530: #define FW2X_CTRL_RESERVED1 __BIT(32)
531: #define FW2X_CTRL_10BASET_EEE __BIT(33)
532: #define FW2X_CTRL_RESERVED2 __BIT(34)
533: #define FW2X_CTRL_PAUSE __BIT(35)
534: #define FW2X_CTRL_ASYMMETRIC_PAUSE __BIT(36)
535: #define FW2X_CTRL_100BASETX_EEE __BIT(37)
536: #define FW2X_CTRL_RESERVED3 __BIT(38)
537: #define FW2X_CTRL_RESERVED4 __BIT(39)
538: #define FW2X_CTRL_1000BASET_FD_EEE __BIT(40)
539: #define FW2X_CTRL_2P5GBASET_FD_EEE __BIT(41)
540: #define FW2X_CTRL_5GBASET_FD_EEE __BIT(42)
541: #define FW2X_CTRL_10GBASET_FD_EEE __BIT(43)
542: #define FW2X_CTRL_RESERVED5 __BIT(44)
543: #define FW2X_CTRL_RESERVED6 __BIT(45)
544: #define FW2X_CTRL_RESERVED7 __BIT(46)
545: #define FW2X_CTRL_RESERVED8 __BIT(47)
546: #define FW2X_CTRL_RESERVED9 __BIT(48)
547: #define FW2X_CTRL_CABLE_DIAG __BIT(49)
548: #define FW2X_CTRL_TEMPERATURE __BIT(50)
549: #define FW2X_CTRL_DOWNSHIFT __BIT(51)
550: #define FW2X_CTRL_PTP_AVB_EN __BIT(52)
551: #define FW2X_CTRL_MEDIA_DETECT __BIT(53)
552: #define FW2X_CTRL_LINK_DROP __BIT(54)
553: #define FW2X_CTRL_SLEEP_PROXY __BIT(55)
554: #define FW2X_CTRL_WOL __BIT(56)
555: #define FW2X_CTRL_MAC_STOP __BIT(57)
556: #define FW2X_CTRL_EXT_LOOPBACK __BIT(58)
557: #define FW2X_CTRL_INT_LOOPBACK __BIT(59)
558: #define FW2X_CTRL_EFUSE_AGENT __BIT(60)
559: #define FW2X_CTRL_WOL_TIMER __BIT(61)
560: #define FW2X_CTRL_STATISTICS __BIT(62)
561: #define FW2X_CTRL_TRANSACTION_ID __BIT(63)
562:
563: #define FW2X_SNPRINTB \
564: "\177\020" \
565: "b\x23" "PAUSE\0" \
566: "b\x24" "ASYMMETRIC-PAUSE\0" \
567: "b\x31" "CABLE-DIAG\0" \
568: "b\x32" "TEMPERATURE\0" \
569: "b\x33" "DOWNSHIFT\0" \
570: "b\x34" "PTP-AVB\0" \
571: "b\x35" "MEDIA-DETECT\0" \
572: "b\x36" "LINK-DROP\0" \
573: "b\x37" "SLEEP-PROXY\0" \
574: "b\x38" "WOL\0" \
575: "b\x39" "MAC-STOP\0" \
576: "b\x3a" "EXT-LOOPBACK\0" \
577: "b\x3b" "INT-LOOPBACK\0" \
578: "b\x3c" "EFUSE-AGENT\0" \
579: "b\x3d" "WOL-TIMER\0" \
580: "b\x3e" "STATISTICS\0" \
581: "b\x3f" "TRANSACTION-ID\0" \
582: "\0"
583:
584: #define FW2X_CTRL_RATE_100M FW2X_CTRL_100BASETX_FD
585: #define FW2X_CTRL_RATE_1G FW2X_CTRL_1000BASET_FD
586: #define FW2X_CTRL_RATE_2G5 FW2X_CTRL_2P5GBASET_FD
587: #define FW2X_CTRL_RATE_5G FW2X_CTRL_5GBASET_FD
588: #define FW2X_CTRL_RATE_10G FW2X_CTRL_10GBASET_FD
589: #define FW2X_CTRL_RATE_MASK \
590: (FW2X_CTRL_RATE_100M | \
591: FW2X_CTRL_RATE_1G | \
592: FW2X_CTRL_RATE_2G5 | \
593: FW2X_CTRL_RATE_5G | \
594: FW2X_CTRL_RATE_10G)
595: #define FW2X_CTRL_EEE_MASK \
596: (FW2X_CTRL_10BASET_EEE | \
597: FW2X_CTRL_100BASETX_EEE | \
598: FW2X_CTRL_1000BASET_FD_EEE | \
599: FW2X_CTRL_2P5GBASET_FD_EEE | \
600: FW2X_CTRL_5GBASET_FD_EEE | \
601: FW2X_CTRL_10GBASET_FD_EEE)
602:
603: typedef enum aq_fw_bootloader_mode {
604: FW_BOOT_MODE_UNKNOWN = 0,
605: FW_BOOT_MODE_FLB,
606: FW_BOOT_MODE_RBL_FLASH,
607: FW_BOOT_MODE_RBL_HOST_BOOTLOAD
608: } aq_fw_bootloader_mode_t;
609:
610: #define AQ_WRITE_REG(sc, reg, val) \
611: bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
612:
613: #define AQ_READ_REG(sc, reg) \
614: bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
615:
616: #define AQ_READ64_REG(sc, reg) \
617: ((uint64_t)AQ_READ_REG(sc, reg) | \
618: (((uint64_t)AQ_READ_REG(sc, (reg) + 4)) << 32))
619:
620: #define AQ_WRITE64_REG(sc, reg, val) \
621: do { \
622: AQ_WRITE_REG(sc, reg, (uint32_t)val); \
623: AQ_WRITE_REG(sc, reg + 4, (uint32_t)(val >> 32)); \
624: } while (/* CONSTCOND */0)
625:
626: #define AQ_READ_REG_BIT(sc, reg, mask) \
627: __SHIFTOUT(AQ_READ_REG(sc, reg), mask)
628:
629: #define AQ_WRITE_REG_BIT(sc, reg, mask, val) \
630: do { \
631: uint32_t _v; \
632: _v = AQ_READ_REG((sc), (reg)); \
633: _v &= ~(mask); \
634: if ((val) != 0) \
635: _v |= __SHIFTIN((val), (mask)); \
636: AQ_WRITE_REG((sc), (reg), _v); \
637: } while (/* CONSTCOND */ 0)
638:
639: #define WAIT_FOR(expr, us, n, errp) \
640: do { \
641: unsigned int _n; \
642: for (_n = n; (!(expr)) && _n != 0; --_n) { \
643: delay((us)); \
644: } \
645: if ((errp != NULL)) { \
646: if (_n == 0) \
647: *(errp) = ETIMEDOUT; \
648: else \
649: *(errp) = 0; \
650: } \
651: } while (/* CONSTCOND */ 0)
652:
653: #define msec_delay(x) DELAY(1000 * (x))
654:
655: typedef struct aq_mailbox_header {
656: uint32_t version;
657: uint32_t transaction_id;
658: int32_t error;
1.19 ryo 659: } __packed __aligned(4) aq_mailbox_header_t;
1.1 ryo 660:
661: typedef struct aq_hw_stats_s {
662: uint32_t uprc;
663: uint32_t mprc;
664: uint32_t bprc;
665: uint32_t erpt;
666: uint32_t uptc;
667: uint32_t mptc;
668: uint32_t bptc;
669: uint32_t erpr;
670: uint32_t mbtc;
671: uint32_t bbtc;
672: uint32_t mbrc;
673: uint32_t bbrc;
674: uint32_t ubrc;
675: uint32_t ubtc;
676: uint32_t ptc;
677: uint32_t prc;
678: uint32_t dpc; /* not exists in fw2x_msm_statistics */
679: uint32_t cprc; /* not exists in fw2x_msm_statistics */
1.19 ryo 680: } __packed __aligned(4) aq_hw_stats_s_t;
1.1 ryo 681:
682: typedef struct fw1x_mailbox {
683: aq_mailbox_header_t header;
684: aq_hw_stats_s_t msm;
1.19 ryo 685: } __packed __aligned(4) fw1x_mailbox_t;
1.1 ryo 686:
687: typedef struct fw2x_msm_statistics {
688: uint32_t uprc;
689: uint32_t mprc;
690: uint32_t bprc;
691: uint32_t erpt;
692: uint32_t uptc;
693: uint32_t mptc;
694: uint32_t bptc;
695: uint32_t erpr;
696: uint32_t mbtc;
697: uint32_t bbtc;
698: uint32_t mbrc;
699: uint32_t bbrc;
700: uint32_t ubrc;
701: uint32_t ubtc;
702: uint32_t ptc;
703: uint32_t prc;
1.19 ryo 704: } __packed __aligned(4) fw2x_msm_statistics_t;
1.1 ryo 705:
706: typedef struct fw2x_phy_cable_diag_data {
707: uint32_t lane_data[4];
1.19 ryo 708: } __packed __aligned(4) fw2x_phy_cable_diag_data_t;
1.1 ryo 709:
710: typedef struct fw2x_capabilities {
711: uint32_t caps_lo;
712: uint32_t caps_hi;
1.19 ryo 713: } __packed __aligned(4) fw2x_capabilities_t;
1.1 ryo 714:
715: typedef struct fw2x_mailbox { /* struct fwHostInterface */
716: aq_mailbox_header_t header;
717: fw2x_msm_statistics_t msm; /* msmStatistics_t msm; */
1.4 ryo 718:
719: uint32_t phy_info1;
720: #define PHYINFO1_FAULT_CODE __BITS(31,16)
721: #define PHYINFO1_PHY_H_BIT __BITS(0,15)
722: uint32_t phy_info2;
723: #define PHYINFO2_TEMPERATURE __BITS(15,0)
724: #define PHYINFO2_CABLE_LEN __BITS(23,16)
725:
1.1 ryo 726: fw2x_phy_cable_diag_data_t diag_data;
727: uint32_t reserved[8];
728:
729: fw2x_capabilities_t caps;
730:
731: /* ... */
1.19 ryo 732: } __packed __aligned(4) fw2x_mailbox_t;
1.1 ryo 733:
734: typedef enum aq_link_speed {
735: AQ_LINK_NONE = 0,
736: AQ_LINK_100M = (1 << 0),
737: AQ_LINK_1G = (1 << 1),
738: AQ_LINK_2G5 = (1 << 2),
739: AQ_LINK_5G = (1 << 3),
740: AQ_LINK_10G = (1 << 4)
741: } aq_link_speed_t;
742: #define AQ_LINK_ALL (AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | \
743: AQ_LINK_5G | AQ_LINK_10G )
744: #define AQ_LINK_AUTO AQ_LINK_ALL
745:
746: typedef enum aq_link_fc {
747: AQ_FC_NONE = 0,
748: AQ_FC_RX = __BIT(0),
749: AQ_FC_TX = __BIT(1),
750: AQ_FC_ALL = (AQ_FC_RX | AQ_FC_TX)
751: } aq_link_fc_t;
752:
753: typedef enum aq_link_eee {
754: AQ_EEE_DISABLE = 0,
755: AQ_EEE_ENABLE = 1
756: } aq_link_eee_t;
757:
758: typedef enum aq_hw_fw_mpi_state {
759: MPI_DEINIT = 0,
760: MPI_RESET = 1,
761: MPI_INIT = 2,
762: MPI_POWER = 4
763: } aq_hw_fw_mpi_state_t;
764:
765: enum aq_media_type {
766: AQ_MEDIA_TYPE_UNKNOWN = 0,
767: AQ_MEDIA_TYPE_FIBRE,
768: AQ_MEDIA_TYPE_TP
769: };
770:
771: struct aq_rx_desc_read {
772: uint64_t buf_addr;
773: uint64_t hdr_addr;
1.19 ryo 774: } __packed __aligned(8);
1.1 ryo 775:
776: struct aq_rx_desc_wb {
777: uint32_t type;
778: #define RXDESC_TYPE_RSSTYPE __BITS(3,0)
779: #define RXDESC_TYPE_RSSTYPE_NONE 0
780: #define RXDESC_TYPE_RSSTYPE_IPV4 2
781: #define RXDESC_TYPE_RSSTYPE_IPV6 3
782: #define RXDESC_TYPE_RSSTYPE_IPV4_TCP 4
783: #define RXDESC_TYPE_RSSTYPE_IPV6_TCP 5
784: #define RXDESC_TYPE_RSSTYPE_IPV4_UDP 6
785: #define RXDESC_TYPE_RSSTYPE_IPV6_UDP 7
786: #define RXDESC_TYPE_PKTTYPE_ETHER __BITS(5,4)
787: #define RXDESC_TYPE_PKTTYPE_ETHER_IPV4 0
788: #define RXDESC_TYPE_PKTTYPE_ETHER_IPV6 1
789: #define RXDESC_TYPE_PKTTYPE_ETHER_OTHERS 2
790: #define RXDESC_TYPE_PKTTYPE_ETHER_ARP 3
791: #define RXDESC_TYPE_PKTTYPE_PROTO __BITS(8,6)
792: #define RXDESC_TYPE_PKTTYPE_PROTO_TCP 0
793: #define RXDESC_TYPE_PKTTYPE_PROTO_UDP 1
794: #define RXDESC_TYPE_PKTTYPE_PROTO_SCTP 2
795: #define RXDESC_TYPE_PKTTYPE_PROTO_ICMP 3
796: #define RXDESC_TYPE_PKTTYPE_PROTO_OTHERS 4
797: #define RXDESC_TYPE_PKTTYPE_VLAN __BIT(9)
798: #define RXDESC_TYPE_PKTTYPE_VLAN_DOUBLE __BIT(10)
799: #define RXDESC_TYPE_MAC_DMA_ERR __BIT(12)
800: #define RXDESC_TYPE_RESERVED __BITS(18,13)
801: #define RXDESC_TYPE_IPV4_CSUM_CHECKED __BIT(19) /* PKTTYPE_ETHER_IPV4 */
802: #define RXDESC_TYPE_TCPUDP_CSUM_CHECKED __BIT(20)
803: #define RXDESC_TYPE_SPH __BIT(21)
804: #define RXDESC_TYPE_HDR_LEN __BITS(31,22)
805: uint32_t rss_hash;
806: uint16_t status;
807: #define RXDESC_STATUS_DD __BIT(0)
808: #define RXDESC_STATUS_EOP __BIT(1)
809: #define RXDESC_STATUS_MACERR __BIT(2)
810: #define RXDESC_STATUS_IPV4_CSUM_NG __BIT(3)
811: #define RXDESC_STATUS_TCPUDP_CSUM_ERROR __BIT(4)
812: #define RXDESC_STATUS_TCPUDP_CSUM_OK __BIT(5)
813:
814: #define RXDESC_STATUS_STAT __BITS(2,5)
815: #define RXDESC_STATUS_ESTAT __BITS(6,11)
816: #define RXDESC_STATUS_RSC_CNT __BITS(12,15)
817: uint16_t pkt_len;
818: uint16_t next_desc_ptr;
819: uint16_t vlan;
1.19 ryo 820: } __packed __aligned(4);
1.1 ryo 821:
822: typedef union aq_rx_desc {
823: struct aq_rx_desc_read read;
824: struct aq_rx_desc_wb wb;
1.19 ryo 825: } __packed __aligned(8) aq_rx_desc_t;
1.1 ryo 826:
827: typedef struct aq_tx_desc {
828: uint64_t buf_addr;
829: uint32_t ctl1;
830: #define AQ_TXDESC_CTL1_TYPE_MASK 0x00000003
831: #define AQ_TXDESC_CTL1_TYPE_TXD 0x00000001
832: #define AQ_TXDESC_CTL1_TYPE_TXC 0x00000002
833: #define AQ_TXDESC_CTL1_BLEN __BITS(19,4) /* TXD */
834: #define AQ_TXDESC_CTL1_DD __BIT(20) /* TXD */
835: #define AQ_TXDESC_CTL1_EOP __BIT(21) /* TXD */
836: #define AQ_TXDESC_CTL1_CMD_VLAN __BIT(22) /* TXD */
837: #define AQ_TXDESC_CTL1_CMD_FCS __BIT(23) /* TXD */
838: #define AQ_TXDESC_CTL1_CMD_IP4CSUM __BIT(24) /* TXD */
839: #define AQ_TXDESC_CTL1_CMD_L4CSUM __BIT(25) /* TXD */
840: #define AQ_TXDESC_CTL1_CMD_LSO __BIT(26) /* TXD */
841: #define AQ_TXDESC_CTL1_CMD_WB __BIT(27) /* TXD */
842: #define AQ_TXDESC_CTL1_CMD_VXLAN __BIT(28) /* TXD */
843: #define AQ_TXDESC_CTL1_VID __BITS(15,4) /* TXC */
844: #define AQ_TXDESC_CTL1_LSO_IPV6 __BIT(21) /* TXC */
845: #define AQ_TXDESC_CTL1_LSO_TCP __BIT(22) /* TXC */
846: uint32_t ctl2;
847: #define AQ_TXDESC_CTL2_LEN __BITS(31,14)
848: #define AQ_TXDESC_CTL2_CTX_EN __BIT(13)
849: #define AQ_TXDESC_CTL2_CTX_IDX __BIT(12)
1.19 ryo 850: } __packed __aligned(8) aq_tx_desc_t;
1.1 ryo 851:
852: struct aq_txring {
853: struct aq_softc *txr_sc;
854: int txr_index;
855: kmutex_t txr_mutex;
856: bool txr_active;
857:
858: pcq_t *txr_pcq;
859: void *txr_softint;
860:
861: aq_tx_desc_t *txr_txdesc; /* aq_tx_desc_t[AQ_TXD_NUM] */
862: bus_dmamap_t txr_txdesc_dmamap;
863: bus_dma_segment_t txr_txdesc_seg[1];
864: bus_size_t txr_txdesc_size;
865:
866: struct {
867: struct mbuf *m;
868: bus_dmamap_t dmamap;
869: } txr_mbufs[AQ_TXD_NUM];
870: unsigned int txr_prodidx;
871: unsigned int txr_considx;
872: int txr_nfree;
873: };
874:
875: struct aq_rxring {
876: struct aq_softc *rxr_sc;
877: int rxr_index;
878: kmutex_t rxr_mutex;
879: bool rxr_active;
880:
881: aq_rx_desc_t *rxr_rxdesc; /* aq_rx_desc_t[AQ_RXD_NUM] */
882: bus_dmamap_t rxr_rxdesc_dmamap;
883: bus_dma_segment_t rxr_rxdesc_seg[1];
884: bus_size_t rxr_rxdesc_size;
885: struct {
886: struct mbuf *m;
887: bus_dmamap_t dmamap;
888: } rxr_mbufs[AQ_RXD_NUM];
889: unsigned int rxr_readidx;
890: };
891:
892: struct aq_queue {
893: struct aq_softc *sc;
894: struct aq_txring txring;
895: struct aq_rxring rxring;
896: };
897:
898: struct aq_softc;
899: struct aq_firmware_ops {
900: int (*reset)(struct aq_softc *);
901: int (*set_mode)(struct aq_softc *, aq_hw_fw_mpi_state_t,
902: aq_link_speed_t, aq_link_fc_t, aq_link_eee_t);
903: int (*get_mode)(struct aq_softc *, aq_hw_fw_mpi_state_t *,
904: aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *);
905: int (*get_stats)(struct aq_softc *, aq_hw_stats_s_t *);
1.4 ryo 906: #if NSYSMON_ENVSYS > 0
907: int (*get_temperature)(struct aq_softc *, uint32_t *);
908: #endif
1.1 ryo 909: };
910:
911: #ifdef AQ_EVENT_COUNTERS
912: #define AQ_EVCNT_DECL(name) \
913: char sc_evcount_##name##_name[32]; \
914: struct evcnt sc_evcount_##name##_ev;
915: #define AQ_EVCNT_ATTACH(sc, name, desc, evtype) \
916: do { \
917: snprintf((sc)->sc_evcount_##name##_name, \
918: sizeof((sc)->sc_evcount_##name##_name), \
919: "%s", desc); \
920: evcnt_attach_dynamic(&(sc)->sc_evcount_##name##_ev, \
921: (evtype), NULL, device_xname((sc)->sc_dev), \
922: (sc)->sc_evcount_##name##_name); \
923: } while (/*CONSTCOND*/0)
924: #define AQ_EVCNT_ATTACH_MISC(sc, name, desc) \
925: AQ_EVCNT_ATTACH(sc, name, desc, EVCNT_TYPE_MISC)
926: #define AQ_EVCNT_DETACH(sc, name) \
927: evcnt_detach(&(sc)->sc_evcount_##name##_ev)
928: #define AQ_EVCNT_ADD(sc, name, val) \
929: ((sc)->sc_evcount_##name##_ev.ev_count += (val))
930: #endif /* AQ_EVENT_COUNTERS */
931:
932: #define AQ_LOCK(sc) mutex_enter(&(sc)->sc_mutex);
933: #define AQ_UNLOCK(sc) mutex_exit(&(sc)->sc_mutex);
934:
1.4 ryo 935: /* lock for FW2X_MPI_{CONTROL,STATE]_REG read-modify-write */
936: #define AQ_MPI_LOCK(sc) mutex_enter(&(sc)->sc_mpi_mutex);
937: #define AQ_MPI_UNLOCK(sc) mutex_exit(&(sc)->sc_mpi_mutex);
938:
939:
1.1 ryo 940: struct aq_softc {
941: device_t sc_dev;
942:
943: bus_space_tag_t sc_iot;
944: bus_space_handle_t sc_ioh;
945: bus_size_t sc_iosize;
1.17 msaitoh 946: bus_dma_tag_t sc_dmat;
1.1 ryo 947:
948: void *sc_ihs[AQ_NINTR_MAX];
949: pci_intr_handle_t *sc_intrs;
950:
951: int sc_tx_irq[AQ_RSSQUEUE_MAX];
952: int sc_rx_irq[AQ_RSSQUEUE_MAX];
953: int sc_linkstat_irq;
954: bool sc_use_txrx_independent_intr;
955: bool sc_poll_linkstat;
956: bool sc_detect_linkstat;
957:
1.4 ryo 958: #if NSYSMON_ENVSYS > 0
959: struct sysmon_envsys *sc_sme;
960: envsys_data_t sc_sensor_temp;
961: #endif
962:
1.1 ryo 963: callout_t sc_tick_ch;
964:
965: int sc_nintrs;
966: bool sc_msix;
967:
968: struct aq_queue sc_queue[AQ_RSSQUEUE_MAX];
969: int sc_nqueues;
970:
971: pci_chipset_tag_t sc_pc;
972: pcitag_t sc_pcitag;
973: uint16_t sc_product;
974: uint16_t sc_revision;
975:
976: kmutex_t sc_mutex;
1.4 ryo 977: kmutex_t sc_mpi_mutex;
1.1 ryo 978:
1.8 maxv 979: const struct aq_firmware_ops *sc_fw_ops;
1.1 ryo 980: uint64_t sc_fw_caps;
981: enum aq_media_type sc_media_type;
982: aq_link_speed_t sc_available_rates;
983:
984: aq_link_speed_t sc_link_rate;
985: aq_link_fc_t sc_link_fc;
986: aq_link_eee_t sc_link_eee;
987:
988: uint32_t sc_fw_version;
989: #define FW_VERSION_MAJOR(sc) (((sc)->sc_fw_version >> 24) & 0xff)
990: #define FW_VERSION_MINOR(sc) (((sc)->sc_fw_version >> 16) & 0xff)
991: #define FW_VERSION_BUILD(sc) ((sc)->sc_fw_version & 0xffff)
992: uint32_t sc_features;
993: #define FEATURES_MIPS 0x00000001
994: #define FEATURES_TPO2 0x00000002
995: #define FEATURES_RPF2 0x00000004
996: #define FEATURES_MPI_AQ 0x00000008
997: #define FEATURES_REV_A0 0x10000000
998: #define FEATURES_REV_A (FEATURES_REV_A0)
999: #define FEATURES_REV_B0 0x20000000
1000: #define FEATURES_REV_B1 0x40000000
1001: #define FEATURES_REV_B (FEATURES_REV_B0|FEATURES_REV_B1)
1.23 ! ryo 1002: uint32_t sc_max_mtu;
1.1 ryo 1003: uint32_t sc_mbox_addr;
1004:
1005: bool sc_rbl_enabled;
1006: bool sc_fast_start_enabled;
1007: bool sc_flash_present;
1008:
1009: bool sc_intr_moderation_enable;
1010: bool sc_rss_enable;
1011:
1012: struct ethercom sc_ethercom;
1013: struct ether_addr sc_enaddr;
1014: struct ifmedia sc_media;
1015: int sc_ec_capenable; /* last ec_capenable */
1016: unsigned short sc_if_flags; /* last if_flags */
1017:
1018: #ifdef AQ_EVENT_COUNTERS
1019: aq_hw_stats_s_t sc_statistics[2];
1020: int sc_statistics_idx;
1021: bool sc_poll_statistics;
1022:
1023: AQ_EVCNT_DECL(uprc);
1024: AQ_EVCNT_DECL(mprc);
1025: AQ_EVCNT_DECL(bprc);
1026: AQ_EVCNT_DECL(erpt);
1027: AQ_EVCNT_DECL(uptc);
1028: AQ_EVCNT_DECL(mptc);
1029: AQ_EVCNT_DECL(bptc);
1030: AQ_EVCNT_DECL(erpr);
1031: AQ_EVCNT_DECL(mbtc);
1032: AQ_EVCNT_DECL(bbtc);
1033: AQ_EVCNT_DECL(mbrc);
1034: AQ_EVCNT_DECL(bbrc);
1035: AQ_EVCNT_DECL(ubrc);
1036: AQ_EVCNT_DECL(ubtc);
1037: AQ_EVCNT_DECL(ptc);
1038: AQ_EVCNT_DECL(prc);
1039: AQ_EVCNT_DECL(dpc);
1040: AQ_EVCNT_DECL(cprc);
1041: #endif
1042: };
1043:
1044: static int aq_match(device_t, cfdata_t, void *);
1045: static void aq_attach(device_t, device_t, void *);
1046: static int aq_detach(device_t, int);
1047:
1048: static int aq_setup_msix(struct aq_softc *, struct pci_attach_args *, int,
1049: bool, bool);
1050: static int aq_setup_legacy(struct aq_softc *, struct pci_attach_args *,
1051: pci_intr_type_t);
1052: static int aq_establish_msix_intr(struct aq_softc *, bool, bool);
1053:
1054: static int aq_ifmedia_change(struct ifnet * const);
1055: static void aq_ifmedia_status(struct ifnet * const, struct ifmediareq *);
1.10 ryo 1056: static int aq_vlan_cb(struct ethercom *ec, uint16_t vid, bool set);
1.1 ryo 1057: static int aq_ifflags_cb(struct ethercom *);
1058: static int aq_init(struct ifnet *);
1059: static void aq_send_common_locked(struct ifnet *, struct aq_softc *,
1060: struct aq_txring *, bool);
1061: static int aq_transmit(struct ifnet *, struct mbuf *);
1062: static void aq_deferred_transmit(void *);
1063: static void aq_start(struct ifnet *);
1064: static void aq_stop(struct ifnet *, int);
1065: static void aq_watchdog(struct ifnet *);
1066: static int aq_ioctl(struct ifnet *, unsigned long, void *);
1067:
1068: static int aq_txrx_rings_alloc(struct aq_softc *);
1069: static void aq_txrx_rings_free(struct aq_softc *);
1070: static int aq_tx_pcq_alloc(struct aq_softc *, struct aq_txring *);
1071: static void aq_tx_pcq_free(struct aq_softc *, struct aq_txring *);
1072:
1073: static void aq_initmedia(struct aq_softc *);
1074: static void aq_enable_intr(struct aq_softc *, bool, bool);
1075:
1.4 ryo 1076: #if NSYSMON_ENVSYS > 0
1077: static void aq_temp_refresh(struct sysmon_envsys *, envsys_data_t *);
1078: #endif
1.1 ryo 1079: static void aq_tick(void *);
1080: static int aq_legacy_intr(void *);
1081: static int aq_link_intr(void *);
1082: static int aq_txrx_intr(void *);
1083: static int aq_tx_intr(void *);
1084: static int aq_rx_intr(void *);
1085:
1086: static int aq_set_linkmode(struct aq_softc *, aq_link_speed_t, aq_link_fc_t,
1087: aq_link_eee_t);
1088: static int aq_get_linkmode(struct aq_softc *, aq_link_speed_t *, aq_link_fc_t *,
1089: aq_link_eee_t *);
1090:
1091: static int aq_fw_reset(struct aq_softc *);
1092: static int aq_fw_version_init(struct aq_softc *);
1093: static int aq_hw_init(struct aq_softc *);
1094: static int aq_hw_init_ucp(struct aq_softc *);
1095: static int aq_hw_reset(struct aq_softc *);
1096: static int aq_fw_downld_dwords(struct aq_softc *, uint32_t, uint32_t *,
1097: uint32_t);
1098: static int aq_get_mac_addr(struct aq_softc *);
1099: static int aq_init_rss(struct aq_softc *);
1100: static int aq_set_capability(struct aq_softc *);
1101:
1102: static int fw1x_reset(struct aq_softc *);
1103: static int fw1x_set_mode(struct aq_softc *, aq_hw_fw_mpi_state_t,
1104: aq_link_speed_t, aq_link_fc_t, aq_link_eee_t);
1105: static int fw1x_get_mode(struct aq_softc *, aq_hw_fw_mpi_state_t *,
1106: aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *);
1107: static int fw1x_get_stats(struct aq_softc *, aq_hw_stats_s_t *);
1108:
1109: static int fw2x_reset(struct aq_softc *);
1110: static int fw2x_set_mode(struct aq_softc *, aq_hw_fw_mpi_state_t,
1111: aq_link_speed_t, aq_link_fc_t, aq_link_eee_t);
1112: static int fw2x_get_mode(struct aq_softc *, aq_hw_fw_mpi_state_t *,
1113: aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *);
1114: static int fw2x_get_stats(struct aq_softc *, aq_hw_stats_s_t *);
1.4 ryo 1115: #if NSYSMON_ENVSYS > 0
1116: static int fw2x_get_temperature(struct aq_softc *, uint32_t *);
1117: #endif
1.1 ryo 1118:
1.8 maxv 1119: static const struct aq_firmware_ops aq_fw1x_ops = {
1.1 ryo 1120: .reset = fw1x_reset,
1121: .set_mode = fw1x_set_mode,
1122: .get_mode = fw1x_get_mode,
1.4 ryo 1123: .get_stats = fw1x_get_stats,
1124: #if NSYSMON_ENVSYS > 0
1125: .get_temperature = NULL
1126: #endif
1.1 ryo 1127: };
1128:
1.8 maxv 1129: static const struct aq_firmware_ops aq_fw2x_ops = {
1.1 ryo 1130: .reset = fw2x_reset,
1131: .set_mode = fw2x_set_mode,
1132: .get_mode = fw2x_get_mode,
1.4 ryo 1133: .get_stats = fw2x_get_stats,
1134: #if NSYSMON_ENVSYS > 0
1135: .get_temperature = fw2x_get_temperature
1136: #endif
1.1 ryo 1137: };
1138:
1139: CFATTACH_DECL3_NEW(aq, sizeof(struct aq_softc),
1140: aq_match, aq_attach, aq_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
1141:
1142: static const struct aq_product {
1143: pci_vendor_id_t aq_vendor;
1144: pci_product_id_t aq_product;
1145: const char *aq_name;
1146: enum aq_media_type aq_media_type;
1147: aq_link_speed_t aq_available_rates;
1148: } aq_products[] = {
1.14 ryo 1149: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100,
1150: "Aquantia AQC100 10 Gigabit Network Adapter",
1151: AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL
1152: },
1.1 ryo 1153: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107,
1154: "Aquantia AQC107 10 Gigabit Network Adapter",
1155: AQ_MEDIA_TYPE_TP, AQ_LINK_ALL
1156: },
1157: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108,
1158: "Aquantia AQC108 5 Gigabit Network Adapter",
1159: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1160: },
1161: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109,
1162: "Aquantia AQC109 2.5 Gigabit Network Adapter",
1163: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1164: },
1165: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111,
1166: "Aquantia AQC111 5 Gigabit Network Adapter",
1167: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1168: },
1169: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112,
1170: "Aquantia AQC112 2.5 Gigabit Network Adapter",
1171: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1172: },
1.15 ryo 1173: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100S,
1.16 ryo 1174: "Aquantia AQC100S 10 Gigabit Network Adapter",
1.15 ryo 1175: AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL
1176: },
1.1 ryo 1177: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107S,
1178: "Aquantia AQC107S 10 Gigabit Network Adapter",
1179: AQ_MEDIA_TYPE_TP, AQ_LINK_ALL
1180: },
1181: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108S,
1182: "Aquantia AQC108S 5 Gigabit Network Adapter",
1183: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1184: },
1185: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109S,
1186: "Aquantia AQC109S 2.5 Gigabit Network Adapter",
1187: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1188: },
1189: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111S,
1190: "Aquantia AQC111S 5 Gigabit Network Adapter",
1191: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1192: },
1193: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112S,
1194: "Aquantia AQC112S 2.5 Gigabit Network Adapter",
1195: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1196: },
1.15 ryo 1197: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D100,
1198: "Aquantia D100 10 Gigabit Network Adapter",
1199: AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL
1200: },
1.1 ryo 1201: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D107,
1202: "Aquantia D107 10 Gigabit Network Adapter",
1203: AQ_MEDIA_TYPE_TP, AQ_LINK_ALL
1204: },
1205: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D108,
1206: "Aquantia D108 5 Gigabit Network Adapter",
1207: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1208: },
1209: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D109,
1210: "Aquantia D109 2.5 Gigabit Network Adapter",
1211: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1212: }
1213: };
1214:
1215: static const struct aq_product *
1216: aq_lookup(const struct pci_attach_args *pa)
1217: {
1218: unsigned int i;
1219:
1220: for (i = 0; i < __arraycount(aq_products); i++) {
1221: if (PCI_VENDOR(pa->pa_id) == aq_products[i].aq_vendor &&
1222: PCI_PRODUCT(pa->pa_id) == aq_products[i].aq_product)
1223: return &aq_products[i];
1224: }
1225: return NULL;
1226: }
1227:
1228: static int
1229: aq_match(device_t parent, cfdata_t cf, void *aux)
1230: {
1231: struct pci_attach_args *pa = aux;
1232:
1233: if (aq_lookup(pa) != NULL)
1234: return 1;
1235:
1236: return 0;
1237: }
1238:
1239: static void
1240: aq_attach(device_t parent, device_t self, void *aux)
1241: {
1242: struct aq_softc *sc = device_private(self);
1243: struct pci_attach_args *pa = aux;
1244: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1245: pci_chipset_tag_t pc;
1246: pcitag_t tag;
1247: pcireg_t command, memtype, bar;
1248: const struct aq_product *aqp;
1249: int error;
1250:
1251: sc->sc_dev = self;
1252: mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_NET);
1.4 ryo 1253: mutex_init(&sc->sc_mpi_mutex, MUTEX_DEFAULT, IPL_NET);
1.1 ryo 1254:
1255: sc->sc_pc = pc = pa->pa_pc;
1256: sc->sc_pcitag = tag = pa->pa_tag;
1257: sc->sc_dmat = pci_dma64_available(pa) ? pa->pa_dmat64 : pa->pa_dmat;
1258:
1259: command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1260: command |= PCI_COMMAND_MASTER_ENABLE;
1261: pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
1262:
1263: sc->sc_product = PCI_PRODUCT(pa->pa_id);
1264: sc->sc_revision = PCI_REVISION(pa->pa_class);
1265:
1266: aqp = aq_lookup(pa);
1267: KASSERT(aqp != NULL);
1268:
1269: pci_aprint_devinfo_fancy(pa, "Ethernet controller", aqp->aq_name, 1);
1270:
1271: bar = pci_conf_read(pc, tag, PCI_BAR(0));
1272: if ((PCI_MAPREG_MEM_ADDR(bar) == 0) ||
1273: (PCI_MAPREG_TYPE(bar) != PCI_MAPREG_TYPE_MEM)) {
1274: aprint_error_dev(sc->sc_dev, "wrong BAR type\n");
1275: return;
1276: }
1277: memtype = pci_mapreg_type(pc, tag, PCI_BAR(0));
1278: if (pci_mapreg_map(pa, PCI_BAR(0), memtype, 0, &sc->sc_iot, &sc->sc_ioh,
1279: NULL, &sc->sc_iosize) != 0) {
1280: aprint_error_dev(sc->sc_dev, "unable to map register\n");
1281: return;
1282: }
1283:
1284: sc->sc_nqueues = MIN(ncpu, AQ_RSSQUEUE_MAX);
1285:
1286: /* max queue num is 8, and must be 2^n */
1287: if (ncpu >= 8)
1288: sc->sc_nqueues = 8;
1289: else if (ncpu >= 4)
1290: sc->sc_nqueues = 4;
1291: else if (ncpu >= 2)
1292: sc->sc_nqueues = 2;
1293: else
1294: sc->sc_nqueues = 1;
1295:
1296: int msixcount = pci_msix_count(pa->pa_pc, pa->pa_tag);
1297: #ifndef CONFIG_NO_TXRX_INDEPENDENT
1298: if (msixcount >= (sc->sc_nqueues * 2 + 1)) {
1299: /* TX intrs + RX intrs + LINKSTAT intrs */
1300: sc->sc_use_txrx_independent_intr = true;
1301: sc->sc_poll_linkstat = false;
1302: sc->sc_msix = true;
1303: } else if (msixcount >= (sc->sc_nqueues * 2)) {
1304: /* TX intrs + RX intrs */
1305: sc->sc_use_txrx_independent_intr = true;
1306: sc->sc_poll_linkstat = true;
1307: sc->sc_msix = true;
1308: } else
1309: #endif
1310: if (msixcount >= (sc->sc_nqueues + 1)) {
1311: /* TX/RX intrs LINKSTAT intrs */
1312: sc->sc_use_txrx_independent_intr = false;
1313: sc->sc_poll_linkstat = false;
1314: sc->sc_msix = true;
1315: } else if (msixcount >= sc->sc_nqueues) {
1316: /* TX/RX intrs */
1317: sc->sc_use_txrx_independent_intr = false;
1318: sc->sc_poll_linkstat = true;
1319: sc->sc_msix = true;
1320: } else {
1321: /* giving up using MSI-X */
1322: sc->sc_msix = false;
1323: }
1324:
1.13 ryo 1325: /* XXX: on FIBRE, linkstat interrupt does not occur on boot? */
1326: if (aqp->aq_media_type == AQ_MEDIA_TYPE_FIBRE)
1327: sc->sc_poll_linkstat = true;
1328:
1329: #ifdef AQ_FORCE_POLL_LINKSTAT
1330: sc->sc_poll_linkstat = true;
1331: #endif
1332:
1.1 ryo 1333: aprint_debug_dev(sc->sc_dev,
1334: "ncpu=%d, pci_msix_count=%d."
1335: " allocate %d interrupts for %d%s queues%s\n",
1336: ncpu, msixcount,
1337: (sc->sc_use_txrx_independent_intr ?
1338: (sc->sc_nqueues * 2) : sc->sc_nqueues) +
1339: (sc->sc_poll_linkstat ? 0 : 1),
1340: sc->sc_nqueues,
1341: sc->sc_use_txrx_independent_intr ? "*2" : "",
1342: sc->sc_poll_linkstat ? "" : ", and link status");
1343:
1344: if (sc->sc_msix)
1345: error = aq_setup_msix(sc, pa, sc->sc_nqueues,
1346: sc->sc_use_txrx_independent_intr, !sc->sc_poll_linkstat);
1347: else
1348: error = ENODEV;
1349:
1350: if (error != 0) {
1351: /* if MSI-X failed, fallback to MSI with single queue */
1352: sc->sc_use_txrx_independent_intr = false;
1353: sc->sc_poll_linkstat = false;
1354: sc->sc_msix = false;
1355: sc->sc_nqueues = 1;
1356: error = aq_setup_legacy(sc, pa, PCI_INTR_TYPE_MSI);
1357: }
1358: if (error != 0) {
1359: /* if MSI failed, fallback to INTx */
1360: error = aq_setup_legacy(sc, pa, PCI_INTR_TYPE_INTX);
1361: }
1362: if (error != 0)
1363: return;
1364:
1365: callout_init(&sc->sc_tick_ch, 0);
1366: callout_setfunc(&sc->sc_tick_ch, aq_tick, sc);
1367:
1368: sc->sc_intr_moderation_enable = CONFIG_INTR_MODERATION_ENABLE;
1369:
1370: if (sc->sc_msix && (sc->sc_nqueues > 1))
1371: sc->sc_rss_enable = true;
1372: else
1373: sc->sc_rss_enable = false;
1374:
1375: error = aq_txrx_rings_alloc(sc);
1376: if (error != 0)
1377: goto attach_failure;
1378:
1379: error = aq_fw_reset(sc);
1380: if (error != 0)
1381: goto attach_failure;
1382:
1383: error = aq_fw_version_init(sc);
1384: if (error != 0)
1385: goto attach_failure;
1386:
1387: error = aq_hw_init_ucp(sc);
1388: if (error < 0)
1389: goto attach_failure;
1390:
1391: KASSERT(sc->sc_mbox_addr != 0);
1392: error = aq_hw_reset(sc);
1393: if (error != 0)
1394: goto attach_failure;
1395:
1396: aq_get_mac_addr(sc);
1397: aq_init_rss(sc);
1398:
1399: error = aq_hw_init(sc); /* initialize and interrupts */
1400: if (error != 0)
1401: goto attach_failure;
1402:
1403: sc->sc_media_type = aqp->aq_media_type;
1404: sc->sc_available_rates = aqp->aq_available_rates;
1405:
1406: sc->sc_ethercom.ec_ifmedia = &sc->sc_media;
1407: ifmedia_init(&sc->sc_media, IFM_IMASK,
1408: aq_ifmedia_change, aq_ifmedia_status);
1409: aq_initmedia(sc);
1410:
1411: strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
1412: ifp->if_softc = sc;
1413: ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1.20 ryo 1414: ifp->if_extflags = IFEF_MPSAFE;
1.1 ryo 1415: ifp->if_baudrate = IF_Gbps(10);
1416: ifp->if_init = aq_init;
1417: ifp->if_ioctl = aq_ioctl;
1418: if (sc->sc_msix && (sc->sc_nqueues > 1))
1419: ifp->if_transmit = aq_transmit;
1420: ifp->if_start = aq_start;
1421: ifp->if_stop = aq_stop;
1422: ifp->if_watchdog = aq_watchdog;
1423: IFQ_SET_READY(&ifp->if_snd);
1424:
1425: /* initialize capabilities */
1426: sc->sc_ethercom.ec_capabilities = 0;
1427: sc->sc_ethercom.ec_capenable = 0;
1428: #if notyet
1429: /* TODO */
1430: sc->sc_ethercom.ec_capabilities |= ETHERCAP_EEE;
1431: #endif
1432: sc->sc_ethercom.ec_capabilities |=
1433: ETHERCAP_JUMBO_MTU |
1434: ETHERCAP_VLAN_MTU |
1.10 ryo 1435: ETHERCAP_VLAN_HWTAGGING |
1436: ETHERCAP_VLAN_HWFILTER;
1.1 ryo 1437: sc->sc_ethercom.ec_capenable |=
1.10 ryo 1438: ETHERCAP_VLAN_HWTAGGING |
1439: ETHERCAP_VLAN_HWFILTER;
1.1 ryo 1440:
1441: ifp->if_capabilities = 0;
1442: ifp->if_capenable = 0;
1443: #ifdef CONFIG_LRO_SUPPORT
1444: ifp->if_capabilities |= IFCAP_LRO;
1445: ifp->if_capenable |= IFCAP_LRO;
1446: #endif
1447: #if notyet
1448: /* TSO */
1449: ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
1450: #endif
1451:
1452: /* TX hardware checksum offloadding */
1453: ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx;
1454: ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv6_Tx;
1455: ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv6_Tx;
1456: /* RX hardware checksum offloadding */
1457: ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx;
1.21 ryo 1458: ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_TCPv6_Rx;
1459: ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Rx | IFCAP_CSUM_UDPv6_Rx;
1.1 ryo 1460:
1.20 ryo 1461: error = if_initialize(ifp);
1462: if (error != 0) {
1463: aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n",
1464: error);
1465: goto attach_failure;
1466: }
1467: ifp->if_percpuq = if_percpuq_create(ifp);
1.1 ryo 1468: if_deferred_start_init(ifp, NULL);
1469: ether_ifattach(ifp, sc->sc_enaddr.ether_addr_octet);
1.10 ryo 1470: ether_set_vlan_cb(&sc->sc_ethercom, aq_vlan_cb);
1.1 ryo 1471: ether_set_ifflags_cb(&sc->sc_ethercom, aq_ifflags_cb);
1.20 ryo 1472: if_register(ifp);
1.1 ryo 1473:
1474: aq_enable_intr(sc, true, false); /* only intr about link */
1475:
1476: /* update media */
1477: aq_ifmedia_change(ifp);
1478:
1.4 ryo 1479: #if NSYSMON_ENVSYS > 0
1480: /* temperature monitoring */
1481: if (sc->sc_fw_ops != NULL && sc->sc_fw_ops->get_temperature != NULL &&
1482: (sc->sc_fw_caps & FW2X_CTRL_TEMPERATURE) != 0) {
1483:
1484: sc->sc_sme = sysmon_envsys_create();
1485: sc->sc_sme->sme_name = device_xname(self);
1486: sc->sc_sme->sme_cookie = sc;
1487: sc->sc_sme->sme_flags = 0;
1488: sc->sc_sme->sme_refresh = aq_temp_refresh;
1489: sc->sc_sensor_temp.units = ENVSYS_STEMP;
1490: sc->sc_sensor_temp.state = ENVSYS_SINVALID;
1491: snprintf(sc->sc_sensor_temp.desc, ENVSYS_DESCLEN, "PHY");
1492:
1493: sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor_temp);
1494: sysmon_envsys_register(sc->sc_sme);
1495:
1496: /*
1497: * for unknown reasons, the first call of fw2x_get_temperature()
1498: * will always fail (firmware matter?), so run once now.
1499: */
1500: aq_temp_refresh(sc->sc_sme, &sc->sc_sensor_temp);
1501: }
1502: #endif
1503:
1.1 ryo 1504: #ifdef AQ_EVENT_COUNTERS
1505: /* get starting statistics values */
1506: if (sc->sc_fw_ops != NULL && sc->sc_fw_ops->get_stats != NULL &&
1507: sc->sc_fw_ops->get_stats(sc, &sc->sc_statistics[0]) == 0) {
1508: sc->sc_poll_statistics = true;
1509: }
1510:
1511: AQ_EVCNT_ATTACH_MISC(sc, uprc, "RX unicast packet");
1512: AQ_EVCNT_ATTACH_MISC(sc, bprc, "RX broadcast packet");
1513: AQ_EVCNT_ATTACH_MISC(sc, mprc, "RX multicast packet");
1514: AQ_EVCNT_ATTACH_MISC(sc, erpr, "RX error packet");
1515: AQ_EVCNT_ATTACH_MISC(sc, ubrc, "RX unicast bytes");
1516: AQ_EVCNT_ATTACH_MISC(sc, bbrc, "RX broadcast bytes");
1517: AQ_EVCNT_ATTACH_MISC(sc, mbrc, "RX multicast bytes");
1518: AQ_EVCNT_ATTACH_MISC(sc, prc, "RX good packet");
1519: AQ_EVCNT_ATTACH_MISC(sc, uptc, "TX unicast packet");
1520: AQ_EVCNT_ATTACH_MISC(sc, bptc, "TX broadcast packet");
1521: AQ_EVCNT_ATTACH_MISC(sc, mptc, "TX multicast packet");
1522: AQ_EVCNT_ATTACH_MISC(sc, erpt, "TX error packet");
1523: AQ_EVCNT_ATTACH_MISC(sc, ubtc, "TX unicast bytes");
1524: AQ_EVCNT_ATTACH_MISC(sc, bbtc, "TX broadcast bytes");
1525: AQ_EVCNT_ATTACH_MISC(sc, mbtc, "TX multicast bytes");
1526: AQ_EVCNT_ATTACH_MISC(sc, ptc, "TX good packet");
1527: AQ_EVCNT_ATTACH_MISC(sc, dpc, "DMA drop packet");
1528: AQ_EVCNT_ATTACH_MISC(sc, cprc, "RX coalesced packet");
1529: #endif
1530:
1531: return;
1532:
1533: attach_failure:
1534: aq_detach(self, 0);
1535: }
1536:
1537: static int
1538: aq_detach(device_t self, int flags __unused)
1539: {
1540: struct aq_softc *sc = device_private(self);
1541: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1542: int i, s;
1543:
1544: if (sc->sc_iosize != 0) {
1545: if (ifp->if_softc != NULL) {
1546: s = splnet();
1547: aq_stop(ifp, 0);
1548: splx(s);
1549: }
1550:
1551: for (i = 0; i < AQ_NINTR_MAX; i++) {
1552: if (sc->sc_ihs[i] != NULL) {
1553: pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
1554: sc->sc_ihs[i] = NULL;
1555: }
1556: }
1557: if (sc->sc_nintrs > 0) {
1558: pci_intr_release(sc->sc_pc, sc->sc_intrs,
1559: sc->sc_nintrs);
1560: sc->sc_intrs = NULL;
1561: sc->sc_nintrs = 0;
1562: }
1563:
1564: aq_txrx_rings_free(sc);
1565:
1566: if (ifp->if_softc != NULL) {
1567: ether_ifdetach(ifp);
1568: if_detach(ifp);
1569: }
1570:
1571: aprint_debug_dev(sc->sc_dev, "%s: bus_space_unmap\n", __func__);
1572: bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize);
1573: sc->sc_iosize = 0;
1574: }
1575:
1576: callout_stop(&sc->sc_tick_ch);
1577:
1.4 ryo 1578: #if NSYSMON_ENVSYS > 0
1579: if (sc->sc_sme != NULL) {
1580: /* all sensors associated with this will also be detached */
1581: sysmon_envsys_unregister(sc->sc_sme);
1582: sc->sc_sme = NULL;
1583: }
1584: #endif
1585:
1.1 ryo 1586: #ifdef AQ_EVENT_COUNTERS
1587: AQ_EVCNT_DETACH(sc, uprc);
1588: AQ_EVCNT_DETACH(sc, mprc);
1589: AQ_EVCNT_DETACH(sc, bprc);
1590: AQ_EVCNT_DETACH(sc, erpt);
1591: AQ_EVCNT_DETACH(sc, uptc);
1592: AQ_EVCNT_DETACH(sc, mptc);
1593: AQ_EVCNT_DETACH(sc, bptc);
1594: AQ_EVCNT_DETACH(sc, erpr);
1595: AQ_EVCNT_DETACH(sc, mbtc);
1596: AQ_EVCNT_DETACH(sc, bbtc);
1597: AQ_EVCNT_DETACH(sc, mbrc);
1598: AQ_EVCNT_DETACH(sc, bbrc);
1599: AQ_EVCNT_DETACH(sc, ubrc);
1600: AQ_EVCNT_DETACH(sc, ubtc);
1601: AQ_EVCNT_DETACH(sc, ptc);
1602: AQ_EVCNT_DETACH(sc, prc);
1603: AQ_EVCNT_DETACH(sc, dpc);
1604: AQ_EVCNT_DETACH(sc, cprc);
1605: #endif
1606:
1.7 thorpej 1607: ifmedia_fini(&sc->sc_media);
1608:
1.4 ryo 1609: mutex_destroy(&sc->sc_mpi_mutex);
1.1 ryo 1610: mutex_destroy(&sc->sc_mutex);
1611:
1612: return 0;
1613: }
1614:
1615: static int
1616: aq_establish_intr(struct aq_softc *sc, int intno, kcpuset_t *affinity,
1617: int (*func)(void *), void *arg, const char *xname)
1618: {
1619: char intrbuf[PCI_INTRSTR_LEN];
1620: pci_chipset_tag_t pc = sc->sc_pc;
1621: void *vih;
1622: const char *intrstr = NULL;
1623:
1624: intrstr = pci_intr_string(pc, sc->sc_intrs[intno], intrbuf,
1625: sizeof(intrbuf));
1626:
1627: pci_intr_setattr(pc, &sc->sc_intrs[intno], PCI_INTR_MPSAFE, true);
1628:
1629: vih = pci_intr_establish_xname(pc, sc->sc_intrs[intno],
1630: IPL_NET, func, arg, xname);
1631: if (vih == NULL) {
1632: aprint_error_dev(sc->sc_dev,
1633: "unable to establish MSI-X%s%s for %s\n",
1634: intrstr ? " at " : "",
1635: intrstr ? intrstr : "", xname);
1636: return EIO;
1637: }
1638: sc->sc_ihs[intno] = vih;
1639:
1640: if (affinity != NULL) {
1641: /* Round-robin affinity */
1642: kcpuset_zero(affinity);
1643: kcpuset_set(affinity, intno % ncpu);
1644: interrupt_distribute(vih, affinity, NULL);
1645: }
1646:
1647: return 0;
1648: }
1649:
1650: static int
1651: aq_establish_msix_intr(struct aq_softc *sc, bool txrx_independent,
1652: bool linkintr)
1653: {
1654: kcpuset_t *affinity;
1655: int error, intno, i;
1656: char intr_xname[INTRDEVNAMEBUF];
1657:
1658: kcpuset_create(&affinity, false);
1659:
1660: intno = 0;
1661:
1662: if (txrx_independent) {
1663: for (i = 0; i < sc->sc_nqueues; i++) {
1664: snprintf(intr_xname, sizeof(intr_xname), "%s RX%d",
1665: device_xname(sc->sc_dev), i);
1666: sc->sc_rx_irq[i] = intno;
1667: error = aq_establish_intr(sc, intno++, affinity,
1668: aq_rx_intr, &sc->sc_queue[i].rxring, intr_xname);
1669: if (error != 0)
1670: goto fail;
1671: }
1672: for (i = 0; i < sc->sc_nqueues; i++) {
1673: snprintf(intr_xname, sizeof(intr_xname), "%s TX%d",
1674: device_xname(sc->sc_dev), i);
1675: sc->sc_tx_irq[i] = intno;
1676: error = aq_establish_intr(sc, intno++, affinity,
1677: aq_tx_intr, &sc->sc_queue[i].txring, intr_xname);
1678: if (error != 0)
1679: goto fail;
1680: }
1681: } else {
1682: for (i = 0; i < sc->sc_nqueues; i++) {
1683: snprintf(intr_xname, sizeof(intr_xname), "%s TXRX%d",
1684: device_xname(sc->sc_dev), i);
1685: sc->sc_rx_irq[i] = intno;
1686: sc->sc_tx_irq[i] = intno;
1687: error = aq_establish_intr(sc, intno++, affinity,
1688: aq_txrx_intr, &sc->sc_queue[i], intr_xname);
1689: if (error != 0)
1690: goto fail;
1691: }
1692: }
1693:
1694: if (linkintr) {
1695: snprintf(intr_xname, sizeof(intr_xname), "%s LINK",
1696: device_xname(sc->sc_dev));
1697: sc->sc_linkstat_irq = intno;
1698: error = aq_establish_intr(sc, intno++, affinity,
1699: aq_link_intr, sc, intr_xname);
1700: if (error != 0)
1701: goto fail;
1702: }
1703:
1704: kcpuset_destroy(affinity);
1705: return 0;
1706:
1707: fail:
1708: for (i = 0; i < AQ_NINTR_MAX; i++) {
1709: if (sc->sc_ihs[i] != NULL) {
1710: pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
1711: sc->sc_ihs[i] = NULL;
1712: }
1713: }
1714:
1715: kcpuset_destroy(affinity);
1716: return ENOMEM;
1717: }
1718:
1719: static int
1720: aq_setup_msix(struct aq_softc *sc, struct pci_attach_args *pa, int nqueue,
1721: bool txrx_independent, bool linkintr)
1722: {
1723: int error, nintr;
1724:
1725: if (txrx_independent)
1726: nintr = nqueue * 2;
1727: else
1728: nintr = nqueue;
1729:
1730: if (linkintr)
1731: nintr++;
1732:
1733: error = pci_msix_alloc_exact(pa, &sc->sc_intrs, nintr);
1734: if (error != 0) {
1735: aprint_error_dev(sc->sc_dev,
1736: "failed to allocate MSI-X interrupts\n");
1737: goto fail;
1738: }
1739:
1740: error = aq_establish_msix_intr(sc, txrx_independent, linkintr);
1741: if (error == 0) {
1742: sc->sc_nintrs = nintr;
1743: } else {
1744: pci_intr_release(sc->sc_pc, sc->sc_intrs, nintr);
1745: sc->sc_nintrs = 0;
1746: }
1747: fail:
1748: return error;
1749:
1750: }
1751:
1752: static int
1753: aq_setup_legacy(struct aq_softc *sc, struct pci_attach_args *pa,
1754: pci_intr_type_t inttype)
1755: {
1756: int counts[PCI_INTR_TYPE_SIZE];
1757: int error, nintr;
1758:
1759: nintr = 1;
1760:
1761: memset(counts, 0, sizeof(counts));
1762: counts[inttype] = nintr;
1763:
1764: error = pci_intr_alloc(pa, &sc->sc_intrs, counts, inttype);
1765: if (error != 0) {
1766: aprint_error_dev(sc->sc_dev,
1767: "failed to allocate%s interrupts\n",
1768: (inttype == PCI_INTR_TYPE_MSI) ? " MSI" : "");
1769: return error;
1770: }
1771: error = aq_establish_intr(sc, 0, NULL, aq_legacy_intr, sc,
1772: device_xname(sc->sc_dev));
1773: if (error == 0) {
1774: sc->sc_nintrs = nintr;
1775: } else {
1776: pci_intr_release(sc->sc_pc, sc->sc_intrs, nintr);
1777: sc->sc_nintrs = 0;
1778: }
1779: return error;
1780: }
1781:
1782: static void
1783: global_software_reset(struct aq_softc *sc)
1784: {
1785: uint32_t v;
1786:
1787: AQ_WRITE_REG_BIT(sc, RX_SYSCONTROL_REG, RX_SYSCONTROL_RESET_DIS, 0);
1788: AQ_WRITE_REG_BIT(sc, TX_SYSCONTROL_REG, TX_SYSCONTROL_RESET_DIS, 0);
1789: AQ_WRITE_REG_BIT(sc, FW_MPI_RESETCTRL_REG,
1790: FW_MPI_RESETCTRL_RESET_DIS, 0);
1791:
1792: v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG);
1793: v &= ~AQ_FW_SOFTRESET_DIS;
1794: v |= AQ_FW_SOFTRESET_RESET;
1795: AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v);
1796: }
1797:
1798: static int
1799: mac_soft_reset_rbl(struct aq_softc *sc, aq_fw_bootloader_mode_t *mode)
1800: {
1801: int timo;
1802:
1803: aprint_debug_dev(sc->sc_dev, "RBL> MAC reset STARTED!\n");
1804:
1805: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1);
1806: AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1);
1807: AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0);
1808:
1809: /* MAC FW will reload PHY FW if 1E.1000.3 was cleaned - #undone */
1810: AQ_WRITE_REG(sc, FW_BOOT_EXIT_CODE_REG, RBL_STATUS_DEAD);
1811:
1812: global_software_reset(sc);
1813:
1814: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e0);
1815:
1816: /* Wait for RBL to finish boot process. */
1817: #define RBL_TIMEOUT_MS 10000
1818: uint16_t rbl_status;
1819: for (timo = RBL_TIMEOUT_MS; timo > 0; timo--) {
1820: rbl_status = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG) & 0xffff;
1821: if (rbl_status != 0 && rbl_status != RBL_STATUS_DEAD)
1822: break;
1823: msec_delay(1);
1824: }
1825: if (timo <= 0) {
1826: aprint_error_dev(sc->sc_dev,
1827: "RBL> RBL restart failed: timeout\n");
1828: return EBUSY;
1829: }
1830: switch (rbl_status) {
1831: case RBL_STATUS_SUCCESS:
1832: if (mode != NULL)
1833: *mode = FW_BOOT_MODE_RBL_FLASH;
1834: aprint_debug_dev(sc->sc_dev, "RBL> reset complete! [Flash]\n");
1835: break;
1836: case RBL_STATUS_HOST_BOOT:
1837: if (mode != NULL)
1838: *mode = FW_BOOT_MODE_RBL_HOST_BOOTLOAD;
1839: aprint_debug_dev(sc->sc_dev,
1840: "RBL> reset complete! [Host Bootload]\n");
1841: break;
1842: case RBL_STATUS_FAILURE:
1843: default:
1844: aprint_error_dev(sc->sc_dev,
1845: "unknown RBL status 0x%x\n", rbl_status);
1846: return EBUSY;
1847: }
1848:
1849: return 0;
1850: }
1851:
1852: static int
1853: mac_soft_reset_flb(struct aq_softc *sc)
1854: {
1855: uint32_t v;
1856: int timo;
1857:
1858: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1);
1859: /*
1860: * Let Felicity hardware to complete SMBUS transaction before
1861: * Global software reset.
1862: */
1863: msec_delay(50);
1864:
1865: /*
1866: * If SPI burst transaction was interrupted(before running the script),
1867: * global software reset may not clear SPI interface.
1868: * Clean it up manually before global reset.
1869: */
1870: AQ_WRITE_REG(sc, AQ_GLB_NVR_PROVISIONING2_REG, 0x00a0);
1871: AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x009f);
1872: AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x809f);
1873: msec_delay(50);
1874:
1875: v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG);
1876: v &= ~AQ_FW_SOFTRESET_DIS;
1877: v |= AQ_FW_SOFTRESET_RESET;
1878: AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v);
1879:
1880: /* Kickstart. */
1881: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0);
1882: AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0);
1883: if (!sc->sc_fast_start_enabled)
1884: AQ_WRITE_REG(sc, AQ_GLB_GENERAL_PROVISIONING9_REG, 1);
1885:
1886: /*
1887: * For the case SPI burst transaction was interrupted (by MCP reset
1888: * above), wait until it is completed by hardware.
1889: */
1890: msec_delay(50);
1891:
1892: /* MAC Kickstart */
1893: if (!sc->sc_fast_start_enabled) {
1894: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x180e0);
1895:
1896: uint32_t flb_status;
1897: for (timo = 0; timo < 1000; timo++) {
1898: flb_status = AQ_READ_REG(sc,
1899: FW_MPI_DAISY_CHAIN_STATUS_REG) & 0x10;
1900: if (flb_status != 0)
1901: break;
1902: msec_delay(1);
1903: }
1904: if (flb_status == 0) {
1905: aprint_error_dev(sc->sc_dev,
1906: "FLB> MAC kickstart failed: timed out\n");
1907: return ETIMEDOUT;
1908: }
1909: aprint_debug_dev(sc->sc_dev,
1910: "FLB> MAC kickstart done, %d ms\n", timo);
1911: /* FW reset */
1912: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0);
1913: /*
1914: * Let Felicity hardware complete SMBUS transaction before
1915: * Global software reset.
1916: */
1917: msec_delay(50);
1918: sc->sc_fast_start_enabled = true;
1919: }
1920: AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1);
1921:
1922: /* PHY Kickstart: #undone */
1923: global_software_reset(sc);
1924:
1925: for (timo = 0; timo < 1000; timo++) {
1926: if (AQ_READ_REG(sc, AQ_FW_VERSION_REG) != 0)
1927: break;
1928: msec_delay(10);
1929: }
1930: if (timo >= 1000) {
1931: aprint_error_dev(sc->sc_dev, "FLB> Global Soft Reset failed\n");
1932: return ETIMEDOUT;
1933: }
1934: aprint_debug_dev(sc->sc_dev, "FLB> F/W restart: %d ms\n", timo * 10);
1935: return 0;
1936:
1937: }
1938:
1939: static int
1940: mac_soft_reset(struct aq_softc *sc, aq_fw_bootloader_mode_t *mode)
1941: {
1942: if (sc->sc_rbl_enabled)
1943: return mac_soft_reset_rbl(sc, mode);
1944:
1945: if (mode != NULL)
1946: *mode = FW_BOOT_MODE_FLB;
1947: return mac_soft_reset_flb(sc);
1948: }
1949:
1950: static int
1951: aq_fw_read_version(struct aq_softc *sc)
1952: {
1953: int i, error = EBUSY;
1954: #define MAC_FW_START_TIMEOUT_MS 10000
1955: for (i = 0; i < MAC_FW_START_TIMEOUT_MS; i++) {
1956: sc->sc_fw_version = AQ_READ_REG(sc, AQ_FW_VERSION_REG);
1957: if (sc->sc_fw_version != 0) {
1958: error = 0;
1959: break;
1960: }
1961: delay(1000);
1962: }
1963: return error;
1964: }
1965:
1966: static int
1967: aq_fw_reset(struct aq_softc *sc)
1968: {
1969: uint32_t ver, v, bootExitCode;
1970: int i, error;
1971:
1972: ver = AQ_READ_REG(sc, AQ_FW_VERSION_REG);
1973:
1974: for (i = 1000; i > 0; i--) {
1975: v = AQ_READ_REG(sc, FW_MPI_DAISY_CHAIN_STATUS_REG);
1976: bootExitCode = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG);
1977: if (v != 0x06000000 || bootExitCode != 0)
1978: break;
1979: }
1980: if (i <= 0) {
1981: aprint_error_dev(sc->sc_dev,
1982: "F/W reset failed. Neither RBL nor FLB started\n");
1983: return ETIMEDOUT;
1984: }
1985: sc->sc_rbl_enabled = (bootExitCode != 0);
1986:
1987: /*
1988: * Having FW version 0 is an indicator that cold start
1989: * is in progress. This means two things:
1990: * 1) Driver have to wait for FW/HW to finish boot (500ms giveup)
1991: * 2) Driver may skip reset sequence and save time.
1992: */
1993: if (sc->sc_fast_start_enabled && (ver != 0)) {
1994: error = aq_fw_read_version(sc);
1995: /* Skip reset as it just completed */
1996: if (error == 0)
1997: return 0;
1998: }
1999:
2000: aq_fw_bootloader_mode_t mode = FW_BOOT_MODE_UNKNOWN;
2001: error = mac_soft_reset(sc, &mode);
2002: if (error != 0) {
2003: aprint_error_dev(sc->sc_dev, "MAC reset failed: %d\n", error);
2004: return error;
2005: }
2006:
2007: switch (mode) {
2008: case FW_BOOT_MODE_FLB:
2009: aprint_debug_dev(sc->sc_dev,
2010: "FLB> F/W successfully loaded from flash.\n");
2011: sc->sc_flash_present = true;
2012: return aq_fw_read_version(sc);
2013: case FW_BOOT_MODE_RBL_FLASH:
2014: aprint_debug_dev(sc->sc_dev,
2015: "RBL> F/W loaded from flash. Host Bootload disabled.\n");
2016: sc->sc_flash_present = true;
2017: return aq_fw_read_version(sc);
2018: case FW_BOOT_MODE_UNKNOWN:
2019: aprint_error_dev(sc->sc_dev,
2020: "F/W bootload error: unknown bootloader type\n");
2021: return ENOTSUP;
2022: case FW_BOOT_MODE_RBL_HOST_BOOTLOAD:
2023: aprint_debug_dev(sc->sc_dev, "RBL> Host Bootload mode\n");
2024: break;
2025: }
2026:
2027: /*
2028: * XXX: TODO: add support Host Boot
2029: */
2030: aprint_error_dev(sc->sc_dev,
2031: "RBL> F/W Host Bootload not implemented\n");
2032: return ENOTSUP;
2033: }
2034:
2035: static int
2036: aq_hw_reset(struct aq_softc *sc)
2037: {
2038: int error;
2039:
2040: /* disable irq */
2041: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS, 0);
2042:
2043: /* apply */
2044: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_IRQ, 1);
2045:
2046: /* wait ack 10 times by 1ms */
2047: WAIT_FOR(
2048: (AQ_READ_REG(sc, AQ_INTR_CTRL_REG) & AQ_INTR_CTRL_RESET_IRQ) == 0,
2049: 1000, 10, &error);
2050: if (error != 0) {
2051: aprint_error_dev(sc->sc_dev,
2052: "atlantic: IRQ reset failed: %d\n", error);
2053: return error;
2054: }
2055:
2056: return sc->sc_fw_ops->reset(sc);
2057: }
2058:
2059: static int
2060: aq_hw_init_ucp(struct aq_softc *sc)
2061: {
2062: int timo;
2063:
2064: if (FW_VERSION_MAJOR(sc) == 1) {
2065: if (AQ_READ_REG(sc, FW1X_MPI_INIT2_REG) == 0) {
2066: uint32_t data;
2067: cprng_fast(&data, sizeof(data));
2068: data &= 0xfefefefe;
2069: data |= 0x02020202;
2070: AQ_WRITE_REG(sc, FW1X_MPI_INIT2_REG, data);
2071: }
2072: AQ_WRITE_REG(sc, FW1X_MPI_INIT1_REG, 0);
2073: }
2074:
2075: for (timo = 100; timo > 0; timo--) {
2076: sc->sc_mbox_addr = AQ_READ_REG(sc, FW_MPI_MBOX_ADDR_REG);
2077: if (sc->sc_mbox_addr != 0)
2078: break;
2079: delay(1000);
2080: }
2081:
2082: #define AQ_FW_MIN_VERSION 0x01050006
2083: #define AQ_FW_MIN_VERSION_STR "1.5.6"
2084: if (sc->sc_fw_version < AQ_FW_MIN_VERSION) {
2085: aprint_error_dev(sc->sc_dev,
2086: "atlantic: wrong FW version: " AQ_FW_MIN_VERSION_STR
2087: " or later required, this is %d.%d.%d\n",
2088: FW_VERSION_MAJOR(sc),
2089: FW_VERSION_MINOR(sc),
2090: FW_VERSION_BUILD(sc));
2091: return ENOTSUP;
2092: }
2093:
2094: return 0;
2095: }
2096:
2097: static int
2098: aq_fw_version_init(struct aq_softc *sc)
2099: {
2100: int error = 0;
2101: char fw_vers[sizeof("F/W version xxxxx.xxxxx.xxxxx")];
2102:
2103: if (FW_VERSION_MAJOR(sc) == 1) {
2104: sc->sc_fw_ops = &aq_fw1x_ops;
2105: } else if ((FW_VERSION_MAJOR(sc) == 2) || (FW_VERSION_MAJOR(sc) == 3)) {
2106: sc->sc_fw_ops = &aq_fw2x_ops;
2107: } else {
2108: aprint_error_dev(sc->sc_dev,
2109: "Unsupported F/W version %d.%d.%d\n",
2110: FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc),
2111: FW_VERSION_BUILD(sc));
2112: return ENOTSUP;
2113: }
2114: snprintf(fw_vers, sizeof(fw_vers), "F/W version %d.%d.%d",
2115: FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc), FW_VERSION_BUILD(sc));
2116:
2117: /* detect revision */
2118: uint32_t hwrev = AQ_READ_REG(sc, AQ_HW_REVISION_REG);
2119: switch (hwrev & 0x0000000f) {
2120: case 0x01:
2121: aprint_normal_dev(sc->sc_dev, "Atlantic revision A0, %s\n",
2122: fw_vers);
2123: sc->sc_features |= FEATURES_REV_A0 |
2124: FEATURES_MPI_AQ | FEATURES_MIPS;
1.23 ! ryo 2125: sc->sc_max_mtu = AQ_JUMBO_MTU_REV_A;
1.1 ryo 2126: break;
2127: case 0x02:
2128: aprint_normal_dev(sc->sc_dev, "Atlantic revision B0, %s\n",
2129: fw_vers);
2130: sc->sc_features |= FEATURES_REV_B0 |
2131: FEATURES_MPI_AQ | FEATURES_MIPS |
2132: FEATURES_TPO2 | FEATURES_RPF2;
1.23 ! ryo 2133: sc->sc_max_mtu = AQ_JUMBO_MTU_REV_B;
1.1 ryo 2134: break;
2135: case 0x0A:
2136: aprint_normal_dev(sc->sc_dev, "Atlantic revision B1, %s\n",
2137: fw_vers);
2138: sc->sc_features |= FEATURES_REV_B1 |
2139: FEATURES_MPI_AQ | FEATURES_MIPS |
2140: FEATURES_TPO2 | FEATURES_RPF2;
1.23 ! ryo 2141: sc->sc_max_mtu = AQ_JUMBO_MTU_REV_B;
1.1 ryo 2142: break;
2143: default:
2144: aprint_error_dev(sc->sc_dev,
2145: "Unknown revision (0x%08x)\n", hwrev);
1.23 ! ryo 2146: sc->sc_features = 0;
! 2147: sc->sc_max_mtu = ETHERMTU;
1.1 ryo 2148: error = ENOTSUP;
2149: break;
2150: }
2151: return error;
2152: }
2153:
2154: static int
2155: fw1x_reset(struct aq_softc *sc)
2156: {
2157: struct aq_mailbox_header mbox;
2158: const int retryCount = 1000;
2159: uint32_t tid0;
2160: int i;
2161:
2162: tid0 = ~0; /*< Initial value of MBOX transactionId. */
2163:
2164: for (i = 0; i < retryCount; ++i) {
2165: /*
2166: * Read the beginning of Statistics structure to capture
2167: * the Transaction ID.
2168: */
2169: aq_fw_downld_dwords(sc, sc->sc_mbox_addr,
2170: (uint32_t *)&mbox, sizeof(mbox) / sizeof(uint32_t));
2171:
2172: /* Successfully read the stats. */
2173: if (tid0 == ~0U) {
2174: /* We have read the initial value. */
2175: tid0 = mbox.transaction_id;
2176: continue;
2177: } else if (mbox.transaction_id != tid0) {
2178: /*
2179: * Compare transaction ID to initial value.
2180: * If it's different means f/w is alive.
2181: * We're done.
2182: */
2183: return 0;
2184: }
2185:
2186: /*
2187: * Transaction ID value haven't changed since last time.
2188: * Try reading the stats again.
2189: */
2190: delay(10);
2191: }
2192: aprint_error_dev(sc->sc_dev, "F/W 1.x reset finalize timeout\n");
2193: return EBUSY;
2194: }
2195:
2196: static int
2197: fw1x_set_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t mode,
2198: aq_link_speed_t speed, aq_link_fc_t fc, aq_link_eee_t eee)
2199: {
2200: uint32_t mpictrl = 0;
2201: uint32_t mpispeed = 0;
2202:
2203: if (speed & AQ_LINK_10G)
2204: mpispeed |= FW1X_CTRL_10G;
2205: if (speed & AQ_LINK_5G)
2206: mpispeed |= (FW1X_CTRL_5G | FW1X_CTRL_5GSR);
2207: if (speed & AQ_LINK_2G5)
2208: mpispeed |= FW1X_CTRL_2G5;
2209: if (speed & AQ_LINK_1G)
2210: mpispeed |= FW1X_CTRL_1G;
2211: if (speed & AQ_LINK_100M)
2212: mpispeed |= FW1X_CTRL_100M;
2213:
2214: mpictrl |= __SHIFTIN(mode, FW1X_MPI_STATE_MODE);
2215: mpictrl |= __SHIFTIN(mpispeed, FW1X_MPI_STATE_SPEED);
2216: AQ_WRITE_REG(sc, FW1X_MPI_CONTROL_REG, mpictrl);
2217: return 0;
2218: }
2219:
2220: static int
2221: fw1x_get_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t *modep,
2222: aq_link_speed_t *speedp, aq_link_fc_t *fcp, aq_link_eee_t *eeep)
2223: {
2224: uint32_t mpistate, mpi_speed;
2225: aq_link_speed_t speed = AQ_LINK_NONE;
2226:
2227: mpistate = AQ_READ_REG(sc, FW1X_MPI_STATE_REG);
2228:
2229: if (modep != NULL)
2230: *modep = __SHIFTOUT(mpistate, FW1X_MPI_STATE_MODE);
2231:
2232: mpi_speed = __SHIFTOUT(mpistate, FW1X_MPI_STATE_SPEED);
2233: if (mpi_speed & FW1X_CTRL_10G)
2234: speed = AQ_LINK_10G;
2235: else if (mpi_speed & (FW1X_CTRL_5G|FW1X_CTRL_5GSR))
2236: speed = AQ_LINK_5G;
2237: else if (mpi_speed & FW1X_CTRL_2G5)
2238: speed = AQ_LINK_2G5;
2239: else if (mpi_speed & FW1X_CTRL_1G)
2240: speed = AQ_LINK_1G;
2241: else if (mpi_speed & FW1X_CTRL_100M)
2242: speed = AQ_LINK_100M;
2243:
2244: if (speedp != NULL)
2245: *speedp = speed;
2246:
2247: if (fcp != NULL)
2248: *fcp = AQ_FC_NONE;
2249:
2250: if (eeep != NULL)
2251: *eeep = AQ_EEE_DISABLE;
2252:
2253: return 0;
2254: }
2255:
2256: static int
2257: fw1x_get_stats(struct aq_softc *sc, aq_hw_stats_s_t *stats)
2258: {
2259: int error;
2260:
2261: error = aq_fw_downld_dwords(sc,
2262: sc->sc_mbox_addr + offsetof(fw1x_mailbox_t, msm), (uint32_t *)stats,
2263: sizeof(aq_hw_stats_s_t) / sizeof(uint32_t));
2264: if (error < 0) {
2265: device_printf(sc->sc_dev,
2266: "fw1x> download statistics data FAILED, error %d", error);
2267: return error;
2268: }
2269:
2270: stats->dpc = AQ_READ_REG(sc, RX_DMA_DROP_PKT_CNT_REG);
2271: stats->cprc = AQ_READ_REG(sc, RX_DMA_COALESCED_PKT_CNT_REG);
2272: return 0;
2273: }
2274:
2275: static int
2276: fw2x_reset(struct aq_softc *sc)
2277: {
2278: fw2x_capabilities_t caps = { 0 };
2279: int error;
2280:
2281: error = aq_fw_downld_dwords(sc,
2282: sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, caps),
2283: (uint32_t *)&caps, sizeof caps / sizeof(uint32_t));
2284: if (error != 0) {
2285: aprint_error_dev(sc->sc_dev,
2286: "fw2x> can't get F/W capabilities mask, error %d\n",
2287: error);
2288: return error;
2289: }
2290: sc->sc_fw_caps = caps.caps_lo | ((uint64_t)caps.caps_hi << 32);
2291:
2292: char buf[256];
2293: snprintb(buf, sizeof(buf), FW2X_SNPRINTB, sc->sc_fw_caps);
2294: aprint_verbose_dev(sc->sc_dev, "fw2x> F/W capabilities=%s\n", buf);
2295:
2296: return 0;
2297: }
2298:
2299: static int
2300: fw2x_set_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t mode,
2301: aq_link_speed_t speed, aq_link_fc_t fc, aq_link_eee_t eee)
2302: {
1.4 ryo 2303: uint64_t mpi_ctrl;
2304: int error = 0;
2305:
2306: AQ_MPI_LOCK(sc);
2307:
2308: mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);
1.1 ryo 2309:
2310: switch (mode) {
2311: case MPI_INIT:
2312: mpi_ctrl &= ~FW2X_CTRL_RATE_MASK;
2313: if (speed & AQ_LINK_10G)
2314: mpi_ctrl |= FW2X_CTRL_RATE_10G;
2315: if (speed & AQ_LINK_5G)
2316: mpi_ctrl |= FW2X_CTRL_RATE_5G;
2317: if (speed & AQ_LINK_2G5)
2318: mpi_ctrl |= FW2X_CTRL_RATE_2G5;
2319: if (speed & AQ_LINK_1G)
2320: mpi_ctrl |= FW2X_CTRL_RATE_1G;
2321: if (speed & AQ_LINK_100M)
2322: mpi_ctrl |= FW2X_CTRL_RATE_100M;
2323:
2324: mpi_ctrl &= ~FW2X_CTRL_LINK_DROP;
2325:
2326: mpi_ctrl &= ~FW2X_CTRL_EEE_MASK;
2327: if (eee == AQ_EEE_ENABLE)
2328: mpi_ctrl |= FW2X_CTRL_EEE_MASK;
2329:
2330: mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE);
2331: if (fc & AQ_FC_RX)
2332: mpi_ctrl |= FW2X_CTRL_PAUSE;
2333: if (fc & AQ_FC_TX)
2334: mpi_ctrl |= FW2X_CTRL_ASYMMETRIC_PAUSE;
2335: break;
2336: case MPI_DEINIT:
2337: mpi_ctrl &= ~(FW2X_CTRL_RATE_MASK | FW2X_CTRL_EEE_MASK);
2338: mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE);
2339: break;
2340: default:
2341: device_printf(sc->sc_dev, "fw2x> unknown MPI state %d\n", mode);
1.4 ryo 2342: error = EINVAL;
2343: goto failure;
1.1 ryo 2344: }
1.4 ryo 2345: AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl);
1.1 ryo 2346:
1.4 ryo 2347: failure:
2348: AQ_MPI_UNLOCK(sc);
2349: return error;
1.1 ryo 2350: }
2351:
2352: static int
2353: fw2x_get_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t *modep,
2354: aq_link_speed_t *speedp, aq_link_fc_t *fcp, aq_link_eee_t *eeep)
2355: {
2356: uint64_t mpi_state = AQ_READ64_REG(sc, FW2X_MPI_STATE_REG);
2357:
2358: if (modep != NULL) {
2359: uint64_t mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);
2360: if (mpi_ctrl & FW2X_CTRL_RATE_MASK)
2361: *modep = MPI_INIT;
2362: else
2363: *modep = MPI_DEINIT;
2364: }
2365:
2366: aq_link_speed_t speed = AQ_LINK_NONE;
2367: if (mpi_state & FW2X_CTRL_RATE_10G)
2368: speed = AQ_LINK_10G;
2369: else if (mpi_state & FW2X_CTRL_RATE_5G)
2370: speed = AQ_LINK_5G;
2371: else if (mpi_state & FW2X_CTRL_RATE_2G5)
2372: speed = AQ_LINK_2G5;
2373: else if (mpi_state & FW2X_CTRL_RATE_1G)
2374: speed = AQ_LINK_1G;
2375: else if (mpi_state & FW2X_CTRL_RATE_100M)
2376: speed = AQ_LINK_100M;
2377:
2378: if (speedp != NULL)
2379: *speedp = speed;
2380:
2381: aq_link_fc_t fc = AQ_FC_NONE;
2382: if (mpi_state & FW2X_CTRL_PAUSE)
2383: fc |= AQ_FC_RX;
2384: if (mpi_state & FW2X_CTRL_ASYMMETRIC_PAUSE)
2385: fc |= AQ_FC_TX;
2386: if (fcp != NULL)
2387: *fcp = fc;
2388:
2389: /* XXX: TODO: EEE */
2390: if (eeep != NULL)
2391: *eeep = AQ_EEE_DISABLE;
2392:
2393: return 0;
2394: }
2395:
2396: static int
2397: toggle_mpi_ctrl_and_wait(struct aq_softc *sc, uint64_t mask,
2398: uint32_t timeout_ms, uint32_t try_count)
2399: {
2400: uint64_t mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);
2401: uint64_t mpi_state = AQ_READ64_REG(sc, FW2X_MPI_STATE_REG);
2402: int error;
2403:
2404: /* First, check that control and state values are consistent */
2405: if ((mpi_ctrl & mask) != (mpi_state & mask)) {
2406: device_printf(sc->sc_dev,
2407: "fw2x> MPI control (%#llx) and state (%#llx)"
2408: " are not consistent for mask %#llx!\n",
2409: (unsigned long long)mpi_ctrl, (unsigned long long)mpi_state,
2410: (unsigned long long)mask);
2411: return EINVAL;
2412: }
2413:
2414: /* Invert bits (toggle) in control register */
2415: mpi_ctrl ^= mask;
2416: AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl);
2417:
2418: /* Clear all bits except masked */
2419: mpi_ctrl &= mask;
2420:
2421: /* Wait for FW reflecting change in state register */
2422: WAIT_FOR((AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG) & mask) == mpi_ctrl,
2423: 1000 * timeout_ms, try_count, &error);
2424: if (error != 0) {
2425: device_printf(sc->sc_dev,
2426: "f/w2x> timeout while waiting for response"
2427: " in state register for bit %#llx!",
2428: (unsigned long long)mask);
2429: return error;
2430: }
2431: return 0;
2432: }
2433:
2434: static int
2435: fw2x_get_stats(struct aq_softc *sc, aq_hw_stats_s_t *stats)
2436: {
2437: int error;
2438:
1.4 ryo 2439: AQ_MPI_LOCK(sc);
1.1 ryo 2440: /* Say to F/W to update the statistics */
2441: error = toggle_mpi_ctrl_and_wait(sc, FW2X_CTRL_STATISTICS, 1, 25);
2442: if (error != 0) {
2443: device_printf(sc->sc_dev,
2444: "fw2x> statistics update error %d\n", error);
1.4 ryo 2445: goto failure;
1.1 ryo 2446: }
2447:
2448: CTASSERT(sizeof(fw2x_msm_statistics_t) <= sizeof(struct aq_hw_stats_s));
2449: error = aq_fw_downld_dwords(sc,
2450: sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, msm), (uint32_t *)stats,
2451: sizeof(fw2x_msm_statistics_t) / sizeof(uint32_t));
2452: if (error != 0) {
2453: device_printf(sc->sc_dev,
2454: "fw2x> download statistics data FAILED, error %d", error);
1.4 ryo 2455: goto failure;
1.1 ryo 2456: }
2457: stats->dpc = AQ_READ_REG(sc, RX_DMA_DROP_PKT_CNT_REG);
2458: stats->cprc = AQ_READ_REG(sc, RX_DMA_COALESCED_PKT_CNT_REG);
2459:
1.4 ryo 2460: failure:
2461: AQ_MPI_UNLOCK(sc);
2462: return error;
2463: }
2464:
2465: #if NSYSMON_ENVSYS > 0
2466: static int
2467: fw2x_get_temperature(struct aq_softc *sc, uint32_t *temp)
2468: {
2469: int error;
2470: uint32_t value, celsius;
2471:
2472: AQ_MPI_LOCK(sc);
2473:
2474: /* Say to F/W to update the temperature */
2475: error = toggle_mpi_ctrl_and_wait(sc, FW2X_CTRL_TEMPERATURE, 1, 25);
2476: if (error != 0)
2477: goto failure;
2478:
2479: error = aq_fw_downld_dwords(sc,
2480: sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, phy_info2),
2481: &value, sizeof(value) / sizeof(uint32_t));
2482: if (error != 0)
2483: goto failure;
2484:
2485: /* 1/256 decrees C to microkelvin */
2486: celsius = __SHIFTOUT(value, PHYINFO2_TEMPERATURE);
2487: if (celsius == 0) {
2488: error = EIO;
2489: goto failure;
2490: }
2491: *temp = celsius * (1000000 / 256) + 273150000;
2492:
2493: failure:
2494: AQ_MPI_UNLOCK(sc);
1.1 ryo 2495: return 0;
2496: }
1.4 ryo 2497: #endif
1.1 ryo 2498:
2499: static int
2500: aq_fw_downld_dwords(struct aq_softc *sc, uint32_t addr, uint32_t *p,
2501: uint32_t cnt)
2502: {
2503: uint32_t v;
2504: int error = 0;
2505:
2506: WAIT_FOR(AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG) == 1, 1, 10000, &error);
2507: if (error != 0) {
2508: AQ_WRITE_REG(sc, AQ_FW_SEM_RAM_REG, 1);
2509: v = AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG);
2510: if (v == 0) {
2511: device_printf(sc->sc_dev,
2512: "%s:%d: timeout\n", __func__, __LINE__);
2513: return ETIMEDOUT;
2514: }
2515: }
2516:
2517: AQ_WRITE_REG(sc, AQ_FW_MBOX_ADDR_REG, addr);
2518:
2519: error = 0;
2520: for (; cnt > 0 && error == 0; cnt--) {
2521: /* execute mailbox interface */
2522: AQ_WRITE_REG_BIT(sc, AQ_FW_MBOX_CMD_REG,
2523: AQ_FW_MBOX_CMD_EXECUTE, 1);
2524: if (sc->sc_features & FEATURES_REV_B1) {
2525: WAIT_FOR(AQ_READ_REG(sc, AQ_FW_MBOX_ADDR_REG) != addr,
2526: 1, 1000, &error);
2527: } else {
2528: WAIT_FOR((AQ_READ_REG(sc, AQ_FW_MBOX_CMD_REG) &
2529: AQ_FW_MBOX_CMD_BUSY) == 0,
2530: 1, 1000, &error);
2531: }
2532: *p++ = AQ_READ_REG(sc, AQ_FW_MBOX_VAL_REG);
2533: addr += sizeof(uint32_t);
2534: }
2535: AQ_WRITE_REG(sc, AQ_FW_SEM_RAM_REG, 1);
2536:
2537: if (error != 0)
2538: device_printf(sc->sc_dev,
2539: "%s:%d: timeout\n", __func__, __LINE__);
2540:
2541: return error;
2542: }
2543:
2544: /* read my mac address */
2545: static int
2546: aq_get_mac_addr(struct aq_softc *sc)
2547: {
2548: uint32_t mac_addr[2];
2549: uint32_t efuse_shadow_addr;
2550: int err;
2551:
2552: efuse_shadow_addr = 0;
2553: if (FW_VERSION_MAJOR(sc) >= 2)
2554: efuse_shadow_addr = AQ_READ_REG(sc, FW2X_MPI_EFUSEADDR_REG);
2555: else
2556: efuse_shadow_addr = AQ_READ_REG(sc, FW1X_MPI_EFUSEADDR_REG);
2557:
2558: if (efuse_shadow_addr == 0) {
2559: aprint_error_dev(sc->sc_dev, "cannot get efuse addr\n");
2560: return ENXIO;
2561: }
2562:
2563: memset(mac_addr, 0, sizeof(mac_addr));
2564: err = aq_fw_downld_dwords(sc, efuse_shadow_addr + (40 * 4),
2565: mac_addr, __arraycount(mac_addr));
2566: if (err < 0)
2567: return err;
2568:
2569: if (mac_addr[0] == 0 && mac_addr[1] == 0) {
2570: aprint_error_dev(sc->sc_dev, "mac address not found\n");
2571: return ENXIO;
2572: }
2573:
1.18 ryo 2574: mac_addr[0] = htobe32(mac_addr[0]);
2575: mac_addr[1] = htobe32(mac_addr[1]);
1.1 ryo 2576:
2577: memcpy(sc->sc_enaddr.ether_addr_octet,
2578: (uint8_t *)mac_addr, ETHER_ADDR_LEN);
2579: aprint_normal_dev(sc->sc_dev, "Etheraddr: %s\n",
2580: ether_sprintf(sc->sc_enaddr.ether_addr_octet));
2581:
2582: return 0;
2583: }
2584:
2585: /* set multicast filter. index 0 for own address */
2586: static int
2587: aq_set_mac_addr(struct aq_softc *sc, int index, uint8_t *enaddr)
2588: {
2589: uint32_t h, l;
2590:
2591: if (index >= AQ_HW_MAC_NUM)
2592: return EINVAL;
2593:
2594: if (enaddr == NULL) {
2595: /* disable */
2596: AQ_WRITE_REG_BIT(sc,
2597: RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0);
2598: return 0;
2599: }
2600:
2601: h = (enaddr[0] << 8) | (enaddr[1]);
1.5 msaitoh 2602: l = ((uint32_t)enaddr[2] << 24) | (enaddr[3] << 16) |
1.1 ryo 2603: (enaddr[4] << 8) | (enaddr[5]);
2604:
2605: /* disable, set, and enable */
2606: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0);
2607: AQ_WRITE_REG(sc, RPF_L2UC_LSW_REG(index), l);
2608: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index),
2609: RPF_L2UC_MSW_MACADDR_HI, h);
2610: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_ACTION, 1);
2611: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 1);
2612:
2613: return 0;
2614: }
2615:
2616: static int
2617: aq_set_capability(struct aq_softc *sc)
2618: {
2619: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2620: int ip4csum_tx =
2621: ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) == 0) ? 0 : 1;
2622: int ip4csum_rx =
2623: ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) ? 0 : 1;
2624: int l4csum_tx = ((ifp->if_capenable &
2625: (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx |
2626: IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) == 0) ? 0 : 1;
2627: int l4csum_rx =
2628: ((ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
2629: IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) == 0) ? 0 : 1;
2630: uint32_t lso =
2631: ((ifp->if_capenable & (IFCAP_TSOv4 | IFCAP_TSOv6)) == 0) ?
2632: 0 : 0xffffffff;
2633: uint32_t lro = ((ifp->if_capenable & IFCAP_LRO) == 0) ?
2634: 0 : 0xffffffff;
2635: uint32_t i, v;
2636:
2637: /* TX checksums offloads*/
2638: AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_IP4CSUM_EN, ip4csum_tx);
2639: AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_L4CSUM_EN, l4csum_tx);
2640:
2641: /* RX checksums offloads*/
2642: AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_IP4CSUM_EN, ip4csum_rx);
2643: AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_L4CSUM_EN, l4csum_rx);
2644:
2645: /* LSO offloads*/
2646: AQ_WRITE_REG(sc, TDM_LSO_EN_REG, lso);
2647:
2648: #define AQ_B0_LRO_RXD_MAX 16
2649: v = (8 < AQ_B0_LRO_RXD_MAX) ? 3 :
2650: (4 < AQ_B0_LRO_RXD_MAX) ? 2 :
2651: (2 < AQ_B0_LRO_RXD_MAX) ? 1 : 0;
2652: for (i = 0; i < AQ_RINGS_NUM; i++) {
2653: AQ_WRITE_REG_BIT(sc, RPO_LRO_LDES_MAX_REG(i),
2654: RPO_LRO_LDES_MAX_MASK(i), v);
2655: }
2656:
2657: AQ_WRITE_REG_BIT(sc, RPO_LRO_TB_DIV_REG, RPO_LRO_TB_DIV, 0x61a);
2658: AQ_WRITE_REG_BIT(sc, RPO_LRO_INACTIVE_IVAL_REG,
2659: RPO_LRO_INACTIVE_IVAL, 0);
2660: /*
2661: * the LRO timebase divider is 5 uS (0x61a),
2662: * to get a maximum coalescing interval of 250 uS,
2663: * we need to multiply by 50(0x32) to get
2664: * the default value 250 uS
2665: */
2666: AQ_WRITE_REG_BIT(sc, RPO_LRO_MAX_COALESCING_IVAL_REG,
2667: RPO_LRO_MAX_COALESCING_IVAL, 50);
2668: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2669: RPO_LRO_CONF_QSESSION_LIMIT, 1);
2670: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2671: RPO_LRO_CONF_TOTAL_DESC_LIMIT, 2);
2672: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2673: RPO_LRO_CONF_PATCHOPTIMIZATION_EN, 0);
2674: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2675: RPO_LRO_CONF_MIN_PAYLOAD_OF_FIRST_PKT, 10);
2676: AQ_WRITE_REG(sc, RPO_LRO_RSC_MAX_REG, 1);
2677: AQ_WRITE_REG(sc, RPO_LRO_ENABLE_REG, lro);
2678:
2679: return 0;
2680: }
2681:
2682: static int
2683: aq_set_filter(struct aq_softc *sc)
2684: {
2685: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2686: struct ethercom *ec = &sc->sc_ethercom;
2687: struct ether_multi *enm;
2688: struct ether_multistep step;
2689: int idx, error = 0;
2690:
2691: if (ifp->if_flags & IFF_PROMISC) {
2692: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_PROMISC,
2693: (ifp->if_flags & IFF_PROMISC) ? 1 : 0);
2694: ec->ec_flags |= ETHER_F_ALLMULTI;
2695: goto done;
2696: }
2697:
2698: /* clear all table */
2699: for (idx = 0; idx < AQ_HW_MAC_NUM; idx++) {
2700: if (idx == AQ_HW_MAC_OWN) /* already used for own */
2701: continue;
2702: aq_set_mac_addr(sc, idx, NULL);
2703: }
2704:
2705: /* don't accept all multicast */
2706: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG,
2707: RPF_MCAST_FILTER_MASK_ALLMULTI, 0);
2708: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0),
2709: RPF_MCAST_FILTER_EN, 0);
2710:
2711: idx = 0;
2712: ETHER_LOCK(ec);
2713: ETHER_FIRST_MULTI(step, ec, enm);
2714: while (enm != NULL) {
2715: if (idx == AQ_HW_MAC_OWN)
2716: idx++;
2717:
2718: if ((idx >= AQ_HW_MAC_NUM) ||
2719: memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
2720: /*
2721: * too many filters.
2722: * fallback to accept all multicast addresses.
2723: */
2724: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG,
2725: RPF_MCAST_FILTER_MASK_ALLMULTI, 1);
2726: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0),
2727: RPF_MCAST_FILTER_EN, 1);
2728: ec->ec_flags |= ETHER_F_ALLMULTI;
2729: ETHER_UNLOCK(ec);
2730: goto done;
2731: }
2732:
2733: /* add a filter */
2734: aq_set_mac_addr(sc, idx++, enm->enm_addrlo);
2735:
2736: ETHER_NEXT_MULTI(step, enm);
2737: }
2738: ec->ec_flags &= ~ETHER_F_ALLMULTI;
2739: ETHER_UNLOCK(ec);
2740:
2741: done:
2742: return error;
2743: }
2744:
2745: static int
2746: aq_ifmedia_change(struct ifnet * const ifp)
2747: {
2748: struct aq_softc *sc = ifp->if_softc;
2749: aq_link_speed_t rate = AQ_LINK_NONE;
2750: aq_link_fc_t fc = AQ_FC_NONE;
2751: aq_link_eee_t eee = AQ_EEE_DISABLE;
2752:
2753: if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER)
2754: return EINVAL;
2755:
2756: switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) {
2757: case IFM_AUTO:
2758: rate = AQ_LINK_AUTO;
2759: break;
2760: case IFM_NONE:
2761: rate = AQ_LINK_NONE;
2762: break;
2763: case IFM_100_TX:
2764: rate = AQ_LINK_100M;
2765: break;
2766: case IFM_1000_T:
2767: rate = AQ_LINK_1G;
2768: break;
2769: case IFM_2500_T:
2770: rate = AQ_LINK_2G5;
2771: break;
2772: case IFM_5000_T:
2773: rate = AQ_LINK_5G;
2774: break;
2775: case IFM_10G_T:
2776: rate = AQ_LINK_10G;
2777: break;
2778: default:
2779: device_printf(sc->sc_dev, "unknown media: 0x%X\n",
2780: IFM_SUBTYPE(sc->sc_media.ifm_media));
2781: return ENODEV;
2782: }
2783:
2784: if (sc->sc_media.ifm_media & IFM_FLOW)
2785: fc = AQ_FC_ALL;
2786:
2787: /* XXX: todo EEE */
2788:
2789: /* re-initialize hardware with new parameters */
2790: aq_set_linkmode(sc, rate, fc, eee);
2791:
2792: return 0;
2793: }
2794:
2795: static void
2796: aq_ifmedia_status(struct ifnet * const ifp, struct ifmediareq *ifmr)
2797: {
2798: struct aq_softc *sc = ifp->if_softc;
2799:
1.11 ryo 2800: /* update ifm_active */
1.1 ryo 2801: ifmr->ifm_active = IFM_ETHER;
1.11 ryo 2802: if (sc->sc_link_fc & AQ_FC_RX)
2803: ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2804: if (sc->sc_link_fc & AQ_FC_TX)
2805: ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2806:
2807: switch (sc->sc_link_rate) {
2808: case AQ_LINK_100M:
2809: /* XXX: need to detect fulldup or halfdup */
2810: ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
2811: break;
2812: case AQ_LINK_1G:
2813: ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
2814: break;
2815: case AQ_LINK_2G5:
2816: ifmr->ifm_active |= IFM_2500_T | IFM_FDX;
2817: break;
2818: case AQ_LINK_5G:
2819: ifmr->ifm_active |= IFM_5000_T | IFM_FDX;
2820: break;
2821: case AQ_LINK_10G:
2822: ifmr->ifm_active |= IFM_10G_T | IFM_FDX;
2823: break;
2824: default:
2825: ifmr->ifm_active |= IFM_NONE;
2826: break;
2827: }
2828:
2829: /* update ifm_status */
1.1 ryo 2830: ifmr->ifm_status = IFM_AVALID;
2831: if (sc->sc_link_rate != AQ_LINK_NONE)
2832: ifmr->ifm_status |= IFM_ACTIVE;
2833: }
2834:
2835: static void
2836: aq_initmedia(struct aq_softc *sc)
2837: {
2838: #define IFMEDIA_ETHER_ADD(sc, media) \
2839: ifmedia_add(&(sc)->sc_media, IFM_ETHER | media, 0, NULL);
2840:
2841: IFMEDIA_ETHER_ADD(sc, IFM_NONE);
2842: if (sc->sc_available_rates & AQ_LINK_100M) {
2843: IFMEDIA_ETHER_ADD(sc, IFM_100_TX);
2844: IFMEDIA_ETHER_ADD(sc, IFM_100_TX | IFM_FLOW);
2845: IFMEDIA_ETHER_ADD(sc, IFM_100_TX | IFM_FDX | IFM_FLOW);
2846: }
2847: if (sc->sc_available_rates & AQ_LINK_1G) {
2848: IFMEDIA_ETHER_ADD(sc, IFM_1000_T | IFM_FDX);
2849: IFMEDIA_ETHER_ADD(sc, IFM_1000_T | IFM_FDX | IFM_FLOW);
2850: }
2851: if (sc->sc_available_rates & AQ_LINK_2G5) {
2852: IFMEDIA_ETHER_ADD(sc, IFM_2500_T | IFM_FDX);
2853: IFMEDIA_ETHER_ADD(sc, IFM_2500_T | IFM_FDX | IFM_FLOW);
2854: }
2855: if (sc->sc_available_rates & AQ_LINK_5G) {
2856: IFMEDIA_ETHER_ADD(sc, IFM_5000_T | IFM_FDX);
2857: IFMEDIA_ETHER_ADD(sc, IFM_5000_T | IFM_FDX | IFM_FLOW);
2858: }
2859: if (sc->sc_available_rates & AQ_LINK_10G) {
2860: IFMEDIA_ETHER_ADD(sc, IFM_10G_T | IFM_FDX);
2861: IFMEDIA_ETHER_ADD(sc, IFM_10G_T | IFM_FDX | IFM_FLOW);
2862: }
2863: IFMEDIA_ETHER_ADD(sc, IFM_AUTO);
2864: IFMEDIA_ETHER_ADD(sc, IFM_AUTO | IFM_FLOW);
2865:
2866: /* default: auto without flowcontrol */
2867: ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO);
2868: aq_set_linkmode(sc, AQ_LINK_AUTO, AQ_FC_NONE, AQ_EEE_DISABLE);
2869: }
2870:
2871: static int
2872: aq_set_linkmode(struct aq_softc *sc, aq_link_speed_t speed, aq_link_fc_t fc,
2873: aq_link_eee_t eee)
2874: {
2875: return sc->sc_fw_ops->set_mode(sc, MPI_INIT, speed, fc, eee);
2876: }
2877:
2878: static int
2879: aq_get_linkmode(struct aq_softc *sc, aq_link_speed_t *speed, aq_link_fc_t *fc,
2880: aq_link_eee_t *eee)
2881: {
2882: aq_hw_fw_mpi_state_t mode;
2883: int error;
2884:
2885: error = sc->sc_fw_ops->get_mode(sc, &mode, speed, fc, eee);
2886: if (error != 0)
2887: return error;
2888: if (mode != MPI_INIT)
2889: return ENXIO;
2890:
2891: return 0;
2892: }
2893:
2894: static void
2895: aq_hw_init_tx_path(struct aq_softc *sc)
2896: {
2897: /* Tx TC/RSS number config */
2898: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_TC_MODE_EN, 1);
2899:
2900: AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG,
2901: THM_LSO_TCP_FLAG1_FIRST, 0x0ff6);
2902: AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG,
2903: THM_LSO_TCP_FLAG1_MID, 0x0ff6);
2904: AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG2_REG,
2905: THM_LSO_TCP_FLAG2_LAST, 0x0f7f);
2906:
2907: /* misc */
2908: AQ_WRITE_REG(sc, TX_TPO2_REG,
2909: (sc->sc_features & FEATURES_TPO2) ? TX_TPO2_EN : 0);
2910: AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_EN, 0);
2911: AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_MODE, 0);
2912:
2913: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_SCP_INS_EN, 1);
2914: }
2915:
2916: static void
2917: aq_hw_init_rx_path(struct aq_softc *sc)
2918: {
2919: int i;
2920:
2921: /* clear setting */
2922: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_TC_MODE, 0);
2923: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_FC_MODE, 0);
2924: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG, 0);
2925: for (i = 0; i < 32; i++) {
2926: AQ_WRITE_REG_BIT(sc, RPF_ETHERTYPE_FILTER_REG(i),
2927: RPF_ETHERTYPE_FILTER_EN, 0);
2928: }
2929:
2930: if (sc->sc_rss_enable) {
2931: /* Rx TC/RSS number config */
2932: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_TC_MODE, 1);
2933:
2934: /* Rx flow control */
2935: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_FC_MODE, 1);
2936:
2937: /* RSS Ring selection */
2938: switch (sc->sc_nqueues) {
2939: case 2:
2940: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG,
2941: RX_FLR_RSS_CONTROL1_EN | 0x11111111);
2942: break;
2943: case 4:
2944: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG,
2945: RX_FLR_RSS_CONTROL1_EN | 0x22222222);
2946: break;
2947: case 8:
2948: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG,
2949: RX_FLR_RSS_CONTROL1_EN | 0x33333333);
2950: break;
2951: }
2952: }
2953:
2954: /* L2 and Multicast filters */
2955: for (i = 0; i < AQ_HW_MAC_NUM; i++) {
2956: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_EN, 0);
2957: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_ACTION,
2958: RPF_ACTION_HOST);
2959: }
2960: AQ_WRITE_REG(sc, RPF_MCAST_FILTER_MASK_REG, 0);
2961: AQ_WRITE_REG(sc, RPF_MCAST_FILTER_REG(0), 0x00010fff);
2962:
2963: /* Vlan filters */
2964: AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_OUTER,
2965: ETHERTYPE_QINQ);
2966: AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_INNER,
2967: ETHERTYPE_VLAN);
1.10 ryo 2968: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, RPF_VLAN_MODE_PROMISC, 0);
1.1 ryo 2969:
2970: if (sc->sc_features & FEATURES_REV_B) {
2971: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG,
2972: RPF_VLAN_MODE_ACCEPT_UNTAGGED, 1);
2973: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG,
2974: RPF_VLAN_MODE_UNTAGGED_ACTION, RPF_ACTION_HOST);
2975: }
2976:
2977: /* misc */
2978: if (sc->sc_features & FEATURES_RPF2)
2979: AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG, RX_TCP_RSS_HASH_RPF2);
2980: else
2981: AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG, 0);
2982:
2983: /*
2984: * XXX: RX_TCP_RSS_HASH_REG:
2985: * linux set 0x000f0000
2986: * freebsd set 0x000f001e
2987: */
2988: /* RSS hash type set for IP/TCP */
2989: AQ_WRITE_REG_BIT(sc, RX_TCP_RSS_HASH_REG,
2990: RX_TCP_RSS_HASH_TYPE, 0x001e);
2991:
2992: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_EN, 1);
2993: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_ACTION, RPF_ACTION_HOST);
2994: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_THRESHOLD, 0xffff);
2995:
2996: AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_EN, 0);
2997: AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_MODE, 0);
2998: }
2999:
3000: static void
3001: aq_hw_interrupt_moderation_set(struct aq_softc *sc)
3002: {
3003: int i;
3004:
3005: if (sc->sc_intr_moderation_enable) {
3006: unsigned int tx_min, rx_min; /* 0-255 */
3007: unsigned int tx_max, rx_max; /* 0-511? */
3008:
3009: switch (sc->sc_link_rate) {
3010: case AQ_LINK_100M:
3011: tx_min = 0x4f;
3012: tx_max = 0xff;
3013: rx_min = 0x04;
3014: rx_max = 0x50;
3015: break;
3016: case AQ_LINK_1G:
3017: default:
3018: tx_min = 0x4f;
3019: tx_max = 0xff;
3020: rx_min = 0x30;
3021: rx_max = 0x80;
3022: break;
3023: case AQ_LINK_2G5:
3024: tx_min = 0x4f;
3025: tx_max = 0xff;
3026: rx_min = 0x18;
3027: rx_max = 0xe0;
3028: break;
3029: case AQ_LINK_5G:
3030: tx_min = 0x4f;
3031: tx_max = 0xff;
3032: rx_min = 0x0c;
3033: rx_max = 0x70;
3034: break;
3035: case AQ_LINK_10G:
3036: tx_min = 0x4f;
3037: tx_max = 0x1ff;
3038: rx_min = 0x06; /* freebsd use 80 */
3039: rx_max = 0x38; /* freebsd use 120 */
3040: break;
3041: }
3042:
3043: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3044: TX_DMA_INT_DESC_WRWB_EN, 0);
3045: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3046: TX_DMA_INT_DESC_MODERATE_EN, 1);
3047: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3048: RX_DMA_INT_DESC_WRWB_EN, 0);
3049: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3050: RX_DMA_INT_DESC_MODERATE_EN, 1);
3051:
3052: for (i = 0; i < AQ_RINGS_NUM; i++) {
3053: AQ_WRITE_REG(sc, TX_INTR_MODERATION_CTL_REG(i),
3054: __SHIFTIN(tx_min, TX_INTR_MODERATION_CTL_MIN) |
3055: __SHIFTIN(tx_max, TX_INTR_MODERATION_CTL_MAX) |
3056: TX_INTR_MODERATION_CTL_EN);
3057: }
3058: for (i = 0; i < AQ_RINGS_NUM; i++) {
3059: AQ_WRITE_REG(sc, RX_INTR_MODERATION_CTL_REG(i),
3060: __SHIFTIN(rx_min, RX_INTR_MODERATION_CTL_MIN) |
3061: __SHIFTIN(rx_max, RX_INTR_MODERATION_CTL_MAX) |
3062: RX_INTR_MODERATION_CTL_EN);
3063: }
3064:
3065: } else {
3066: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3067: TX_DMA_INT_DESC_WRWB_EN, 1);
3068: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3069: TX_DMA_INT_DESC_MODERATE_EN, 0);
3070: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3071: RX_DMA_INT_DESC_WRWB_EN, 1);
3072: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3073: RX_DMA_INT_DESC_MODERATE_EN, 0);
3074:
3075: for (i = 0; i < AQ_RINGS_NUM; i++) {
3076: AQ_WRITE_REG(sc, TX_INTR_MODERATION_CTL_REG(i), 0);
3077: }
3078: for (i = 0; i < AQ_RINGS_NUM; i++) {
3079: AQ_WRITE_REG(sc, RX_INTR_MODERATION_CTL_REG(i), 0);
3080: }
3081: }
3082: }
3083:
3084: static void
3085: aq_hw_qos_set(struct aq_softc *sc)
3086: {
3087: uint32_t tc = 0;
3088: uint32_t buff_size;
3089:
3090: /* TPS Descriptor rate init */
3091: AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_TA_RST, 0);
3092: AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_LIM, 0xa);
3093:
3094: /* TPS VM init */
3095: AQ_WRITE_REG_BIT(sc, TPS_DESC_VM_ARB_MODE_REG, TPS_DESC_VM_ARB_MODE, 0);
3096:
3097: /* TPS TC credits init */
3098: AQ_WRITE_REG_BIT(sc, TPS_DESC_TC_ARB_MODE_REG, TPS_DESC_TC_ARB_MODE, 0);
3099: AQ_WRITE_REG_BIT(sc, TPS_DATA_TC_ARB_MODE_REG, TPS_DATA_TC_ARB_MODE, 0);
3100:
3101: AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc),
3102: TPS_DATA_TCT_CREDIT_MAX, 0xfff);
3103: AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc),
3104: TPS_DATA_TCT_WEIGHT, 0x64);
3105: AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc),
3106: TPS_DESC_TCT_CREDIT_MAX, 0x50);
3107: AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc),
3108: TPS_DESC_TCT_WEIGHT, 0x1e);
3109:
3110: /* Tx buf size */
3111: tc = 0;
3112: buff_size = AQ_HW_TXBUF_MAX;
3113: AQ_WRITE_REG_BIT(sc, TPB_TXB_BUFSIZE_REG(tc), TPB_TXB_BUFSIZE,
3114: buff_size);
3115: AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_HI,
3116: (buff_size * (1024 / 32) * 66) / 100);
3117: AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_LO,
3118: (buff_size * (1024 / 32) * 50) / 100);
3119:
3120: /* QoS Rx buf size per TC */
3121: tc = 0;
3122: buff_size = AQ_HW_RXBUF_MAX;
3123: AQ_WRITE_REG_BIT(sc, RPB_RXB_BUFSIZE_REG(tc), RPB_RXB_BUFSIZE,
3124: buff_size);
3125: AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_EN, 0);
3126: AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_THRESH_HI,
3127: (buff_size * (1024 / 32) * 66) / 100);
3128: AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_THRESH_LO,
3129: (buff_size * (1024 / 32) * 50) / 100);
3130:
3131: /* QoS 802.1p priority -> TC mapping */
3132: int i_priority;
3133: for (i_priority = 0; i_priority < 8; i_priority++) {
3134: AQ_WRITE_REG_BIT(sc, RPF_RPB_RX_TC_UPT_REG,
3135: RPF_RPB_RX_TC_UPT_MASK(i_priority), 0);
3136: }
3137: }
3138:
3139: /* called once from aq_attach */
3140: static int
3141: aq_init_rss(struct aq_softc *sc)
3142: {
3143: CTASSERT(AQ_RSS_HASHKEY_SIZE == RSS_KEYSIZE);
3144: uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
3145: uint8_t rss_table[AQ_RSS_INDIRECTION_TABLE_MAX];
3146: unsigned int i;
3147: int error;
3148:
3149: /* initialize rss key */
3150: rss_getkey((uint8_t *)rss_key);
3151:
3152: /* hash to ring table */
3153: for (i = 0; i < AQ_RSS_INDIRECTION_TABLE_MAX; i++) {
3154: rss_table[i] = i % sc->sc_nqueues;
3155: }
3156:
3157: /*
3158: * set rss key
3159: */
3160: for (i = 0; i < __arraycount(rss_key); i++) {
3161: uint32_t key_data = sc->sc_rss_enable ? ntohl(rss_key[i]) : 0;
3162: AQ_WRITE_REG(sc, RPF_RSS_KEY_WR_DATA_REG, key_data);
3163: AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG,
3164: RPF_RSS_KEY_ADDR, __arraycount(rss_key) - 1 - i);
3165: AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG,
3166: RPF_RSS_KEY_WR_EN, 1);
3167: WAIT_FOR(AQ_READ_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG,
3168: RPF_RSS_KEY_WR_EN) == 0, 1000, 10, &error);
3169: if (error != 0) {
3170: device_printf(sc->sc_dev, "%s: rss key write timeout\n",
3171: __func__);
3172: goto rss_set_timeout;
3173: }
3174: }
3175:
3176: /*
3177: * set rss indirection table
3178: *
3179: * AQ's rss redirect table is consist of 3bit*64 (192bit) packed array.
3180: * we'll make it by __BITMAP(3) macros.
3181: */
3182: __BITMAP_TYPE(, uint16_t, 3 * AQ_RSS_INDIRECTION_TABLE_MAX) bit3x64;
3183: __BITMAP_ZERO(&bit3x64);
3184:
3185: #define AQ_3BIT_PACKED_ARRAY_SET(bitmap, idx, val) \
3186: do { \
3187: if (val & 1) { \
3188: __BITMAP_SET((idx) * 3, (bitmap)); \
3189: } else { \
3190: __BITMAP_CLR((idx) * 3, (bitmap)); \
3191: } \
3192: if (val & 2) { \
3193: __BITMAP_SET((idx) * 3 + 1, (bitmap)); \
3194: } else { \
3195: __BITMAP_CLR((idx) * 3 + 1, (bitmap)); \
3196: } \
3197: if (val & 4) { \
3198: __BITMAP_SET((idx) * 3 + 2, (bitmap)); \
3199: } else { \
3200: __BITMAP_CLR((idx) * 3 + 2, (bitmap)); \
3201: } \
3202: } while (0 /* CONSTCOND */)
3203:
3204: for (i = 0; i < AQ_RSS_INDIRECTION_TABLE_MAX; i++) {
3205: AQ_3BIT_PACKED_ARRAY_SET(&bit3x64, i, rss_table[i]);
3206: }
3207:
3208: /* write 192bit data in steps of 16bit */
3209: for (i = 0; i < (int)__arraycount(bit3x64._b); i++) {
3210: AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_WR_DATA_REG,
3211: RPF_RSS_REDIR_WR_DATA, bit3x64._b[i]);
3212: AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG,
3213: RPF_RSS_REDIR_ADDR, i);
3214: AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG,
3215: RPF_RSS_REDIR_WR_EN, 1);
3216:
3217: WAIT_FOR(AQ_READ_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG,
3218: RPF_RSS_REDIR_WR_EN) == 0, 1000, 10, &error);
3219: if (error != 0)
3220: break;
3221: }
3222:
3223: rss_set_timeout:
3224: return error;
3225: }
3226:
3227: static void
3228: aq_hw_l3_filter_set(struct aq_softc *sc)
3229: {
3230: int i;
3231:
3232: /* clear all filter */
3233: for (i = 0; i < 8; i++) {
3234: AQ_WRITE_REG_BIT(sc, RPF_L3_FILTER_REG(i),
3235: RPF_L3_FILTER_L4_EN, 0);
3236: }
3237: }
3238:
3239: static void
1.10 ryo 3240: aq_set_vlan_filters(struct aq_softc *sc)
1.1 ryo 3241: {
1.10 ryo 3242: struct ethercom *ec = &sc->sc_ethercom;
3243: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
3244: struct vlanid_list *vlanidp;
1.1 ryo 3245: int i;
3246:
1.10 ryo 3247: ETHER_LOCK(ec);
3248:
3249: /* disable all vlan filters */
3250: for (i = 0; i < RPF_VLAN_MAX_FILTERS; i++)
3251: AQ_WRITE_REG(sc, RPF_VLAN_FILTER_REG(i), 0);
3252:
3253: /* count VID */
3254: i = 0;
3255: SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list)
3256: i++;
3257:
3258: if (((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_HWFILTER) == 0) ||
3259: (ifp->if_flags & IFF_PROMISC) ||
3260: (i > RPF_VLAN_MAX_FILTERS)) {
3261: /*
3262: * no vlan hwfilter, in promiscuous mode, or too many VID?
3263: * must receive all VID
3264: */
3265: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG,
3266: RPF_VLAN_MODE_PROMISC, 1);
3267: goto done;
3268: }
3269:
3270: /* receive only selected VID */
3271: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, RPF_VLAN_MODE_PROMISC, 0);
3272: i = 0;
3273: SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) {
1.1 ryo 3274: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
1.10 ryo 3275: RPF_VLAN_FILTER_EN, 1);
1.1 ryo 3276: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3277: RPF_VLAN_FILTER_RXQ_EN, 0);
1.10 ryo 3278: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3279: RPF_VLAN_FILTER_RXQ, 0);
3280: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3281: RPF_VLAN_FILTER_ACTION, RPF_ACTION_HOST);
3282: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3283: RPF_VLAN_FILTER_ID, vlanidp->vid);
3284: i++;
1.1 ryo 3285: }
1.10 ryo 3286:
3287: done:
3288: ETHER_UNLOCK(ec);
1.1 ryo 3289: }
3290:
3291: static int
3292: aq_hw_init(struct aq_softc *sc)
3293: {
3294: uint32_t v;
3295:
3296: /* Force limit MRRS on RDM/TDM to 2K */
3297: v = AQ_READ_REG(sc, AQ_PCI_REG_CONTROL_6_REG);
3298: AQ_WRITE_REG(sc, AQ_PCI_REG_CONTROL_6_REG, (v & ~0x0707) | 0x0404);
3299:
3300: /*
3301: * TX DMA total request limit. B0 hardware is not capable to
3302: * handle more than (8K-MRRS) incoming DMA data.
3303: * Value 24 in 256byte units
3304: */
3305: AQ_WRITE_REG(sc, AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG, 24);
3306:
3307: aq_hw_init_tx_path(sc);
3308: aq_hw_init_rx_path(sc);
3309:
3310: aq_hw_interrupt_moderation_set(sc);
3311:
3312: aq_set_mac_addr(sc, AQ_HW_MAC_OWN, sc->sc_enaddr.ether_addr_octet);
3313: aq_set_linkmode(sc, AQ_LINK_NONE, AQ_FC_NONE, AQ_EEE_DISABLE);
3314:
3315: aq_hw_qos_set(sc);
3316:
3317: /* Enable interrupt */
3318: int irqmode;
3319: if (sc->sc_msix)
3320: irqmode = AQ_INTR_CTRL_IRQMODE_MSIX;
3321: else
3322: irqmode = AQ_INTR_CTRL_IRQMODE_MSI;
3323:
3324: AQ_WRITE_REG(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS);
3325: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_MULTIVEC,
3326: sc->sc_msix ? 1 : 0);
3327: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_IRQMODE, irqmode);
3328:
3329: AQ_WRITE_REG(sc, AQ_INTR_AUTOMASK_REG, 0xffffffff);
3330:
3331: AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(0),
1.5 msaitoh 3332: ((AQ_B0_ERR_INT << 24) | (1U << 31)) |
1.1 ryo 3333: ((AQ_B0_ERR_INT << 16) | (1 << 23))
3334: );
3335:
3336: /* link interrupt */
3337: if (!sc->sc_msix)
3338: sc->sc_linkstat_irq = AQ_LINKSTAT_IRQ;
3339: AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(3),
3340: __BIT(7) | sc->sc_linkstat_irq);
3341:
3342: return 0;
3343: }
3344:
3345: static int
3346: aq_update_link_status(struct aq_softc *sc)
3347: {
3348: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
3349: aq_link_speed_t rate = AQ_LINK_NONE;
3350: aq_link_fc_t fc = AQ_FC_NONE;
3351: aq_link_eee_t eee = AQ_EEE_DISABLE;
3352: unsigned int speed;
3353: int changed = 0;
3354:
3355: aq_get_linkmode(sc, &rate, &fc, &eee);
3356:
3357: if (sc->sc_link_rate != rate)
3358: changed = 1;
3359: if (sc->sc_link_fc != fc)
3360: changed = 1;
3361: if (sc->sc_link_eee != eee)
3362: changed = 1;
3363:
3364: if (changed) {
3365: switch (rate) {
3366: case AQ_LINK_100M:
3367: speed = 100;
3368: break;
3369: case AQ_LINK_1G:
3370: speed = 1000;
3371: break;
3372: case AQ_LINK_2G5:
3373: speed = 2500;
3374: break;
3375: case AQ_LINK_5G:
3376: speed = 5000;
3377: break;
3378: case AQ_LINK_10G:
3379: speed = 10000;
3380: break;
3381: case AQ_LINK_NONE:
3382: default:
3383: speed = 0;
3384: break;
3385: }
3386:
3387: if (sc->sc_link_rate == AQ_LINK_NONE) {
3388: /* link DOWN -> UP */
3389: device_printf(sc->sc_dev, "link is UP: speed=%u\n",
3390: speed);
3391: if_link_state_change(ifp, LINK_STATE_UP);
3392: } else if (rate == AQ_LINK_NONE) {
3393: /* link UP -> DOWN */
3394: device_printf(sc->sc_dev, "link is DOWN\n");
3395: if_link_state_change(ifp, LINK_STATE_DOWN);
3396: } else {
3397: device_printf(sc->sc_dev,
3398: "link mode changed: speed=%u, fc=0x%x, eee=%x\n",
3399: speed, fc, eee);
3400: }
3401:
3402: sc->sc_link_rate = rate;
3403: sc->sc_link_fc = fc;
3404: sc->sc_link_eee = eee;
3405:
3406: /* update interrupt timing according to new link speed */
3407: aq_hw_interrupt_moderation_set(sc);
3408: }
3409:
3410: return changed;
3411: }
3412:
3413: #ifdef AQ_EVENT_COUNTERS
3414: static void
3415: aq_update_statistics(struct aq_softc *sc)
3416: {
3417: int prev = sc->sc_statistics_idx;
3418: int cur = prev ^ 1;
3419:
3420: sc->sc_fw_ops->get_stats(sc, &sc->sc_statistics[cur]);
3421:
3422: /*
3423: * aq's internal statistics counter is 32bit.
3424: * cauculate delta, and add to evcount
3425: */
3426: #define ADD_DELTA(cur, prev, name) \
3427: do { \
3428: uint32_t n; \
3429: n = (uint32_t)(sc->sc_statistics[cur].name - \
3430: sc->sc_statistics[prev].name); \
3431: if (n != 0) { \
3432: AQ_EVCNT_ADD(sc, name, n); \
3433: } \
3434: } while (/*CONSTCOND*/0);
3435:
3436: ADD_DELTA(cur, prev, uprc);
3437: ADD_DELTA(cur, prev, mprc);
3438: ADD_DELTA(cur, prev, bprc);
3439: ADD_DELTA(cur, prev, prc);
3440: ADD_DELTA(cur, prev, erpr);
3441: ADD_DELTA(cur, prev, uptc);
3442: ADD_DELTA(cur, prev, mptc);
3443: ADD_DELTA(cur, prev, bptc);
3444: ADD_DELTA(cur, prev, ptc);
3445: ADD_DELTA(cur, prev, erpt);
3446: ADD_DELTA(cur, prev, mbtc);
3447: ADD_DELTA(cur, prev, bbtc);
3448: ADD_DELTA(cur, prev, mbrc);
3449: ADD_DELTA(cur, prev, bbrc);
3450: ADD_DELTA(cur, prev, ubrc);
3451: ADD_DELTA(cur, prev, ubtc);
3452: ADD_DELTA(cur, prev, dpc);
3453: ADD_DELTA(cur, prev, cprc);
3454:
3455: sc->sc_statistics_idx = cur;
3456: }
3457: #endif /* AQ_EVENT_COUNTERS */
3458:
3459: /* allocate and map one DMA block */
3460: static int
3461: _alloc_dma(struct aq_softc *sc, bus_size_t size, bus_size_t *sizep,
3462: void **addrp, bus_dmamap_t *mapp, bus_dma_segment_t *seg)
3463: {
3464: int nsegs, error;
3465:
3466: if ((error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, seg,
3467: 1, &nsegs, 0)) != 0) {
3468: aprint_error_dev(sc->sc_dev,
3469: "unable to allocate DMA buffer, error=%d\n", error);
3470: goto fail_alloc;
3471: }
3472:
3473: if ((error = bus_dmamem_map(sc->sc_dmat, seg, 1, size, addrp,
3474: BUS_DMA_COHERENT)) != 0) {
3475: aprint_error_dev(sc->sc_dev,
3476: "unable to map DMA buffer, error=%d\n", error);
3477: goto fail_map;
3478: }
3479:
3480: if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
3481: 0, mapp)) != 0) {
3482: aprint_error_dev(sc->sc_dev,
3483: "unable to create DMA map, error=%d\n", error);
3484: goto fail_create;
3485: }
3486:
3487: if ((error = bus_dmamap_load(sc->sc_dmat, *mapp, *addrp, size, NULL,
3488: 0)) != 0) {
3489: aprint_error_dev(sc->sc_dev,
3490: "unable to load DMA map, error=%d\n", error);
3491: goto fail_load;
3492: }
3493:
3494: *sizep = size;
3495: return 0;
3496:
3497: fail_load:
3498: bus_dmamap_destroy(sc->sc_dmat, *mapp);
3499: *mapp = NULL;
3500: fail_create:
3501: bus_dmamem_unmap(sc->sc_dmat, *addrp, size);
3502: *addrp = NULL;
3503: fail_map:
3504: bus_dmamem_free(sc->sc_dmat, seg, 1);
3505: memset(seg, 0, sizeof(*seg));
3506: fail_alloc:
3507: *sizep = 0;
3508: return error;
3509: }
3510:
3511: static void
3512: _free_dma(struct aq_softc *sc, bus_size_t *sizep, void **addrp,
3513: bus_dmamap_t *mapp, bus_dma_segment_t *seg)
3514: {
3515: if (*mapp != NULL) {
3516: bus_dmamap_destroy(sc->sc_dmat, *mapp);
3517: *mapp = NULL;
3518: }
3519: if (*addrp != NULL) {
3520: bus_dmamem_unmap(sc->sc_dmat, *addrp, *sizep);
3521: *addrp = NULL;
3522: }
3523: if (*sizep != 0) {
3524: bus_dmamem_free(sc->sc_dmat, seg, 1);
3525: memset(seg, 0, sizeof(*seg));
3526: *sizep = 0;
3527: }
3528: }
3529:
3530: static int
3531: aq_txring_alloc(struct aq_softc *sc, struct aq_txring *txring)
3532: {
3533: int i, error;
3534:
3535: /* allocate tx descriptors */
3536: error = _alloc_dma(sc, sizeof(aq_tx_desc_t) * AQ_TXD_NUM,
3537: &txring->txr_txdesc_size, (void **)&txring->txr_txdesc,
3538: &txring->txr_txdesc_dmamap, txring->txr_txdesc_seg);
3539: if (error != 0)
3540: return error;
3541:
3542: memset(txring->txr_txdesc, 0, sizeof(aq_tx_desc_t) * AQ_TXD_NUM);
3543:
3544: /* fill tx ring with dmamap */
3545: for (i = 0; i < AQ_TXD_NUM; i++) {
3546: #define AQ_MAXDMASIZE (16 * 1024)
3547: #define AQ_NTXSEGS 32
3548: /* XXX: TODO: error check */
3549: bus_dmamap_create(sc->sc_dmat, AQ_MAXDMASIZE, AQ_NTXSEGS,
3550: AQ_MAXDMASIZE, 0, 0, &txring->txr_mbufs[i].dmamap);
3551: }
3552: return 0;
3553: }
3554:
3555: static void
3556: aq_txring_free(struct aq_softc *sc, struct aq_txring *txring)
3557: {
3558: int i;
3559:
3560: _free_dma(sc, &txring->txr_txdesc_size, (void **)&txring->txr_txdesc,
3561: &txring->txr_txdesc_dmamap, txring->txr_txdesc_seg);
3562:
3563: for (i = 0; i < AQ_TXD_NUM; i++) {
3564: if (txring->txr_mbufs[i].dmamap != NULL) {
3565: if (txring->txr_mbufs[i].m != NULL) {
3566: bus_dmamap_unload(sc->sc_dmat,
3567: txring->txr_mbufs[i].dmamap);
3568: m_freem(txring->txr_mbufs[i].m);
3569: txring->txr_mbufs[i].m = NULL;
3570: }
3571: bus_dmamap_destroy(sc->sc_dmat,
3572: txring->txr_mbufs[i].dmamap);
3573: txring->txr_mbufs[i].dmamap = NULL;
3574: }
3575: }
3576: }
3577:
3578: static int
3579: aq_rxring_alloc(struct aq_softc *sc, struct aq_rxring *rxring)
3580: {
3581: int i, error;
3582:
3583: /* allocate rx descriptors */
3584: error = _alloc_dma(sc, sizeof(aq_rx_desc_t) * AQ_RXD_NUM,
3585: &rxring->rxr_rxdesc_size, (void **)&rxring->rxr_rxdesc,
3586: &rxring->rxr_rxdesc_dmamap, rxring->rxr_rxdesc_seg);
3587: if (error != 0)
3588: return error;
3589:
3590: memset(rxring->rxr_rxdesc, 0, sizeof(aq_rx_desc_t) * AQ_RXD_NUM);
3591:
3592: /* fill rxring with dmamaps */
3593: for (i = 0; i < AQ_RXD_NUM; i++) {
3594: rxring->rxr_mbufs[i].m = NULL;
3595: /* XXX: TODO: error check */
3596: bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 0,
3597: &rxring->rxr_mbufs[i].dmamap);
3598: }
3599: return 0;
3600: }
3601:
3602: static void
3603: aq_rxdrain(struct aq_softc *sc, struct aq_rxring *rxring)
3604: {
3605: int i;
3606:
3607: /* free all mbufs allocated for RX */
3608: for (i = 0; i < AQ_RXD_NUM; i++) {
3609: if (rxring->rxr_mbufs[i].m != NULL) {
3610: bus_dmamap_unload(sc->sc_dmat,
3611: rxring->rxr_mbufs[i].dmamap);
3612: m_freem(rxring->rxr_mbufs[i].m);
3613: rxring->rxr_mbufs[i].m = NULL;
3614: }
3615: }
3616: }
3617:
3618: static void
3619: aq_rxring_free(struct aq_softc *sc, struct aq_rxring *rxring)
3620: {
3621: int i;
3622:
3623: /* free all mbufs and dmamaps */
3624: aq_rxdrain(sc, rxring);
3625: for (i = 0; i < AQ_RXD_NUM; i++) {
3626: if (rxring->rxr_mbufs[i].dmamap != NULL) {
3627: bus_dmamap_destroy(sc->sc_dmat,
3628: rxring->rxr_mbufs[i].dmamap);
3629: rxring->rxr_mbufs[i].dmamap = NULL;
3630: }
3631: }
3632:
3633: /* free RX descriptor */
3634: _free_dma(sc, &rxring->rxr_rxdesc_size, (void **)&rxring->rxr_rxdesc,
3635: &rxring->rxr_rxdesc_dmamap, rxring->rxr_rxdesc_seg);
3636: }
3637:
3638: static void
3639: aq_rxring_setmbuf(struct aq_softc *sc, struct aq_rxring *rxring, int idx,
3640: struct mbuf *m)
3641: {
3642: int error;
3643:
3644: /* if mbuf already exists, unload and free */
3645: if (rxring->rxr_mbufs[idx].m != NULL) {
3646: bus_dmamap_unload(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap);
3647: m_freem(rxring->rxr_mbufs[idx].m);
3648: rxring->rxr_mbufs[idx].m = NULL;
3649: }
3650:
3651: rxring->rxr_mbufs[idx].m = m;
3652:
3653: m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
3654: error = bus_dmamap_load_mbuf(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap,
3655: m, BUS_DMA_READ | BUS_DMA_NOWAIT);
3656: if (error) {
3657: device_printf(sc->sc_dev,
3658: "unable to load rx DMA map %d, error = %d\n", idx, error);
3659: panic("%s: unable to load rx DMA map. error=%d",
3660: __func__, error);
3661: }
3662: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap, 0,
3663: rxring->rxr_mbufs[idx].dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
3664: }
3665:
3666: static inline void
3667: aq_rxring_reset_desc(struct aq_softc *sc, struct aq_rxring *rxring, int idx)
3668: {
3669: /* refill rxdesc, and sync */
3670: rxring->rxr_rxdesc[idx].read.buf_addr =
3671: htole64(rxring->rxr_mbufs[idx].dmamap->dm_segs[0].ds_addr);
3672: rxring->rxr_rxdesc[idx].read.hdr_addr = 0;
3673: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_rxdesc_dmamap,
3674: sizeof(aq_rx_desc_t) * idx, sizeof(aq_rx_desc_t),
3675: BUS_DMASYNC_PREWRITE);
3676: }
3677:
3678: static struct mbuf *
3679: aq_alloc_mbuf(void)
3680: {
3681: struct mbuf *m;
3682:
3683: MGETHDR(m, M_DONTWAIT, MT_DATA);
3684: if (m == NULL)
3685: return NULL;
3686:
3687: MCLGET(m, M_DONTWAIT);
3688: if ((m->m_flags & M_EXT) == 0) {
3689: m_freem(m);
3690: return NULL;
3691: }
3692:
3693: return m;
3694: }
3695:
3696: /* allocate mbuf and unload dmamap */
3697: static int
3698: aq_rxring_add(struct aq_softc *sc, struct aq_rxring *rxring, int idx)
3699: {
3700: struct mbuf *m;
3701:
3702: m = aq_alloc_mbuf();
3703: if (m == NULL)
3704: return ENOBUFS;
3705:
3706: aq_rxring_setmbuf(sc, rxring, idx, m);
3707: return 0;
3708: }
3709:
3710: static int
3711: aq_txrx_rings_alloc(struct aq_softc *sc)
3712: {
3713: int n, error;
3714:
3715: for (n = 0; n < sc->sc_nqueues; n++) {
3716: sc->sc_queue[n].sc = sc;
3717: sc->sc_queue[n].txring.txr_sc = sc;
3718: sc->sc_queue[n].txring.txr_index = n;
3719: mutex_init(&sc->sc_queue[n].txring.txr_mutex, MUTEX_DEFAULT,
3720: IPL_NET);
3721: error = aq_txring_alloc(sc, &sc->sc_queue[n].txring);
3722: if (error != 0)
3723: goto failure;
3724:
3725: error = aq_tx_pcq_alloc(sc, &sc->sc_queue[n].txring);
3726: if (error != 0)
3727: goto failure;
3728:
3729: sc->sc_queue[n].rxring.rxr_sc = sc;
3730: sc->sc_queue[n].rxring.rxr_index = n;
3731: mutex_init(&sc->sc_queue[n].rxring.rxr_mutex, MUTEX_DEFAULT,
3732: IPL_NET);
3733: error = aq_rxring_alloc(sc, &sc->sc_queue[n].rxring);
3734: if (error != 0)
3735: break;
3736: }
3737:
3738: failure:
3739: return error;
3740: }
3741:
3742: static void
3743: aq_txrx_rings_free(struct aq_softc *sc)
3744: {
3745: int n;
3746:
3747: for (n = 0; n < sc->sc_nqueues; n++) {
3748: aq_txring_free(sc, &sc->sc_queue[n].txring);
3749: mutex_destroy(&sc->sc_queue[n].txring.txr_mutex);
3750:
3751: aq_tx_pcq_free(sc, &sc->sc_queue[n].txring);
3752:
3753: aq_rxring_free(sc, &sc->sc_queue[n].rxring);
3754: mutex_destroy(&sc->sc_queue[n].rxring.rxr_mutex);
3755: }
3756: }
3757:
3758: static int
3759: aq_tx_pcq_alloc(struct aq_softc *sc, struct aq_txring *txring)
3760: {
3761: int error = 0;
3762: txring->txr_softint = NULL;
3763:
3764: txring->txr_pcq = pcq_create(AQ_TXD_NUM, KM_NOSLEEP);
3765: if (txring->txr_pcq == NULL) {
3766: aprint_error_dev(sc->sc_dev,
3767: "unable to allocate pcq for TXring[%d]\n",
3768: txring->txr_index);
3769: error = ENOMEM;
3770: goto done;
3771: }
3772:
3773: txring->txr_softint = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
3774: aq_deferred_transmit, txring);
3775: if (txring->txr_softint == NULL) {
3776: aprint_error_dev(sc->sc_dev,
3777: "unable to establish softint for TXring[%d]\n",
3778: txring->txr_index);
3779: error = ENOENT;
3780: }
3781:
3782: done:
3783: return error;
3784: }
3785:
3786: static void
3787: aq_tx_pcq_free(struct aq_softc *sc, struct aq_txring *txring)
3788: {
3789: struct mbuf *m;
3790:
3791: if (txring->txr_softint != NULL) {
3792: softint_disestablish(txring->txr_softint);
3793: txring->txr_softint = NULL;
3794: }
3795:
3796: if (txring->txr_pcq != NULL) {
3797: while ((m = pcq_get(txring->txr_pcq)) != NULL)
3798: m_freem(m);
3799: pcq_destroy(txring->txr_pcq);
3800: txring->txr_pcq = NULL;
3801: }
3802: }
3803:
1.4 ryo 3804: #if NSYSMON_ENVSYS > 0
3805: static void
3806: aq_temp_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
3807: {
3808: struct aq_softc *sc;
3809: uint32_t temp;
3810: int error;
3811:
3812: sc = sme->sme_cookie;
3813:
3814: error = sc->sc_fw_ops->get_temperature(sc, &temp);
3815: if (error == 0) {
3816: edata->value_cur = temp;
3817: edata->state = ENVSYS_SVALID;
3818: } else {
3819: edata->state = ENVSYS_SINVALID;
3820: }
3821: }
3822: #endif
3823:
1.1 ryo 3824: static void
3825: aq_tick(void *arg)
3826: {
3827: struct aq_softc *sc = arg;
3828:
3829: if (sc->sc_poll_linkstat || sc->sc_detect_linkstat) {
3830: sc->sc_detect_linkstat = false;
3831: aq_update_link_status(sc);
3832: }
3833:
3834: #ifdef AQ_EVENT_COUNTERS
3835: if (sc->sc_poll_statistics)
3836: aq_update_statistics(sc);
3837: #endif
3838:
3839: if (sc->sc_poll_linkstat
3840: #ifdef AQ_EVENT_COUNTERS
3841: || sc->sc_poll_statistics
3842: #endif
3843: ) {
3844: callout_schedule(&sc->sc_tick_ch, hz);
3845: }
3846: }
3847:
3848: /* interrupt enable/disable */
3849: static void
3850: aq_enable_intr(struct aq_softc *sc, bool link, bool txrx)
3851: {
3852: uint32_t imask = 0;
3853: int i;
3854:
3855: if (txrx) {
3856: for (i = 0; i < sc->sc_nqueues; i++) {
3857: imask |= __BIT(sc->sc_tx_irq[i]);
3858: imask |= __BIT(sc->sc_rx_irq[i]);
3859: }
3860: }
3861:
3862: if (link)
3863: imask |= __BIT(sc->sc_linkstat_irq);
3864:
3865: AQ_WRITE_REG(sc, AQ_INTR_MASK_REG, imask);
3866: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff);
3867: }
3868:
3869: static int
3870: aq_legacy_intr(void *arg)
3871: {
3872: struct aq_softc *sc = arg;
3873: uint32_t status;
3874: int nintr = 0;
3875:
3876: status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
3877: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff);
3878:
3879: if (status & __BIT(sc->sc_linkstat_irq)) {
3880: sc->sc_detect_linkstat = true;
3881: callout_schedule(&sc->sc_tick_ch, 0);
3882: nintr++;
3883: }
3884:
3885: if (status & __BIT(sc->sc_rx_irq[0])) {
3886: nintr += aq_rx_intr(&sc->sc_queue[0].rxring);
3887: }
3888:
3889: if (status & __BIT(sc->sc_tx_irq[0])) {
3890: nintr += aq_tx_intr(&sc->sc_queue[0].txring);
3891: }
3892:
3893: return nintr;
3894: }
3895:
3896: static int
3897: aq_txrx_intr(void *arg)
3898: {
3899: struct aq_queue *queue = arg;
3900: struct aq_softc *sc = queue->sc;
3901: struct aq_txring *txring = &queue->txring;
3902: struct aq_rxring *rxring = &queue->rxring;
3903: uint32_t status;
3904: int nintr = 0;
3905: int txringidx, rxringidx, txirq, rxirq;
3906:
3907: txringidx = txring->txr_index;
3908: rxringidx = rxring->rxr_index;
3909: txirq = sc->sc_tx_irq[txringidx];
3910: rxirq = sc->sc_rx_irq[rxringidx];
3911:
3912: status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
3913: if ((status & (__BIT(txirq) | __BIT(rxirq))) == 0) {
3914: /* stray interrupt? */
3915: return 0;
3916: }
3917:
3918: nintr += aq_rx_intr(rxring);
3919: nintr += aq_tx_intr(txring);
3920:
3921: return nintr;
3922: }
3923:
3924: static int
3925: aq_link_intr(void *arg)
3926: {
3927: struct aq_softc *sc = arg;
3928: uint32_t status;
3929: int nintr = 0;
3930:
3931: status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
3932: if (status & __BIT(sc->sc_linkstat_irq)) {
3933: sc->sc_detect_linkstat = true;
3934: callout_schedule(&sc->sc_tick_ch, 0);
3935: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG,
3936: __BIT(sc->sc_linkstat_irq));
3937: nintr++;
3938: }
3939:
3940: return nintr;
3941: }
3942:
3943: static void
3944: aq_txring_reset(struct aq_softc *sc, struct aq_txring *txring, bool start)
3945: {
3946: const int ringidx = txring->txr_index;
3947: int i;
3948:
3949: mutex_enter(&txring->txr_mutex);
3950:
3951: txring->txr_prodidx = 0;
3952: txring->txr_considx = 0;
3953: txring->txr_nfree = AQ_TXD_NUM;
3954: txring->txr_active = false;
3955:
3956: /* free mbufs untransmitted */
3957: for (i = 0; i < AQ_TXD_NUM; i++) {
3958: if (txring->txr_mbufs[i].m != NULL) {
3959: m_freem(txring->txr_mbufs[i].m);
3960: txring->txr_mbufs[i].m = NULL;
3961: }
3962: }
3963:
3964: /* disable DMA */
3965: AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx), TX_DMA_DESC_EN, 0);
3966:
3967: if (start) {
3968: /* TX descriptor physical address */
3969: paddr_t paddr = txring->txr_txdesc_dmamap->dm_segs[0].ds_addr;
3970: AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRLSW_REG(ringidx), paddr);
3971: AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRMSW_REG(ringidx),
3972: (uint32_t)((uint64_t)paddr >> 32));
3973:
3974: /* TX descriptor size */
3975: AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx), TX_DMA_DESC_LEN,
3976: AQ_TXD_NUM / 8);
3977:
3978: /* reload TAIL pointer */
3979: txring->txr_prodidx = txring->txr_considx =
3980: AQ_READ_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(ringidx));
3981: AQ_WRITE_REG(sc, TX_DMA_DESC_WRWB_THRESH_REG(ringidx), 0);
3982:
3983: /* Mapping interrupt vector */
3984: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(ringidx),
3985: AQ_INTR_IRQ_MAP_TX_IRQMAP(ringidx), sc->sc_tx_irq[ringidx]);
3986: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(ringidx),
3987: AQ_INTR_IRQ_MAP_TX_EN(ringidx), true);
3988:
3989: /* enable DMA */
3990: AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx),
3991: TX_DMA_DESC_EN, 1);
3992:
3993: const int cpuid = 0; /* XXX? */
3994: AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(ringidx),
3995: TDM_DCAD_CPUID, cpuid);
3996: AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(ringidx),
3997: TDM_DCAD_CPUID_EN, 0);
3998:
3999: txring->txr_active = true;
4000: }
4001:
4002: mutex_exit(&txring->txr_mutex);
4003: }
4004:
4005: static int
4006: aq_rxring_reset(struct aq_softc *sc, struct aq_rxring *rxring, bool start)
4007: {
4008: const int ringidx = rxring->rxr_index;
4009: int i;
4010: int error = 0;
4011:
4012: mutex_enter(&rxring->rxr_mutex);
4013: rxring->rxr_active = false;
4014:
4015: /* disable DMA */
4016: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), RX_DMA_DESC_EN, 0);
4017:
4018: /* free all RX mbufs */
4019: aq_rxdrain(sc, rxring);
4020:
4021: if (start) {
4022: for (i = 0; i < AQ_RXD_NUM; i++) {
4023: error = aq_rxring_add(sc, rxring, i);
4024: if (error != 0) {
4025: aq_rxdrain(sc, rxring);
4026: return error;
4027: }
4028: aq_rxring_reset_desc(sc, rxring, i);
4029: }
4030:
4031: /* RX descriptor physical address */
4032: paddr_t paddr = rxring->rxr_rxdesc_dmamap->dm_segs[0].ds_addr;
4033: AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRLSW_REG(ringidx), paddr);
4034: AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRMSW_REG(ringidx),
4035: (uint32_t)((uint64_t)paddr >> 32));
4036:
4037: /* RX descriptor size */
4038: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), RX_DMA_DESC_LEN,
4039: AQ_RXD_NUM / 8);
4040:
4041: /* maximum receive frame size */
4042: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(ringidx),
4043: RX_DMA_DESC_BUFSIZE_DATA, MCLBYTES / 1024);
4044: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(ringidx),
4045: RX_DMA_DESC_BUFSIZE_HDR, 0 / 1024);
4046:
4047: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
4048: RX_DMA_DESC_HEADER_SPLIT, 0);
4049: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
4050: RX_DMA_DESC_VLAN_STRIP,
4051: (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) ?
4052: 1 : 0);
4053:
4054: /*
4055: * reload TAIL pointer, and update readidx
4056: * (HEAD pointer cannot write)
4057: */
4058: rxring->rxr_readidx = AQ_READ_REG_BIT(sc,
4059: RX_DMA_DESC_HEAD_PTR_REG(ringidx), RX_DMA_DESC_HEAD_PTR);
4060: AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(ringidx),
4061: (rxring->rxr_readidx + AQ_RXD_NUM - 1) % AQ_RXD_NUM);
4062:
4063: /* Rx ring set mode */
4064:
4065: /* Mapping interrupt vector */
4066: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(ringidx),
4067: AQ_INTR_IRQ_MAP_RX_IRQMAP(ringidx), sc->sc_rx_irq[ringidx]);
4068: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(ringidx),
4069: AQ_INTR_IRQ_MAP_RX_EN(ringidx), 1);
4070:
4071: const int cpuid = 0; /* XXX? */
4072: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4073: RX_DMA_DCAD_CPUID, cpuid);
4074: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4075: RX_DMA_DCAD_DESC_EN, 0);
4076: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4077: RX_DMA_DCAD_HEADER_EN, 0);
4078: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4079: RX_DMA_DCAD_PAYLOAD_EN, 0);
4080:
4081: /* enable DMA. start receiving */
4082: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
4083: RX_DMA_DESC_EN, 1);
4084:
4085: rxring->rxr_active = true;
4086: }
4087:
4088: mutex_exit(&rxring->rxr_mutex);
4089: return error;
4090: }
4091:
4092: #define TXRING_NEXTIDX(idx) \
4093: (((idx) >= (AQ_TXD_NUM - 1)) ? 0 : ((idx) + 1))
4094: #define RXRING_NEXTIDX(idx) \
4095: (((idx) >= (AQ_RXD_NUM - 1)) ? 0 : ((idx) + 1))
4096:
4097: static int
4098: aq_encap_txring(struct aq_softc *sc, struct aq_txring *txring, struct mbuf **mp)
4099: {
4100: bus_dmamap_t map;
4101: struct mbuf *m = *mp;
4102: uint32_t ctl1, ctl1_ctx, ctl2;
4103: int idx, i, error;
4104:
4105: idx = txring->txr_prodidx;
4106: map = txring->txr_mbufs[idx].dmamap;
4107:
4108: error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
4109: BUS_DMA_WRITE | BUS_DMA_NOWAIT);
4110: if (error == EFBIG) {
4111: struct mbuf *n;
4112: n = m_defrag(m, M_DONTWAIT);
4113: if (n == NULL)
4114: return EFBIG;
4115: /* m_defrag() preserve m */
4116: KASSERT(n == m);
4117: error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
4118: BUS_DMA_WRITE | BUS_DMA_NOWAIT);
4119: }
4120: if (error != 0)
4121: return error;
4122:
4123: /*
4124: * check spaces of free descriptors.
4125: * +1 is additional descriptor for context (vlan, etc,.)
4126: */
4127: if ((map->dm_nsegs + 1) > txring->txr_nfree) {
4128: device_printf(sc->sc_dev,
4129: "TX: not enough descriptors left %d for %d segs\n",
4130: txring->txr_nfree, map->dm_nsegs + 1);
4131: bus_dmamap_unload(sc->sc_dmat, map);
4132: return ENOBUFS;
4133: }
4134:
4135: /* sync dma for mbuf */
4136: bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
4137: BUS_DMASYNC_PREWRITE);
4138:
4139: ctl1_ctx = 0;
4140: ctl2 = __SHIFTIN(m->m_pkthdr.len, AQ_TXDESC_CTL2_LEN);
4141:
4142: if (vlan_has_tag(m)) {
4143: ctl1 = AQ_TXDESC_CTL1_TYPE_TXC;
4144: ctl1 |= __SHIFTIN(vlan_get_tag(m), AQ_TXDESC_CTL1_VID);
4145:
4146: ctl1_ctx |= AQ_TXDESC_CTL1_CMD_VLAN;
4147: ctl2 |= AQ_TXDESC_CTL2_CTX_EN;
4148:
4149: /* fill context descriptor and forward index */
4150: txring->txr_txdesc[idx].buf_addr = 0;
4151: txring->txr_txdesc[idx].ctl1 = htole32(ctl1);
4152: txring->txr_txdesc[idx].ctl2 = 0;
4153:
4154: idx = TXRING_NEXTIDX(idx);
4155: txring->txr_nfree--;
4156: }
4157:
4158: if (m->m_pkthdr.csum_flags & M_CSUM_IPv4)
4159: ctl1_ctx |= AQ_TXDESC_CTL1_CMD_IP4CSUM;
4160: if (m->m_pkthdr.csum_flags &
4161: (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv6)) {
4162: ctl1_ctx |= AQ_TXDESC_CTL1_CMD_L4CSUM;
4163: }
4164:
4165: /* fill descriptor(s) */
4166: for (i = 0; i < map->dm_nsegs; i++) {
4167: ctl1 = ctl1_ctx | AQ_TXDESC_CTL1_TYPE_TXD |
4168: __SHIFTIN(map->dm_segs[i].ds_len, AQ_TXDESC_CTL1_BLEN);
4169: ctl1 |= AQ_TXDESC_CTL1_CMD_FCS;
4170:
4171: if (i == 0) {
4172: /* remember mbuf of these descriptors */
4173: txring->txr_mbufs[idx].m = m;
4174: } else {
4175: txring->txr_mbufs[idx].m = NULL;
4176: }
4177:
4178: if (i == map->dm_nsegs - 1) {
4179: /* last segment, mark an EndOfPacket, and cause intr */
4180: ctl1 |= AQ_TXDESC_CTL1_EOP | AQ_TXDESC_CTL1_CMD_WB;
4181: }
4182:
4183: txring->txr_txdesc[idx].buf_addr =
4184: htole64(map->dm_segs[i].ds_addr);
4185: txring->txr_txdesc[idx].ctl1 = htole32(ctl1);
4186: txring->txr_txdesc[idx].ctl2 = htole32(ctl2);
4187:
4188: bus_dmamap_sync(sc->sc_dmat, txring->txr_txdesc_dmamap,
4189: sizeof(aq_tx_desc_t) * idx, sizeof(aq_tx_desc_t),
4190: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4191:
4192: idx = TXRING_NEXTIDX(idx);
4193: txring->txr_nfree--;
4194: }
4195:
4196: txring->txr_prodidx = idx;
4197:
4198: return 0;
4199: }
4200:
4201: static int
4202: aq_tx_intr(void *arg)
4203: {
4204: struct aq_txring *txring = arg;
4205: struct aq_softc *sc = txring->txr_sc;
4206: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1.3 ryo 4207: struct mbuf *m;
1.1 ryo 4208: const int ringidx = txring->txr_index;
4209: unsigned int idx, hw_head, n = 0;
4210:
4211: mutex_enter(&txring->txr_mutex);
4212:
4213: if (!txring->txr_active)
4214: goto tx_intr_done;
4215:
4216: hw_head = AQ_READ_REG_BIT(sc, TX_DMA_DESC_HEAD_PTR_REG(ringidx),
4217: TX_DMA_DESC_HEAD_PTR);
4218: if (hw_head == txring->txr_considx) {
4219: goto tx_intr_done;
4220: }
4221:
1.6 thorpej 4222: net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
4223:
1.1 ryo 4224: for (idx = txring->txr_considx; idx != hw_head;
4225: idx = TXRING_NEXTIDX(idx), n++) {
4226:
1.3 ryo 4227: if ((m = txring->txr_mbufs[idx].m) != NULL) {
1.1 ryo 4228: bus_dmamap_unload(sc->sc_dmat,
4229: txring->txr_mbufs[idx].dmamap);
1.3 ryo 4230:
1.6 thorpej 4231: if_statinc_ref(nsr, if_opackets);
4232: if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len);
1.3 ryo 4233: if (m->m_flags & M_MCAST)
1.6 thorpej 4234: if_statinc_ref(nsr, if_omcasts);
1.3 ryo 4235:
4236: m_freem(m);
1.1 ryo 4237: txring->txr_mbufs[idx].m = NULL;
4238: }
4239:
4240: txring->txr_nfree++;
4241: }
4242: txring->txr_considx = idx;
4243:
1.6 thorpej 4244: IF_STAT_PUTREF(ifp);
4245:
1.1 ryo 4246: if (ringidx == 0 && txring->txr_nfree >= AQ_TXD_MIN)
4247: ifp->if_flags &= ~IFF_OACTIVE;
4248:
4249: /* no more pending TX packet, cancel watchdog */
4250: if (txring->txr_nfree >= AQ_TXD_NUM)
4251: ifp->if_timer = 0;
4252:
4253: tx_intr_done:
4254: mutex_exit(&txring->txr_mutex);
4255:
4256: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_tx_irq[ringidx]));
4257: return n;
4258: }
4259:
4260: static int
4261: aq_rx_intr(void *arg)
4262: {
4263: struct aq_rxring *rxring = arg;
4264: struct aq_softc *sc = rxring->rxr_sc;
4265: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
4266: const int ringidx = rxring->rxr_index;
4267: aq_rx_desc_t *rxd;
4268: struct mbuf *m, *m0, *mprev, *new_m;
4269: uint32_t rxd_type, rxd_hash __unused;
4270: uint16_t rxd_status, rxd_pktlen;
4271: uint16_t rxd_nextdescptr __unused, rxd_vlan __unused;
4272: unsigned int idx, n = 0;
4273:
4274: mutex_enter(&rxring->rxr_mutex);
4275:
4276: if (!rxring->rxr_active)
4277: goto rx_intr_done;
4278:
4279: if (rxring->rxr_readidx == AQ_READ_REG_BIT(sc,
4280: RX_DMA_DESC_HEAD_PTR_REG(ringidx), RX_DMA_DESC_HEAD_PTR)) {
4281: goto rx_intr_done;
4282: }
4283:
1.6 thorpej 4284: net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
4285:
1.1 ryo 4286: m0 = mprev = NULL;
4287: for (idx = rxring->rxr_readidx;
4288: idx != AQ_READ_REG_BIT(sc, RX_DMA_DESC_HEAD_PTR_REG(ringidx),
4289: RX_DMA_DESC_HEAD_PTR); idx = RXRING_NEXTIDX(idx), n++) {
4290:
4291: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_rxdesc_dmamap,
4292: sizeof(aq_rx_desc_t) * idx, sizeof(aq_rx_desc_t),
4293: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4294:
4295: rxd = &rxring->rxr_rxdesc[idx];
4296: rxd_status = le16toh(rxd->wb.status);
4297:
4298: if ((rxd_status & RXDESC_STATUS_DD) == 0)
4299: break; /* not yet done */
4300:
4301: rxd_type = le32toh(rxd->wb.type);
4302: rxd_pktlen = le16toh(rxd->wb.pkt_len);
4303: rxd_nextdescptr = le16toh(rxd->wb.next_desc_ptr);
4304: rxd_hash = le32toh(rxd->wb.rss_hash);
4305: rxd_vlan = le16toh(rxd->wb.vlan);
4306:
4307: if ((rxd_status & RXDESC_STATUS_MACERR) ||
4308: (rxd_type & RXDESC_TYPE_MAC_DMA_ERR)) {
1.6 thorpej 4309: if_statinc_ref(nsr, if_ierrors);
1.1 ryo 4310: goto rx_next;
4311: }
4312:
4313: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap, 0,
4314: rxring->rxr_mbufs[idx].dmamap->dm_mapsize,
4315: BUS_DMASYNC_POSTREAD);
4316: m = rxring->rxr_mbufs[idx].m;
4317:
4318: new_m = aq_alloc_mbuf();
4319: if (new_m == NULL) {
4320: /*
4321: * cannot allocate new mbuf.
4322: * discard this packet, and reuse mbuf for next.
4323: */
1.6 thorpej 4324: if_statinc_ref(nsr, if_iqdrops);
1.1 ryo 4325: goto rx_next;
4326: }
4327: rxring->rxr_mbufs[idx].m = NULL;
4328: aq_rxring_setmbuf(sc, rxring, idx, new_m);
4329:
4330: if (m0 == NULL) {
4331: m0 = m;
4332: } else {
4333: if (m->m_flags & M_PKTHDR)
4334: m_remove_pkthdr(m);
4335: mprev->m_next = m;
4336: }
4337: mprev = m;
4338:
4339: if ((rxd_status & RXDESC_STATUS_EOP) == 0) {
4340: m->m_len = MCLBYTES;
4341: } else {
4342: /* last buffer */
4343: m->m_len = rxd_pktlen % MCLBYTES;
4344: m0->m_pkthdr.len = rxd_pktlen;
4345: /* VLAN offloading */
4346: if ((sc->sc_ethercom.ec_capenable &
4347: ETHERCAP_VLAN_HWTAGGING) &&
4348: (__SHIFTOUT(rxd_type, RXDESC_TYPE_PKTTYPE_VLAN) ||
4349: __SHIFTOUT(rxd_type,
4350: RXDESC_TYPE_PKTTYPE_VLAN_DOUBLE))) {
4351: vlan_set_tag(m0, rxd_vlan);
4352: }
4353:
4354: /* Checksum offloading */
4355: unsigned int pkttype_eth =
4356: __SHIFTOUT(rxd_type, RXDESC_TYPE_PKTTYPE_ETHER);
4357: if ((ifp->if_capabilities & IFCAP_CSUM_IPv4_Rx) &&
4358: (pkttype_eth == RXDESC_TYPE_PKTTYPE_ETHER_IPV4) &&
4359: __SHIFTOUT(rxd_type,
4360: RXDESC_TYPE_IPV4_CSUM_CHECKED)) {
4361: m0->m_pkthdr.csum_flags |= M_CSUM_IPv4;
4362: if (__SHIFTOUT(rxd_status,
4363: RXDESC_STATUS_IPV4_CSUM_NG))
4364: m0->m_pkthdr.csum_flags |=
4365: M_CSUM_IPv4_BAD;
4366: }
1.21 ryo 4367:
1.1 ryo 4368: /*
1.21 ryo 4369: * aq will always mark BAD for fragment packets,
4370: * but this is not a problem because the IP stack
4371: * ignores the CSUM flag in fragment packets.
1.1 ryo 4372: */
4373: if (__SHIFTOUT(rxd_type,
4374: RXDESC_TYPE_TCPUDP_CSUM_CHECKED)) {
4375: bool checked = false;
4376: unsigned int pkttype_proto =
4377: __SHIFTOUT(rxd_type,
4378: RXDESC_TYPE_PKTTYPE_PROTO);
4379:
4380: if (pkttype_proto ==
4381: RXDESC_TYPE_PKTTYPE_PROTO_TCP) {
4382: if ((pkttype_eth ==
4383: RXDESC_TYPE_PKTTYPE_ETHER_IPV4) &&
4384: (ifp->if_capabilities &
4385: IFCAP_CSUM_TCPv4_Rx)) {
4386: m0->m_pkthdr.csum_flags |=
4387: M_CSUM_TCPv4;
4388: checked = true;
4389: } else if ((pkttype_eth ==
4390: RXDESC_TYPE_PKTTYPE_ETHER_IPV6) &&
4391: (ifp->if_capabilities &
4392: IFCAP_CSUM_TCPv6_Rx)) {
4393: m0->m_pkthdr.csum_flags |=
4394: M_CSUM_TCPv6;
4395: checked = true;
4396: }
4397: } else if (pkttype_proto ==
4398: RXDESC_TYPE_PKTTYPE_PROTO_UDP) {
4399: if ((pkttype_eth ==
4400: RXDESC_TYPE_PKTTYPE_ETHER_IPV4) &&
4401: (ifp->if_capabilities &
4402: IFCAP_CSUM_UDPv4_Rx)) {
4403: m0->m_pkthdr.csum_flags |=
4404: M_CSUM_UDPv4;
4405: checked = true;
4406: } else if ((pkttype_eth ==
4407: RXDESC_TYPE_PKTTYPE_ETHER_IPV6) &&
4408: (ifp->if_capabilities &
4409: IFCAP_CSUM_UDPv6_Rx)) {
4410: m0->m_pkthdr.csum_flags |=
4411: M_CSUM_UDPv6;
4412: checked = true;
4413: }
4414: }
4415: if (checked &&
4416: (__SHIFTOUT(rxd_status,
4417: RXDESC_STATUS_TCPUDP_CSUM_ERROR) ||
4418: !__SHIFTOUT(rxd_status,
4419: RXDESC_STATUS_TCPUDP_CSUM_OK))) {
4420: m0->m_pkthdr.csum_flags |=
4421: M_CSUM_TCP_UDP_BAD;
4422: }
4423: }
1.21 ryo 4424:
1.1 ryo 4425: m_set_rcvif(m0, ifp);
1.6 thorpej 4426: if_statinc_ref(nsr, if_ipackets);
4427: if_statadd_ref(nsr, if_ibytes, m0->m_pkthdr.len);
1.1 ryo 4428: if_percpuq_enqueue(ifp->if_percpuq, m0);
4429: m0 = mprev = NULL;
4430: }
4431:
4432: rx_next:
4433: aq_rxring_reset_desc(sc, rxring, idx);
4434: AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(ringidx), idx);
4435: }
4436: rxring->rxr_readidx = idx;
4437:
1.6 thorpej 4438: IF_STAT_PUTREF(ifp);
4439:
1.1 ryo 4440: rx_intr_done:
4441: mutex_exit(&rxring->rxr_mutex);
4442:
4443: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_rx_irq[ringidx]));
4444: return n;
4445: }
4446:
4447: static int
1.10 ryo 4448: aq_vlan_cb(struct ethercom *ec, uint16_t vid, bool set)
4449: {
4450: struct ifnet *ifp = &ec->ec_if;
4451: struct aq_softc *sc = ifp->if_softc;
4452:
4453: aq_set_vlan_filters(sc);
4454: return 0;
4455: }
4456:
4457: static int
1.1 ryo 4458: aq_ifflags_cb(struct ethercom *ec)
4459: {
4460: struct ifnet *ifp = &ec->ec_if;
4461: struct aq_softc *sc = ifp->if_softc;
4462: int i, ecchange, error = 0;
4463: unsigned short iffchange;
4464:
4465: AQ_LOCK(sc);
4466:
4467: iffchange = ifp->if_flags ^ sc->sc_if_flags;
4468: if ((iffchange & IFF_PROMISC) != 0)
4469: error = aq_set_filter(sc);
4470:
4471: ecchange = ec->ec_capenable ^ sc->sc_ec_capenable;
4472: if (ecchange & ETHERCAP_VLAN_HWTAGGING) {
4473: for (i = 0; i < AQ_RINGS_NUM; i++) {
4474: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(i),
4475: RX_DMA_DESC_VLAN_STRIP,
4476: (ec->ec_capenable & ETHERCAP_VLAN_HWTAGGING) ?
4477: 1 : 0);
4478: }
4479: }
4480:
1.10 ryo 4481: /* vlan configuration depends on also interface promiscuous mode */
4482: if ((ecchange & ETHERCAP_VLAN_HWFILTER) || (iffchange & IFF_PROMISC))
4483: aq_set_vlan_filters(sc);
4484:
1.1 ryo 4485: sc->sc_ec_capenable = ec->ec_capenable;
4486: sc->sc_if_flags = ifp->if_flags;
4487:
4488: AQ_UNLOCK(sc);
4489:
4490: return error;
4491: }
4492:
4493: static int
4494: aq_init(struct ifnet *ifp)
4495: {
4496: struct aq_softc *sc = ifp->if_softc;
4497: int i, error = 0;
4498:
1.22 ryo 4499: aq_stop(ifp, false);
4500:
1.1 ryo 4501: AQ_LOCK(sc);
4502:
1.10 ryo 4503: aq_set_vlan_filters(sc);
1.1 ryo 4504: aq_set_capability(sc);
4505:
4506: for (i = 0; i < sc->sc_nqueues; i++) {
4507: aq_txring_reset(sc, &sc->sc_queue[i].txring, true);
4508: }
4509:
4510: /* invalidate RX descriptor cache */
4511: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT,
4512: AQ_READ_REG_BIT(sc,
4513: RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT) ^ 1);
4514:
4515: /* start RX */
4516: for (i = 0; i < sc->sc_nqueues; i++) {
4517: error = aq_rxring_reset(sc, &sc->sc_queue[i].rxring, true);
4518: if (error != 0) {
4519: device_printf(sc->sc_dev, "%s: cannot allocate rxbuf\n",
4520: __func__);
4521: goto aq_init_failure;
4522: }
4523: }
4524: aq_init_rss(sc);
4525: aq_hw_l3_filter_set(sc);
4526:
4527: /* need to start callout? */
4528: if (sc->sc_poll_linkstat
4529: #ifdef AQ_EVENT_COUNTERS
4530: || sc->sc_poll_statistics
4531: #endif
4532: ) {
4533: callout_schedule(&sc->sc_tick_ch, hz);
4534: }
4535:
4536: /* ready */
4537: ifp->if_flags |= IFF_RUNNING;
4538: ifp->if_flags &= ~IFF_OACTIVE;
4539:
4540: /* start TX and RX */
4541: aq_enable_intr(sc, true, true);
4542: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_EN, 1);
4543: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 1);
4544:
4545: aq_init_failure:
4546: sc->sc_if_flags = ifp->if_flags;
4547:
4548: AQ_UNLOCK(sc);
4549:
4550: return error;
4551: }
4552:
4553: static void
4554: aq_send_common_locked(struct ifnet *ifp, struct aq_softc *sc,
4555: struct aq_txring *txring, bool is_transmit)
4556: {
4557: struct mbuf *m;
4558: int npkt, error;
4559:
4560: if ((ifp->if_flags & IFF_RUNNING) == 0)
4561: return;
4562:
4563: for (npkt = 0; ; npkt++) {
4564: if (is_transmit)
4565: m = pcq_peek(txring->txr_pcq);
4566: else
4567: IFQ_POLL(&ifp->if_snd, m);
4568:
4569: if (m == NULL)
4570: break;
4571:
4572: if (txring->txr_nfree < AQ_TXD_MIN)
4573: break;
4574:
4575: if (is_transmit)
4576: pcq_get(txring->txr_pcq);
4577: else
4578: IFQ_DEQUEUE(&ifp->if_snd, m);
4579:
4580: error = aq_encap_txring(sc, txring, &m);
4581: if (error != 0) {
4582: /* too many mbuf chains? or not enough descriptors? */
4583: m_freem(m);
1.6 thorpej 4584: if_statinc(ifp, if_oerrors);
1.2 ryo 4585: if (txring->txr_index == 0 && error == ENOBUFS)
1.1 ryo 4586: ifp->if_flags |= IFF_OACTIVE;
4587: break;
4588: }
4589:
4590: /* update tail ptr */
4591: AQ_WRITE_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(txring->txr_index),
4592: txring->txr_prodidx);
4593:
4594: /* Pass the packet to any BPF listeners */
4595: bpf_mtap(ifp, m, BPF_D_OUT);
4596: }
4597:
1.2 ryo 4598: if (txring->txr_index == 0 && txring->txr_nfree < AQ_TXD_MIN)
1.1 ryo 4599: ifp->if_flags |= IFF_OACTIVE;
4600:
4601: if (npkt)
4602: ifp->if_timer = 5;
4603: }
4604:
4605: static void
4606: aq_start(struct ifnet *ifp)
4607: {
4608: struct aq_softc *sc;
4609: struct aq_txring *txring;
4610:
4611: sc = ifp->if_softc;
4612: txring = &sc->sc_queue[0].txring; /* aq_start() always use TX ring[0] */
4613:
4614: mutex_enter(&txring->txr_mutex);
4615: if (txring->txr_active && !ISSET(ifp->if_flags, IFF_OACTIVE))
4616: aq_send_common_locked(ifp, sc, txring, false);
4617: mutex_exit(&txring->txr_mutex);
4618: }
4619:
4620: static inline unsigned int
4621: aq_select_txqueue(struct aq_softc *sc, struct mbuf *m)
4622: {
4623: return (cpu_index(curcpu()) % sc->sc_nqueues);
4624: }
4625:
4626: static int
4627: aq_transmit(struct ifnet *ifp, struct mbuf *m)
4628: {
4629: struct aq_softc *sc = ifp->if_softc;
4630: struct aq_txring *txring;
4631: int ringidx;
4632:
4633: ringidx = aq_select_txqueue(sc, m);
4634: txring = &sc->sc_queue[ringidx].txring;
4635:
4636: if (__predict_false(!pcq_put(txring->txr_pcq, m))) {
4637: m_freem(m);
4638: return ENOBUFS;
4639: }
4640:
4641: if (mutex_tryenter(&txring->txr_mutex)) {
4642: aq_send_common_locked(ifp, sc, txring, true);
4643: mutex_exit(&txring->txr_mutex);
4644: } else {
4645: softint_schedule(txring->txr_softint);
4646: }
4647: return 0;
4648: }
4649:
4650: static void
4651: aq_deferred_transmit(void *arg)
4652: {
4653: struct aq_txring *txring = arg;
4654: struct aq_softc *sc = txring->txr_sc;
4655: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
4656:
4657: mutex_enter(&txring->txr_mutex);
4658: if (pcq_peek(txring->txr_pcq) != NULL)
4659: aq_send_common_locked(ifp, sc, txring, true);
4660: mutex_exit(&txring->txr_mutex);
4661: }
4662:
4663: static void
4664: aq_stop(struct ifnet *ifp, int disable)
4665: {
4666: struct aq_softc *sc = ifp->if_softc;
4667: int i;
4668:
4669: AQ_LOCK(sc);
4670:
4671: ifp->if_timer = 0;
4672:
1.22 ryo 4673: if ((ifp->if_flags & IFF_RUNNING) == 0)
4674: goto already_stopped;
4675:
1.1 ryo 4676: /* disable tx/rx interrupts */
4677: aq_enable_intr(sc, true, false);
4678:
4679: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_EN, 0);
4680: for (i = 0; i < sc->sc_nqueues; i++) {
4681: aq_txring_reset(sc, &sc->sc_queue[i].txring, false);
4682: }
4683:
4684: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 0);
4685: for (i = 0; i < sc->sc_nqueues; i++) {
4686: aq_rxring_reset(sc, &sc->sc_queue[i].rxring, false);
4687: }
4688:
4689: /* invalidate RX descriptor cache */
4690: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT,
4691: AQ_READ_REG_BIT(sc,
4692: RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT) ^ 1);
4693:
4694: ifp->if_timer = 0;
4695:
1.22 ryo 4696: already_stopped:
1.1 ryo 4697: if (!disable) {
4698: /* when pmf stop, disable link status intr and callout */
4699: aq_enable_intr(sc, false, false);
4700: callout_stop(&sc->sc_tick_ch);
4701: }
4702:
4703: ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
4704:
4705: AQ_UNLOCK(sc);
4706: }
4707:
4708: static void
4709: aq_watchdog(struct ifnet *ifp)
4710: {
4711: struct aq_softc *sc = ifp->if_softc;
4712: struct aq_txring *txring;
4713: int n, head, tail;
4714:
4715: AQ_LOCK(sc);
4716:
4717: device_printf(sc->sc_dev, "%s: INTR_MASK/STATUS = %08x/%08x\n",
4718: __func__, AQ_READ_REG(sc, AQ_INTR_MASK_REG),
4719: AQ_READ_REG(sc, AQ_INTR_STATUS_REG));
4720:
4721: for (n = 0; n < sc->sc_nqueues; n++) {
4722: txring = &sc->sc_queue[n].txring;
4723: head = AQ_READ_REG_BIT(sc,
4724: TX_DMA_DESC_HEAD_PTR_REG(txring->txr_index),
4725: TX_DMA_DESC_HEAD_PTR),
4726: tail = AQ_READ_REG(sc,
4727: TX_DMA_DESC_TAIL_PTR_REG(txring->txr_index));
4728:
4729: device_printf(sc->sc_dev, "%s: TXring[%d] HEAD/TAIL=%d/%d\n",
4730: __func__, txring->txr_index, head, tail);
4731:
4732: aq_tx_intr(txring);
4733: }
4734:
4735: AQ_UNLOCK(sc);
4736:
4737: aq_init(ifp);
4738: }
4739:
4740: static int
4741: aq_ioctl(struct ifnet *ifp, unsigned long cmd, void *data)
4742: {
4743: struct aq_softc *sc __unused;
4744: struct ifreq *ifr __unused;
1.6 thorpej 4745: int error, s;
1.1 ryo 4746:
4747: sc = (struct aq_softc *)ifp->if_softc;
4748: ifr = (struct ifreq *)data;
4749: error = 0;
4750:
4751: s = splnet();
1.23 ! ryo 4752: switch (cmd) {
! 4753: case SIOCSIFMTU:
! 4754: if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > sc->sc_max_mtu) {
! 4755: error = EINVAL;
! 4756: } else {
! 4757: ifp->if_mtu = ifr->ifr_mtu;
! 4758: error = 0; /* no need to reset (no ENETRESET) */
! 4759: }
! 4760: break;
! 4761: default:
! 4762: error = ether_ioctl(ifp, cmd, data);
! 4763: break;
! 4764: }
1.1 ryo 4765: splx(s);
4766:
4767: if (error != ENETRESET)
4768: return error;
4769:
4770: switch (cmd) {
4771: case SIOCSIFCAP:
4772: error = aq_set_capability(sc);
4773: break;
4774: case SIOCADDMULTI:
4775: case SIOCDELMULTI:
4776: if ((ifp->if_flags & IFF_RUNNING) == 0)
4777: break;
4778:
4779: /*
4780: * Multicast list has changed; set the hardware filter
4781: * accordingly.
4782: */
4783: error = aq_set_filter(sc);
4784: break;
4785: }
4786:
4787: return error;
4788: }
4789:
4790:
4791: MODULE(MODULE_CLASS_DRIVER, if_aq, "pci");
4792:
4793: #ifdef _MODULE
4794: #include "ioconf.c"
4795: #endif
4796:
4797: static int
4798: if_aq_modcmd(modcmd_t cmd, void *opaque)
4799: {
4800: int error = 0;
4801:
4802: switch (cmd) {
4803: case MODULE_CMD_INIT:
4804: #ifdef _MODULE
4805: error = config_init_component(cfdriver_ioconf_if_aq,
4806: cfattach_ioconf_if_aq, cfdata_ioconf_if_aq);
4807: #endif
4808: return error;
4809: case MODULE_CMD_FINI:
4810: #ifdef _MODULE
4811: error = config_fini_component(cfdriver_ioconf_if_aq,
4812: cfattach_ioconf_if_aq, cfdata_ioconf_if_aq);
4813: #endif
4814: return error;
4815: default:
4816: return ENOTTY;
4817: }
4818: }
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