Annotation of src/sys/dev/pci/if_aq.c, Revision 1.15
1.15 ! ryo 1: /* $NetBSD: if_aq.c,v 1.14 2020/04/23 06:28:34 ryo Exp $ */
1.1 ryo 2:
3: /**
4: * aQuantia Corporation Network Driver
5: * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: *
11: * (1) Redistributions of source code must retain the above
12: * copyright notice, this list of conditions and the following
13: * disclaimer.
14: *
15: * (2) Redistributions in binary form must reproduce the above
16: * copyright notice, this list of conditions and the following
17: * disclaimer in the documentation and/or other materials provided
18: * with the distribution.
19: *
20: * (3) The name of the author may not be used to endorse or promote
21: * products derived from this software without specific prior
22: * written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
25: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
28: * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
30: * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33: * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34: * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35: *
36: */
37:
38: /*-
39: * Copyright (c) 2020 Ryo Shimizu <ryo@nerv.org>
40: * All rights reserved.
41: *
42: * Redistribution and use in source and binary forms, with or without
43: * modification, are permitted provided that the following conditions
44: * are met:
45: * 1. Redistributions of source code must retain the above copyright
46: * notice, this list of conditions and the following disclaimer.
47: * 2. Redistributions in binary form must reproduce the above copyright
48: * notice, this list of conditions and the following disclaimer in the
49: * documentation and/or other materials provided with the distribution.
50: *
51: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
52: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
53: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
54: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
55: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
56: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
57: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
58: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
59: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
60: * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
61: * POSSIBILITY OF SUCH DAMAGE.
62: */
63:
64: #include <sys/cdefs.h>
1.15 ! ryo 65: __KERNEL_RCSID(0, "$NetBSD: if_aq.c,v 1.14 2020/04/23 06:28:34 ryo Exp $");
1.1 ryo 66:
67: #ifdef _KERNEL_OPT
68: #include "opt_if_aq.h"
1.4 ryo 69: #include "sysmon_envsys.h"
1.1 ryo 70: #endif
71:
72: #include <sys/param.h>
73: #include <sys/types.h>
74: #include <sys/bitops.h>
75: #include <sys/cprng.h>
76: #include <sys/cpu.h>
77: #include <sys/interrupt.h>
78: #include <sys/module.h>
79: #include <sys/pcq.h>
80:
81: #include <net/bpf.h>
82: #include <net/if.h>
83: #include <net/if_dl.h>
84: #include <net/if_media.h>
85: #include <net/if_ether.h>
86: #include <net/rss_config.h>
87:
88: #include <dev/pci/pcivar.h>
89: #include <dev/pci/pcireg.h>
90: #include <dev/pci/pcidevs.h>
1.4 ryo 91: #include <dev/sysmon/sysmonvar.h>
1.1 ryo 92:
93: /* driver configuration */
94: #define CONFIG_INTR_MODERATION_ENABLE true /* delayed interrupt */
95: #undef CONFIG_LRO_SUPPORT /* no LRO not suppoted */
96: #undef CONFIG_NO_TXRX_INDEPENDENT /* share TX/RX interrupts */
97:
98: #define AQ_NINTR_MAX (AQ_RSSQUEUE_MAX + AQ_RSSQUEUE_MAX + 1)
99: /* TX + RX + LINK. must be <= 32 */
100: #define AQ_LINKSTAT_IRQ 31 /* for legacy mode */
101:
102: #define AQ_TXD_NUM 2048 /* per ring. 8*n && 32~8184 */
103: #define AQ_RXD_NUM 2048 /* per ring. 8*n && 32~8184 */
104: /* minimum required to send a packet (vlan needs additional TX descriptor) */
105: #define AQ_TXD_MIN (1 + 1)
106:
107:
108: /* hardware specification */
109: #define AQ_RINGS_NUM 32
110: #define AQ_RSSQUEUE_MAX 8
111: #define AQ_RX_DESCRIPTOR_MIN 32
112: #define AQ_TX_DESCRIPTOR_MIN 32
113: #define AQ_RX_DESCRIPTOR_MAX 8184
114: #define AQ_TX_DESCRIPTOR_MAX 8184
115: #define AQ_TRAFFICCLASS_NUM 8
116: #define AQ_RSS_HASHKEY_SIZE 40
117: #define AQ_RSS_INDIRECTION_TABLE_MAX 64
118:
119: /*
120: * TERMINOLOGY
121: * MPI = MAC PHY INTERFACE?
122: * RPO = RX Protocol Offloading
123: * TPO = TX Protocol Offloading
124: * RPF = RX Packet Filter
125: * TPB = TX Packet buffer
126: * RPB = RX Packet buffer
127: */
128:
129: /* registers */
130: #define AQ_FW_SOFTRESET_REG 0x0000
131: #define AQ_FW_SOFTRESET_RESET __BIT(15) /* soft reset bit */
132: #define AQ_FW_SOFTRESET_DIS __BIT(14) /* reset disable */
133:
134: #define AQ_FW_VERSION_REG 0x0018
135: #define AQ_HW_REVISION_REG 0x001c
136: #define AQ_GLB_NVR_INTERFACE1_REG 0x0100
137:
138: #define AQ_FW_MBOX_CMD_REG 0x0200
139: #define AQ_FW_MBOX_CMD_EXECUTE 0x00008000
140: #define AQ_FW_MBOX_CMD_BUSY 0x00000100
141: #define AQ_FW_MBOX_ADDR_REG 0x0208
142: #define AQ_FW_MBOX_VAL_REG 0x020c
143:
144: #define FW2X_LED_MIN_VERSION 0x03010026 /* >= 3.1.38 */
145: #define FW2X_LED_REG 0x031c
146: #define FW2X_LED_DEFAULT 0x00000000
147: #define FW2X_LED_NONE 0x0000003f
148: #define FW2X_LINKLED __BITS(0,1)
149: #define FW2X_LINKLED_ACTIVE 0
150: #define FW2X_LINKLED_ON 1
151: #define FW2X_LINKLED_BLINK 2
152: #define FW2X_LINKLED_OFF 3
153: #define FW2X_STATUSLED __BITS(2,5)
154: #define FW2X_STATUSLED_ORANGE 0
155: #define FW2X_STATUSLED_ORANGE_BLINK 2
156: #define FW2X_STATUSLED_OFF 3
157: #define FW2X_STATUSLED_GREEN 4
158: #define FW2X_STATUSLED_ORANGE_GREEN_BLINK 8
159: #define FW2X_STATUSLED_GREEN_BLINK 10
160:
161: #define FW_MPI_MBOX_ADDR_REG 0x0360
162: #define FW1X_MPI_INIT1_REG 0x0364
163: #define FW1X_MPI_CONTROL_REG 0x0368
164: #define FW1X_MPI_STATE_REG 0x036c
165: #define FW1X_MPI_STATE_MODE __BITS(7,0)
166: #define FW1X_MPI_STATE_SPEED __BITS(32,16)
167: #define FW1X_MPI_STATE_DISABLE_DIRTYWAKE __BITS(25)
168: #define FW1X_MPI_STATE_DOWNSHIFT __BITS(31,28)
169: #define FW1X_MPI_INIT2_REG 0x0370
170: #define FW1X_MPI_EFUSEADDR_REG 0x0374
171:
172: #define FW2X_MPI_EFUSEADDR_REG 0x0364
173: #define FW2X_MPI_CONTROL_REG 0x0368 /* 64bit */
174: #define FW2X_MPI_STATE_REG 0x0370 /* 64bit */
175: #define FW_BOOT_EXIT_CODE_REG 0x0388
176: #define RBL_STATUS_DEAD 0x0000dead
177: #define RBL_STATUS_SUCCESS 0x0000abba
178: #define RBL_STATUS_FAILURE 0x00000bad
179: #define RBL_STATUS_HOST_BOOT 0x0000f1a7
180:
181: #define AQ_FW_GLB_CPU_SEM_REG(i) (0x03a0 + (i) * 4)
182: #define AQ_FW_SEM_RAM_REG AQ_FW_GLB_CPU_SEM_REG(2)
183:
184: #define AQ_FW_GLB_CTL2_REG 0x0404
185: #define AQ_FW_GLB_CTL2_MCP_UP_FORCE_INTERRUPT __BIT(1)
186:
187: #define AQ_GLB_GENERAL_PROVISIONING9_REG 0x0520
188: #define AQ_GLB_NVR_PROVISIONING2_REG 0x0534
189:
190: #define FW_MPI_DAISY_CHAIN_STATUS_REG 0x0704
191:
192: #define AQ_PCI_REG_CONTROL_6_REG 0x1014
193:
194: // msix bitmap */
195: #define AQ_INTR_STATUS_REG 0x2000 /* intr status */
196: #define AQ_INTR_STATUS_CLR_REG 0x2050 /* intr status clear */
197: #define AQ_INTR_MASK_REG 0x2060 /* intr mask set */
198: #define AQ_INTR_MASK_CLR_REG 0x2070 /* intr mask clear */
199: #define AQ_INTR_AUTOMASK_REG 0x2090
200:
201: /* AQ_INTR_IRQ_MAP_TXRX_REG[AQ_RINGS_NUM] 0x2100-0x2140 */
202: #define AQ_INTR_IRQ_MAP_TXRX_REG(i) (0x2100 + ((i) / 2) * 4)
203: #define AQ_INTR_IRQ_MAP_TX_REG(i) AQ_INTR_IRQ_MAP_TXRX_REG(i)
204: #define AQ_INTR_IRQ_MAP_TX_IRQMAP(i) (__BITS(28,24) >> (((i) & 1)*8))
205: #define AQ_INTR_IRQ_MAP_TX_EN(i) (__BIT(31) >> (((i) & 1)*8))
206: #define AQ_INTR_IRQ_MAP_RX_REG(i) AQ_INTR_IRQ_MAP_TXRX_REG(i)
207: #define AQ_INTR_IRQ_MAP_RX_IRQMAP(i) (__BITS(12,8) >> (((i) & 1)*8))
208: #define AQ_INTR_IRQ_MAP_RX_EN(i) (__BIT(15) >> (((i) & 1)*8))
209:
210: /* AQ_GEN_INTR_MAP_REG[AQ_RINGS_NUM] 0x2180-0x2200 */
211: #define AQ_GEN_INTR_MAP_REG(i) (0x2180 + (i) * 4)
1.5 msaitoh 212: #define AQ_B0_ERR_INT 8U
1.1 ryo 213:
214: #define AQ_INTR_CTRL_REG 0x2300
215: #define AQ_INTR_CTRL_IRQMODE __BITS(1,0)
216: #define AQ_INTR_CTRL_IRQMODE_LEGACY 0
217: #define AQ_INTR_CTRL_IRQMODE_MSI 1
218: #define AQ_INTR_CTRL_IRQMODE_MSIX 2
219: #define AQ_INTR_CTRL_MULTIVEC __BIT(2)
220: #define AQ_INTR_CTRL_AUTO_MASK __BIT(5)
221: #define AQ_INTR_CTRL_CLR_ON_READ __BIT(7)
222: #define AQ_INTR_CTRL_RESET_DIS __BIT(29)
223: #define AQ_INTR_CTRL_RESET_IRQ __BIT(31)
224:
225: #define AQ_MBOXIF_POWER_GATING_CONTROL_REG 0x32a8
226:
227: #define FW_MPI_RESETCTRL_REG 0x4000
228: #define FW_MPI_RESETCTRL_RESET_DIS __BIT(29)
229:
230: #define RX_SYSCONTROL_REG 0x5000
231: #define RX_SYSCONTROL_RPB_DMA_LOOPBACK __BIT(6)
232: #define RX_SYSCONTROL_RPF_TPO_LOOPBACK __BIT(8)
233: #define RX_SYSCONTROL_RESET_DIS __BIT(29)
234:
235: #define RX_TCP_RSS_HASH_REG 0x5040
236: #define RX_TCP_RSS_HASH_RPF2 __BITS(19,16)
237: #define RX_TCP_RSS_HASH_TYPE __BITS(15,0)
238:
239: /* for RPF_*_REG.ACTION */
240: #define RPF_ACTION_DISCARD 0
241: #define RPF_ACTION_HOST 1
242: #define RPF_ACTION_MANAGEMENT 2
243: #define RPF_ACTION_HOST_MANAGEMENT 3
244: #define RPF_ACTION_WOL 4
245:
246: #define RPF_L2BC_REG 0x5100
247: #define RPF_L2BC_EN __BIT(0)
248: #define RPF_L2BC_PROMISC __BIT(3)
249: #define RPF_L2BC_ACTION __BITS(12,14)
250: #define RPF_L2BC_THRESHOLD __BITS(31,16)
251:
252: /* RPF_L2UC_*_REG[34] (actual [38]?) */
253: #define RPF_L2UC_LSW_REG(i) (0x5110 + (i) * 8)
254: #define RPF_L2UC_MSW_REG(i) (0x5114 + (i) * 8)
255: #define RPF_L2UC_MSW_MACADDR_HI __BITS(15,0)
256: #define RPF_L2UC_MSW_ACTION __BITS(18,16)
257: #define RPF_L2UC_MSW_EN __BIT(31)
258: #define AQ_HW_MAC_OWN 0 /* index of own address */
259: #define AQ_HW_MAC_NUM 34
260:
1.9 ryo 261: /* RPF_MCAST_FILTER_REG[8] 0x5250-0x5270 */
1.1 ryo 262: #define RPF_MCAST_FILTER_REG(i) (0x5250 + (i) * 4)
263: #define RPF_MCAST_FILTER_EN __BIT(31)
264: #define RPF_MCAST_FILTER_MASK_REG 0x5270
265: #define RPF_MCAST_FILTER_MASK_ALLMULTI __BIT(14)
266:
267: #define RPF_VLAN_MODE_REG 0x5280
268: #define RPF_VLAN_MODE_PROMISC __BIT(1)
269: #define RPF_VLAN_MODE_ACCEPT_UNTAGGED __BIT(2)
270: #define RPF_VLAN_MODE_UNTAGGED_ACTION __BITS(5,3)
271:
272: #define RPF_VLAN_TPID_REG 0x5284
273: #define RPF_VLAN_TPID_OUTER __BITS(31,16)
274: #define RPF_VLAN_TPID_INNER __BITS(15,0)
275:
1.9 ryo 276: /* RPF_VLAN_FILTER_REG[RPF_VLAN_MAX_FILTERS] 0x5290-0x52d0 */
1.1 ryo 277: #define RPF_VLAN_MAX_FILTERS 16
278: #define RPF_VLAN_FILTER_REG(i) (0x5290 + (i) * 4)
279: #define RPF_VLAN_FILTER_EN __BIT(31)
280: #define RPF_VLAN_FILTER_RXQ_EN __BIT(28)
281: #define RPF_VLAN_FILTER_RXQ __BITS(24,20)
282: #define RPF_VLAN_FILTER_ACTION __BITS(18,16)
283: #define RPF_VLAN_FILTER_ID __BITS(11,0)
284:
285: /* RPF_ETHERTYPE_FILTER_REG[AQ_RINGS_NUM] 0x5300-0x5380 */
286: #define RPF_ETHERTYPE_FILTER_REG(i) (0x5300 + (i) * 4)
287: #define RPF_ETHERTYPE_FILTER_EN __BIT(31)
288: #define RPF_ETHERTYPE_FILTER_PRIO_EN __BIT(30)
289: #define RPF_ETHERTYPE_FILTER_RXQF_EN __BIT(29)
290: #define RPF_ETHERTYPE_FILTER_PRIO __BITS(28,26)
291: #define RPF_ETHERTYPE_FILTER_RXQF __BITS(24,20)
292: #define RPF_ETHERTYPE_FILTER_MNG_RXQF __BIT(19)
293: #define RPF_ETHERTYPE_FILTER_ACTION __BITS(18,16)
294: #define RPF_ETHERTYPE_FILTER_VAL __BITS(15,0)
295:
296: /* RPF_L3_FILTER_REG[8] 0x5380-0x53a0 */
297: #define RPF_L3_FILTER_REG(i) (0x5380 + (i) * 4)
298: #define RPF_L3_FILTER_L4_EN __BIT(31)
299: #define RPF_L3_FILTER_IPV6_EN __BIT(30)
300: #define RPF_L3_FILTER_SRCADDR_EN __BIT(29)
301: #define RPF_L3_FILTER_DSTADDR_EN __BIT(28)
302: #define RPF_L3_FILTER_L4_SRCPORT_EN __BIT(27)
303: #define RPF_L3_FILTER_L4_DSTPORT_EN __BIT(26)
304: #define RPF_L3_FILTER_L4_PROTO_EN __BIT(25)
305: #define RPF_L3_FILTER_ARP_EN __BIT(24)
306: #define RPF_L3_FILTER_L4_RXQUEUE_EN __BIT(23)
307: #define RPF_L3_FILTER_L4_RXQUEUE_MANAGEMENT_EN __BIT(22)
308: #define RPF_L3_FILTER_L4_ACTION __BITS(16,18)
309: #define RPF_L3_FILTER_L4_RXQUEUE __BITS(12,8)
310: #define RPF_L3_FILTER_L4_PROTO __BITS(2,0)
311: #define RPF_L3_FILTER_L4_PROTO_TCP 0
312: #define RPF_L3_FILTER_L4_PROTO_UDP 1
313: #define RPF_L3_FILTER_L4_PROTO_SCTP 2
314: #define RPF_L3_FILTER_L4_PROTO_ICMP 3
315: /* parameters of RPF_L3_FILTER_REG[8] */
316: #define RPF_L3_FILTER_SRCADDR_REG(i) (0x53b0 + (i) * 4)
317: #define RPF_L3_FILTER_DSTADDR_REG(i) (0x53d0 + (i) * 4)
318: #define RPF_L3_FILTER_L4_SRCPORT_REG(i) (0x5400 + (i) * 4)
319: #define RPF_L3_FILTER_L4_DSTPORT_REG(i) (0x5420 + (i) * 4)
320:
321: #define RX_FLR_RSS_CONTROL1_REG 0x54c0
322: #define RX_FLR_RSS_CONTROL1_EN __BIT(31)
323:
324: #define RPF_RPB_RX_TC_UPT_REG 0x54c4
325: #define RPF_RPB_RX_TC_UPT_MASK(i) (0x00000007 << ((i) * 4))
326:
327: #define RPF_RSS_KEY_ADDR_REG 0x54d0
328: #define RPF_RSS_KEY_ADDR __BITS(4,0)
329: #define RPF_RSS_KEY_WR_EN __BIT(5)
330: #define RPF_RSS_KEY_WR_DATA_REG 0x54d4
331: #define RPF_RSS_KEY_RD_DATA_REG 0x54d8
332:
333: #define RPF_RSS_REDIR_ADDR_REG 0x54e0
334: #define RPF_RSS_REDIR_ADDR __BITS(3,0)
335: #define RPF_RSS_REDIR_WR_EN __BIT(4)
336:
337: #define RPF_RSS_REDIR_WR_DATA_REG 0x54e4
338: #define RPF_RSS_REDIR_WR_DATA __BITS(15,0)
339:
340: #define RPO_HWCSUM_REG 0x5580
341: #define RPO_HWCSUM_IP4CSUM_EN __BIT(1)
342: #define RPO_HWCSUM_L4CSUM_EN __BIT(0) /* TCP/UDP/SCTP */
343:
344: #define RPO_LRO_ENABLE_REG 0x5590
345:
346: #define RPO_LRO_CONF_REG 0x5594
347: #define RPO_LRO_CONF_QSESSION_LIMIT __BITS(13,12)
348: #define RPO_LRO_CONF_TOTAL_DESC_LIMIT __BITS(6,5)
349: #define RPO_LRO_CONF_PATCHOPTIMIZATION_EN __BIT(15)
350: #define RPO_LRO_CONF_MIN_PAYLOAD_OF_FIRST_PKT __BITS(4,0)
351: #define RPO_LRO_RSC_MAX_REG 0x5598
352:
353: /* RPO_LRO_LDES_MAX_REG[32/8] 0x55a0-0x55b0 */
354: #define RPO_LRO_LDES_MAX_REG(i) (0x55a0 + (i / 8) * 4)
355: #define RPO_LRO_LDES_MAX_MASK(i) (0x00000003 << ((i & 7) * 4))
356: #define RPO_LRO_TB_DIV_REG 0x5620
357: #define RPO_LRO_TB_DIV __BITS(20,31)
358: #define RPO_LRO_INACTIVE_IVAL_REG 0x5620
359: #define RPO_LRO_INACTIVE_IVAL __BITS(10,19)
360: #define RPO_LRO_MAX_COALESCING_IVAL_REG 0x5620
361: #define RPO_LRO_MAX_COALESCING_IVAL __BITS(9,0)
362:
363: #define RPB_RPF_RX_REG 0x5700
364: #define RPB_RPF_RX_TC_MODE __BIT(8)
365: #define RPB_RPF_RX_FC_MODE __BITS(5,4)
366: #define RPB_RPF_RX_BUF_EN __BIT(0)
367:
368: /* RPB_RXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x5710-0x5790 */
369: #define RPB_RXB_BUFSIZE_REG(i) (0x5710 + (i) * 0x10)
370: #define RPB_RXB_BUFSIZE __BITS(8,0)
371: #define RPB_RXB_XOFF_REG(i) (0x5714 + (i) * 0x10)
372: #define RPB_RXB_XOFF_EN __BIT(31)
373: #define RPB_RXB_XOFF_THRESH_HI __BITS(29,16)
374: #define RPB_RXB_XOFF_THRESH_LO __BITS(13,0)
375:
376: #define RX_DMA_DESC_CACHE_INIT_REG 0x5a00
377: #define RX_DMA_DESC_CACHE_INIT __BIT(0)
378:
379: #define RX_DMA_INT_DESC_WRWB_EN_REG 0x05a30
380: #define RX_DMA_INT_DESC_WRWB_EN __BIT(2)
381: #define RX_DMA_INT_DESC_MODERATE_EN __BIT(3)
382:
383: /* RX_INTR_MODERATION_CTL_REG[AQ_RINGS_NUM] 0x5a40-0x5ac0 */
384: #define RX_INTR_MODERATION_CTL_REG(i) (0x5a40 + (i) * 4)
385: #define RX_INTR_MODERATION_CTL_EN __BIT(1)
386: #define RX_INTR_MODERATION_CTL_MIN __BITS(15,8)
387: #define RX_INTR_MODERATION_CTL_MAX __BITS(24,16)
388:
389: /* RX_DMA_DESC_*[AQ_RINGS_NUM] 0x5b00-0x5f00 */
390: #define RX_DMA_DESC_BASE_ADDRLSW_REG(i) (0x5b00 + (i) * 0x20)
391: #define RX_DMA_DESC_BASE_ADDRMSW_REG(i) (0x5b04 + (i) * 0x20)
392: #define RX_DMA_DESC_REG(i) (0x5b08 + (i) * 0x20)
393: #define RX_DMA_DESC_LEN __BITS(12,3) /* RXD_NUM/8 */
394: #define RX_DMA_DESC_RESET __BIT(25)
395: #define RX_DMA_DESC_HEADER_SPLIT __BIT(28)
396: #define RX_DMA_DESC_VLAN_STRIP __BIT(29)
397: #define RX_DMA_DESC_EN __BIT(31)
398: #define RX_DMA_DESC_HEAD_PTR_REG(i) (0x5b0c + (i) * 0x20)
399: #define RX_DMA_DESC_HEAD_PTR __BITS(12,0)
400: #define RX_DMA_DESC_TAIL_PTR_REG(i) (0x5b10 + (i) * 0x20)
401: #define RX_DMA_DESC_BUFSIZE_REG(i) (0x5b18 + (i) * 0x20)
402: #define RX_DMA_DESC_BUFSIZE_DATA __BITS(4,0)
403: #define RX_DMA_DESC_BUFSIZE_HDR __BITS(12,8)
404:
405: /* RX_DMA_DCAD_REG[AQ_RINGS_NUM] 0x6100-0x6180 */
406: #define RX_DMA_DCAD_REG(i) (0x6100 + (i) * 4)
407: #define RX_DMA_DCAD_CPUID __BITS(7,0)
408: #define RX_DMA_DCAD_PAYLOAD_EN __BIT(29)
409: #define RX_DMA_DCAD_HEADER_EN __BIT(30)
410: #define RX_DMA_DCAD_DESC_EN __BIT(31)
411:
412: #define RX_DMA_DCA_REG 0x6180
413: #define RX_DMA_DCA_EN __BIT(31)
414: #define RX_DMA_DCA_MODE __BITS(3,0)
415:
416: /* counters */
417: #define RX_DMA_GOOD_PKT_COUNTERLSW 0x6800
418: #define RX_DMA_GOOD_OCTET_COUNTERLSW 0x6808
419: #define RX_DMA_DROP_PKT_CNT_REG 0x6818
420: #define RX_DMA_COALESCED_PKT_CNT_REG 0x6820
421:
422: #define TX_SYSCONTROL_REG 0x7000
423: #define TX_SYSCONTROL_TPB_DMA_LOOPBACK __BIT(6)
424: #define TX_SYSCONTROL_TPO_PKT_LOOPBACK __BIT(7)
425: #define TX_SYSCONTROL_RESET_DIS __BIT(29)
426:
427: #define TX_TPO2_REG 0x7040
428: #define TX_TPO2_EN __BIT(16)
429:
430: #define TPS_DESC_VM_ARB_MODE_REG 0x7300
431: #define TPS_DESC_VM_ARB_MODE __BIT(0)
432: #define TPS_DESC_RATE_REG 0x7310
433: #define TPS_DESC_RATE_TA_RST __BIT(31)
434: #define TPS_DESC_RATE_LIM __BITS(10,0)
435: #define TPS_DESC_TC_ARB_MODE_REG 0x7200
436: #define TPS_DESC_TC_ARB_MODE __BITS(1,0)
437: #define TPS_DATA_TC_ARB_MODE_REG 0x7100
438: #define TPS_DATA_TC_ARB_MODE __BIT(0)
439:
440: /* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7110-0x7130 */
441: #define TPS_DATA_TCT_REG(i) (0x7110 + (i) * 4)
442: #define TPS_DATA_TCT_CREDIT_MAX __BITS(16,27)
443: #define TPS_DATA_TCT_WEIGHT __BITS(8,0)
444: /* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7210-0x7230 */
445: #define TPS_DESC_TCT_REG(i) (0x7210 + (i) * 4)
446: #define TPS_DESC_TCT_CREDIT_MAX __BITS(16,27)
447: #define TPS_DESC_TCT_WEIGHT __BITS(8,0)
448:
449: #define AQ_HW_TXBUF_MAX 160
450: #define AQ_HW_RXBUF_MAX 320
451:
452: #define TPO_HWCSUM_REG 0x7800
453: #define TPO_HWCSUM_IP4CSUM_EN __BIT(1)
454: #define TPO_HWCSUM_L4CSUM_EN __BIT(0) /* TCP/UDP/SCTP */
455:
456: #define TDM_LSO_EN_REG 0x7810
457:
458: #define THM_LSO_TCP_FLAG1_REG 0x7820
459: #define THM_LSO_TCP_FLAG1_FIRST __BITS(11,0)
460: #define THM_LSO_TCP_FLAG1_MID __BITS(27,16)
461: #define THM_LSO_TCP_FLAG2_REG 0x7824
462: #define THM_LSO_TCP_FLAG2_LAST __BITS(11,0)
463:
464: #define TPB_TX_BUF_REG 0x7900
465: #define TPB_TX_BUF_EN __BIT(0)
466: #define TPB_TX_BUF_SCP_INS_EN __BIT(2)
467: #define TPB_TX_BUF_TC_MODE_EN __BIT(8)
468:
469: /* TPB_TXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x7910-7990 */
470: #define TPB_TXB_BUFSIZE_REG(i) (0x7910 + (i) * 0x10)
471: #define TPB_TXB_BUFSIZE __BITS(7,0)
472: #define TPB_TXB_THRESH_REG(i) (0x7914 + (i) * 0x10)
473: #define TPB_TXB_THRESH_HI __BITS(16,28)
474: #define TPB_TXB_THRESH_LO __BITS(12,0)
475:
476: #define AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG 0x7b20
477: #define TX_DMA_INT_DESC_WRWB_EN_REG 0x7b40
478: #define TX_DMA_INT_DESC_WRWB_EN __BIT(1)
479: #define TX_DMA_INT_DESC_MODERATE_EN __BIT(4)
480:
481: /* TX_DMA_DESC_*[AQ_RINGS_NUM] 0x7c00-0x8400 */
482: #define TX_DMA_DESC_BASE_ADDRLSW_REG(i) (0x7c00 + (i) * 0x40)
483: #define TX_DMA_DESC_BASE_ADDRMSW_REG(i) (0x7c04 + (i) * 0x40)
484: #define TX_DMA_DESC_REG(i) (0x7c08 + (i) * 0x40)
485: #define TX_DMA_DESC_LEN __BITS(12, 3) /* TXD_NUM/8 */
486: #define TX_DMA_DESC_EN __BIT(31)
487: #define TX_DMA_DESC_HEAD_PTR_REG(i) (0x7c0c + (i) * 0x40)
488: #define TX_DMA_DESC_HEAD_PTR __BITS(12,0)
489: #define TX_DMA_DESC_TAIL_PTR_REG(i) (0x7c10 + (i) * 0x40)
490: #define TX_DMA_DESC_WRWB_THRESH_REG(i) (0x7c18 + (i) * 0x40)
491: #define TX_DMA_DESC_WRWB_THRESH __BITS(14,8)
492:
493: /* TDM_DCAD_REG[AQ_RINGS_NUM] 0x8400-0x8480 */
494: #define TDM_DCAD_REG(i) (0x8400 + (i) * 4)
495: #define TDM_DCAD_CPUID __BITS(7,0)
496: #define TDM_DCAD_CPUID_EN __BIT(31)
497:
498: #define TDM_DCA_REG 0x8480
499: #define TDM_DCA_EN __BIT(31)
500: #define TDM_DCA_MODE __BITS(3,0)
501:
502: /* TX_INTR_MODERATION_CTL_REG[AQ_RINGS_NUM] 0x8980-0x8a00 */
503: #define TX_INTR_MODERATION_CTL_REG(i) (0x8980 + (i) * 4)
504: #define TX_INTR_MODERATION_CTL_EN __BIT(1)
505: #define TX_INTR_MODERATION_CTL_MIN __BITS(15,8)
506: #define TX_INTR_MODERATION_CTL_MAX __BITS(24,16)
507:
508: #define FW1X_CTRL_10G __BIT(0)
509: #define FW1X_CTRL_5G __BIT(1)
510: #define FW1X_CTRL_5GSR __BIT(2)
511: #define FW1X_CTRL_2G5 __BIT(3)
512: #define FW1X_CTRL_1G __BIT(4)
513: #define FW1X_CTRL_100M __BIT(5)
514:
515: #define FW2X_CTRL_10BASET_HD __BIT(0)
516: #define FW2X_CTRL_10BASET_FD __BIT(1)
517: #define FW2X_CTRL_100BASETX_HD __BIT(2)
518: #define FW2X_CTRL_100BASET4_HD __BIT(3)
519: #define FW2X_CTRL_100BASET2_HD __BIT(4)
520: #define FW2X_CTRL_100BASETX_FD __BIT(5)
521: #define FW2X_CTRL_100BASET2_FD __BIT(6)
522: #define FW2X_CTRL_1000BASET_HD __BIT(7)
523: #define FW2X_CTRL_1000BASET_FD __BIT(8)
524: #define FW2X_CTRL_2P5GBASET_FD __BIT(9)
525: #define FW2X_CTRL_5GBASET_FD __BIT(10)
526: #define FW2X_CTRL_10GBASET_FD __BIT(11)
527: #define FW2X_CTRL_RESERVED1 __BIT(32)
528: #define FW2X_CTRL_10BASET_EEE __BIT(33)
529: #define FW2X_CTRL_RESERVED2 __BIT(34)
530: #define FW2X_CTRL_PAUSE __BIT(35)
531: #define FW2X_CTRL_ASYMMETRIC_PAUSE __BIT(36)
532: #define FW2X_CTRL_100BASETX_EEE __BIT(37)
533: #define FW2X_CTRL_RESERVED3 __BIT(38)
534: #define FW2X_CTRL_RESERVED4 __BIT(39)
535: #define FW2X_CTRL_1000BASET_FD_EEE __BIT(40)
536: #define FW2X_CTRL_2P5GBASET_FD_EEE __BIT(41)
537: #define FW2X_CTRL_5GBASET_FD_EEE __BIT(42)
538: #define FW2X_CTRL_10GBASET_FD_EEE __BIT(43)
539: #define FW2X_CTRL_RESERVED5 __BIT(44)
540: #define FW2X_CTRL_RESERVED6 __BIT(45)
541: #define FW2X_CTRL_RESERVED7 __BIT(46)
542: #define FW2X_CTRL_RESERVED8 __BIT(47)
543: #define FW2X_CTRL_RESERVED9 __BIT(48)
544: #define FW2X_CTRL_CABLE_DIAG __BIT(49)
545: #define FW2X_CTRL_TEMPERATURE __BIT(50)
546: #define FW2X_CTRL_DOWNSHIFT __BIT(51)
547: #define FW2X_CTRL_PTP_AVB_EN __BIT(52)
548: #define FW2X_CTRL_MEDIA_DETECT __BIT(53)
549: #define FW2X_CTRL_LINK_DROP __BIT(54)
550: #define FW2X_CTRL_SLEEP_PROXY __BIT(55)
551: #define FW2X_CTRL_WOL __BIT(56)
552: #define FW2X_CTRL_MAC_STOP __BIT(57)
553: #define FW2X_CTRL_EXT_LOOPBACK __BIT(58)
554: #define FW2X_CTRL_INT_LOOPBACK __BIT(59)
555: #define FW2X_CTRL_EFUSE_AGENT __BIT(60)
556: #define FW2X_CTRL_WOL_TIMER __BIT(61)
557: #define FW2X_CTRL_STATISTICS __BIT(62)
558: #define FW2X_CTRL_TRANSACTION_ID __BIT(63)
559:
560: #define FW2X_SNPRINTB \
561: "\177\020" \
562: "b\x23" "PAUSE\0" \
563: "b\x24" "ASYMMETRIC-PAUSE\0" \
564: "b\x31" "CABLE-DIAG\0" \
565: "b\x32" "TEMPERATURE\0" \
566: "b\x33" "DOWNSHIFT\0" \
567: "b\x34" "PTP-AVB\0" \
568: "b\x35" "MEDIA-DETECT\0" \
569: "b\x36" "LINK-DROP\0" \
570: "b\x37" "SLEEP-PROXY\0" \
571: "b\x38" "WOL\0" \
572: "b\x39" "MAC-STOP\0" \
573: "b\x3a" "EXT-LOOPBACK\0" \
574: "b\x3b" "INT-LOOPBACK\0" \
575: "b\x3c" "EFUSE-AGENT\0" \
576: "b\x3d" "WOL-TIMER\0" \
577: "b\x3e" "STATISTICS\0" \
578: "b\x3f" "TRANSACTION-ID\0" \
579: "\0"
580:
581: #define FW2X_CTRL_RATE_100M FW2X_CTRL_100BASETX_FD
582: #define FW2X_CTRL_RATE_1G FW2X_CTRL_1000BASET_FD
583: #define FW2X_CTRL_RATE_2G5 FW2X_CTRL_2P5GBASET_FD
584: #define FW2X_CTRL_RATE_5G FW2X_CTRL_5GBASET_FD
585: #define FW2X_CTRL_RATE_10G FW2X_CTRL_10GBASET_FD
586: #define FW2X_CTRL_RATE_MASK \
587: (FW2X_CTRL_RATE_100M | \
588: FW2X_CTRL_RATE_1G | \
589: FW2X_CTRL_RATE_2G5 | \
590: FW2X_CTRL_RATE_5G | \
591: FW2X_CTRL_RATE_10G)
592: #define FW2X_CTRL_EEE_MASK \
593: (FW2X_CTRL_10BASET_EEE | \
594: FW2X_CTRL_100BASETX_EEE | \
595: FW2X_CTRL_1000BASET_FD_EEE | \
596: FW2X_CTRL_2P5GBASET_FD_EEE | \
597: FW2X_CTRL_5GBASET_FD_EEE | \
598: FW2X_CTRL_10GBASET_FD_EEE)
599:
600: typedef enum aq_fw_bootloader_mode {
601: FW_BOOT_MODE_UNKNOWN = 0,
602: FW_BOOT_MODE_FLB,
603: FW_BOOT_MODE_RBL_FLASH,
604: FW_BOOT_MODE_RBL_HOST_BOOTLOAD
605: } aq_fw_bootloader_mode_t;
606:
607: #define AQ_WRITE_REG(sc, reg, val) \
608: bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
609:
610: #define AQ_READ_REG(sc, reg) \
611: bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
612:
613: #define AQ_READ64_REG(sc, reg) \
614: ((uint64_t)AQ_READ_REG(sc, reg) | \
615: (((uint64_t)AQ_READ_REG(sc, (reg) + 4)) << 32))
616:
617: #define AQ_WRITE64_REG(sc, reg, val) \
618: do { \
619: AQ_WRITE_REG(sc, reg, (uint32_t)val); \
620: AQ_WRITE_REG(sc, reg + 4, (uint32_t)(val >> 32)); \
621: } while (/* CONSTCOND */0)
622:
623: #define AQ_READ_REG_BIT(sc, reg, mask) \
624: __SHIFTOUT(AQ_READ_REG(sc, reg), mask)
625:
626: #define AQ_WRITE_REG_BIT(sc, reg, mask, val) \
627: do { \
628: uint32_t _v; \
629: _v = AQ_READ_REG((sc), (reg)); \
630: _v &= ~(mask); \
631: if ((val) != 0) \
632: _v |= __SHIFTIN((val), (mask)); \
633: AQ_WRITE_REG((sc), (reg), _v); \
634: } while (/* CONSTCOND */ 0)
635:
636: #define WAIT_FOR(expr, us, n, errp) \
637: do { \
638: unsigned int _n; \
639: for (_n = n; (!(expr)) && _n != 0; --_n) { \
640: delay((us)); \
641: } \
642: if ((errp != NULL)) { \
643: if (_n == 0) \
644: *(errp) = ETIMEDOUT; \
645: else \
646: *(errp) = 0; \
647: } \
648: } while (/* CONSTCOND */ 0)
649:
650: #define msec_delay(x) DELAY(1000 * (x))
651:
652: typedef struct aq_mailbox_header {
653: uint32_t version;
654: uint32_t transaction_id;
655: int32_t error;
656: } __packed aq_mailbox_header_t;
657:
658: typedef struct aq_hw_stats_s {
659: uint32_t uprc;
660: uint32_t mprc;
661: uint32_t bprc;
662: uint32_t erpt;
663: uint32_t uptc;
664: uint32_t mptc;
665: uint32_t bptc;
666: uint32_t erpr;
667: uint32_t mbtc;
668: uint32_t bbtc;
669: uint32_t mbrc;
670: uint32_t bbrc;
671: uint32_t ubrc;
672: uint32_t ubtc;
673: uint32_t ptc;
674: uint32_t prc;
675: uint32_t dpc; /* not exists in fw2x_msm_statistics */
676: uint32_t cprc; /* not exists in fw2x_msm_statistics */
677: } __packed aq_hw_stats_s_t;
678:
679: typedef struct fw1x_mailbox {
680: aq_mailbox_header_t header;
681: aq_hw_stats_s_t msm;
682: } __packed fw1x_mailbox_t;
683:
684: typedef struct fw2x_msm_statistics {
685: uint32_t uprc;
686: uint32_t mprc;
687: uint32_t bprc;
688: uint32_t erpt;
689: uint32_t uptc;
690: uint32_t mptc;
691: uint32_t bptc;
692: uint32_t erpr;
693: uint32_t mbtc;
694: uint32_t bbtc;
695: uint32_t mbrc;
696: uint32_t bbrc;
697: uint32_t ubrc;
698: uint32_t ubtc;
699: uint32_t ptc;
700: uint32_t prc;
701: } __packed fw2x_msm_statistics_t;
702:
703: typedef struct fw2x_phy_cable_diag_data {
704: uint32_t lane_data[4];
705: } __packed fw2x_phy_cable_diag_data_t;
706:
707: typedef struct fw2x_capabilities {
708: uint32_t caps_lo;
709: uint32_t caps_hi;
710: } __packed fw2x_capabilities_t;
711:
712: typedef struct fw2x_mailbox { /* struct fwHostInterface */
713: aq_mailbox_header_t header;
714: fw2x_msm_statistics_t msm; /* msmStatistics_t msm; */
1.4 ryo 715:
716: uint32_t phy_info1;
717: #define PHYINFO1_FAULT_CODE __BITS(31,16)
718: #define PHYINFO1_PHY_H_BIT __BITS(0,15)
719: uint32_t phy_info2;
720: #define PHYINFO2_TEMPERATURE __BITS(15,0)
721: #define PHYINFO2_CABLE_LEN __BITS(23,16)
722:
1.1 ryo 723: fw2x_phy_cable_diag_data_t diag_data;
724: uint32_t reserved[8];
725:
726: fw2x_capabilities_t caps;
727:
728: /* ... */
729: } __packed fw2x_mailbox_t;
730:
731: typedef enum aq_link_speed {
732: AQ_LINK_NONE = 0,
733: AQ_LINK_100M = (1 << 0),
734: AQ_LINK_1G = (1 << 1),
735: AQ_LINK_2G5 = (1 << 2),
736: AQ_LINK_5G = (1 << 3),
737: AQ_LINK_10G = (1 << 4)
738: } aq_link_speed_t;
739: #define AQ_LINK_ALL (AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | \
740: AQ_LINK_5G | AQ_LINK_10G )
741: #define AQ_LINK_AUTO AQ_LINK_ALL
742:
743: typedef enum aq_link_fc {
744: AQ_FC_NONE = 0,
745: AQ_FC_RX = __BIT(0),
746: AQ_FC_TX = __BIT(1),
747: AQ_FC_ALL = (AQ_FC_RX | AQ_FC_TX)
748: } aq_link_fc_t;
749:
750: typedef enum aq_link_eee {
751: AQ_EEE_DISABLE = 0,
752: AQ_EEE_ENABLE = 1
753: } aq_link_eee_t;
754:
755: typedef enum aq_hw_fw_mpi_state {
756: MPI_DEINIT = 0,
757: MPI_RESET = 1,
758: MPI_INIT = 2,
759: MPI_POWER = 4
760: } aq_hw_fw_mpi_state_t;
761:
762: enum aq_media_type {
763: AQ_MEDIA_TYPE_UNKNOWN = 0,
764: AQ_MEDIA_TYPE_FIBRE,
765: AQ_MEDIA_TYPE_TP
766: };
767:
768: struct aq_rx_desc_read {
769: uint64_t buf_addr;
770: uint64_t hdr_addr;
771: } __packed;
772:
773: struct aq_rx_desc_wb {
774: uint32_t type;
775: #define RXDESC_TYPE_RSSTYPE __BITS(3,0)
776: #define RXDESC_TYPE_RSSTYPE_NONE 0
777: #define RXDESC_TYPE_RSSTYPE_IPV4 2
778: #define RXDESC_TYPE_RSSTYPE_IPV6 3
779: #define RXDESC_TYPE_RSSTYPE_IPV4_TCP 4
780: #define RXDESC_TYPE_RSSTYPE_IPV6_TCP 5
781: #define RXDESC_TYPE_RSSTYPE_IPV4_UDP 6
782: #define RXDESC_TYPE_RSSTYPE_IPV6_UDP 7
783: #define RXDESC_TYPE_PKTTYPE_ETHER __BITS(5,4)
784: #define RXDESC_TYPE_PKTTYPE_ETHER_IPV4 0
785: #define RXDESC_TYPE_PKTTYPE_ETHER_IPV6 1
786: #define RXDESC_TYPE_PKTTYPE_ETHER_OTHERS 2
787: #define RXDESC_TYPE_PKTTYPE_ETHER_ARP 3
788: #define RXDESC_TYPE_PKTTYPE_PROTO __BITS(8,6)
789: #define RXDESC_TYPE_PKTTYPE_PROTO_TCP 0
790: #define RXDESC_TYPE_PKTTYPE_PROTO_UDP 1
791: #define RXDESC_TYPE_PKTTYPE_PROTO_SCTP 2
792: #define RXDESC_TYPE_PKTTYPE_PROTO_ICMP 3
793: #define RXDESC_TYPE_PKTTYPE_PROTO_OTHERS 4
794: #define RXDESC_TYPE_PKTTYPE_VLAN __BIT(9)
795: #define RXDESC_TYPE_PKTTYPE_VLAN_DOUBLE __BIT(10)
796: #define RXDESC_TYPE_MAC_DMA_ERR __BIT(12)
797: #define RXDESC_TYPE_RESERVED __BITS(18,13)
798: #define RXDESC_TYPE_IPV4_CSUM_CHECKED __BIT(19) /* PKTTYPE_ETHER_IPV4 */
799: #define RXDESC_TYPE_TCPUDP_CSUM_CHECKED __BIT(20)
800: #define RXDESC_TYPE_SPH __BIT(21)
801: #define RXDESC_TYPE_HDR_LEN __BITS(31,22)
802: uint32_t rss_hash;
803: uint16_t status;
804: #define RXDESC_STATUS_DD __BIT(0)
805: #define RXDESC_STATUS_EOP __BIT(1)
806: #define RXDESC_STATUS_MACERR __BIT(2)
807: #define RXDESC_STATUS_IPV4_CSUM_NG __BIT(3)
808: #define RXDESC_STATUS_TCPUDP_CSUM_ERROR __BIT(4)
809: #define RXDESC_STATUS_TCPUDP_CSUM_OK __BIT(5)
810:
811: #define RXDESC_STATUS_STAT __BITS(2,5)
812: #define RXDESC_STATUS_ESTAT __BITS(6,11)
813: #define RXDESC_STATUS_RSC_CNT __BITS(12,15)
814: uint16_t pkt_len;
815: uint16_t next_desc_ptr;
816: uint16_t vlan;
817: } __packed;
818:
819: typedef union aq_rx_desc {
820: struct aq_rx_desc_read read;
821: struct aq_rx_desc_wb wb;
822: } __packed aq_rx_desc_t;
823:
824: typedef struct aq_tx_desc {
825: uint64_t buf_addr;
826: uint32_t ctl1;
827: #define AQ_TXDESC_CTL1_TYPE_MASK 0x00000003
828: #define AQ_TXDESC_CTL1_TYPE_TXD 0x00000001
829: #define AQ_TXDESC_CTL1_TYPE_TXC 0x00000002
830: #define AQ_TXDESC_CTL1_BLEN __BITS(19,4) /* TXD */
831: #define AQ_TXDESC_CTL1_DD __BIT(20) /* TXD */
832: #define AQ_TXDESC_CTL1_EOP __BIT(21) /* TXD */
833: #define AQ_TXDESC_CTL1_CMD_VLAN __BIT(22) /* TXD */
834: #define AQ_TXDESC_CTL1_CMD_FCS __BIT(23) /* TXD */
835: #define AQ_TXDESC_CTL1_CMD_IP4CSUM __BIT(24) /* TXD */
836: #define AQ_TXDESC_CTL1_CMD_L4CSUM __BIT(25) /* TXD */
837: #define AQ_TXDESC_CTL1_CMD_LSO __BIT(26) /* TXD */
838: #define AQ_TXDESC_CTL1_CMD_WB __BIT(27) /* TXD */
839: #define AQ_TXDESC_CTL1_CMD_VXLAN __BIT(28) /* TXD */
840: #define AQ_TXDESC_CTL1_VID __BITS(15,4) /* TXC */
841: #define AQ_TXDESC_CTL1_LSO_IPV6 __BIT(21) /* TXC */
842: #define AQ_TXDESC_CTL1_LSO_TCP __BIT(22) /* TXC */
843: uint32_t ctl2;
844: #define AQ_TXDESC_CTL2_LEN __BITS(31,14)
845: #define AQ_TXDESC_CTL2_CTX_EN __BIT(13)
846: #define AQ_TXDESC_CTL2_CTX_IDX __BIT(12)
847: } __packed aq_tx_desc_t;
848:
849: struct aq_txring {
850: struct aq_softc *txr_sc;
851: int txr_index;
852: kmutex_t txr_mutex;
853: bool txr_active;
854:
855: pcq_t *txr_pcq;
856: void *txr_softint;
857:
858: aq_tx_desc_t *txr_txdesc; /* aq_tx_desc_t[AQ_TXD_NUM] */
859: bus_dmamap_t txr_txdesc_dmamap;
860: bus_dma_segment_t txr_txdesc_seg[1];
861: bus_size_t txr_txdesc_size;
862:
863: struct {
864: struct mbuf *m;
865: bus_dmamap_t dmamap;
866: } txr_mbufs[AQ_TXD_NUM];
867: unsigned int txr_prodidx;
868: unsigned int txr_considx;
869: int txr_nfree;
870: };
871:
872: struct aq_rxring {
873: struct aq_softc *rxr_sc;
874: int rxr_index;
875: kmutex_t rxr_mutex;
876: bool rxr_active;
877:
878: aq_rx_desc_t *rxr_rxdesc; /* aq_rx_desc_t[AQ_RXD_NUM] */
879: bus_dmamap_t rxr_rxdesc_dmamap;
880: bus_dma_segment_t rxr_rxdesc_seg[1];
881: bus_size_t rxr_rxdesc_size;
882: struct {
883: struct mbuf *m;
884: bus_dmamap_t dmamap;
885: } rxr_mbufs[AQ_RXD_NUM];
886: unsigned int rxr_readidx;
887: };
888:
889: struct aq_queue {
890: struct aq_softc *sc;
891: struct aq_txring txring;
892: struct aq_rxring rxring;
893: };
894:
895: struct aq_softc;
896: struct aq_firmware_ops {
897: int (*reset)(struct aq_softc *);
898: int (*set_mode)(struct aq_softc *, aq_hw_fw_mpi_state_t,
899: aq_link_speed_t, aq_link_fc_t, aq_link_eee_t);
900: int (*get_mode)(struct aq_softc *, aq_hw_fw_mpi_state_t *,
901: aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *);
902: int (*get_stats)(struct aq_softc *, aq_hw_stats_s_t *);
1.4 ryo 903: #if NSYSMON_ENVSYS > 0
904: int (*get_temperature)(struct aq_softc *, uint32_t *);
905: #endif
1.1 ryo 906: };
907:
908: #ifdef AQ_EVENT_COUNTERS
909: #define AQ_EVCNT_DECL(name) \
910: char sc_evcount_##name##_name[32]; \
911: struct evcnt sc_evcount_##name##_ev;
912: #define AQ_EVCNT_ATTACH(sc, name, desc, evtype) \
913: do { \
914: snprintf((sc)->sc_evcount_##name##_name, \
915: sizeof((sc)->sc_evcount_##name##_name), \
916: "%s", desc); \
917: evcnt_attach_dynamic(&(sc)->sc_evcount_##name##_ev, \
918: (evtype), NULL, device_xname((sc)->sc_dev), \
919: (sc)->sc_evcount_##name##_name); \
920: } while (/*CONSTCOND*/0)
921: #define AQ_EVCNT_ATTACH_MISC(sc, name, desc) \
922: AQ_EVCNT_ATTACH(sc, name, desc, EVCNT_TYPE_MISC)
923: #define AQ_EVCNT_DETACH(sc, name) \
924: evcnt_detach(&(sc)->sc_evcount_##name##_ev)
925: #define AQ_EVCNT_ADD(sc, name, val) \
926: ((sc)->sc_evcount_##name##_ev.ev_count += (val))
927: #endif /* AQ_EVENT_COUNTERS */
928:
929: #define AQ_LOCK(sc) mutex_enter(&(sc)->sc_mutex);
930: #define AQ_UNLOCK(sc) mutex_exit(&(sc)->sc_mutex);
931:
1.4 ryo 932: /* lock for FW2X_MPI_{CONTROL,STATE]_REG read-modify-write */
933: #define AQ_MPI_LOCK(sc) mutex_enter(&(sc)->sc_mpi_mutex);
934: #define AQ_MPI_UNLOCK(sc) mutex_exit(&(sc)->sc_mpi_mutex);
935:
936:
1.1 ryo 937: struct aq_softc {
938: device_t sc_dev;
939:
940: bus_space_tag_t sc_iot;
941: bus_space_handle_t sc_ioh;
942: bus_size_t sc_iosize;
943: bus_dma_tag_t sc_dmat;;
944:
945: void *sc_ihs[AQ_NINTR_MAX];
946: pci_intr_handle_t *sc_intrs;
947:
948: int sc_tx_irq[AQ_RSSQUEUE_MAX];
949: int sc_rx_irq[AQ_RSSQUEUE_MAX];
950: int sc_linkstat_irq;
951: bool sc_use_txrx_independent_intr;
952: bool sc_poll_linkstat;
953: bool sc_detect_linkstat;
954:
1.4 ryo 955: #if NSYSMON_ENVSYS > 0
956: struct sysmon_envsys *sc_sme;
957: envsys_data_t sc_sensor_temp;
958: #endif
959:
1.1 ryo 960: callout_t sc_tick_ch;
961:
962: int sc_nintrs;
963: bool sc_msix;
964:
965: struct aq_queue sc_queue[AQ_RSSQUEUE_MAX];
966: int sc_nqueues;
967:
968: pci_chipset_tag_t sc_pc;
969: pcitag_t sc_pcitag;
970: uint16_t sc_product;
971: uint16_t sc_revision;
972:
973: kmutex_t sc_mutex;
1.4 ryo 974: kmutex_t sc_mpi_mutex;
1.1 ryo 975:
1.8 maxv 976: const struct aq_firmware_ops *sc_fw_ops;
1.1 ryo 977: uint64_t sc_fw_caps;
978: enum aq_media_type sc_media_type;
979: aq_link_speed_t sc_available_rates;
980:
981: aq_link_speed_t sc_link_rate;
982: aq_link_fc_t sc_link_fc;
983: aq_link_eee_t sc_link_eee;
984:
985: uint32_t sc_fw_version;
986: #define FW_VERSION_MAJOR(sc) (((sc)->sc_fw_version >> 24) & 0xff)
987: #define FW_VERSION_MINOR(sc) (((sc)->sc_fw_version >> 16) & 0xff)
988: #define FW_VERSION_BUILD(sc) ((sc)->sc_fw_version & 0xffff)
989: uint32_t sc_features;
990: #define FEATURES_MIPS 0x00000001
991: #define FEATURES_TPO2 0x00000002
992: #define FEATURES_RPF2 0x00000004
993: #define FEATURES_MPI_AQ 0x00000008
994: #define FEATURES_REV_A0 0x10000000
995: #define FEATURES_REV_A (FEATURES_REV_A0)
996: #define FEATURES_REV_B0 0x20000000
997: #define FEATURES_REV_B1 0x40000000
998: #define FEATURES_REV_B (FEATURES_REV_B0|FEATURES_REV_B1)
999: uint32_t sc_mbox_addr;
1000:
1001: bool sc_rbl_enabled;
1002: bool sc_fast_start_enabled;
1003: bool sc_flash_present;
1004:
1005: bool sc_intr_moderation_enable;
1006: bool sc_rss_enable;
1007:
1008: struct ethercom sc_ethercom;
1009: struct ether_addr sc_enaddr;
1010: struct ifmedia sc_media;
1011: int sc_ec_capenable; /* last ec_capenable */
1012: unsigned short sc_if_flags; /* last if_flags */
1013:
1014: #ifdef AQ_EVENT_COUNTERS
1015: aq_hw_stats_s_t sc_statistics[2];
1016: int sc_statistics_idx;
1017: bool sc_poll_statistics;
1018:
1019: AQ_EVCNT_DECL(uprc);
1020: AQ_EVCNT_DECL(mprc);
1021: AQ_EVCNT_DECL(bprc);
1022: AQ_EVCNT_DECL(erpt);
1023: AQ_EVCNT_DECL(uptc);
1024: AQ_EVCNT_DECL(mptc);
1025: AQ_EVCNT_DECL(bptc);
1026: AQ_EVCNT_DECL(erpr);
1027: AQ_EVCNT_DECL(mbtc);
1028: AQ_EVCNT_DECL(bbtc);
1029: AQ_EVCNT_DECL(mbrc);
1030: AQ_EVCNT_DECL(bbrc);
1031: AQ_EVCNT_DECL(ubrc);
1032: AQ_EVCNT_DECL(ubtc);
1033: AQ_EVCNT_DECL(ptc);
1034: AQ_EVCNT_DECL(prc);
1035: AQ_EVCNT_DECL(dpc);
1036: AQ_EVCNT_DECL(cprc);
1037: #endif
1038: };
1039:
1040: static int aq_match(device_t, cfdata_t, void *);
1041: static void aq_attach(device_t, device_t, void *);
1042: static int aq_detach(device_t, int);
1043:
1044: static int aq_setup_msix(struct aq_softc *, struct pci_attach_args *, int,
1045: bool, bool);
1046: static int aq_setup_legacy(struct aq_softc *, struct pci_attach_args *,
1047: pci_intr_type_t);
1048: static int aq_establish_msix_intr(struct aq_softc *, bool, bool);
1049:
1050: static int aq_ifmedia_change(struct ifnet * const);
1051: static void aq_ifmedia_status(struct ifnet * const, struct ifmediareq *);
1.10 ryo 1052: static int aq_vlan_cb(struct ethercom *ec, uint16_t vid, bool set);
1.1 ryo 1053: static int aq_ifflags_cb(struct ethercom *);
1054: static int aq_init(struct ifnet *);
1055: static void aq_send_common_locked(struct ifnet *, struct aq_softc *,
1056: struct aq_txring *, bool);
1057: static int aq_transmit(struct ifnet *, struct mbuf *);
1058: static void aq_deferred_transmit(void *);
1059: static void aq_start(struct ifnet *);
1060: static void aq_stop(struct ifnet *, int);
1061: static void aq_watchdog(struct ifnet *);
1062: static int aq_ioctl(struct ifnet *, unsigned long, void *);
1063:
1064: static int aq_txrx_rings_alloc(struct aq_softc *);
1065: static void aq_txrx_rings_free(struct aq_softc *);
1066: static int aq_tx_pcq_alloc(struct aq_softc *, struct aq_txring *);
1067: static void aq_tx_pcq_free(struct aq_softc *, struct aq_txring *);
1068:
1069: static void aq_initmedia(struct aq_softc *);
1070: static void aq_enable_intr(struct aq_softc *, bool, bool);
1071:
1.4 ryo 1072: #if NSYSMON_ENVSYS > 0
1073: static void aq_temp_refresh(struct sysmon_envsys *, envsys_data_t *);
1074: #endif
1.1 ryo 1075: static void aq_tick(void *);
1076: static int aq_legacy_intr(void *);
1077: static int aq_link_intr(void *);
1078: static int aq_txrx_intr(void *);
1079: static int aq_tx_intr(void *);
1080: static int aq_rx_intr(void *);
1081:
1082: static int aq_set_linkmode(struct aq_softc *, aq_link_speed_t, aq_link_fc_t,
1083: aq_link_eee_t);
1084: static int aq_get_linkmode(struct aq_softc *, aq_link_speed_t *, aq_link_fc_t *,
1085: aq_link_eee_t *);
1086:
1087: static int aq_fw_reset(struct aq_softc *);
1088: static int aq_fw_version_init(struct aq_softc *);
1089: static int aq_hw_init(struct aq_softc *);
1090: static int aq_hw_init_ucp(struct aq_softc *);
1091: static int aq_hw_reset(struct aq_softc *);
1092: static int aq_fw_downld_dwords(struct aq_softc *, uint32_t, uint32_t *,
1093: uint32_t);
1094: static int aq_get_mac_addr(struct aq_softc *);
1095: static int aq_init_rss(struct aq_softc *);
1096: static int aq_set_capability(struct aq_softc *);
1097:
1098: static int fw1x_reset(struct aq_softc *);
1099: static int fw1x_set_mode(struct aq_softc *, aq_hw_fw_mpi_state_t,
1100: aq_link_speed_t, aq_link_fc_t, aq_link_eee_t);
1101: static int fw1x_get_mode(struct aq_softc *, aq_hw_fw_mpi_state_t *,
1102: aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *);
1103: static int fw1x_get_stats(struct aq_softc *, aq_hw_stats_s_t *);
1104:
1105: static int fw2x_reset(struct aq_softc *);
1106: static int fw2x_set_mode(struct aq_softc *, aq_hw_fw_mpi_state_t,
1107: aq_link_speed_t, aq_link_fc_t, aq_link_eee_t);
1108: static int fw2x_get_mode(struct aq_softc *, aq_hw_fw_mpi_state_t *,
1109: aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *);
1110: static int fw2x_get_stats(struct aq_softc *, aq_hw_stats_s_t *);
1.4 ryo 1111: #if NSYSMON_ENVSYS > 0
1112: static int fw2x_get_temperature(struct aq_softc *, uint32_t *);
1113: #endif
1.1 ryo 1114:
1.8 maxv 1115: static const struct aq_firmware_ops aq_fw1x_ops = {
1.1 ryo 1116: .reset = fw1x_reset,
1117: .set_mode = fw1x_set_mode,
1118: .get_mode = fw1x_get_mode,
1.4 ryo 1119: .get_stats = fw1x_get_stats,
1120: #if NSYSMON_ENVSYS > 0
1121: .get_temperature = NULL
1122: #endif
1.1 ryo 1123: };
1124:
1.8 maxv 1125: static const struct aq_firmware_ops aq_fw2x_ops = {
1.1 ryo 1126: .reset = fw2x_reset,
1127: .set_mode = fw2x_set_mode,
1128: .get_mode = fw2x_get_mode,
1.4 ryo 1129: .get_stats = fw2x_get_stats,
1130: #if NSYSMON_ENVSYS > 0
1131: .get_temperature = fw2x_get_temperature
1132: #endif
1.1 ryo 1133: };
1134:
1135: CFATTACH_DECL3_NEW(aq, sizeof(struct aq_softc),
1136: aq_match, aq_attach, aq_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
1137:
1138: static const struct aq_product {
1139: pci_vendor_id_t aq_vendor;
1140: pci_product_id_t aq_product;
1141: const char *aq_name;
1142: enum aq_media_type aq_media_type;
1143: aq_link_speed_t aq_available_rates;
1144: } aq_products[] = {
1.14 ryo 1145: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100,
1146: "Aquantia AQC100 10 Gigabit Network Adapter",
1147: AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL
1148: },
1.1 ryo 1149: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107,
1150: "Aquantia AQC107 10 Gigabit Network Adapter",
1151: AQ_MEDIA_TYPE_TP, AQ_LINK_ALL
1152: },
1153: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108,
1154: "Aquantia AQC108 5 Gigabit Network Adapter",
1155: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1156: },
1157: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109,
1158: "Aquantia AQC109 2.5 Gigabit Network Adapter",
1159: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1160: },
1161: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111,
1162: "Aquantia AQC111 5 Gigabit Network Adapter",
1163: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1164: },
1165: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112,
1166: "Aquantia AQC112 2.5 Gigabit Network Adapter",
1167: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1168: },
1.15 ! ryo 1169: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100S,
! 1170: "Aquantia AQC100 10 Gigabit Network Adapter",
! 1171: AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL
! 1172: },
1.1 ryo 1173: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107S,
1174: "Aquantia AQC107S 10 Gigabit Network Adapter",
1175: AQ_MEDIA_TYPE_TP, AQ_LINK_ALL
1176: },
1177: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108S,
1178: "Aquantia AQC108S 5 Gigabit Network Adapter",
1179: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1180: },
1181: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109S,
1182: "Aquantia AQC109S 2.5 Gigabit Network Adapter",
1183: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1184: },
1185: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111S,
1186: "Aquantia AQC111S 5 Gigabit Network Adapter",
1187: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1188: },
1189: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112S,
1190: "Aquantia AQC112S 2.5 Gigabit Network Adapter",
1191: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1192: },
1.15 ! ryo 1193: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D100,
! 1194: "Aquantia D100 10 Gigabit Network Adapter",
! 1195: AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL
! 1196: },
1.1 ryo 1197: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D107,
1198: "Aquantia D107 10 Gigabit Network Adapter",
1199: AQ_MEDIA_TYPE_TP, AQ_LINK_ALL
1200: },
1201: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D108,
1202: "Aquantia D108 5 Gigabit Network Adapter",
1203: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1204: },
1205: { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D109,
1206: "Aquantia D109 2.5 Gigabit Network Adapter",
1207: AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1208: }
1209: };
1210:
1211: static const struct aq_product *
1212: aq_lookup(const struct pci_attach_args *pa)
1213: {
1214: unsigned int i;
1215:
1216: for (i = 0; i < __arraycount(aq_products); i++) {
1217: if (PCI_VENDOR(pa->pa_id) == aq_products[i].aq_vendor &&
1218: PCI_PRODUCT(pa->pa_id) == aq_products[i].aq_product)
1219: return &aq_products[i];
1220: }
1221: return NULL;
1222: }
1223:
1224: static int
1225: aq_match(device_t parent, cfdata_t cf, void *aux)
1226: {
1227: struct pci_attach_args *pa = aux;
1228:
1229: if (aq_lookup(pa) != NULL)
1230: return 1;
1231:
1232: return 0;
1233: }
1234:
1235: static void
1236: aq_attach(device_t parent, device_t self, void *aux)
1237: {
1238: struct aq_softc *sc = device_private(self);
1239: struct pci_attach_args *pa = aux;
1240: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1241: pci_chipset_tag_t pc;
1242: pcitag_t tag;
1243: pcireg_t command, memtype, bar;
1244: const struct aq_product *aqp;
1245: int error;
1246:
1247: sc->sc_dev = self;
1248: mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_NET);
1.4 ryo 1249: mutex_init(&sc->sc_mpi_mutex, MUTEX_DEFAULT, IPL_NET);
1.1 ryo 1250:
1251: sc->sc_pc = pc = pa->pa_pc;
1252: sc->sc_pcitag = tag = pa->pa_tag;
1253: sc->sc_dmat = pci_dma64_available(pa) ? pa->pa_dmat64 : pa->pa_dmat;
1254:
1255: command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1256: command |= PCI_COMMAND_MASTER_ENABLE;
1257: pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
1258:
1259: sc->sc_product = PCI_PRODUCT(pa->pa_id);
1260: sc->sc_revision = PCI_REVISION(pa->pa_class);
1261:
1262: aqp = aq_lookup(pa);
1263: KASSERT(aqp != NULL);
1264:
1265: pci_aprint_devinfo_fancy(pa, "Ethernet controller", aqp->aq_name, 1);
1266:
1267: bar = pci_conf_read(pc, tag, PCI_BAR(0));
1268: if ((PCI_MAPREG_MEM_ADDR(bar) == 0) ||
1269: (PCI_MAPREG_TYPE(bar) != PCI_MAPREG_TYPE_MEM)) {
1270: aprint_error_dev(sc->sc_dev, "wrong BAR type\n");
1271: return;
1272: }
1273: memtype = pci_mapreg_type(pc, tag, PCI_BAR(0));
1274: if (pci_mapreg_map(pa, PCI_BAR(0), memtype, 0, &sc->sc_iot, &sc->sc_ioh,
1275: NULL, &sc->sc_iosize) != 0) {
1276: aprint_error_dev(sc->sc_dev, "unable to map register\n");
1277: return;
1278: }
1279:
1280: sc->sc_nqueues = MIN(ncpu, AQ_RSSQUEUE_MAX);
1281:
1282: /* max queue num is 8, and must be 2^n */
1283: if (ncpu >= 8)
1284: sc->sc_nqueues = 8;
1285: else if (ncpu >= 4)
1286: sc->sc_nqueues = 4;
1287: else if (ncpu >= 2)
1288: sc->sc_nqueues = 2;
1289: else
1290: sc->sc_nqueues = 1;
1291:
1292: int msixcount = pci_msix_count(pa->pa_pc, pa->pa_tag);
1293: #ifndef CONFIG_NO_TXRX_INDEPENDENT
1294: if (msixcount >= (sc->sc_nqueues * 2 + 1)) {
1295: /* TX intrs + RX intrs + LINKSTAT intrs */
1296: sc->sc_use_txrx_independent_intr = true;
1297: sc->sc_poll_linkstat = false;
1298: sc->sc_msix = true;
1299: } else if (msixcount >= (sc->sc_nqueues * 2)) {
1300: /* TX intrs + RX intrs */
1301: sc->sc_use_txrx_independent_intr = true;
1302: sc->sc_poll_linkstat = true;
1303: sc->sc_msix = true;
1304: } else
1305: #endif
1306: if (msixcount >= (sc->sc_nqueues + 1)) {
1307: /* TX/RX intrs LINKSTAT intrs */
1308: sc->sc_use_txrx_independent_intr = false;
1309: sc->sc_poll_linkstat = false;
1310: sc->sc_msix = true;
1311: } else if (msixcount >= sc->sc_nqueues) {
1312: /* TX/RX intrs */
1313: sc->sc_use_txrx_independent_intr = false;
1314: sc->sc_poll_linkstat = true;
1315: sc->sc_msix = true;
1316: } else {
1317: /* giving up using MSI-X */
1318: sc->sc_msix = false;
1319: }
1320:
1.13 ryo 1321: /* XXX: on FIBRE, linkstat interrupt does not occur on boot? */
1322: if (aqp->aq_media_type == AQ_MEDIA_TYPE_FIBRE)
1323: sc->sc_poll_linkstat = true;
1324:
1325: #ifdef AQ_FORCE_POLL_LINKSTAT
1326: sc->sc_poll_linkstat = true;
1327: #endif
1328:
1.1 ryo 1329: aprint_debug_dev(sc->sc_dev,
1330: "ncpu=%d, pci_msix_count=%d."
1331: " allocate %d interrupts for %d%s queues%s\n",
1332: ncpu, msixcount,
1333: (sc->sc_use_txrx_independent_intr ?
1334: (sc->sc_nqueues * 2) : sc->sc_nqueues) +
1335: (sc->sc_poll_linkstat ? 0 : 1),
1336: sc->sc_nqueues,
1337: sc->sc_use_txrx_independent_intr ? "*2" : "",
1338: sc->sc_poll_linkstat ? "" : ", and link status");
1339:
1340: if (sc->sc_msix)
1341: error = aq_setup_msix(sc, pa, sc->sc_nqueues,
1342: sc->sc_use_txrx_independent_intr, !sc->sc_poll_linkstat);
1343: else
1344: error = ENODEV;
1345:
1346: if (error != 0) {
1347: /* if MSI-X failed, fallback to MSI with single queue */
1348: sc->sc_use_txrx_independent_intr = false;
1349: sc->sc_poll_linkstat = false;
1350: sc->sc_msix = false;
1351: sc->sc_nqueues = 1;
1352: error = aq_setup_legacy(sc, pa, PCI_INTR_TYPE_MSI);
1353: }
1354: if (error != 0) {
1355: /* if MSI failed, fallback to INTx */
1356: error = aq_setup_legacy(sc, pa, PCI_INTR_TYPE_INTX);
1357: }
1358: if (error != 0)
1359: return;
1360:
1361: callout_init(&sc->sc_tick_ch, 0);
1362: callout_setfunc(&sc->sc_tick_ch, aq_tick, sc);
1363:
1364: sc->sc_intr_moderation_enable = CONFIG_INTR_MODERATION_ENABLE;
1365:
1366: if (sc->sc_msix && (sc->sc_nqueues > 1))
1367: sc->sc_rss_enable = true;
1368: else
1369: sc->sc_rss_enable = false;
1370:
1371: error = aq_txrx_rings_alloc(sc);
1372: if (error != 0)
1373: goto attach_failure;
1374:
1375: error = aq_fw_reset(sc);
1376: if (error != 0)
1377: goto attach_failure;
1378:
1379: error = aq_fw_version_init(sc);
1380: if (error != 0)
1381: goto attach_failure;
1382:
1383: error = aq_hw_init_ucp(sc);
1384: if (error < 0)
1385: goto attach_failure;
1386:
1387: KASSERT(sc->sc_mbox_addr != 0);
1388: error = aq_hw_reset(sc);
1389: if (error != 0)
1390: goto attach_failure;
1391:
1392: aq_get_mac_addr(sc);
1393: aq_init_rss(sc);
1394:
1395: error = aq_hw_init(sc); /* initialize and interrupts */
1396: if (error != 0)
1397: goto attach_failure;
1398:
1399: sc->sc_media_type = aqp->aq_media_type;
1400: sc->sc_available_rates = aqp->aq_available_rates;
1401:
1402: sc->sc_ethercom.ec_ifmedia = &sc->sc_media;
1403: ifmedia_init(&sc->sc_media, IFM_IMASK,
1404: aq_ifmedia_change, aq_ifmedia_status);
1405: aq_initmedia(sc);
1406:
1407: strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
1408: ifp->if_softc = sc;
1409: ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1410: ifp->if_baudrate = IF_Gbps(10);
1411: ifp->if_init = aq_init;
1412: ifp->if_ioctl = aq_ioctl;
1413: if (sc->sc_msix && (sc->sc_nqueues > 1))
1414: ifp->if_transmit = aq_transmit;
1415: ifp->if_start = aq_start;
1416: ifp->if_stop = aq_stop;
1417: ifp->if_watchdog = aq_watchdog;
1418: IFQ_SET_READY(&ifp->if_snd);
1419:
1420: /* initialize capabilities */
1421: sc->sc_ethercom.ec_capabilities = 0;
1422: sc->sc_ethercom.ec_capenable = 0;
1423: #if notyet
1424: /* TODO */
1425: sc->sc_ethercom.ec_capabilities |= ETHERCAP_EEE;
1426: #endif
1427: sc->sc_ethercom.ec_capabilities |=
1428: ETHERCAP_JUMBO_MTU |
1429: ETHERCAP_VLAN_MTU |
1.10 ryo 1430: ETHERCAP_VLAN_HWTAGGING |
1431: ETHERCAP_VLAN_HWFILTER;
1.1 ryo 1432: sc->sc_ethercom.ec_capenable |=
1.10 ryo 1433: ETHERCAP_VLAN_HWTAGGING |
1434: ETHERCAP_VLAN_HWFILTER;
1.1 ryo 1435:
1436: ifp->if_capabilities = 0;
1437: ifp->if_capenable = 0;
1438: #ifdef CONFIG_LRO_SUPPORT
1439: ifp->if_capabilities |= IFCAP_LRO;
1440: ifp->if_capenable |= IFCAP_LRO;
1441: #endif
1442: #if notyet
1443: /* TSO */
1444: ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
1445: #endif
1446:
1447: #if notyet
1448: /*
1449: * XXX:
1450: * Rx L4 CSUM doesn't work well for fragment packet.
1451: * aq marks 'CHEDKED' and 'BAD' for them.
1452: * we need to ignore (clear) hw-csum flags if the packet is fragmented
1453: *
1454: * TODO: test with LRO enabled
1455: */
1456: ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_TCPv6_Rx;
1457: ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Rx | IFCAP_CSUM_UDPv6_Rx;
1458: #endif
1459: /* TX hardware checksum offloadding */
1460: ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx;
1461: ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv6_Tx;
1462: ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv6_Tx;
1463: /* RX hardware checksum offloadding */
1464: ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx;
1465:
1466: if_attach(ifp);
1467: if_deferred_start_init(ifp, NULL);
1468: ether_ifattach(ifp, sc->sc_enaddr.ether_addr_octet);
1.10 ryo 1469: ether_set_vlan_cb(&sc->sc_ethercom, aq_vlan_cb);
1.1 ryo 1470: ether_set_ifflags_cb(&sc->sc_ethercom, aq_ifflags_cb);
1471:
1472: aq_enable_intr(sc, true, false); /* only intr about link */
1473:
1474: /* update media */
1475: aq_ifmedia_change(ifp);
1476:
1.4 ryo 1477: #if NSYSMON_ENVSYS > 0
1478: /* temperature monitoring */
1479: if (sc->sc_fw_ops != NULL && sc->sc_fw_ops->get_temperature != NULL &&
1480: (sc->sc_fw_caps & FW2X_CTRL_TEMPERATURE) != 0) {
1481:
1482: sc->sc_sme = sysmon_envsys_create();
1483: sc->sc_sme->sme_name = device_xname(self);
1484: sc->sc_sme->sme_cookie = sc;
1485: sc->sc_sme->sme_flags = 0;
1486: sc->sc_sme->sme_refresh = aq_temp_refresh;
1487: sc->sc_sensor_temp.units = ENVSYS_STEMP;
1488: sc->sc_sensor_temp.state = ENVSYS_SINVALID;
1489: snprintf(sc->sc_sensor_temp.desc, ENVSYS_DESCLEN, "PHY");
1490:
1491: sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor_temp);
1492: sysmon_envsys_register(sc->sc_sme);
1493:
1494: /*
1495: * for unknown reasons, the first call of fw2x_get_temperature()
1496: * will always fail (firmware matter?), so run once now.
1497: */
1498: aq_temp_refresh(sc->sc_sme, &sc->sc_sensor_temp);
1499: }
1500: #endif
1501:
1.1 ryo 1502: #ifdef AQ_EVENT_COUNTERS
1503: /* get starting statistics values */
1504: if (sc->sc_fw_ops != NULL && sc->sc_fw_ops->get_stats != NULL &&
1505: sc->sc_fw_ops->get_stats(sc, &sc->sc_statistics[0]) == 0) {
1506: sc->sc_poll_statistics = true;
1507: }
1508:
1509: AQ_EVCNT_ATTACH_MISC(sc, uprc, "RX unicast packet");
1510: AQ_EVCNT_ATTACH_MISC(sc, bprc, "RX broadcast packet");
1511: AQ_EVCNT_ATTACH_MISC(sc, mprc, "RX multicast packet");
1512: AQ_EVCNT_ATTACH_MISC(sc, erpr, "RX error packet");
1513: AQ_EVCNT_ATTACH_MISC(sc, ubrc, "RX unicast bytes");
1514: AQ_EVCNT_ATTACH_MISC(sc, bbrc, "RX broadcast bytes");
1515: AQ_EVCNT_ATTACH_MISC(sc, mbrc, "RX multicast bytes");
1516: AQ_EVCNT_ATTACH_MISC(sc, prc, "RX good packet");
1517: AQ_EVCNT_ATTACH_MISC(sc, uptc, "TX unicast packet");
1518: AQ_EVCNT_ATTACH_MISC(sc, bptc, "TX broadcast packet");
1519: AQ_EVCNT_ATTACH_MISC(sc, mptc, "TX multicast packet");
1520: AQ_EVCNT_ATTACH_MISC(sc, erpt, "TX error packet");
1521: AQ_EVCNT_ATTACH_MISC(sc, ubtc, "TX unicast bytes");
1522: AQ_EVCNT_ATTACH_MISC(sc, bbtc, "TX broadcast bytes");
1523: AQ_EVCNT_ATTACH_MISC(sc, mbtc, "TX multicast bytes");
1524: AQ_EVCNT_ATTACH_MISC(sc, ptc, "TX good packet");
1525: AQ_EVCNT_ATTACH_MISC(sc, dpc, "DMA drop packet");
1526: AQ_EVCNT_ATTACH_MISC(sc, cprc, "RX coalesced packet");
1527: #endif
1528:
1529: return;
1530:
1531: attach_failure:
1532: aq_detach(self, 0);
1533: }
1534:
1535: static int
1536: aq_detach(device_t self, int flags __unused)
1537: {
1538: struct aq_softc *sc = device_private(self);
1539: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1540: int i, s;
1541:
1542: if (sc->sc_iosize != 0) {
1543: if (ifp->if_softc != NULL) {
1544: s = splnet();
1545: aq_stop(ifp, 0);
1546: splx(s);
1547: }
1548:
1549: for (i = 0; i < AQ_NINTR_MAX; i++) {
1550: if (sc->sc_ihs[i] != NULL) {
1551: pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
1552: sc->sc_ihs[i] = NULL;
1553: }
1554: }
1555: if (sc->sc_nintrs > 0) {
1556: pci_intr_release(sc->sc_pc, sc->sc_intrs,
1557: sc->sc_nintrs);
1558: sc->sc_intrs = NULL;
1559: sc->sc_nintrs = 0;
1560: }
1561:
1562: aq_txrx_rings_free(sc);
1563:
1564: if (ifp->if_softc != NULL) {
1565: ether_ifdetach(ifp);
1566: if_detach(ifp);
1567: }
1568:
1569: aprint_debug_dev(sc->sc_dev, "%s: bus_space_unmap\n", __func__);
1570: bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize);
1571: sc->sc_iosize = 0;
1572: }
1573:
1574: callout_stop(&sc->sc_tick_ch);
1575:
1.4 ryo 1576: #if NSYSMON_ENVSYS > 0
1577: if (sc->sc_sme != NULL) {
1578: /* all sensors associated with this will also be detached */
1579: sysmon_envsys_unregister(sc->sc_sme);
1580: sc->sc_sme = NULL;
1581: }
1582: #endif
1583:
1.1 ryo 1584: #ifdef AQ_EVENT_COUNTERS
1585: AQ_EVCNT_DETACH(sc, uprc);
1586: AQ_EVCNT_DETACH(sc, mprc);
1587: AQ_EVCNT_DETACH(sc, bprc);
1588: AQ_EVCNT_DETACH(sc, erpt);
1589: AQ_EVCNT_DETACH(sc, uptc);
1590: AQ_EVCNT_DETACH(sc, mptc);
1591: AQ_EVCNT_DETACH(sc, bptc);
1592: AQ_EVCNT_DETACH(sc, erpr);
1593: AQ_EVCNT_DETACH(sc, mbtc);
1594: AQ_EVCNT_DETACH(sc, bbtc);
1595: AQ_EVCNT_DETACH(sc, mbrc);
1596: AQ_EVCNT_DETACH(sc, bbrc);
1597: AQ_EVCNT_DETACH(sc, ubrc);
1598: AQ_EVCNT_DETACH(sc, ubtc);
1599: AQ_EVCNT_DETACH(sc, ptc);
1600: AQ_EVCNT_DETACH(sc, prc);
1601: AQ_EVCNT_DETACH(sc, dpc);
1602: AQ_EVCNT_DETACH(sc, cprc);
1603: #endif
1604:
1.7 thorpej 1605: ifmedia_fini(&sc->sc_media);
1606:
1.4 ryo 1607: mutex_destroy(&sc->sc_mpi_mutex);
1.1 ryo 1608: mutex_destroy(&sc->sc_mutex);
1609:
1610: return 0;
1611: }
1612:
1613: static int
1614: aq_establish_intr(struct aq_softc *sc, int intno, kcpuset_t *affinity,
1615: int (*func)(void *), void *arg, const char *xname)
1616: {
1617: char intrbuf[PCI_INTRSTR_LEN];
1618: pci_chipset_tag_t pc = sc->sc_pc;
1619: void *vih;
1620: const char *intrstr = NULL;
1621:
1622: intrstr = pci_intr_string(pc, sc->sc_intrs[intno], intrbuf,
1623: sizeof(intrbuf));
1624:
1625: pci_intr_setattr(pc, &sc->sc_intrs[intno], PCI_INTR_MPSAFE, true);
1626:
1627: vih = pci_intr_establish_xname(pc, sc->sc_intrs[intno],
1628: IPL_NET, func, arg, xname);
1629: if (vih == NULL) {
1630: aprint_error_dev(sc->sc_dev,
1631: "unable to establish MSI-X%s%s for %s\n",
1632: intrstr ? " at " : "",
1633: intrstr ? intrstr : "", xname);
1634: return EIO;
1635: }
1636: sc->sc_ihs[intno] = vih;
1637:
1638: if (affinity != NULL) {
1639: /* Round-robin affinity */
1640: kcpuset_zero(affinity);
1641: kcpuset_set(affinity, intno % ncpu);
1642: interrupt_distribute(vih, affinity, NULL);
1643: }
1644:
1645: return 0;
1646: }
1647:
1648: static int
1649: aq_establish_msix_intr(struct aq_softc *sc, bool txrx_independent,
1650: bool linkintr)
1651: {
1652: kcpuset_t *affinity;
1653: int error, intno, i;
1654: char intr_xname[INTRDEVNAMEBUF];
1655:
1656: kcpuset_create(&affinity, false);
1657:
1658: intno = 0;
1659:
1660: if (txrx_independent) {
1661: for (i = 0; i < sc->sc_nqueues; i++) {
1662: snprintf(intr_xname, sizeof(intr_xname), "%s RX%d",
1663: device_xname(sc->sc_dev), i);
1664: sc->sc_rx_irq[i] = intno;
1665: error = aq_establish_intr(sc, intno++, affinity,
1666: aq_rx_intr, &sc->sc_queue[i].rxring, intr_xname);
1667: if (error != 0)
1668: goto fail;
1669: }
1670: for (i = 0; i < sc->sc_nqueues; i++) {
1671: snprintf(intr_xname, sizeof(intr_xname), "%s TX%d",
1672: device_xname(sc->sc_dev), i);
1673: sc->sc_tx_irq[i] = intno;
1674: error = aq_establish_intr(sc, intno++, affinity,
1675: aq_tx_intr, &sc->sc_queue[i].txring, intr_xname);
1676: if (error != 0)
1677: goto fail;
1678: }
1679: } else {
1680: for (i = 0; i < sc->sc_nqueues; i++) {
1681: snprintf(intr_xname, sizeof(intr_xname), "%s TXRX%d",
1682: device_xname(sc->sc_dev), i);
1683: sc->sc_rx_irq[i] = intno;
1684: sc->sc_tx_irq[i] = intno;
1685: error = aq_establish_intr(sc, intno++, affinity,
1686: aq_txrx_intr, &sc->sc_queue[i], intr_xname);
1687: if (error != 0)
1688: goto fail;
1689: }
1690: }
1691:
1692: if (linkintr) {
1693: snprintf(intr_xname, sizeof(intr_xname), "%s LINK",
1694: device_xname(sc->sc_dev));
1695: sc->sc_linkstat_irq = intno;
1696: error = aq_establish_intr(sc, intno++, affinity,
1697: aq_link_intr, sc, intr_xname);
1698: if (error != 0)
1699: goto fail;
1700: }
1701:
1702: kcpuset_destroy(affinity);
1703: return 0;
1704:
1705: fail:
1706: for (i = 0; i < AQ_NINTR_MAX; i++) {
1707: if (sc->sc_ihs[i] != NULL) {
1708: pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
1709: sc->sc_ihs[i] = NULL;
1710: }
1711: }
1712:
1713: kcpuset_destroy(affinity);
1714: return ENOMEM;
1715: }
1716:
1717: static int
1718: aq_setup_msix(struct aq_softc *sc, struct pci_attach_args *pa, int nqueue,
1719: bool txrx_independent, bool linkintr)
1720: {
1721: int error, nintr;
1722:
1723: if (txrx_independent)
1724: nintr = nqueue * 2;
1725: else
1726: nintr = nqueue;
1727:
1728: if (linkintr)
1729: nintr++;
1730:
1731: error = pci_msix_alloc_exact(pa, &sc->sc_intrs, nintr);
1732: if (error != 0) {
1733: aprint_error_dev(sc->sc_dev,
1734: "failed to allocate MSI-X interrupts\n");
1735: goto fail;
1736: }
1737:
1738: error = aq_establish_msix_intr(sc, txrx_independent, linkintr);
1739: if (error == 0) {
1740: sc->sc_nintrs = nintr;
1741: } else {
1742: pci_intr_release(sc->sc_pc, sc->sc_intrs, nintr);
1743: sc->sc_nintrs = 0;
1744: }
1745: fail:
1746: return error;
1747:
1748: }
1749:
1750: static int
1751: aq_setup_legacy(struct aq_softc *sc, struct pci_attach_args *pa,
1752: pci_intr_type_t inttype)
1753: {
1754: int counts[PCI_INTR_TYPE_SIZE];
1755: int error, nintr;
1756:
1757: nintr = 1;
1758:
1759: memset(counts, 0, sizeof(counts));
1760: counts[inttype] = nintr;
1761:
1762: error = pci_intr_alloc(pa, &sc->sc_intrs, counts, inttype);
1763: if (error != 0) {
1764: aprint_error_dev(sc->sc_dev,
1765: "failed to allocate%s interrupts\n",
1766: (inttype == PCI_INTR_TYPE_MSI) ? " MSI" : "");
1767: return error;
1768: }
1769: error = aq_establish_intr(sc, 0, NULL, aq_legacy_intr, sc,
1770: device_xname(sc->sc_dev));
1771: if (error == 0) {
1772: sc->sc_nintrs = nintr;
1773: } else {
1774: pci_intr_release(sc->sc_pc, sc->sc_intrs, nintr);
1775: sc->sc_nintrs = 0;
1776: }
1777: return error;
1778: }
1779:
1780: static void
1781: global_software_reset(struct aq_softc *sc)
1782: {
1783: uint32_t v;
1784:
1785: AQ_WRITE_REG_BIT(sc, RX_SYSCONTROL_REG, RX_SYSCONTROL_RESET_DIS, 0);
1786: AQ_WRITE_REG_BIT(sc, TX_SYSCONTROL_REG, TX_SYSCONTROL_RESET_DIS, 0);
1787: AQ_WRITE_REG_BIT(sc, FW_MPI_RESETCTRL_REG,
1788: FW_MPI_RESETCTRL_RESET_DIS, 0);
1789:
1790: v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG);
1791: v &= ~AQ_FW_SOFTRESET_DIS;
1792: v |= AQ_FW_SOFTRESET_RESET;
1793: AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v);
1794: }
1795:
1796: static int
1797: mac_soft_reset_rbl(struct aq_softc *sc, aq_fw_bootloader_mode_t *mode)
1798: {
1799: int timo;
1800:
1801: aprint_debug_dev(sc->sc_dev, "RBL> MAC reset STARTED!\n");
1802:
1803: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1);
1804: AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1);
1805: AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0);
1806:
1807: /* MAC FW will reload PHY FW if 1E.1000.3 was cleaned - #undone */
1808: AQ_WRITE_REG(sc, FW_BOOT_EXIT_CODE_REG, RBL_STATUS_DEAD);
1809:
1810: global_software_reset(sc);
1811:
1812: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e0);
1813:
1814: /* Wait for RBL to finish boot process. */
1815: #define RBL_TIMEOUT_MS 10000
1816: uint16_t rbl_status;
1817: for (timo = RBL_TIMEOUT_MS; timo > 0; timo--) {
1818: rbl_status = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG) & 0xffff;
1819: if (rbl_status != 0 && rbl_status != RBL_STATUS_DEAD)
1820: break;
1821: msec_delay(1);
1822: }
1823: if (timo <= 0) {
1824: aprint_error_dev(sc->sc_dev,
1825: "RBL> RBL restart failed: timeout\n");
1826: return EBUSY;
1827: }
1828: switch (rbl_status) {
1829: case RBL_STATUS_SUCCESS:
1830: if (mode != NULL)
1831: *mode = FW_BOOT_MODE_RBL_FLASH;
1832: aprint_debug_dev(sc->sc_dev, "RBL> reset complete! [Flash]\n");
1833: break;
1834: case RBL_STATUS_HOST_BOOT:
1835: if (mode != NULL)
1836: *mode = FW_BOOT_MODE_RBL_HOST_BOOTLOAD;
1837: aprint_debug_dev(sc->sc_dev,
1838: "RBL> reset complete! [Host Bootload]\n");
1839: break;
1840: case RBL_STATUS_FAILURE:
1841: default:
1842: aprint_error_dev(sc->sc_dev,
1843: "unknown RBL status 0x%x\n", rbl_status);
1844: return EBUSY;
1845: }
1846:
1847: return 0;
1848: }
1849:
1850: static int
1851: mac_soft_reset_flb(struct aq_softc *sc)
1852: {
1853: uint32_t v;
1854: int timo;
1855:
1856: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1);
1857: /*
1858: * Let Felicity hardware to complete SMBUS transaction before
1859: * Global software reset.
1860: */
1861: msec_delay(50);
1862:
1863: /*
1864: * If SPI burst transaction was interrupted(before running the script),
1865: * global software reset may not clear SPI interface.
1866: * Clean it up manually before global reset.
1867: */
1868: AQ_WRITE_REG(sc, AQ_GLB_NVR_PROVISIONING2_REG, 0x00a0);
1869: AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x009f);
1870: AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x809f);
1871: msec_delay(50);
1872:
1873: v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG);
1874: v &= ~AQ_FW_SOFTRESET_DIS;
1875: v |= AQ_FW_SOFTRESET_RESET;
1876: AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v);
1877:
1878: /* Kickstart. */
1879: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0);
1880: AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0);
1881: if (!sc->sc_fast_start_enabled)
1882: AQ_WRITE_REG(sc, AQ_GLB_GENERAL_PROVISIONING9_REG, 1);
1883:
1884: /*
1885: * For the case SPI burst transaction was interrupted (by MCP reset
1886: * above), wait until it is completed by hardware.
1887: */
1888: msec_delay(50);
1889:
1890: /* MAC Kickstart */
1891: if (!sc->sc_fast_start_enabled) {
1892: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x180e0);
1893:
1894: uint32_t flb_status;
1895: for (timo = 0; timo < 1000; timo++) {
1896: flb_status = AQ_READ_REG(sc,
1897: FW_MPI_DAISY_CHAIN_STATUS_REG) & 0x10;
1898: if (flb_status != 0)
1899: break;
1900: msec_delay(1);
1901: }
1902: if (flb_status == 0) {
1903: aprint_error_dev(sc->sc_dev,
1904: "FLB> MAC kickstart failed: timed out\n");
1905: return ETIMEDOUT;
1906: }
1907: aprint_debug_dev(sc->sc_dev,
1908: "FLB> MAC kickstart done, %d ms\n", timo);
1909: /* FW reset */
1910: AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0);
1911: /*
1912: * Let Felicity hardware complete SMBUS transaction before
1913: * Global software reset.
1914: */
1915: msec_delay(50);
1916: sc->sc_fast_start_enabled = true;
1917: }
1918: AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1);
1919:
1920: /* PHY Kickstart: #undone */
1921: global_software_reset(sc);
1922:
1923: for (timo = 0; timo < 1000; timo++) {
1924: if (AQ_READ_REG(sc, AQ_FW_VERSION_REG) != 0)
1925: break;
1926: msec_delay(10);
1927: }
1928: if (timo >= 1000) {
1929: aprint_error_dev(sc->sc_dev, "FLB> Global Soft Reset failed\n");
1930: return ETIMEDOUT;
1931: }
1932: aprint_debug_dev(sc->sc_dev, "FLB> F/W restart: %d ms\n", timo * 10);
1933: return 0;
1934:
1935: }
1936:
1937: static int
1938: mac_soft_reset(struct aq_softc *sc, aq_fw_bootloader_mode_t *mode)
1939: {
1940: if (sc->sc_rbl_enabled)
1941: return mac_soft_reset_rbl(sc, mode);
1942:
1943: if (mode != NULL)
1944: *mode = FW_BOOT_MODE_FLB;
1945: return mac_soft_reset_flb(sc);
1946: }
1947:
1948: static int
1949: aq_fw_read_version(struct aq_softc *sc)
1950: {
1951: int i, error = EBUSY;
1952: #define MAC_FW_START_TIMEOUT_MS 10000
1953: for (i = 0; i < MAC_FW_START_TIMEOUT_MS; i++) {
1954: sc->sc_fw_version = AQ_READ_REG(sc, AQ_FW_VERSION_REG);
1955: if (sc->sc_fw_version != 0) {
1956: error = 0;
1957: break;
1958: }
1959: delay(1000);
1960: }
1961: return error;
1962: }
1963:
1964: static int
1965: aq_fw_reset(struct aq_softc *sc)
1966: {
1967: uint32_t ver, v, bootExitCode;
1968: int i, error;
1969:
1970: ver = AQ_READ_REG(sc, AQ_FW_VERSION_REG);
1971:
1972: for (i = 1000; i > 0; i--) {
1973: v = AQ_READ_REG(sc, FW_MPI_DAISY_CHAIN_STATUS_REG);
1974: bootExitCode = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG);
1975: if (v != 0x06000000 || bootExitCode != 0)
1976: break;
1977: }
1978: if (i <= 0) {
1979: aprint_error_dev(sc->sc_dev,
1980: "F/W reset failed. Neither RBL nor FLB started\n");
1981: return ETIMEDOUT;
1982: }
1983: sc->sc_rbl_enabled = (bootExitCode != 0);
1984:
1985: /*
1986: * Having FW version 0 is an indicator that cold start
1987: * is in progress. This means two things:
1988: * 1) Driver have to wait for FW/HW to finish boot (500ms giveup)
1989: * 2) Driver may skip reset sequence and save time.
1990: */
1991: if (sc->sc_fast_start_enabled && (ver != 0)) {
1992: error = aq_fw_read_version(sc);
1993: /* Skip reset as it just completed */
1994: if (error == 0)
1995: return 0;
1996: }
1997:
1998: aq_fw_bootloader_mode_t mode = FW_BOOT_MODE_UNKNOWN;
1999: error = mac_soft_reset(sc, &mode);
2000: if (error != 0) {
2001: aprint_error_dev(sc->sc_dev, "MAC reset failed: %d\n", error);
2002: return error;
2003: }
2004:
2005: switch (mode) {
2006: case FW_BOOT_MODE_FLB:
2007: aprint_debug_dev(sc->sc_dev,
2008: "FLB> F/W successfully loaded from flash.\n");
2009: sc->sc_flash_present = true;
2010: return aq_fw_read_version(sc);
2011: case FW_BOOT_MODE_RBL_FLASH:
2012: aprint_debug_dev(sc->sc_dev,
2013: "RBL> F/W loaded from flash. Host Bootload disabled.\n");
2014: sc->sc_flash_present = true;
2015: return aq_fw_read_version(sc);
2016: case FW_BOOT_MODE_UNKNOWN:
2017: aprint_error_dev(sc->sc_dev,
2018: "F/W bootload error: unknown bootloader type\n");
2019: return ENOTSUP;
2020: case FW_BOOT_MODE_RBL_HOST_BOOTLOAD:
2021: aprint_debug_dev(sc->sc_dev, "RBL> Host Bootload mode\n");
2022: break;
2023: }
2024:
2025: /*
2026: * XXX: TODO: add support Host Boot
2027: */
2028: aprint_error_dev(sc->sc_dev,
2029: "RBL> F/W Host Bootload not implemented\n");
2030: return ENOTSUP;
2031: }
2032:
2033: static int
2034: aq_hw_reset(struct aq_softc *sc)
2035: {
2036: int error;
2037:
2038: /* disable irq */
2039: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS, 0);
2040:
2041: /* apply */
2042: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_IRQ, 1);
2043:
2044: /* wait ack 10 times by 1ms */
2045: WAIT_FOR(
2046: (AQ_READ_REG(sc, AQ_INTR_CTRL_REG) & AQ_INTR_CTRL_RESET_IRQ) == 0,
2047: 1000, 10, &error);
2048: if (error != 0) {
2049: aprint_error_dev(sc->sc_dev,
2050: "atlantic: IRQ reset failed: %d\n", error);
2051: return error;
2052: }
2053:
2054: return sc->sc_fw_ops->reset(sc);
2055: }
2056:
2057: static int
2058: aq_hw_init_ucp(struct aq_softc *sc)
2059: {
2060: int timo;
2061:
2062: if (FW_VERSION_MAJOR(sc) == 1) {
2063: if (AQ_READ_REG(sc, FW1X_MPI_INIT2_REG) == 0) {
2064: uint32_t data;
2065: cprng_fast(&data, sizeof(data));
2066: data &= 0xfefefefe;
2067: data |= 0x02020202;
2068: AQ_WRITE_REG(sc, FW1X_MPI_INIT2_REG, data);
2069: }
2070: AQ_WRITE_REG(sc, FW1X_MPI_INIT1_REG, 0);
2071: }
2072:
2073: for (timo = 100; timo > 0; timo--) {
2074: sc->sc_mbox_addr = AQ_READ_REG(sc, FW_MPI_MBOX_ADDR_REG);
2075: if (sc->sc_mbox_addr != 0)
2076: break;
2077: delay(1000);
2078: }
2079:
2080: #define AQ_FW_MIN_VERSION 0x01050006
2081: #define AQ_FW_MIN_VERSION_STR "1.5.6"
2082: if (sc->sc_fw_version < AQ_FW_MIN_VERSION) {
2083: aprint_error_dev(sc->sc_dev,
2084: "atlantic: wrong FW version: " AQ_FW_MIN_VERSION_STR
2085: " or later required, this is %d.%d.%d\n",
2086: FW_VERSION_MAJOR(sc),
2087: FW_VERSION_MINOR(sc),
2088: FW_VERSION_BUILD(sc));
2089: return ENOTSUP;
2090: }
2091:
2092: return 0;
2093: }
2094:
2095: static int
2096: aq_fw_version_init(struct aq_softc *sc)
2097: {
2098: int error = 0;
2099: char fw_vers[sizeof("F/W version xxxxx.xxxxx.xxxxx")];
2100:
2101: if (FW_VERSION_MAJOR(sc) == 1) {
2102: sc->sc_fw_ops = &aq_fw1x_ops;
2103: } else if ((FW_VERSION_MAJOR(sc) == 2) || (FW_VERSION_MAJOR(sc) == 3)) {
2104: sc->sc_fw_ops = &aq_fw2x_ops;
2105: } else {
2106: aprint_error_dev(sc->sc_dev,
2107: "Unsupported F/W version %d.%d.%d\n",
2108: FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc),
2109: FW_VERSION_BUILD(sc));
2110: return ENOTSUP;
2111: }
2112: snprintf(fw_vers, sizeof(fw_vers), "F/W version %d.%d.%d",
2113: FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc), FW_VERSION_BUILD(sc));
2114:
2115: /* detect revision */
2116: uint32_t hwrev = AQ_READ_REG(sc, AQ_HW_REVISION_REG);
2117: switch (hwrev & 0x0000000f) {
2118: case 0x01:
2119: aprint_normal_dev(sc->sc_dev, "Atlantic revision A0, %s\n",
2120: fw_vers);
2121: sc->sc_features |= FEATURES_REV_A0 |
2122: FEATURES_MPI_AQ | FEATURES_MIPS;
2123: break;
2124: case 0x02:
2125: aprint_normal_dev(sc->sc_dev, "Atlantic revision B0, %s\n",
2126: fw_vers);
2127: sc->sc_features |= FEATURES_REV_B0 |
2128: FEATURES_MPI_AQ | FEATURES_MIPS |
2129: FEATURES_TPO2 | FEATURES_RPF2;
2130: break;
2131: case 0x0A:
2132: aprint_normal_dev(sc->sc_dev, "Atlantic revision B1, %s\n",
2133: fw_vers);
2134: sc->sc_features |= FEATURES_REV_B1 |
2135: FEATURES_MPI_AQ | FEATURES_MIPS |
2136: FEATURES_TPO2 | FEATURES_RPF2;
2137: break;
2138: default:
2139: aprint_error_dev(sc->sc_dev,
2140: "Unknown revision (0x%08x)\n", hwrev);
2141: error = ENOTSUP;
2142: break;
2143: }
2144: return error;
2145: }
2146:
2147: static int
2148: fw1x_reset(struct aq_softc *sc)
2149: {
2150: struct aq_mailbox_header mbox;
2151: const int retryCount = 1000;
2152: uint32_t tid0;
2153: int i;
2154:
2155: tid0 = ~0; /*< Initial value of MBOX transactionId. */
2156:
2157: for (i = 0; i < retryCount; ++i) {
2158: /*
2159: * Read the beginning of Statistics structure to capture
2160: * the Transaction ID.
2161: */
2162: aq_fw_downld_dwords(sc, sc->sc_mbox_addr,
2163: (uint32_t *)&mbox, sizeof(mbox) / sizeof(uint32_t));
2164:
2165: /* Successfully read the stats. */
2166: if (tid0 == ~0U) {
2167: /* We have read the initial value. */
2168: tid0 = mbox.transaction_id;
2169: continue;
2170: } else if (mbox.transaction_id != tid0) {
2171: /*
2172: * Compare transaction ID to initial value.
2173: * If it's different means f/w is alive.
2174: * We're done.
2175: */
2176: return 0;
2177: }
2178:
2179: /*
2180: * Transaction ID value haven't changed since last time.
2181: * Try reading the stats again.
2182: */
2183: delay(10);
2184: }
2185: aprint_error_dev(sc->sc_dev, "F/W 1.x reset finalize timeout\n");
2186: return EBUSY;
2187: }
2188:
2189: static int
2190: fw1x_set_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t mode,
2191: aq_link_speed_t speed, aq_link_fc_t fc, aq_link_eee_t eee)
2192: {
2193: uint32_t mpictrl = 0;
2194: uint32_t mpispeed = 0;
2195:
2196: if (speed & AQ_LINK_10G)
2197: mpispeed |= FW1X_CTRL_10G;
2198: if (speed & AQ_LINK_5G)
2199: mpispeed |= (FW1X_CTRL_5G | FW1X_CTRL_5GSR);
2200: if (speed & AQ_LINK_2G5)
2201: mpispeed |= FW1X_CTRL_2G5;
2202: if (speed & AQ_LINK_1G)
2203: mpispeed |= FW1X_CTRL_1G;
2204: if (speed & AQ_LINK_100M)
2205: mpispeed |= FW1X_CTRL_100M;
2206:
2207: mpictrl |= __SHIFTIN(mode, FW1X_MPI_STATE_MODE);
2208: mpictrl |= __SHIFTIN(mpispeed, FW1X_MPI_STATE_SPEED);
2209: AQ_WRITE_REG(sc, FW1X_MPI_CONTROL_REG, mpictrl);
2210: return 0;
2211: }
2212:
2213: static int
2214: fw1x_get_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t *modep,
2215: aq_link_speed_t *speedp, aq_link_fc_t *fcp, aq_link_eee_t *eeep)
2216: {
2217: uint32_t mpistate, mpi_speed;
2218: aq_link_speed_t speed = AQ_LINK_NONE;
2219:
2220: mpistate = AQ_READ_REG(sc, FW1X_MPI_STATE_REG);
2221:
2222: if (modep != NULL)
2223: *modep = __SHIFTOUT(mpistate, FW1X_MPI_STATE_MODE);
2224:
2225: mpi_speed = __SHIFTOUT(mpistate, FW1X_MPI_STATE_SPEED);
2226: if (mpi_speed & FW1X_CTRL_10G)
2227: speed = AQ_LINK_10G;
2228: else if (mpi_speed & (FW1X_CTRL_5G|FW1X_CTRL_5GSR))
2229: speed = AQ_LINK_5G;
2230: else if (mpi_speed & FW1X_CTRL_2G5)
2231: speed = AQ_LINK_2G5;
2232: else if (mpi_speed & FW1X_CTRL_1G)
2233: speed = AQ_LINK_1G;
2234: else if (mpi_speed & FW1X_CTRL_100M)
2235: speed = AQ_LINK_100M;
2236:
2237: if (speedp != NULL)
2238: *speedp = speed;
2239:
2240: if (fcp != NULL)
2241: *fcp = AQ_FC_NONE;
2242:
2243: if (eeep != NULL)
2244: *eeep = AQ_EEE_DISABLE;
2245:
2246: return 0;
2247: }
2248:
2249: static int
2250: fw1x_get_stats(struct aq_softc *sc, aq_hw_stats_s_t *stats)
2251: {
2252: int error;
2253:
2254: error = aq_fw_downld_dwords(sc,
2255: sc->sc_mbox_addr + offsetof(fw1x_mailbox_t, msm), (uint32_t *)stats,
2256: sizeof(aq_hw_stats_s_t) / sizeof(uint32_t));
2257: if (error < 0) {
2258: device_printf(sc->sc_dev,
2259: "fw1x> download statistics data FAILED, error %d", error);
2260: return error;
2261: }
2262:
2263: stats->dpc = AQ_READ_REG(sc, RX_DMA_DROP_PKT_CNT_REG);
2264: stats->cprc = AQ_READ_REG(sc, RX_DMA_COALESCED_PKT_CNT_REG);
2265: return 0;
2266: }
2267:
2268: static int
2269: fw2x_reset(struct aq_softc *sc)
2270: {
2271: fw2x_capabilities_t caps = { 0 };
2272: int error;
2273:
2274: error = aq_fw_downld_dwords(sc,
2275: sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, caps),
2276: (uint32_t *)&caps, sizeof caps / sizeof(uint32_t));
2277: if (error != 0) {
2278: aprint_error_dev(sc->sc_dev,
2279: "fw2x> can't get F/W capabilities mask, error %d\n",
2280: error);
2281: return error;
2282: }
2283: sc->sc_fw_caps = caps.caps_lo | ((uint64_t)caps.caps_hi << 32);
2284:
2285: char buf[256];
2286: snprintb(buf, sizeof(buf), FW2X_SNPRINTB, sc->sc_fw_caps);
2287: aprint_verbose_dev(sc->sc_dev, "fw2x> F/W capabilities=%s\n", buf);
2288:
2289: return 0;
2290: }
2291:
2292: static int
2293: fw2x_set_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t mode,
2294: aq_link_speed_t speed, aq_link_fc_t fc, aq_link_eee_t eee)
2295: {
1.4 ryo 2296: uint64_t mpi_ctrl;
2297: int error = 0;
2298:
2299: AQ_MPI_LOCK(sc);
2300:
2301: mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);
1.1 ryo 2302:
2303: switch (mode) {
2304: case MPI_INIT:
2305: mpi_ctrl &= ~FW2X_CTRL_RATE_MASK;
2306: if (speed & AQ_LINK_10G)
2307: mpi_ctrl |= FW2X_CTRL_RATE_10G;
2308: if (speed & AQ_LINK_5G)
2309: mpi_ctrl |= FW2X_CTRL_RATE_5G;
2310: if (speed & AQ_LINK_2G5)
2311: mpi_ctrl |= FW2X_CTRL_RATE_2G5;
2312: if (speed & AQ_LINK_1G)
2313: mpi_ctrl |= FW2X_CTRL_RATE_1G;
2314: if (speed & AQ_LINK_100M)
2315: mpi_ctrl |= FW2X_CTRL_RATE_100M;
2316:
2317: mpi_ctrl &= ~FW2X_CTRL_LINK_DROP;
2318:
2319: mpi_ctrl &= ~FW2X_CTRL_EEE_MASK;
2320: if (eee == AQ_EEE_ENABLE)
2321: mpi_ctrl |= FW2X_CTRL_EEE_MASK;
2322:
2323: mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE);
2324: if (fc & AQ_FC_RX)
2325: mpi_ctrl |= FW2X_CTRL_PAUSE;
2326: if (fc & AQ_FC_TX)
2327: mpi_ctrl |= FW2X_CTRL_ASYMMETRIC_PAUSE;
2328: break;
2329: case MPI_DEINIT:
2330: mpi_ctrl &= ~(FW2X_CTRL_RATE_MASK | FW2X_CTRL_EEE_MASK);
2331: mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE);
2332: break;
2333: default:
2334: device_printf(sc->sc_dev, "fw2x> unknown MPI state %d\n", mode);
1.4 ryo 2335: error = EINVAL;
2336: goto failure;
1.1 ryo 2337: }
1.4 ryo 2338: AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl);
1.1 ryo 2339:
1.4 ryo 2340: failure:
2341: AQ_MPI_UNLOCK(sc);
2342: return error;
1.1 ryo 2343: }
2344:
2345: static int
2346: fw2x_get_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t *modep,
2347: aq_link_speed_t *speedp, aq_link_fc_t *fcp, aq_link_eee_t *eeep)
2348: {
2349: uint64_t mpi_state = AQ_READ64_REG(sc, FW2X_MPI_STATE_REG);
2350:
2351: if (modep != NULL) {
2352: uint64_t mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);
2353: if (mpi_ctrl & FW2X_CTRL_RATE_MASK)
2354: *modep = MPI_INIT;
2355: else
2356: *modep = MPI_DEINIT;
2357: }
2358:
2359: aq_link_speed_t speed = AQ_LINK_NONE;
2360: if (mpi_state & FW2X_CTRL_RATE_10G)
2361: speed = AQ_LINK_10G;
2362: else if (mpi_state & FW2X_CTRL_RATE_5G)
2363: speed = AQ_LINK_5G;
2364: else if (mpi_state & FW2X_CTRL_RATE_2G5)
2365: speed = AQ_LINK_2G5;
2366: else if (mpi_state & FW2X_CTRL_RATE_1G)
2367: speed = AQ_LINK_1G;
2368: else if (mpi_state & FW2X_CTRL_RATE_100M)
2369: speed = AQ_LINK_100M;
2370:
2371: if (speedp != NULL)
2372: *speedp = speed;
2373:
2374: aq_link_fc_t fc = AQ_FC_NONE;
2375: if (mpi_state & FW2X_CTRL_PAUSE)
2376: fc |= AQ_FC_RX;
2377: if (mpi_state & FW2X_CTRL_ASYMMETRIC_PAUSE)
2378: fc |= AQ_FC_TX;
2379: if (fcp != NULL)
2380: *fcp = fc;
2381:
2382: /* XXX: TODO: EEE */
2383: if (eeep != NULL)
2384: *eeep = AQ_EEE_DISABLE;
2385:
2386: return 0;
2387: }
2388:
2389: static int
2390: toggle_mpi_ctrl_and_wait(struct aq_softc *sc, uint64_t mask,
2391: uint32_t timeout_ms, uint32_t try_count)
2392: {
2393: uint64_t mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);
2394: uint64_t mpi_state = AQ_READ64_REG(sc, FW2X_MPI_STATE_REG);
2395: int error;
2396:
2397: /* First, check that control and state values are consistent */
2398: if ((mpi_ctrl & mask) != (mpi_state & mask)) {
2399: device_printf(sc->sc_dev,
2400: "fw2x> MPI control (%#llx) and state (%#llx)"
2401: " are not consistent for mask %#llx!\n",
2402: (unsigned long long)mpi_ctrl, (unsigned long long)mpi_state,
2403: (unsigned long long)mask);
2404: return EINVAL;
2405: }
2406:
2407: /* Invert bits (toggle) in control register */
2408: mpi_ctrl ^= mask;
2409: AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl);
2410:
2411: /* Clear all bits except masked */
2412: mpi_ctrl &= mask;
2413:
2414: /* Wait for FW reflecting change in state register */
2415: WAIT_FOR((AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG) & mask) == mpi_ctrl,
2416: 1000 * timeout_ms, try_count, &error);
2417: if (error != 0) {
2418: device_printf(sc->sc_dev,
2419: "f/w2x> timeout while waiting for response"
2420: " in state register for bit %#llx!",
2421: (unsigned long long)mask);
2422: return error;
2423: }
2424: return 0;
2425: }
2426:
2427: static int
2428: fw2x_get_stats(struct aq_softc *sc, aq_hw_stats_s_t *stats)
2429: {
2430: int error;
2431:
1.4 ryo 2432: AQ_MPI_LOCK(sc);
1.1 ryo 2433: /* Say to F/W to update the statistics */
2434: error = toggle_mpi_ctrl_and_wait(sc, FW2X_CTRL_STATISTICS, 1, 25);
2435: if (error != 0) {
2436: device_printf(sc->sc_dev,
2437: "fw2x> statistics update error %d\n", error);
1.4 ryo 2438: goto failure;
1.1 ryo 2439: }
2440:
2441: CTASSERT(sizeof(fw2x_msm_statistics_t) <= sizeof(struct aq_hw_stats_s));
2442: error = aq_fw_downld_dwords(sc,
2443: sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, msm), (uint32_t *)stats,
2444: sizeof(fw2x_msm_statistics_t) / sizeof(uint32_t));
2445: if (error != 0) {
2446: device_printf(sc->sc_dev,
2447: "fw2x> download statistics data FAILED, error %d", error);
1.4 ryo 2448: goto failure;
1.1 ryo 2449: }
2450: stats->dpc = AQ_READ_REG(sc, RX_DMA_DROP_PKT_CNT_REG);
2451: stats->cprc = AQ_READ_REG(sc, RX_DMA_COALESCED_PKT_CNT_REG);
2452:
1.4 ryo 2453: failure:
2454: AQ_MPI_UNLOCK(sc);
2455: return error;
2456: }
2457:
2458: #if NSYSMON_ENVSYS > 0
2459: static int
2460: fw2x_get_temperature(struct aq_softc *sc, uint32_t *temp)
2461: {
2462: int error;
2463: uint32_t value, celsius;
2464:
2465: AQ_MPI_LOCK(sc);
2466:
2467: /* Say to F/W to update the temperature */
2468: error = toggle_mpi_ctrl_and_wait(sc, FW2X_CTRL_TEMPERATURE, 1, 25);
2469: if (error != 0)
2470: goto failure;
2471:
2472: error = aq_fw_downld_dwords(sc,
2473: sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, phy_info2),
2474: &value, sizeof(value) / sizeof(uint32_t));
2475: if (error != 0)
2476: goto failure;
2477:
2478: /* 1/256 decrees C to microkelvin */
2479: celsius = __SHIFTOUT(value, PHYINFO2_TEMPERATURE);
2480: if (celsius == 0) {
2481: error = EIO;
2482: goto failure;
2483: }
2484: *temp = celsius * (1000000 / 256) + 273150000;
2485:
2486: failure:
2487: AQ_MPI_UNLOCK(sc);
1.1 ryo 2488: return 0;
2489: }
1.4 ryo 2490: #endif
1.1 ryo 2491:
2492: static int
2493: aq_fw_downld_dwords(struct aq_softc *sc, uint32_t addr, uint32_t *p,
2494: uint32_t cnt)
2495: {
2496: uint32_t v;
2497: int error = 0;
2498:
2499: WAIT_FOR(AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG) == 1, 1, 10000, &error);
2500: if (error != 0) {
2501: AQ_WRITE_REG(sc, AQ_FW_SEM_RAM_REG, 1);
2502: v = AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG);
2503: if (v == 0) {
2504: device_printf(sc->sc_dev,
2505: "%s:%d: timeout\n", __func__, __LINE__);
2506: return ETIMEDOUT;
2507: }
2508: }
2509:
2510: AQ_WRITE_REG(sc, AQ_FW_MBOX_ADDR_REG, addr);
2511:
2512: error = 0;
2513: for (; cnt > 0 && error == 0; cnt--) {
2514: /* execute mailbox interface */
2515: AQ_WRITE_REG_BIT(sc, AQ_FW_MBOX_CMD_REG,
2516: AQ_FW_MBOX_CMD_EXECUTE, 1);
2517: if (sc->sc_features & FEATURES_REV_B1) {
2518: WAIT_FOR(AQ_READ_REG(sc, AQ_FW_MBOX_ADDR_REG) != addr,
2519: 1, 1000, &error);
2520: } else {
2521: WAIT_FOR((AQ_READ_REG(sc, AQ_FW_MBOX_CMD_REG) &
2522: AQ_FW_MBOX_CMD_BUSY) == 0,
2523: 1, 1000, &error);
2524: }
2525: *p++ = AQ_READ_REG(sc, AQ_FW_MBOX_VAL_REG);
2526: addr += sizeof(uint32_t);
2527: }
2528: AQ_WRITE_REG(sc, AQ_FW_SEM_RAM_REG, 1);
2529:
2530: if (error != 0)
2531: device_printf(sc->sc_dev,
2532: "%s:%d: timeout\n", __func__, __LINE__);
2533:
2534: return error;
2535: }
2536:
2537: /* read my mac address */
2538: static int
2539: aq_get_mac_addr(struct aq_softc *sc)
2540: {
2541: uint32_t mac_addr[2];
2542: uint32_t efuse_shadow_addr;
2543: int err;
2544:
2545: efuse_shadow_addr = 0;
2546: if (FW_VERSION_MAJOR(sc) >= 2)
2547: efuse_shadow_addr = AQ_READ_REG(sc, FW2X_MPI_EFUSEADDR_REG);
2548: else
2549: efuse_shadow_addr = AQ_READ_REG(sc, FW1X_MPI_EFUSEADDR_REG);
2550:
2551: if (efuse_shadow_addr == 0) {
2552: aprint_error_dev(sc->sc_dev, "cannot get efuse addr\n");
2553: return ENXIO;
2554: }
2555:
2556: memset(mac_addr, 0, sizeof(mac_addr));
2557: err = aq_fw_downld_dwords(sc, efuse_shadow_addr + (40 * 4),
2558: mac_addr, __arraycount(mac_addr));
2559: if (err < 0)
2560: return err;
2561:
2562: if (mac_addr[0] == 0 && mac_addr[1] == 0) {
2563: aprint_error_dev(sc->sc_dev, "mac address not found\n");
2564: return ENXIO;
2565: }
2566:
2567: mac_addr[0] = bswap32(mac_addr[0]);
2568: mac_addr[1] = bswap32(mac_addr[1]);
2569:
2570: memcpy(sc->sc_enaddr.ether_addr_octet,
2571: (uint8_t *)mac_addr, ETHER_ADDR_LEN);
2572: aprint_normal_dev(sc->sc_dev, "Etheraddr: %s\n",
2573: ether_sprintf(sc->sc_enaddr.ether_addr_octet));
2574:
2575: return 0;
2576: }
2577:
2578: /* set multicast filter. index 0 for own address */
2579: static int
2580: aq_set_mac_addr(struct aq_softc *sc, int index, uint8_t *enaddr)
2581: {
2582: uint32_t h, l;
2583:
2584: if (index >= AQ_HW_MAC_NUM)
2585: return EINVAL;
2586:
2587: if (enaddr == NULL) {
2588: /* disable */
2589: AQ_WRITE_REG_BIT(sc,
2590: RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0);
2591: return 0;
2592: }
2593:
2594: h = (enaddr[0] << 8) | (enaddr[1]);
1.5 msaitoh 2595: l = ((uint32_t)enaddr[2] << 24) | (enaddr[3] << 16) |
1.1 ryo 2596: (enaddr[4] << 8) | (enaddr[5]);
2597:
2598: /* disable, set, and enable */
2599: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0);
2600: AQ_WRITE_REG(sc, RPF_L2UC_LSW_REG(index), l);
2601: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index),
2602: RPF_L2UC_MSW_MACADDR_HI, h);
2603: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_ACTION, 1);
2604: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 1);
2605:
2606: return 0;
2607: }
2608:
2609: static int
2610: aq_set_capability(struct aq_softc *sc)
2611: {
2612: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2613: int ip4csum_tx =
2614: ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) == 0) ? 0 : 1;
2615: int ip4csum_rx =
2616: ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) ? 0 : 1;
2617: int l4csum_tx = ((ifp->if_capenable &
2618: (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx |
2619: IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) == 0) ? 0 : 1;
2620: int l4csum_rx =
2621: ((ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
2622: IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) == 0) ? 0 : 1;
2623: uint32_t lso =
2624: ((ifp->if_capenable & (IFCAP_TSOv4 | IFCAP_TSOv6)) == 0) ?
2625: 0 : 0xffffffff;
2626: uint32_t lro = ((ifp->if_capenable & IFCAP_LRO) == 0) ?
2627: 0 : 0xffffffff;
2628: uint32_t i, v;
2629:
2630: /* TX checksums offloads*/
2631: AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_IP4CSUM_EN, ip4csum_tx);
2632: AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_L4CSUM_EN, l4csum_tx);
2633:
2634: /* RX checksums offloads*/
2635: AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_IP4CSUM_EN, ip4csum_rx);
2636: AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_L4CSUM_EN, l4csum_rx);
2637:
2638: /* LSO offloads*/
2639: AQ_WRITE_REG(sc, TDM_LSO_EN_REG, lso);
2640:
2641: #define AQ_B0_LRO_RXD_MAX 16
2642: v = (8 < AQ_B0_LRO_RXD_MAX) ? 3 :
2643: (4 < AQ_B0_LRO_RXD_MAX) ? 2 :
2644: (2 < AQ_B0_LRO_RXD_MAX) ? 1 : 0;
2645: for (i = 0; i < AQ_RINGS_NUM; i++) {
2646: AQ_WRITE_REG_BIT(sc, RPO_LRO_LDES_MAX_REG(i),
2647: RPO_LRO_LDES_MAX_MASK(i), v);
2648: }
2649:
2650: AQ_WRITE_REG_BIT(sc, RPO_LRO_TB_DIV_REG, RPO_LRO_TB_DIV, 0x61a);
2651: AQ_WRITE_REG_BIT(sc, RPO_LRO_INACTIVE_IVAL_REG,
2652: RPO_LRO_INACTIVE_IVAL, 0);
2653: /*
2654: * the LRO timebase divider is 5 uS (0x61a),
2655: * to get a maximum coalescing interval of 250 uS,
2656: * we need to multiply by 50(0x32) to get
2657: * the default value 250 uS
2658: */
2659: AQ_WRITE_REG_BIT(sc, RPO_LRO_MAX_COALESCING_IVAL_REG,
2660: RPO_LRO_MAX_COALESCING_IVAL, 50);
2661: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2662: RPO_LRO_CONF_QSESSION_LIMIT, 1);
2663: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2664: RPO_LRO_CONF_TOTAL_DESC_LIMIT, 2);
2665: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2666: RPO_LRO_CONF_PATCHOPTIMIZATION_EN, 0);
2667: AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG,
2668: RPO_LRO_CONF_MIN_PAYLOAD_OF_FIRST_PKT, 10);
2669: AQ_WRITE_REG(sc, RPO_LRO_RSC_MAX_REG, 1);
2670: AQ_WRITE_REG(sc, RPO_LRO_ENABLE_REG, lro);
2671:
2672: return 0;
2673: }
2674:
2675: static int
2676: aq_set_filter(struct aq_softc *sc)
2677: {
2678: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2679: struct ethercom *ec = &sc->sc_ethercom;
2680: struct ether_multi *enm;
2681: struct ether_multistep step;
2682: int idx, error = 0;
2683:
2684: if (ifp->if_flags & IFF_PROMISC) {
2685: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_PROMISC,
2686: (ifp->if_flags & IFF_PROMISC) ? 1 : 0);
2687: ec->ec_flags |= ETHER_F_ALLMULTI;
2688: goto done;
2689: }
2690:
2691: /* clear all table */
2692: for (idx = 0; idx < AQ_HW_MAC_NUM; idx++) {
2693: if (idx == AQ_HW_MAC_OWN) /* already used for own */
2694: continue;
2695: aq_set_mac_addr(sc, idx, NULL);
2696: }
2697:
2698: /* don't accept all multicast */
2699: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG,
2700: RPF_MCAST_FILTER_MASK_ALLMULTI, 0);
2701: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0),
2702: RPF_MCAST_FILTER_EN, 0);
2703:
2704: idx = 0;
2705: ETHER_LOCK(ec);
2706: ETHER_FIRST_MULTI(step, ec, enm);
2707: while (enm != NULL) {
2708: if (idx == AQ_HW_MAC_OWN)
2709: idx++;
2710:
2711: if ((idx >= AQ_HW_MAC_NUM) ||
2712: memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
2713: /*
2714: * too many filters.
2715: * fallback to accept all multicast addresses.
2716: */
2717: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG,
2718: RPF_MCAST_FILTER_MASK_ALLMULTI, 1);
2719: AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0),
2720: RPF_MCAST_FILTER_EN, 1);
2721: ec->ec_flags |= ETHER_F_ALLMULTI;
2722: ETHER_UNLOCK(ec);
2723: goto done;
2724: }
2725:
2726: /* add a filter */
2727: aq_set_mac_addr(sc, idx++, enm->enm_addrlo);
2728:
2729: ETHER_NEXT_MULTI(step, enm);
2730: }
2731: ec->ec_flags &= ~ETHER_F_ALLMULTI;
2732: ETHER_UNLOCK(ec);
2733:
2734: done:
2735: return error;
2736: }
2737:
2738: static int
2739: aq_ifmedia_change(struct ifnet * const ifp)
2740: {
2741: struct aq_softc *sc = ifp->if_softc;
2742: aq_link_speed_t rate = AQ_LINK_NONE;
2743: aq_link_fc_t fc = AQ_FC_NONE;
2744: aq_link_eee_t eee = AQ_EEE_DISABLE;
2745:
2746: if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER)
2747: return EINVAL;
2748:
2749: switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) {
2750: case IFM_AUTO:
2751: rate = AQ_LINK_AUTO;
2752: break;
2753: case IFM_NONE:
2754: rate = AQ_LINK_NONE;
2755: break;
2756: case IFM_100_TX:
2757: rate = AQ_LINK_100M;
2758: break;
2759: case IFM_1000_T:
2760: rate = AQ_LINK_1G;
2761: break;
2762: case IFM_2500_T:
2763: rate = AQ_LINK_2G5;
2764: break;
2765: case IFM_5000_T:
2766: rate = AQ_LINK_5G;
2767: break;
2768: case IFM_10G_T:
2769: rate = AQ_LINK_10G;
2770: break;
2771: default:
2772: device_printf(sc->sc_dev, "unknown media: 0x%X\n",
2773: IFM_SUBTYPE(sc->sc_media.ifm_media));
2774: return ENODEV;
2775: }
2776:
2777: if (sc->sc_media.ifm_media & IFM_FLOW)
2778: fc = AQ_FC_ALL;
2779:
2780: /* XXX: todo EEE */
2781:
2782: /* re-initialize hardware with new parameters */
2783: aq_set_linkmode(sc, rate, fc, eee);
2784:
2785: return 0;
2786: }
2787:
2788: static void
2789: aq_ifmedia_status(struct ifnet * const ifp, struct ifmediareq *ifmr)
2790: {
2791: struct aq_softc *sc = ifp->if_softc;
2792:
1.11 ryo 2793: /* update ifm_active */
1.1 ryo 2794: ifmr->ifm_active = IFM_ETHER;
1.11 ryo 2795: if (sc->sc_link_fc & AQ_FC_RX)
2796: ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2797: if (sc->sc_link_fc & AQ_FC_TX)
2798: ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2799:
2800: switch (sc->sc_link_rate) {
2801: case AQ_LINK_100M:
2802: /* XXX: need to detect fulldup or halfdup */
2803: ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
2804: break;
2805: case AQ_LINK_1G:
2806: ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
2807: break;
2808: case AQ_LINK_2G5:
2809: ifmr->ifm_active |= IFM_2500_T | IFM_FDX;
2810: break;
2811: case AQ_LINK_5G:
2812: ifmr->ifm_active |= IFM_5000_T | IFM_FDX;
2813: break;
2814: case AQ_LINK_10G:
2815: ifmr->ifm_active |= IFM_10G_T | IFM_FDX;
2816: break;
2817: default:
2818: ifmr->ifm_active |= IFM_NONE;
2819: break;
2820: }
2821:
2822: /* update ifm_status */
1.1 ryo 2823: ifmr->ifm_status = IFM_AVALID;
2824: if (sc->sc_link_rate != AQ_LINK_NONE)
2825: ifmr->ifm_status |= IFM_ACTIVE;
2826: }
2827:
2828: static void
2829: aq_initmedia(struct aq_softc *sc)
2830: {
2831: #define IFMEDIA_ETHER_ADD(sc, media) \
2832: ifmedia_add(&(sc)->sc_media, IFM_ETHER | media, 0, NULL);
2833:
2834: IFMEDIA_ETHER_ADD(sc, IFM_NONE);
2835: if (sc->sc_available_rates & AQ_LINK_100M) {
2836: IFMEDIA_ETHER_ADD(sc, IFM_100_TX);
2837: IFMEDIA_ETHER_ADD(sc, IFM_100_TX | IFM_FLOW);
2838: IFMEDIA_ETHER_ADD(sc, IFM_100_TX | IFM_FDX | IFM_FLOW);
2839: }
2840: if (sc->sc_available_rates & AQ_LINK_1G) {
2841: IFMEDIA_ETHER_ADD(sc, IFM_1000_T | IFM_FDX);
2842: IFMEDIA_ETHER_ADD(sc, IFM_1000_T | IFM_FDX | IFM_FLOW);
2843: }
2844: if (sc->sc_available_rates & AQ_LINK_2G5) {
2845: IFMEDIA_ETHER_ADD(sc, IFM_2500_T | IFM_FDX);
2846: IFMEDIA_ETHER_ADD(sc, IFM_2500_T | IFM_FDX | IFM_FLOW);
2847: }
2848: if (sc->sc_available_rates & AQ_LINK_5G) {
2849: IFMEDIA_ETHER_ADD(sc, IFM_5000_T | IFM_FDX);
2850: IFMEDIA_ETHER_ADD(sc, IFM_5000_T | IFM_FDX | IFM_FLOW);
2851: }
2852: if (sc->sc_available_rates & AQ_LINK_10G) {
2853: IFMEDIA_ETHER_ADD(sc, IFM_10G_T | IFM_FDX);
2854: IFMEDIA_ETHER_ADD(sc, IFM_10G_T | IFM_FDX | IFM_FLOW);
2855: }
2856: IFMEDIA_ETHER_ADD(sc, IFM_AUTO);
2857: IFMEDIA_ETHER_ADD(sc, IFM_AUTO | IFM_FLOW);
2858:
2859: /* default: auto without flowcontrol */
2860: ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO);
2861: aq_set_linkmode(sc, AQ_LINK_AUTO, AQ_FC_NONE, AQ_EEE_DISABLE);
2862: }
2863:
2864: static int
2865: aq_set_linkmode(struct aq_softc *sc, aq_link_speed_t speed, aq_link_fc_t fc,
2866: aq_link_eee_t eee)
2867: {
2868: return sc->sc_fw_ops->set_mode(sc, MPI_INIT, speed, fc, eee);
2869: }
2870:
2871: static int
2872: aq_get_linkmode(struct aq_softc *sc, aq_link_speed_t *speed, aq_link_fc_t *fc,
2873: aq_link_eee_t *eee)
2874: {
2875: aq_hw_fw_mpi_state_t mode;
2876: int error;
2877:
2878: error = sc->sc_fw_ops->get_mode(sc, &mode, speed, fc, eee);
2879: if (error != 0)
2880: return error;
2881: if (mode != MPI_INIT)
2882: return ENXIO;
2883:
2884: return 0;
2885: }
2886:
2887: static void
2888: aq_hw_init_tx_path(struct aq_softc *sc)
2889: {
2890: /* Tx TC/RSS number config */
2891: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_TC_MODE_EN, 1);
2892:
2893: AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG,
2894: THM_LSO_TCP_FLAG1_FIRST, 0x0ff6);
2895: AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG,
2896: THM_LSO_TCP_FLAG1_MID, 0x0ff6);
2897: AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG2_REG,
2898: THM_LSO_TCP_FLAG2_LAST, 0x0f7f);
2899:
2900: /* misc */
2901: AQ_WRITE_REG(sc, TX_TPO2_REG,
2902: (sc->sc_features & FEATURES_TPO2) ? TX_TPO2_EN : 0);
2903: AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_EN, 0);
2904: AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_MODE, 0);
2905:
2906: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_SCP_INS_EN, 1);
2907: }
2908:
2909: static void
2910: aq_hw_init_rx_path(struct aq_softc *sc)
2911: {
2912: int i;
2913:
2914: /* clear setting */
2915: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_TC_MODE, 0);
2916: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_FC_MODE, 0);
2917: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG, 0);
2918: for (i = 0; i < 32; i++) {
2919: AQ_WRITE_REG_BIT(sc, RPF_ETHERTYPE_FILTER_REG(i),
2920: RPF_ETHERTYPE_FILTER_EN, 0);
2921: }
2922:
2923: if (sc->sc_rss_enable) {
2924: /* Rx TC/RSS number config */
2925: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_TC_MODE, 1);
2926:
2927: /* Rx flow control */
2928: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_FC_MODE, 1);
2929:
2930: /* RSS Ring selection */
2931: switch (sc->sc_nqueues) {
2932: case 2:
2933: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG,
2934: RX_FLR_RSS_CONTROL1_EN | 0x11111111);
2935: break;
2936: case 4:
2937: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG,
2938: RX_FLR_RSS_CONTROL1_EN | 0x22222222);
2939: break;
2940: case 8:
2941: AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG,
2942: RX_FLR_RSS_CONTROL1_EN | 0x33333333);
2943: break;
2944: }
2945: }
2946:
2947: /* L2 and Multicast filters */
2948: for (i = 0; i < AQ_HW_MAC_NUM; i++) {
2949: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_EN, 0);
2950: AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_ACTION,
2951: RPF_ACTION_HOST);
2952: }
2953: AQ_WRITE_REG(sc, RPF_MCAST_FILTER_MASK_REG, 0);
2954: AQ_WRITE_REG(sc, RPF_MCAST_FILTER_REG(0), 0x00010fff);
2955:
2956: /* Vlan filters */
2957: AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_OUTER,
2958: ETHERTYPE_QINQ);
2959: AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_INNER,
2960: ETHERTYPE_VLAN);
1.10 ryo 2961: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, RPF_VLAN_MODE_PROMISC, 0);
1.1 ryo 2962:
2963: if (sc->sc_features & FEATURES_REV_B) {
2964: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG,
2965: RPF_VLAN_MODE_ACCEPT_UNTAGGED, 1);
2966: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG,
2967: RPF_VLAN_MODE_UNTAGGED_ACTION, RPF_ACTION_HOST);
2968: }
2969:
2970: /* misc */
2971: if (sc->sc_features & FEATURES_RPF2)
2972: AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG, RX_TCP_RSS_HASH_RPF2);
2973: else
2974: AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG, 0);
2975:
2976: /*
2977: * XXX: RX_TCP_RSS_HASH_REG:
2978: * linux set 0x000f0000
2979: * freebsd set 0x000f001e
2980: */
2981: /* RSS hash type set for IP/TCP */
2982: AQ_WRITE_REG_BIT(sc, RX_TCP_RSS_HASH_REG,
2983: RX_TCP_RSS_HASH_TYPE, 0x001e);
2984:
2985: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_EN, 1);
2986: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_ACTION, RPF_ACTION_HOST);
2987: AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_THRESHOLD, 0xffff);
2988:
2989: AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_EN, 0);
2990: AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_MODE, 0);
2991: }
2992:
2993: static void
2994: aq_hw_interrupt_moderation_set(struct aq_softc *sc)
2995: {
2996: int i;
2997:
2998: if (sc->sc_intr_moderation_enable) {
2999: unsigned int tx_min, rx_min; /* 0-255 */
3000: unsigned int tx_max, rx_max; /* 0-511? */
3001:
3002: switch (sc->sc_link_rate) {
3003: case AQ_LINK_100M:
3004: tx_min = 0x4f;
3005: tx_max = 0xff;
3006: rx_min = 0x04;
3007: rx_max = 0x50;
3008: break;
3009: case AQ_LINK_1G:
3010: default:
3011: tx_min = 0x4f;
3012: tx_max = 0xff;
3013: rx_min = 0x30;
3014: rx_max = 0x80;
3015: break;
3016: case AQ_LINK_2G5:
3017: tx_min = 0x4f;
3018: tx_max = 0xff;
3019: rx_min = 0x18;
3020: rx_max = 0xe0;
3021: break;
3022: case AQ_LINK_5G:
3023: tx_min = 0x4f;
3024: tx_max = 0xff;
3025: rx_min = 0x0c;
3026: rx_max = 0x70;
3027: break;
3028: case AQ_LINK_10G:
3029: tx_min = 0x4f;
3030: tx_max = 0x1ff;
3031: rx_min = 0x06; /* freebsd use 80 */
3032: rx_max = 0x38; /* freebsd use 120 */
3033: break;
3034: }
3035:
3036: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3037: TX_DMA_INT_DESC_WRWB_EN, 0);
3038: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3039: TX_DMA_INT_DESC_MODERATE_EN, 1);
3040: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3041: RX_DMA_INT_DESC_WRWB_EN, 0);
3042: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3043: RX_DMA_INT_DESC_MODERATE_EN, 1);
3044:
3045: for (i = 0; i < AQ_RINGS_NUM; i++) {
3046: AQ_WRITE_REG(sc, TX_INTR_MODERATION_CTL_REG(i),
3047: __SHIFTIN(tx_min, TX_INTR_MODERATION_CTL_MIN) |
3048: __SHIFTIN(tx_max, TX_INTR_MODERATION_CTL_MAX) |
3049: TX_INTR_MODERATION_CTL_EN);
3050: }
3051: for (i = 0; i < AQ_RINGS_NUM; i++) {
3052: AQ_WRITE_REG(sc, RX_INTR_MODERATION_CTL_REG(i),
3053: __SHIFTIN(rx_min, RX_INTR_MODERATION_CTL_MIN) |
3054: __SHIFTIN(rx_max, RX_INTR_MODERATION_CTL_MAX) |
3055: RX_INTR_MODERATION_CTL_EN);
3056: }
3057:
3058: } else {
3059: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3060: TX_DMA_INT_DESC_WRWB_EN, 1);
3061: AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,
3062: TX_DMA_INT_DESC_MODERATE_EN, 0);
3063: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3064: RX_DMA_INT_DESC_WRWB_EN, 1);
3065: AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,
3066: RX_DMA_INT_DESC_MODERATE_EN, 0);
3067:
3068: for (i = 0; i < AQ_RINGS_NUM; i++) {
3069: AQ_WRITE_REG(sc, TX_INTR_MODERATION_CTL_REG(i), 0);
3070: }
3071: for (i = 0; i < AQ_RINGS_NUM; i++) {
3072: AQ_WRITE_REG(sc, RX_INTR_MODERATION_CTL_REG(i), 0);
3073: }
3074: }
3075: }
3076:
3077: static void
3078: aq_hw_qos_set(struct aq_softc *sc)
3079: {
3080: uint32_t tc = 0;
3081: uint32_t buff_size;
3082:
3083: /* TPS Descriptor rate init */
3084: AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_TA_RST, 0);
3085: AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_LIM, 0xa);
3086:
3087: /* TPS VM init */
3088: AQ_WRITE_REG_BIT(sc, TPS_DESC_VM_ARB_MODE_REG, TPS_DESC_VM_ARB_MODE, 0);
3089:
3090: /* TPS TC credits init */
3091: AQ_WRITE_REG_BIT(sc, TPS_DESC_TC_ARB_MODE_REG, TPS_DESC_TC_ARB_MODE, 0);
3092: AQ_WRITE_REG_BIT(sc, TPS_DATA_TC_ARB_MODE_REG, TPS_DATA_TC_ARB_MODE, 0);
3093:
3094: AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc),
3095: TPS_DATA_TCT_CREDIT_MAX, 0xfff);
3096: AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc),
3097: TPS_DATA_TCT_WEIGHT, 0x64);
3098: AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc),
3099: TPS_DESC_TCT_CREDIT_MAX, 0x50);
3100: AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc),
3101: TPS_DESC_TCT_WEIGHT, 0x1e);
3102:
3103: /* Tx buf size */
3104: tc = 0;
3105: buff_size = AQ_HW_TXBUF_MAX;
3106: AQ_WRITE_REG_BIT(sc, TPB_TXB_BUFSIZE_REG(tc), TPB_TXB_BUFSIZE,
3107: buff_size);
3108: AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_HI,
3109: (buff_size * (1024 / 32) * 66) / 100);
3110: AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_LO,
3111: (buff_size * (1024 / 32) * 50) / 100);
3112:
3113: /* QoS Rx buf size per TC */
3114: tc = 0;
3115: buff_size = AQ_HW_RXBUF_MAX;
3116: AQ_WRITE_REG_BIT(sc, RPB_RXB_BUFSIZE_REG(tc), RPB_RXB_BUFSIZE,
3117: buff_size);
3118: AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_EN, 0);
3119: AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_THRESH_HI,
3120: (buff_size * (1024 / 32) * 66) / 100);
3121: AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_THRESH_LO,
3122: (buff_size * (1024 / 32) * 50) / 100);
3123:
3124: /* QoS 802.1p priority -> TC mapping */
3125: int i_priority;
3126: for (i_priority = 0; i_priority < 8; i_priority++) {
3127: AQ_WRITE_REG_BIT(sc, RPF_RPB_RX_TC_UPT_REG,
3128: RPF_RPB_RX_TC_UPT_MASK(i_priority), 0);
3129: }
3130: }
3131:
3132: /* called once from aq_attach */
3133: static int
3134: aq_init_rss(struct aq_softc *sc)
3135: {
3136: CTASSERT(AQ_RSS_HASHKEY_SIZE == RSS_KEYSIZE);
3137: uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
3138: uint8_t rss_table[AQ_RSS_INDIRECTION_TABLE_MAX];
3139: unsigned int i;
3140: int error;
3141:
3142: /* initialize rss key */
3143: rss_getkey((uint8_t *)rss_key);
3144:
3145: /* hash to ring table */
3146: for (i = 0; i < AQ_RSS_INDIRECTION_TABLE_MAX; i++) {
3147: rss_table[i] = i % sc->sc_nqueues;
3148: }
3149:
3150: /*
3151: * set rss key
3152: */
3153: for (i = 0; i < __arraycount(rss_key); i++) {
3154: uint32_t key_data = sc->sc_rss_enable ? ntohl(rss_key[i]) : 0;
3155: AQ_WRITE_REG(sc, RPF_RSS_KEY_WR_DATA_REG, key_data);
3156: AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG,
3157: RPF_RSS_KEY_ADDR, __arraycount(rss_key) - 1 - i);
3158: AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG,
3159: RPF_RSS_KEY_WR_EN, 1);
3160: WAIT_FOR(AQ_READ_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG,
3161: RPF_RSS_KEY_WR_EN) == 0, 1000, 10, &error);
3162: if (error != 0) {
3163: device_printf(sc->sc_dev, "%s: rss key write timeout\n",
3164: __func__);
3165: goto rss_set_timeout;
3166: }
3167: }
3168:
3169: /*
3170: * set rss indirection table
3171: *
3172: * AQ's rss redirect table is consist of 3bit*64 (192bit) packed array.
3173: * we'll make it by __BITMAP(3) macros.
3174: */
3175: __BITMAP_TYPE(, uint16_t, 3 * AQ_RSS_INDIRECTION_TABLE_MAX) bit3x64;
3176: __BITMAP_ZERO(&bit3x64);
3177:
3178: #define AQ_3BIT_PACKED_ARRAY_SET(bitmap, idx, val) \
3179: do { \
3180: if (val & 1) { \
3181: __BITMAP_SET((idx) * 3, (bitmap)); \
3182: } else { \
3183: __BITMAP_CLR((idx) * 3, (bitmap)); \
3184: } \
3185: if (val & 2) { \
3186: __BITMAP_SET((idx) * 3 + 1, (bitmap)); \
3187: } else { \
3188: __BITMAP_CLR((idx) * 3 + 1, (bitmap)); \
3189: } \
3190: if (val & 4) { \
3191: __BITMAP_SET((idx) * 3 + 2, (bitmap)); \
3192: } else { \
3193: __BITMAP_CLR((idx) * 3 + 2, (bitmap)); \
3194: } \
3195: } while (0 /* CONSTCOND */)
3196:
3197: for (i = 0; i < AQ_RSS_INDIRECTION_TABLE_MAX; i++) {
3198: AQ_3BIT_PACKED_ARRAY_SET(&bit3x64, i, rss_table[i]);
3199: }
3200:
3201: /* write 192bit data in steps of 16bit */
3202: for (i = 0; i < (int)__arraycount(bit3x64._b); i++) {
3203: AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_WR_DATA_REG,
3204: RPF_RSS_REDIR_WR_DATA, bit3x64._b[i]);
3205: AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG,
3206: RPF_RSS_REDIR_ADDR, i);
3207: AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG,
3208: RPF_RSS_REDIR_WR_EN, 1);
3209:
3210: WAIT_FOR(AQ_READ_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG,
3211: RPF_RSS_REDIR_WR_EN) == 0, 1000, 10, &error);
3212: if (error != 0)
3213: break;
3214: }
3215:
3216: rss_set_timeout:
3217: return error;
3218: }
3219:
3220: static void
3221: aq_hw_l3_filter_set(struct aq_softc *sc)
3222: {
3223: int i;
3224:
3225: /* clear all filter */
3226: for (i = 0; i < 8; i++) {
3227: AQ_WRITE_REG_BIT(sc, RPF_L3_FILTER_REG(i),
3228: RPF_L3_FILTER_L4_EN, 0);
3229: }
3230: }
3231:
3232: static void
1.10 ryo 3233: aq_set_vlan_filters(struct aq_softc *sc)
1.1 ryo 3234: {
1.10 ryo 3235: struct ethercom *ec = &sc->sc_ethercom;
3236: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
3237: struct vlanid_list *vlanidp;
1.1 ryo 3238: int i;
3239:
1.10 ryo 3240: ETHER_LOCK(ec);
3241:
3242: /* disable all vlan filters */
3243: for (i = 0; i < RPF_VLAN_MAX_FILTERS; i++)
3244: AQ_WRITE_REG(sc, RPF_VLAN_FILTER_REG(i), 0);
3245:
3246: /* count VID */
3247: i = 0;
3248: SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list)
3249: i++;
3250:
3251: if (((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_HWFILTER) == 0) ||
3252: (ifp->if_flags & IFF_PROMISC) ||
3253: (i > RPF_VLAN_MAX_FILTERS)) {
3254: /*
3255: * no vlan hwfilter, in promiscuous mode, or too many VID?
3256: * must receive all VID
3257: */
3258: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG,
3259: RPF_VLAN_MODE_PROMISC, 1);
3260: goto done;
3261: }
3262:
3263: /* receive only selected VID */
3264: AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, RPF_VLAN_MODE_PROMISC, 0);
3265: i = 0;
3266: SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) {
1.1 ryo 3267: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
1.10 ryo 3268: RPF_VLAN_FILTER_EN, 1);
1.1 ryo 3269: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3270: RPF_VLAN_FILTER_RXQ_EN, 0);
1.10 ryo 3271: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3272: RPF_VLAN_FILTER_RXQ, 0);
3273: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3274: RPF_VLAN_FILTER_ACTION, RPF_ACTION_HOST);
3275: AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i),
3276: RPF_VLAN_FILTER_ID, vlanidp->vid);
3277: i++;
1.1 ryo 3278: }
1.10 ryo 3279:
3280: done:
3281: ETHER_UNLOCK(ec);
1.1 ryo 3282: }
3283:
3284: static int
3285: aq_hw_init(struct aq_softc *sc)
3286: {
3287: uint32_t v;
3288:
3289: /* Force limit MRRS on RDM/TDM to 2K */
3290: v = AQ_READ_REG(sc, AQ_PCI_REG_CONTROL_6_REG);
3291: AQ_WRITE_REG(sc, AQ_PCI_REG_CONTROL_6_REG, (v & ~0x0707) | 0x0404);
3292:
3293: /*
3294: * TX DMA total request limit. B0 hardware is not capable to
3295: * handle more than (8K-MRRS) incoming DMA data.
3296: * Value 24 in 256byte units
3297: */
3298: AQ_WRITE_REG(sc, AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG, 24);
3299:
3300: aq_hw_init_tx_path(sc);
3301: aq_hw_init_rx_path(sc);
3302:
3303: aq_hw_interrupt_moderation_set(sc);
3304:
3305: aq_set_mac_addr(sc, AQ_HW_MAC_OWN, sc->sc_enaddr.ether_addr_octet);
3306: aq_set_linkmode(sc, AQ_LINK_NONE, AQ_FC_NONE, AQ_EEE_DISABLE);
3307:
3308: aq_hw_qos_set(sc);
3309:
3310: /* Enable interrupt */
3311: int irqmode;
3312: if (sc->sc_msix)
3313: irqmode = AQ_INTR_CTRL_IRQMODE_MSIX;
3314: else
3315: irqmode = AQ_INTR_CTRL_IRQMODE_MSI;
3316:
3317: AQ_WRITE_REG(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS);
3318: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_MULTIVEC,
3319: sc->sc_msix ? 1 : 0);
3320: AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_IRQMODE, irqmode);
3321:
3322: AQ_WRITE_REG(sc, AQ_INTR_AUTOMASK_REG, 0xffffffff);
3323:
3324: AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(0),
1.5 msaitoh 3325: ((AQ_B0_ERR_INT << 24) | (1U << 31)) |
1.1 ryo 3326: ((AQ_B0_ERR_INT << 16) | (1 << 23))
3327: );
3328:
3329: /* link interrupt */
3330: if (!sc->sc_msix)
3331: sc->sc_linkstat_irq = AQ_LINKSTAT_IRQ;
3332: AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(3),
3333: __BIT(7) | sc->sc_linkstat_irq);
3334:
3335: return 0;
3336: }
3337:
3338: static int
3339: aq_update_link_status(struct aq_softc *sc)
3340: {
3341: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
3342: aq_link_speed_t rate = AQ_LINK_NONE;
3343: aq_link_fc_t fc = AQ_FC_NONE;
3344: aq_link_eee_t eee = AQ_EEE_DISABLE;
3345: unsigned int speed;
3346: int changed = 0;
3347:
3348: aq_get_linkmode(sc, &rate, &fc, &eee);
3349:
3350: if (sc->sc_link_rate != rate)
3351: changed = 1;
3352: if (sc->sc_link_fc != fc)
3353: changed = 1;
3354: if (sc->sc_link_eee != eee)
3355: changed = 1;
3356:
3357: if (changed) {
3358: switch (rate) {
3359: case AQ_LINK_100M:
3360: speed = 100;
3361: break;
3362: case AQ_LINK_1G:
3363: speed = 1000;
3364: break;
3365: case AQ_LINK_2G5:
3366: speed = 2500;
3367: break;
3368: case AQ_LINK_5G:
3369: speed = 5000;
3370: break;
3371: case AQ_LINK_10G:
3372: speed = 10000;
3373: break;
3374: case AQ_LINK_NONE:
3375: default:
3376: speed = 0;
3377: break;
3378: }
3379:
3380: if (sc->sc_link_rate == AQ_LINK_NONE) {
3381: /* link DOWN -> UP */
3382: device_printf(sc->sc_dev, "link is UP: speed=%u\n",
3383: speed);
3384: if_link_state_change(ifp, LINK_STATE_UP);
3385: } else if (rate == AQ_LINK_NONE) {
3386: /* link UP -> DOWN */
3387: device_printf(sc->sc_dev, "link is DOWN\n");
3388: if_link_state_change(ifp, LINK_STATE_DOWN);
3389: } else {
3390: device_printf(sc->sc_dev,
3391: "link mode changed: speed=%u, fc=0x%x, eee=%x\n",
3392: speed, fc, eee);
3393: }
3394:
3395: sc->sc_link_rate = rate;
3396: sc->sc_link_fc = fc;
3397: sc->sc_link_eee = eee;
3398:
3399: /* update interrupt timing according to new link speed */
3400: aq_hw_interrupt_moderation_set(sc);
3401: }
3402:
3403: return changed;
3404: }
3405:
3406: #ifdef AQ_EVENT_COUNTERS
3407: static void
3408: aq_update_statistics(struct aq_softc *sc)
3409: {
3410: int prev = sc->sc_statistics_idx;
3411: int cur = prev ^ 1;
3412:
3413: sc->sc_fw_ops->get_stats(sc, &sc->sc_statistics[cur]);
3414:
3415: /*
3416: * aq's internal statistics counter is 32bit.
3417: * cauculate delta, and add to evcount
3418: */
3419: #define ADD_DELTA(cur, prev, name) \
3420: do { \
3421: uint32_t n; \
3422: n = (uint32_t)(sc->sc_statistics[cur].name - \
3423: sc->sc_statistics[prev].name); \
3424: if (n != 0) { \
3425: AQ_EVCNT_ADD(sc, name, n); \
3426: } \
3427: } while (/*CONSTCOND*/0);
3428:
3429: ADD_DELTA(cur, prev, uprc);
3430: ADD_DELTA(cur, prev, mprc);
3431: ADD_DELTA(cur, prev, bprc);
3432: ADD_DELTA(cur, prev, prc);
3433: ADD_DELTA(cur, prev, erpr);
3434: ADD_DELTA(cur, prev, uptc);
3435: ADD_DELTA(cur, prev, mptc);
3436: ADD_DELTA(cur, prev, bptc);
3437: ADD_DELTA(cur, prev, ptc);
3438: ADD_DELTA(cur, prev, erpt);
3439: ADD_DELTA(cur, prev, mbtc);
3440: ADD_DELTA(cur, prev, bbtc);
3441: ADD_DELTA(cur, prev, mbrc);
3442: ADD_DELTA(cur, prev, bbrc);
3443: ADD_DELTA(cur, prev, ubrc);
3444: ADD_DELTA(cur, prev, ubtc);
3445: ADD_DELTA(cur, prev, dpc);
3446: ADD_DELTA(cur, prev, cprc);
3447:
3448: sc->sc_statistics_idx = cur;
3449: }
3450: #endif /* AQ_EVENT_COUNTERS */
3451:
3452: /* allocate and map one DMA block */
3453: static int
3454: _alloc_dma(struct aq_softc *sc, bus_size_t size, bus_size_t *sizep,
3455: void **addrp, bus_dmamap_t *mapp, bus_dma_segment_t *seg)
3456: {
3457: int nsegs, error;
3458:
3459: if ((error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, seg,
3460: 1, &nsegs, 0)) != 0) {
3461: aprint_error_dev(sc->sc_dev,
3462: "unable to allocate DMA buffer, error=%d\n", error);
3463: goto fail_alloc;
3464: }
3465:
3466: if ((error = bus_dmamem_map(sc->sc_dmat, seg, 1, size, addrp,
3467: BUS_DMA_COHERENT)) != 0) {
3468: aprint_error_dev(sc->sc_dev,
3469: "unable to map DMA buffer, error=%d\n", error);
3470: goto fail_map;
3471: }
3472:
3473: if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
3474: 0, mapp)) != 0) {
3475: aprint_error_dev(sc->sc_dev,
3476: "unable to create DMA map, error=%d\n", error);
3477: goto fail_create;
3478: }
3479:
3480: if ((error = bus_dmamap_load(sc->sc_dmat, *mapp, *addrp, size, NULL,
3481: 0)) != 0) {
3482: aprint_error_dev(sc->sc_dev,
3483: "unable to load DMA map, error=%d\n", error);
3484: goto fail_load;
3485: }
3486:
3487: *sizep = size;
3488: return 0;
3489:
3490: fail_load:
3491: bus_dmamap_destroy(sc->sc_dmat, *mapp);
3492: *mapp = NULL;
3493: fail_create:
3494: bus_dmamem_unmap(sc->sc_dmat, *addrp, size);
3495: *addrp = NULL;
3496: fail_map:
3497: bus_dmamem_free(sc->sc_dmat, seg, 1);
3498: memset(seg, 0, sizeof(*seg));
3499: fail_alloc:
3500: *sizep = 0;
3501: return error;
3502: }
3503:
3504: static void
3505: _free_dma(struct aq_softc *sc, bus_size_t *sizep, void **addrp,
3506: bus_dmamap_t *mapp, bus_dma_segment_t *seg)
3507: {
3508: if (*mapp != NULL) {
3509: bus_dmamap_destroy(sc->sc_dmat, *mapp);
3510: *mapp = NULL;
3511: }
3512: if (*addrp != NULL) {
3513: bus_dmamem_unmap(sc->sc_dmat, *addrp, *sizep);
3514: *addrp = NULL;
3515: }
3516: if (*sizep != 0) {
3517: bus_dmamem_free(sc->sc_dmat, seg, 1);
3518: memset(seg, 0, sizeof(*seg));
3519: *sizep = 0;
3520: }
3521: }
3522:
3523: static int
3524: aq_txring_alloc(struct aq_softc *sc, struct aq_txring *txring)
3525: {
3526: int i, error;
3527:
3528: /* allocate tx descriptors */
3529: error = _alloc_dma(sc, sizeof(aq_tx_desc_t) * AQ_TXD_NUM,
3530: &txring->txr_txdesc_size, (void **)&txring->txr_txdesc,
3531: &txring->txr_txdesc_dmamap, txring->txr_txdesc_seg);
3532: if (error != 0)
3533: return error;
3534:
3535: memset(txring->txr_txdesc, 0, sizeof(aq_tx_desc_t) * AQ_TXD_NUM);
3536:
3537: /* fill tx ring with dmamap */
3538: for (i = 0; i < AQ_TXD_NUM; i++) {
3539: #define AQ_MAXDMASIZE (16 * 1024)
3540: #define AQ_NTXSEGS 32
3541: /* XXX: TODO: error check */
3542: bus_dmamap_create(sc->sc_dmat, AQ_MAXDMASIZE, AQ_NTXSEGS,
3543: AQ_MAXDMASIZE, 0, 0, &txring->txr_mbufs[i].dmamap);
3544: }
3545: return 0;
3546: }
3547:
3548: static void
3549: aq_txring_free(struct aq_softc *sc, struct aq_txring *txring)
3550: {
3551: int i;
3552:
3553: _free_dma(sc, &txring->txr_txdesc_size, (void **)&txring->txr_txdesc,
3554: &txring->txr_txdesc_dmamap, txring->txr_txdesc_seg);
3555:
3556: for (i = 0; i < AQ_TXD_NUM; i++) {
3557: if (txring->txr_mbufs[i].dmamap != NULL) {
3558: if (txring->txr_mbufs[i].m != NULL) {
3559: bus_dmamap_unload(sc->sc_dmat,
3560: txring->txr_mbufs[i].dmamap);
3561: m_freem(txring->txr_mbufs[i].m);
3562: txring->txr_mbufs[i].m = NULL;
3563: }
3564: bus_dmamap_destroy(sc->sc_dmat,
3565: txring->txr_mbufs[i].dmamap);
3566: txring->txr_mbufs[i].dmamap = NULL;
3567: }
3568: }
3569: }
3570:
3571: static int
3572: aq_rxring_alloc(struct aq_softc *sc, struct aq_rxring *rxring)
3573: {
3574: int i, error;
3575:
3576: /* allocate rx descriptors */
3577: error = _alloc_dma(sc, sizeof(aq_rx_desc_t) * AQ_RXD_NUM,
3578: &rxring->rxr_rxdesc_size, (void **)&rxring->rxr_rxdesc,
3579: &rxring->rxr_rxdesc_dmamap, rxring->rxr_rxdesc_seg);
3580: if (error != 0)
3581: return error;
3582:
3583: memset(rxring->rxr_rxdesc, 0, sizeof(aq_rx_desc_t) * AQ_RXD_NUM);
3584:
3585: /* fill rxring with dmamaps */
3586: for (i = 0; i < AQ_RXD_NUM; i++) {
3587: rxring->rxr_mbufs[i].m = NULL;
3588: /* XXX: TODO: error check */
3589: bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 0,
3590: &rxring->rxr_mbufs[i].dmamap);
3591: }
3592: return 0;
3593: }
3594:
3595: static void
3596: aq_rxdrain(struct aq_softc *sc, struct aq_rxring *rxring)
3597: {
3598: int i;
3599:
3600: /* free all mbufs allocated for RX */
3601: for (i = 0; i < AQ_RXD_NUM; i++) {
3602: if (rxring->rxr_mbufs[i].m != NULL) {
3603: bus_dmamap_unload(sc->sc_dmat,
3604: rxring->rxr_mbufs[i].dmamap);
3605: m_freem(rxring->rxr_mbufs[i].m);
3606: rxring->rxr_mbufs[i].m = NULL;
3607: }
3608: }
3609: }
3610:
3611: static void
3612: aq_rxring_free(struct aq_softc *sc, struct aq_rxring *rxring)
3613: {
3614: int i;
3615:
3616: /* free all mbufs and dmamaps */
3617: aq_rxdrain(sc, rxring);
3618: for (i = 0; i < AQ_RXD_NUM; i++) {
3619: if (rxring->rxr_mbufs[i].dmamap != NULL) {
3620: bus_dmamap_destroy(sc->sc_dmat,
3621: rxring->rxr_mbufs[i].dmamap);
3622: rxring->rxr_mbufs[i].dmamap = NULL;
3623: }
3624: }
3625:
3626: /* free RX descriptor */
3627: _free_dma(sc, &rxring->rxr_rxdesc_size, (void **)&rxring->rxr_rxdesc,
3628: &rxring->rxr_rxdesc_dmamap, rxring->rxr_rxdesc_seg);
3629: }
3630:
3631: static void
3632: aq_rxring_setmbuf(struct aq_softc *sc, struct aq_rxring *rxring, int idx,
3633: struct mbuf *m)
3634: {
3635: int error;
3636:
3637: /* if mbuf already exists, unload and free */
3638: if (rxring->rxr_mbufs[idx].m != NULL) {
3639: bus_dmamap_unload(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap);
3640: m_freem(rxring->rxr_mbufs[idx].m);
3641: rxring->rxr_mbufs[idx].m = NULL;
3642: }
3643:
3644: rxring->rxr_mbufs[idx].m = m;
3645:
3646: m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
3647: error = bus_dmamap_load_mbuf(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap,
3648: m, BUS_DMA_READ | BUS_DMA_NOWAIT);
3649: if (error) {
3650: device_printf(sc->sc_dev,
3651: "unable to load rx DMA map %d, error = %d\n", idx, error);
3652: panic("%s: unable to load rx DMA map. error=%d",
3653: __func__, error);
3654: }
3655: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap, 0,
3656: rxring->rxr_mbufs[idx].dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
3657: }
3658:
3659: static inline void
3660: aq_rxring_reset_desc(struct aq_softc *sc, struct aq_rxring *rxring, int idx)
3661: {
3662: /* refill rxdesc, and sync */
3663: rxring->rxr_rxdesc[idx].read.buf_addr =
3664: htole64(rxring->rxr_mbufs[idx].dmamap->dm_segs[0].ds_addr);
3665: rxring->rxr_rxdesc[idx].read.hdr_addr = 0;
3666: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_rxdesc_dmamap,
3667: sizeof(aq_rx_desc_t) * idx, sizeof(aq_rx_desc_t),
3668: BUS_DMASYNC_PREWRITE);
3669: }
3670:
3671: static struct mbuf *
3672: aq_alloc_mbuf(void)
3673: {
3674: struct mbuf *m;
3675:
3676: MGETHDR(m, M_DONTWAIT, MT_DATA);
3677: if (m == NULL)
3678: return NULL;
3679:
3680: MCLGET(m, M_DONTWAIT);
3681: if ((m->m_flags & M_EXT) == 0) {
3682: m_freem(m);
3683: return NULL;
3684: }
3685:
3686: return m;
3687: }
3688:
3689: /* allocate mbuf and unload dmamap */
3690: static int
3691: aq_rxring_add(struct aq_softc *sc, struct aq_rxring *rxring, int idx)
3692: {
3693: struct mbuf *m;
3694:
3695: m = aq_alloc_mbuf();
3696: if (m == NULL)
3697: return ENOBUFS;
3698:
3699: aq_rxring_setmbuf(sc, rxring, idx, m);
3700: return 0;
3701: }
3702:
3703: static int
3704: aq_txrx_rings_alloc(struct aq_softc *sc)
3705: {
3706: int n, error;
3707:
3708: for (n = 0; n < sc->sc_nqueues; n++) {
3709: sc->sc_queue[n].sc = sc;
3710: sc->sc_queue[n].txring.txr_sc = sc;
3711: sc->sc_queue[n].txring.txr_index = n;
3712: mutex_init(&sc->sc_queue[n].txring.txr_mutex, MUTEX_DEFAULT,
3713: IPL_NET);
3714: error = aq_txring_alloc(sc, &sc->sc_queue[n].txring);
3715: if (error != 0)
3716: goto failure;
3717:
3718: error = aq_tx_pcq_alloc(sc, &sc->sc_queue[n].txring);
3719: if (error != 0)
3720: goto failure;
3721:
3722: sc->sc_queue[n].rxring.rxr_sc = sc;
3723: sc->sc_queue[n].rxring.rxr_index = n;
3724: mutex_init(&sc->sc_queue[n].rxring.rxr_mutex, MUTEX_DEFAULT,
3725: IPL_NET);
3726: error = aq_rxring_alloc(sc, &sc->sc_queue[n].rxring);
3727: if (error != 0)
3728: break;
3729: }
3730:
3731: failure:
3732: return error;
3733: }
3734:
3735: static void
3736: aq_txrx_rings_free(struct aq_softc *sc)
3737: {
3738: int n;
3739:
3740: for (n = 0; n < sc->sc_nqueues; n++) {
3741: aq_txring_free(sc, &sc->sc_queue[n].txring);
3742: mutex_destroy(&sc->sc_queue[n].txring.txr_mutex);
3743:
3744: aq_tx_pcq_free(sc, &sc->sc_queue[n].txring);
3745:
3746: aq_rxring_free(sc, &sc->sc_queue[n].rxring);
3747: mutex_destroy(&sc->sc_queue[n].rxring.rxr_mutex);
3748: }
3749: }
3750:
3751: static int
3752: aq_tx_pcq_alloc(struct aq_softc *sc, struct aq_txring *txring)
3753: {
3754: int error = 0;
3755: txring->txr_softint = NULL;
3756:
3757: txring->txr_pcq = pcq_create(AQ_TXD_NUM, KM_NOSLEEP);
3758: if (txring->txr_pcq == NULL) {
3759: aprint_error_dev(sc->sc_dev,
3760: "unable to allocate pcq for TXring[%d]\n",
3761: txring->txr_index);
3762: error = ENOMEM;
3763: goto done;
3764: }
3765:
3766: txring->txr_softint = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
3767: aq_deferred_transmit, txring);
3768: if (txring->txr_softint == NULL) {
3769: aprint_error_dev(sc->sc_dev,
3770: "unable to establish softint for TXring[%d]\n",
3771: txring->txr_index);
3772: error = ENOENT;
3773: }
3774:
3775: done:
3776: return error;
3777: }
3778:
3779: static void
3780: aq_tx_pcq_free(struct aq_softc *sc, struct aq_txring *txring)
3781: {
3782: struct mbuf *m;
3783:
3784: if (txring->txr_softint != NULL) {
3785: softint_disestablish(txring->txr_softint);
3786: txring->txr_softint = NULL;
3787: }
3788:
3789: if (txring->txr_pcq != NULL) {
3790: while ((m = pcq_get(txring->txr_pcq)) != NULL)
3791: m_freem(m);
3792: pcq_destroy(txring->txr_pcq);
3793: txring->txr_pcq = NULL;
3794: }
3795: }
3796:
1.4 ryo 3797: #if NSYSMON_ENVSYS > 0
3798: static void
3799: aq_temp_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
3800: {
3801: struct aq_softc *sc;
3802: uint32_t temp;
3803: int error;
3804:
3805: sc = sme->sme_cookie;
3806:
3807: error = sc->sc_fw_ops->get_temperature(sc, &temp);
3808: if (error == 0) {
3809: edata->value_cur = temp;
3810: edata->state = ENVSYS_SVALID;
3811: } else {
3812: edata->state = ENVSYS_SINVALID;
3813: }
3814: }
3815: #endif
3816:
1.1 ryo 3817: static void
3818: aq_tick(void *arg)
3819: {
3820: struct aq_softc *sc = arg;
3821:
3822: if (sc->sc_poll_linkstat || sc->sc_detect_linkstat) {
3823: sc->sc_detect_linkstat = false;
3824: aq_update_link_status(sc);
3825: }
3826:
3827: #ifdef AQ_EVENT_COUNTERS
3828: if (sc->sc_poll_statistics)
3829: aq_update_statistics(sc);
3830: #endif
3831:
3832: if (sc->sc_poll_linkstat
3833: #ifdef AQ_EVENT_COUNTERS
3834: || sc->sc_poll_statistics
3835: #endif
3836: ) {
3837: callout_schedule(&sc->sc_tick_ch, hz);
3838: }
3839: }
3840:
3841: /* interrupt enable/disable */
3842: static void
3843: aq_enable_intr(struct aq_softc *sc, bool link, bool txrx)
3844: {
3845: uint32_t imask = 0;
3846: int i;
3847:
3848: if (txrx) {
3849: for (i = 0; i < sc->sc_nqueues; i++) {
3850: imask |= __BIT(sc->sc_tx_irq[i]);
3851: imask |= __BIT(sc->sc_rx_irq[i]);
3852: }
3853: }
3854:
3855: if (link)
3856: imask |= __BIT(sc->sc_linkstat_irq);
3857:
3858: AQ_WRITE_REG(sc, AQ_INTR_MASK_REG, imask);
3859: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff);
3860: }
3861:
3862: static int
3863: aq_legacy_intr(void *arg)
3864: {
3865: struct aq_softc *sc = arg;
3866: uint32_t status;
3867: int nintr = 0;
3868:
3869: status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
3870: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff);
3871:
3872: if (status & __BIT(sc->sc_linkstat_irq)) {
3873: sc->sc_detect_linkstat = true;
3874: callout_schedule(&sc->sc_tick_ch, 0);
3875: nintr++;
3876: }
3877:
3878: if (status & __BIT(sc->sc_rx_irq[0])) {
3879: nintr += aq_rx_intr(&sc->sc_queue[0].rxring);
3880: }
3881:
3882: if (status & __BIT(sc->sc_tx_irq[0])) {
3883: nintr += aq_tx_intr(&sc->sc_queue[0].txring);
3884: }
3885:
3886: return nintr;
3887: }
3888:
3889: static int
3890: aq_txrx_intr(void *arg)
3891: {
3892: struct aq_queue *queue = arg;
3893: struct aq_softc *sc = queue->sc;
3894: struct aq_txring *txring = &queue->txring;
3895: struct aq_rxring *rxring = &queue->rxring;
3896: uint32_t status;
3897: int nintr = 0;
3898: int txringidx, rxringidx, txirq, rxirq;
3899:
3900: txringidx = txring->txr_index;
3901: rxringidx = rxring->rxr_index;
3902: txirq = sc->sc_tx_irq[txringidx];
3903: rxirq = sc->sc_rx_irq[rxringidx];
3904:
3905: status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
3906: if ((status & (__BIT(txirq) | __BIT(rxirq))) == 0) {
3907: /* stray interrupt? */
3908: return 0;
3909: }
3910:
3911: nintr += aq_rx_intr(rxring);
3912: nintr += aq_tx_intr(txring);
3913:
3914: return nintr;
3915: }
3916:
3917: static int
3918: aq_link_intr(void *arg)
3919: {
3920: struct aq_softc *sc = arg;
3921: uint32_t status;
3922: int nintr = 0;
3923:
3924: status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG);
3925: if (status & __BIT(sc->sc_linkstat_irq)) {
3926: sc->sc_detect_linkstat = true;
3927: callout_schedule(&sc->sc_tick_ch, 0);
3928: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG,
3929: __BIT(sc->sc_linkstat_irq));
3930: nintr++;
3931: }
3932:
3933: return nintr;
3934: }
3935:
3936: static void
3937: aq_txring_reset(struct aq_softc *sc, struct aq_txring *txring, bool start)
3938: {
3939: const int ringidx = txring->txr_index;
3940: int i;
3941:
3942: mutex_enter(&txring->txr_mutex);
3943:
3944: txring->txr_prodidx = 0;
3945: txring->txr_considx = 0;
3946: txring->txr_nfree = AQ_TXD_NUM;
3947: txring->txr_active = false;
3948:
3949: /* free mbufs untransmitted */
3950: for (i = 0; i < AQ_TXD_NUM; i++) {
3951: if (txring->txr_mbufs[i].m != NULL) {
3952: m_freem(txring->txr_mbufs[i].m);
3953: txring->txr_mbufs[i].m = NULL;
3954: }
3955: }
3956:
3957: /* disable DMA */
3958: AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx), TX_DMA_DESC_EN, 0);
3959:
3960: if (start) {
3961: /* TX descriptor physical address */
3962: paddr_t paddr = txring->txr_txdesc_dmamap->dm_segs[0].ds_addr;
3963: AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRLSW_REG(ringidx), paddr);
3964: AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRMSW_REG(ringidx),
3965: (uint32_t)((uint64_t)paddr >> 32));
3966:
3967: /* TX descriptor size */
3968: AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx), TX_DMA_DESC_LEN,
3969: AQ_TXD_NUM / 8);
3970:
3971: /* reload TAIL pointer */
3972: txring->txr_prodidx = txring->txr_considx =
3973: AQ_READ_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(ringidx));
3974: AQ_WRITE_REG(sc, TX_DMA_DESC_WRWB_THRESH_REG(ringidx), 0);
3975:
3976: /* Mapping interrupt vector */
3977: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(ringidx),
3978: AQ_INTR_IRQ_MAP_TX_IRQMAP(ringidx), sc->sc_tx_irq[ringidx]);
3979: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(ringidx),
3980: AQ_INTR_IRQ_MAP_TX_EN(ringidx), true);
3981:
3982: /* enable DMA */
3983: AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx),
3984: TX_DMA_DESC_EN, 1);
3985:
3986: const int cpuid = 0; /* XXX? */
3987: AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(ringidx),
3988: TDM_DCAD_CPUID, cpuid);
3989: AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(ringidx),
3990: TDM_DCAD_CPUID_EN, 0);
3991:
3992: txring->txr_active = true;
3993: }
3994:
3995: mutex_exit(&txring->txr_mutex);
3996: }
3997:
3998: static int
3999: aq_rxring_reset(struct aq_softc *sc, struct aq_rxring *rxring, bool start)
4000: {
4001: const int ringidx = rxring->rxr_index;
4002: int i;
4003: int error = 0;
4004:
4005: mutex_enter(&rxring->rxr_mutex);
4006: rxring->rxr_active = false;
4007:
4008: /* disable DMA */
4009: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), RX_DMA_DESC_EN, 0);
4010:
4011: /* free all RX mbufs */
4012: aq_rxdrain(sc, rxring);
4013:
4014: if (start) {
4015: for (i = 0; i < AQ_RXD_NUM; i++) {
4016: error = aq_rxring_add(sc, rxring, i);
4017: if (error != 0) {
4018: aq_rxdrain(sc, rxring);
4019: return error;
4020: }
4021: aq_rxring_reset_desc(sc, rxring, i);
4022: }
4023:
4024: /* RX descriptor physical address */
4025: paddr_t paddr = rxring->rxr_rxdesc_dmamap->dm_segs[0].ds_addr;
4026: AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRLSW_REG(ringidx), paddr);
4027: AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRMSW_REG(ringidx),
4028: (uint32_t)((uint64_t)paddr >> 32));
4029:
4030: /* RX descriptor size */
4031: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), RX_DMA_DESC_LEN,
4032: AQ_RXD_NUM / 8);
4033:
4034: /* maximum receive frame size */
4035: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(ringidx),
4036: RX_DMA_DESC_BUFSIZE_DATA, MCLBYTES / 1024);
4037: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(ringidx),
4038: RX_DMA_DESC_BUFSIZE_HDR, 0 / 1024);
4039:
4040: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
4041: RX_DMA_DESC_HEADER_SPLIT, 0);
4042: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
4043: RX_DMA_DESC_VLAN_STRIP,
4044: (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) ?
4045: 1 : 0);
4046:
4047: /*
4048: * reload TAIL pointer, and update readidx
4049: * (HEAD pointer cannot write)
4050: */
4051: rxring->rxr_readidx = AQ_READ_REG_BIT(sc,
4052: RX_DMA_DESC_HEAD_PTR_REG(ringidx), RX_DMA_DESC_HEAD_PTR);
4053: AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(ringidx),
4054: (rxring->rxr_readidx + AQ_RXD_NUM - 1) % AQ_RXD_NUM);
4055:
4056: /* Rx ring set mode */
4057:
4058: /* Mapping interrupt vector */
4059: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(ringidx),
4060: AQ_INTR_IRQ_MAP_RX_IRQMAP(ringidx), sc->sc_rx_irq[ringidx]);
4061: AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(ringidx),
4062: AQ_INTR_IRQ_MAP_RX_EN(ringidx), 1);
4063:
4064: const int cpuid = 0; /* XXX? */
4065: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4066: RX_DMA_DCAD_CPUID, cpuid);
4067: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4068: RX_DMA_DCAD_DESC_EN, 0);
4069: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4070: RX_DMA_DCAD_HEADER_EN, 0);
4071: AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
4072: RX_DMA_DCAD_PAYLOAD_EN, 0);
4073:
4074: /* enable DMA. start receiving */
4075: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
4076: RX_DMA_DESC_EN, 1);
4077:
4078: rxring->rxr_active = true;
4079: }
4080:
4081: mutex_exit(&rxring->rxr_mutex);
4082: return error;
4083: }
4084:
4085: #define TXRING_NEXTIDX(idx) \
4086: (((idx) >= (AQ_TXD_NUM - 1)) ? 0 : ((idx) + 1))
4087: #define RXRING_NEXTIDX(idx) \
4088: (((idx) >= (AQ_RXD_NUM - 1)) ? 0 : ((idx) + 1))
4089:
4090: static int
4091: aq_encap_txring(struct aq_softc *sc, struct aq_txring *txring, struct mbuf **mp)
4092: {
4093: bus_dmamap_t map;
4094: struct mbuf *m = *mp;
4095: uint32_t ctl1, ctl1_ctx, ctl2;
4096: int idx, i, error;
4097:
4098: idx = txring->txr_prodidx;
4099: map = txring->txr_mbufs[idx].dmamap;
4100:
4101: error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
4102: BUS_DMA_WRITE | BUS_DMA_NOWAIT);
4103: if (error == EFBIG) {
4104: struct mbuf *n;
4105: n = m_defrag(m, M_DONTWAIT);
4106: if (n == NULL)
4107: return EFBIG;
4108: /* m_defrag() preserve m */
4109: KASSERT(n == m);
4110: error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
4111: BUS_DMA_WRITE | BUS_DMA_NOWAIT);
4112: }
4113: if (error != 0)
4114: return error;
4115:
4116: /*
4117: * check spaces of free descriptors.
4118: * +1 is additional descriptor for context (vlan, etc,.)
4119: */
4120: if ((map->dm_nsegs + 1) > txring->txr_nfree) {
4121: device_printf(sc->sc_dev,
4122: "TX: not enough descriptors left %d for %d segs\n",
4123: txring->txr_nfree, map->dm_nsegs + 1);
4124: bus_dmamap_unload(sc->sc_dmat, map);
4125: return ENOBUFS;
4126: }
4127:
4128: /* sync dma for mbuf */
4129: bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
4130: BUS_DMASYNC_PREWRITE);
4131:
4132: ctl1_ctx = 0;
4133: ctl2 = __SHIFTIN(m->m_pkthdr.len, AQ_TXDESC_CTL2_LEN);
4134:
4135: if (vlan_has_tag(m)) {
4136: ctl1 = AQ_TXDESC_CTL1_TYPE_TXC;
4137: ctl1 |= __SHIFTIN(vlan_get_tag(m), AQ_TXDESC_CTL1_VID);
4138:
4139: ctl1_ctx |= AQ_TXDESC_CTL1_CMD_VLAN;
4140: ctl2 |= AQ_TXDESC_CTL2_CTX_EN;
4141:
4142: /* fill context descriptor and forward index */
4143: txring->txr_txdesc[idx].buf_addr = 0;
4144: txring->txr_txdesc[idx].ctl1 = htole32(ctl1);
4145: txring->txr_txdesc[idx].ctl2 = 0;
4146:
4147: idx = TXRING_NEXTIDX(idx);
4148: txring->txr_nfree--;
4149: }
4150:
4151: if (m->m_pkthdr.csum_flags & M_CSUM_IPv4)
4152: ctl1_ctx |= AQ_TXDESC_CTL1_CMD_IP4CSUM;
4153: if (m->m_pkthdr.csum_flags &
4154: (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv6)) {
4155: ctl1_ctx |= AQ_TXDESC_CTL1_CMD_L4CSUM;
4156: }
4157:
4158: /* fill descriptor(s) */
4159: for (i = 0; i < map->dm_nsegs; i++) {
4160: ctl1 = ctl1_ctx | AQ_TXDESC_CTL1_TYPE_TXD |
4161: __SHIFTIN(map->dm_segs[i].ds_len, AQ_TXDESC_CTL1_BLEN);
4162: ctl1 |= AQ_TXDESC_CTL1_CMD_FCS;
4163:
4164: if (i == 0) {
4165: /* remember mbuf of these descriptors */
4166: txring->txr_mbufs[idx].m = m;
4167: } else {
4168: txring->txr_mbufs[idx].m = NULL;
4169: }
4170:
4171: if (i == map->dm_nsegs - 1) {
4172: /* last segment, mark an EndOfPacket, and cause intr */
4173: ctl1 |= AQ_TXDESC_CTL1_EOP | AQ_TXDESC_CTL1_CMD_WB;
4174: }
4175:
4176: txring->txr_txdesc[idx].buf_addr =
4177: htole64(map->dm_segs[i].ds_addr);
4178: txring->txr_txdesc[idx].ctl1 = htole32(ctl1);
4179: txring->txr_txdesc[idx].ctl2 = htole32(ctl2);
4180:
4181: bus_dmamap_sync(sc->sc_dmat, txring->txr_txdesc_dmamap,
4182: sizeof(aq_tx_desc_t) * idx, sizeof(aq_tx_desc_t),
4183: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4184:
4185: idx = TXRING_NEXTIDX(idx);
4186: txring->txr_nfree--;
4187: }
4188:
4189: txring->txr_prodidx = idx;
4190:
4191: return 0;
4192: }
4193:
4194: static int
4195: aq_tx_intr(void *arg)
4196: {
4197: struct aq_txring *txring = arg;
4198: struct aq_softc *sc = txring->txr_sc;
4199: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1.3 ryo 4200: struct mbuf *m;
1.1 ryo 4201: const int ringidx = txring->txr_index;
4202: unsigned int idx, hw_head, n = 0;
4203:
4204: mutex_enter(&txring->txr_mutex);
4205:
4206: if (!txring->txr_active)
4207: goto tx_intr_done;
4208:
4209: hw_head = AQ_READ_REG_BIT(sc, TX_DMA_DESC_HEAD_PTR_REG(ringidx),
4210: TX_DMA_DESC_HEAD_PTR);
4211: if (hw_head == txring->txr_considx) {
4212: goto tx_intr_done;
4213: }
4214:
1.6 thorpej 4215: net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
4216:
1.1 ryo 4217: for (idx = txring->txr_considx; idx != hw_head;
4218: idx = TXRING_NEXTIDX(idx), n++) {
4219:
1.3 ryo 4220: if ((m = txring->txr_mbufs[idx].m) != NULL) {
1.1 ryo 4221: bus_dmamap_unload(sc->sc_dmat,
4222: txring->txr_mbufs[idx].dmamap);
1.3 ryo 4223:
1.6 thorpej 4224: if_statinc_ref(nsr, if_opackets);
4225: if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len);
1.3 ryo 4226: if (m->m_flags & M_MCAST)
1.6 thorpej 4227: if_statinc_ref(nsr, if_omcasts);
1.3 ryo 4228:
4229: m_freem(m);
1.1 ryo 4230: txring->txr_mbufs[idx].m = NULL;
4231: }
4232:
4233: txring->txr_nfree++;
4234: }
4235: txring->txr_considx = idx;
4236:
1.6 thorpej 4237: IF_STAT_PUTREF(ifp);
4238:
1.1 ryo 4239: if (ringidx == 0 && txring->txr_nfree >= AQ_TXD_MIN)
4240: ifp->if_flags &= ~IFF_OACTIVE;
4241:
4242: /* no more pending TX packet, cancel watchdog */
4243: if (txring->txr_nfree >= AQ_TXD_NUM)
4244: ifp->if_timer = 0;
4245:
4246: tx_intr_done:
4247: mutex_exit(&txring->txr_mutex);
4248:
4249: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_tx_irq[ringidx]));
4250: return n;
4251: }
4252:
4253: static int
4254: aq_rx_intr(void *arg)
4255: {
4256: struct aq_rxring *rxring = arg;
4257: struct aq_softc *sc = rxring->rxr_sc;
4258: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
4259: const int ringidx = rxring->rxr_index;
4260: aq_rx_desc_t *rxd;
4261: struct mbuf *m, *m0, *mprev, *new_m;
4262: uint32_t rxd_type, rxd_hash __unused;
4263: uint16_t rxd_status, rxd_pktlen;
4264: uint16_t rxd_nextdescptr __unused, rxd_vlan __unused;
4265: unsigned int idx, n = 0;
4266:
4267: mutex_enter(&rxring->rxr_mutex);
4268:
4269: if (!rxring->rxr_active)
4270: goto rx_intr_done;
4271:
4272: if (rxring->rxr_readidx == AQ_READ_REG_BIT(sc,
4273: RX_DMA_DESC_HEAD_PTR_REG(ringidx), RX_DMA_DESC_HEAD_PTR)) {
4274: goto rx_intr_done;
4275: }
4276:
1.6 thorpej 4277: net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
4278:
1.1 ryo 4279: m0 = mprev = NULL;
4280: for (idx = rxring->rxr_readidx;
4281: idx != AQ_READ_REG_BIT(sc, RX_DMA_DESC_HEAD_PTR_REG(ringidx),
4282: RX_DMA_DESC_HEAD_PTR); idx = RXRING_NEXTIDX(idx), n++) {
4283:
4284: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_rxdesc_dmamap,
4285: sizeof(aq_rx_desc_t) * idx, sizeof(aq_rx_desc_t),
4286: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4287:
4288: rxd = &rxring->rxr_rxdesc[idx];
4289: rxd_status = le16toh(rxd->wb.status);
4290:
4291: if ((rxd_status & RXDESC_STATUS_DD) == 0)
4292: break; /* not yet done */
4293:
4294: rxd_type = le32toh(rxd->wb.type);
4295: rxd_pktlen = le16toh(rxd->wb.pkt_len);
4296: rxd_nextdescptr = le16toh(rxd->wb.next_desc_ptr);
4297: rxd_hash = le32toh(rxd->wb.rss_hash);
4298: rxd_vlan = le16toh(rxd->wb.vlan);
4299:
4300: if ((rxd_status & RXDESC_STATUS_MACERR) ||
4301: (rxd_type & RXDESC_TYPE_MAC_DMA_ERR)) {
1.6 thorpej 4302: if_statinc_ref(nsr, if_ierrors);
1.1 ryo 4303: goto rx_next;
4304: }
4305:
4306: bus_dmamap_sync(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap, 0,
4307: rxring->rxr_mbufs[idx].dmamap->dm_mapsize,
4308: BUS_DMASYNC_POSTREAD);
4309: m = rxring->rxr_mbufs[idx].m;
4310:
4311: new_m = aq_alloc_mbuf();
4312: if (new_m == NULL) {
4313: /*
4314: * cannot allocate new mbuf.
4315: * discard this packet, and reuse mbuf for next.
4316: */
1.6 thorpej 4317: if_statinc_ref(nsr, if_iqdrops);
1.1 ryo 4318: goto rx_next;
4319: }
4320: rxring->rxr_mbufs[idx].m = NULL;
4321: aq_rxring_setmbuf(sc, rxring, idx, new_m);
4322:
4323: if (m0 == NULL) {
4324: m0 = m;
4325: } else {
4326: if (m->m_flags & M_PKTHDR)
4327: m_remove_pkthdr(m);
4328: mprev->m_next = m;
4329: }
4330: mprev = m;
4331:
4332: if ((rxd_status & RXDESC_STATUS_EOP) == 0) {
4333: m->m_len = MCLBYTES;
4334: } else {
4335: /* last buffer */
4336: m->m_len = rxd_pktlen % MCLBYTES;
4337: m0->m_pkthdr.len = rxd_pktlen;
4338: /* VLAN offloading */
4339: if ((sc->sc_ethercom.ec_capenable &
4340: ETHERCAP_VLAN_HWTAGGING) &&
4341: (__SHIFTOUT(rxd_type, RXDESC_TYPE_PKTTYPE_VLAN) ||
4342: __SHIFTOUT(rxd_type,
4343: RXDESC_TYPE_PKTTYPE_VLAN_DOUBLE))) {
4344: vlan_set_tag(m0, rxd_vlan);
4345: }
4346:
4347: /* Checksum offloading */
4348: unsigned int pkttype_eth =
4349: __SHIFTOUT(rxd_type, RXDESC_TYPE_PKTTYPE_ETHER);
4350: if ((ifp->if_capabilities & IFCAP_CSUM_IPv4_Rx) &&
4351: (pkttype_eth == RXDESC_TYPE_PKTTYPE_ETHER_IPV4) &&
4352: __SHIFTOUT(rxd_type,
4353: RXDESC_TYPE_IPV4_CSUM_CHECKED)) {
4354: m0->m_pkthdr.csum_flags |= M_CSUM_IPv4;
4355: if (__SHIFTOUT(rxd_status,
4356: RXDESC_STATUS_IPV4_CSUM_NG))
4357: m0->m_pkthdr.csum_flags |=
4358: M_CSUM_IPv4_BAD;
4359: }
4360: #if notyet
4361: /*
4362: * XXX: aq always marks BAD for fragmented packet.
4363: * we should peek L3 header, and ignore cksum flags
4364: * if the packet is fragmented.
4365: */
4366: if (__SHIFTOUT(rxd_type,
4367: RXDESC_TYPE_TCPUDP_CSUM_CHECKED)) {
4368: bool checked = false;
4369: unsigned int pkttype_proto =
4370: __SHIFTOUT(rxd_type,
4371: RXDESC_TYPE_PKTTYPE_PROTO);
4372:
4373: if (pkttype_proto ==
4374: RXDESC_TYPE_PKTTYPE_PROTO_TCP) {
4375: if ((pkttype_eth ==
4376: RXDESC_TYPE_PKTTYPE_ETHER_IPV4) &&
4377: (ifp->if_capabilities &
4378: IFCAP_CSUM_TCPv4_Rx)) {
4379: m0->m_pkthdr.csum_flags |=
4380: M_CSUM_TCPv4;
4381: checked = true;
4382: } else if ((pkttype_eth ==
4383: RXDESC_TYPE_PKTTYPE_ETHER_IPV6) &&
4384: (ifp->if_capabilities &
4385: IFCAP_CSUM_TCPv6_Rx)) {
4386: m0->m_pkthdr.csum_flags |=
4387: M_CSUM_TCPv6;
4388: checked = true;
4389: }
4390: } else if (pkttype_proto ==
4391: RXDESC_TYPE_PKTTYPE_PROTO_UDP) {
4392: if ((pkttype_eth ==
4393: RXDESC_TYPE_PKTTYPE_ETHER_IPV4) &&
4394: (ifp->if_capabilities &
4395: IFCAP_CSUM_UDPv4_Rx)) {
4396: m0->m_pkthdr.csum_flags |=
4397: M_CSUM_UDPv4;
4398: checked = true;
4399: } else if ((pkttype_eth ==
4400: RXDESC_TYPE_PKTTYPE_ETHER_IPV6) &&
4401: (ifp->if_capabilities &
4402: IFCAP_CSUM_UDPv6_Rx)) {
4403: m0->m_pkthdr.csum_flags |=
4404: M_CSUM_UDPv6;
4405: checked = true;
4406: }
4407: }
4408: if (checked &&
4409: (__SHIFTOUT(rxd_status,
4410: RXDESC_STATUS_TCPUDP_CSUM_ERROR) ||
4411: !__SHIFTOUT(rxd_status,
4412: RXDESC_STATUS_TCPUDP_CSUM_OK))) {
4413: m0->m_pkthdr.csum_flags |=
4414: M_CSUM_TCP_UDP_BAD;
4415: }
4416: }
4417: #endif
4418: m_set_rcvif(m0, ifp);
1.6 thorpej 4419: if_statinc_ref(nsr, if_ipackets);
4420: if_statadd_ref(nsr, if_ibytes, m0->m_pkthdr.len);
1.1 ryo 4421: if_percpuq_enqueue(ifp->if_percpuq, m0);
4422: m0 = mprev = NULL;
4423: }
4424:
4425: rx_next:
4426: aq_rxring_reset_desc(sc, rxring, idx);
4427: AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(ringidx), idx);
4428: }
4429: rxring->rxr_readidx = idx;
4430:
1.6 thorpej 4431: IF_STAT_PUTREF(ifp);
4432:
1.1 ryo 4433: rx_intr_done:
4434: mutex_exit(&rxring->rxr_mutex);
4435:
4436: AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_rx_irq[ringidx]));
4437: return n;
4438: }
4439:
4440: static int
1.10 ryo 4441: aq_vlan_cb(struct ethercom *ec, uint16_t vid, bool set)
4442: {
4443: struct ifnet *ifp = &ec->ec_if;
4444: struct aq_softc *sc = ifp->if_softc;
4445:
4446: aq_set_vlan_filters(sc);
4447: return 0;
4448: }
4449:
4450: static int
1.1 ryo 4451: aq_ifflags_cb(struct ethercom *ec)
4452: {
4453: struct ifnet *ifp = &ec->ec_if;
4454: struct aq_softc *sc = ifp->if_softc;
4455: int i, ecchange, error = 0;
4456: unsigned short iffchange;
4457:
4458: AQ_LOCK(sc);
4459:
4460: iffchange = ifp->if_flags ^ sc->sc_if_flags;
4461: if ((iffchange & IFF_PROMISC) != 0)
4462: error = aq_set_filter(sc);
4463:
4464: ecchange = ec->ec_capenable ^ sc->sc_ec_capenable;
4465: if (ecchange & ETHERCAP_VLAN_HWTAGGING) {
4466: for (i = 0; i < AQ_RINGS_NUM; i++) {
4467: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(i),
4468: RX_DMA_DESC_VLAN_STRIP,
4469: (ec->ec_capenable & ETHERCAP_VLAN_HWTAGGING) ?
4470: 1 : 0);
4471: }
4472: }
4473:
1.10 ryo 4474: /* vlan configuration depends on also interface promiscuous mode */
4475: if ((ecchange & ETHERCAP_VLAN_HWFILTER) || (iffchange & IFF_PROMISC))
4476: aq_set_vlan_filters(sc);
4477:
1.1 ryo 4478: sc->sc_ec_capenable = ec->ec_capenable;
4479: sc->sc_if_flags = ifp->if_flags;
4480:
4481: AQ_UNLOCK(sc);
4482:
4483: return error;
4484: }
4485:
4486: static int
4487: aq_init(struct ifnet *ifp)
4488: {
4489: struct aq_softc *sc = ifp->if_softc;
4490: int i, error = 0;
4491:
4492: AQ_LOCK(sc);
4493:
1.10 ryo 4494: aq_set_vlan_filters(sc);
1.1 ryo 4495: aq_set_capability(sc);
4496:
4497: for (i = 0; i < sc->sc_nqueues; i++) {
4498: aq_txring_reset(sc, &sc->sc_queue[i].txring, true);
4499: }
4500:
4501: /* invalidate RX descriptor cache */
4502: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT,
4503: AQ_READ_REG_BIT(sc,
4504: RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT) ^ 1);
4505:
4506: /* start RX */
4507: for (i = 0; i < sc->sc_nqueues; i++) {
4508: error = aq_rxring_reset(sc, &sc->sc_queue[i].rxring, true);
4509: if (error != 0) {
4510: device_printf(sc->sc_dev, "%s: cannot allocate rxbuf\n",
4511: __func__);
4512: goto aq_init_failure;
4513: }
4514: }
4515: aq_init_rss(sc);
4516: aq_hw_l3_filter_set(sc);
4517:
4518: /* need to start callout? */
4519: if (sc->sc_poll_linkstat
4520: #ifdef AQ_EVENT_COUNTERS
4521: || sc->sc_poll_statistics
4522: #endif
4523: ) {
4524: callout_schedule(&sc->sc_tick_ch, hz);
4525: }
4526:
4527: /* ready */
4528: ifp->if_flags |= IFF_RUNNING;
4529: ifp->if_flags &= ~IFF_OACTIVE;
4530:
4531: /* start TX and RX */
4532: aq_enable_intr(sc, true, true);
4533: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_EN, 1);
4534: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 1);
4535:
4536: aq_init_failure:
4537: sc->sc_if_flags = ifp->if_flags;
4538:
4539: AQ_UNLOCK(sc);
4540:
4541: return error;
4542: }
4543:
4544: static void
4545: aq_send_common_locked(struct ifnet *ifp, struct aq_softc *sc,
4546: struct aq_txring *txring, bool is_transmit)
4547: {
4548: struct mbuf *m;
4549: int npkt, error;
4550:
4551: if ((ifp->if_flags & IFF_RUNNING) == 0)
4552: return;
4553:
4554: for (npkt = 0; ; npkt++) {
4555: if (is_transmit)
4556: m = pcq_peek(txring->txr_pcq);
4557: else
4558: IFQ_POLL(&ifp->if_snd, m);
4559:
4560: if (m == NULL)
4561: break;
4562:
4563: if (txring->txr_nfree < AQ_TXD_MIN)
4564: break;
4565:
4566: if (is_transmit)
4567: pcq_get(txring->txr_pcq);
4568: else
4569: IFQ_DEQUEUE(&ifp->if_snd, m);
4570:
4571: error = aq_encap_txring(sc, txring, &m);
4572: if (error != 0) {
4573: /* too many mbuf chains? or not enough descriptors? */
4574: m_freem(m);
1.6 thorpej 4575: if_statinc(ifp, if_oerrors);
1.2 ryo 4576: if (txring->txr_index == 0 && error == ENOBUFS)
1.1 ryo 4577: ifp->if_flags |= IFF_OACTIVE;
4578: break;
4579: }
4580:
4581: /* update tail ptr */
4582: AQ_WRITE_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(txring->txr_index),
4583: txring->txr_prodidx);
4584:
4585: /* Pass the packet to any BPF listeners */
4586: bpf_mtap(ifp, m, BPF_D_OUT);
4587: }
4588:
1.2 ryo 4589: if (txring->txr_index == 0 && txring->txr_nfree < AQ_TXD_MIN)
1.1 ryo 4590: ifp->if_flags |= IFF_OACTIVE;
4591:
4592: if (npkt)
4593: ifp->if_timer = 5;
4594: }
4595:
4596: static void
4597: aq_start(struct ifnet *ifp)
4598: {
4599: struct aq_softc *sc;
4600: struct aq_txring *txring;
4601:
4602: sc = ifp->if_softc;
4603: txring = &sc->sc_queue[0].txring; /* aq_start() always use TX ring[0] */
4604:
4605: mutex_enter(&txring->txr_mutex);
4606: if (txring->txr_active && !ISSET(ifp->if_flags, IFF_OACTIVE))
4607: aq_send_common_locked(ifp, sc, txring, false);
4608: mutex_exit(&txring->txr_mutex);
4609: }
4610:
4611: static inline unsigned int
4612: aq_select_txqueue(struct aq_softc *sc, struct mbuf *m)
4613: {
4614: return (cpu_index(curcpu()) % sc->sc_nqueues);
4615: }
4616:
4617: static int
4618: aq_transmit(struct ifnet *ifp, struct mbuf *m)
4619: {
4620: struct aq_softc *sc = ifp->if_softc;
4621: struct aq_txring *txring;
4622: int ringidx;
4623:
4624: ringidx = aq_select_txqueue(sc, m);
4625: txring = &sc->sc_queue[ringidx].txring;
4626:
4627: if (__predict_false(!pcq_put(txring->txr_pcq, m))) {
4628: m_freem(m);
4629: return ENOBUFS;
4630: }
4631:
4632: if (mutex_tryenter(&txring->txr_mutex)) {
4633: aq_send_common_locked(ifp, sc, txring, true);
4634: mutex_exit(&txring->txr_mutex);
4635: } else {
4636: softint_schedule(txring->txr_softint);
4637: }
4638: return 0;
4639: }
4640:
4641: static void
4642: aq_deferred_transmit(void *arg)
4643: {
4644: struct aq_txring *txring = arg;
4645: struct aq_softc *sc = txring->txr_sc;
4646: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
4647:
4648: mutex_enter(&txring->txr_mutex);
4649: if (pcq_peek(txring->txr_pcq) != NULL)
4650: aq_send_common_locked(ifp, sc, txring, true);
4651: mutex_exit(&txring->txr_mutex);
4652: }
4653:
4654: static void
4655: aq_stop(struct ifnet *ifp, int disable)
4656: {
4657: struct aq_softc *sc = ifp->if_softc;
4658: int i;
4659:
4660: AQ_LOCK(sc);
4661:
4662: ifp->if_timer = 0;
4663:
4664: /* disable tx/rx interrupts */
4665: aq_enable_intr(sc, true, false);
4666:
4667: AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_EN, 0);
4668: for (i = 0; i < sc->sc_nqueues; i++) {
4669: aq_txring_reset(sc, &sc->sc_queue[i].txring, false);
4670: }
4671:
4672: AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 0);
4673: for (i = 0; i < sc->sc_nqueues; i++) {
4674: aq_rxring_reset(sc, &sc->sc_queue[i].rxring, false);
4675: }
4676:
4677: /* invalidate RX descriptor cache */
4678: AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT,
4679: AQ_READ_REG_BIT(sc,
4680: RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT) ^ 1);
4681:
4682: ifp->if_timer = 0;
4683:
4684: if (!disable) {
4685: /* when pmf stop, disable link status intr and callout */
4686: aq_enable_intr(sc, false, false);
4687: callout_stop(&sc->sc_tick_ch);
4688: }
4689:
4690: ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
4691:
4692: AQ_UNLOCK(sc);
4693: }
4694:
4695: static void
4696: aq_watchdog(struct ifnet *ifp)
4697: {
4698: struct aq_softc *sc = ifp->if_softc;
4699: struct aq_txring *txring;
4700: int n, head, tail;
4701:
4702: AQ_LOCK(sc);
4703:
4704: device_printf(sc->sc_dev, "%s: INTR_MASK/STATUS = %08x/%08x\n",
4705: __func__, AQ_READ_REG(sc, AQ_INTR_MASK_REG),
4706: AQ_READ_REG(sc, AQ_INTR_STATUS_REG));
4707:
4708: for (n = 0; n < sc->sc_nqueues; n++) {
4709: txring = &sc->sc_queue[n].txring;
4710: head = AQ_READ_REG_BIT(sc,
4711: TX_DMA_DESC_HEAD_PTR_REG(txring->txr_index),
4712: TX_DMA_DESC_HEAD_PTR),
4713: tail = AQ_READ_REG(sc,
4714: TX_DMA_DESC_TAIL_PTR_REG(txring->txr_index));
4715:
4716: device_printf(sc->sc_dev, "%s: TXring[%d] HEAD/TAIL=%d/%d\n",
4717: __func__, txring->txr_index, head, tail);
4718:
4719: aq_tx_intr(txring);
4720: }
4721:
4722: AQ_UNLOCK(sc);
4723:
4724: aq_init(ifp);
4725: }
4726:
4727: static int
4728: aq_ioctl(struct ifnet *ifp, unsigned long cmd, void *data)
4729: {
4730: struct aq_softc *sc __unused;
4731: struct ifreq *ifr __unused;
1.6 thorpej 4732: int error, s;
1.1 ryo 4733:
4734: sc = (struct aq_softc *)ifp->if_softc;
4735: ifr = (struct ifreq *)data;
4736: error = 0;
4737:
4738: s = splnet();
4739: error = ether_ioctl(ifp, cmd, data);
4740: splx(s);
4741:
4742: if (error != ENETRESET)
4743: return error;
4744:
4745: switch (cmd) {
4746: case SIOCSIFCAP:
4747: error = aq_set_capability(sc);
4748: break;
4749: case SIOCADDMULTI:
4750: case SIOCDELMULTI:
4751: if ((ifp->if_flags & IFF_RUNNING) == 0)
4752: break;
4753:
4754: /*
4755: * Multicast list has changed; set the hardware filter
4756: * accordingly.
4757: */
4758: error = aq_set_filter(sc);
4759: break;
4760: }
4761:
4762: return error;
4763: }
4764:
4765:
4766: MODULE(MODULE_CLASS_DRIVER, if_aq, "pci");
4767:
4768: #ifdef _MODULE
4769: #include "ioconf.c"
4770: #endif
4771:
4772: static int
4773: if_aq_modcmd(modcmd_t cmd, void *opaque)
4774: {
4775: int error = 0;
4776:
4777: switch (cmd) {
4778: case MODULE_CMD_INIT:
4779: #ifdef _MODULE
4780: error = config_init_component(cfdriver_ioconf_if_aq,
4781: cfattach_ioconf_if_aq, cfdata_ioconf_if_aq);
4782: #endif
4783: return error;
4784: case MODULE_CMD_FINI:
4785: #ifdef _MODULE
4786: error = config_fini_component(cfdriver_ioconf_if_aq,
4787: cfattach_ioconf_if_aq, cfdata_ioconf_if_aq);
4788: #endif
4789: return error;
4790: default:
4791: return ENOTTY;
4792: }
4793: }
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