The NetBSD Project

CVS log for src/sys/dev/nvmm/x86/nvmm_x86_vmxfunc.S

[BACK] Up to [cvs.NetBSD.org] / src / sys / dev / nvmm / x86

Request diff between arbitrary revisions


Default branch: MAIN


Revision 1.6 / (download) - annotate - [select for diffs], Sat Sep 5 07:22:26 2020 UTC (3 years, 7 months ago) by maxv
Branch: MAIN
CVS Tags: thorpej-ifq-base, thorpej-ifq, thorpej-i2c-spi-conf2-base, thorpej-i2c-spi-conf2, thorpej-i2c-spi-conf-base, thorpej-i2c-spi-conf, thorpej-futex2-base, thorpej-futex2, thorpej-futex-base, thorpej-futex, thorpej-cfargs2-base, thorpej-cfargs2, thorpej-cfargs-base, thorpej-cfargs, thorpej-altq-separation-base, thorpej-altq-separation, netbsd-10-base, netbsd-10-0-RELEASE, netbsd-10-0-RC6, netbsd-10-0-RC5, netbsd-10-0-RC4, netbsd-10-0-RC3, netbsd-10-0-RC2, netbsd-10-0-RC1, netbsd-10, cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x, bouyer-sunxi-drm-base, bouyer-sunxi-drm, HEAD
Changes since 1.5: +14 -15 lines
Diff to previous 1.5 (colored)

nvmm: update copyright headers

Revision 1.3.4.1 / (download) - annotate - [select for diffs], Sat Aug 29 17:00:28 2020 UTC (3 years, 7 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-3-RELEASE, netbsd-9-2-RELEASE, netbsd-9-1-RELEASE
Changes since 1.3: +3 -3 lines
Diff to previous 1.3 (colored) next main 1.4 (colored)

Pull up following revision(s) (requested by maxv in ticket #1068):

	sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.71
	sys/dev/nvmm/nvmm.c: revision 1.34
	sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.72
	sys/dev/nvmm/nvmm.c: revision 1.35
	sys/dev/nvmm/nvmm.c: revision 1.36
	sys/dev/nvmm/x86/nvmm_x86_svmfunc.S: revision 1.5
	sys/dev/nvmm/nvmm.c: revision 1.37
	sys/dev/nvmm/x86/nvmm_x86_vmxfunc.S: revision 1.5
	sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.70
	sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.68
	sys/dev/nvmm/x86/nvmm_x86.c: revision 1.15
	sys/dev/nvmm/nvmm_ioctl.h: revision 1.10

Micro-optimize: use pushq instead of pushw. To avoid LCP stalls and
unaligned stack accesses.

nvmm-x86: also flush the guest TLB when CR4.{PCIDE,SMEP} changes

nvmm: localify a variable that doesn't need to be global

nvmm: use relaxed atomics to read nmachines

nvmm-x86-svm: dedup code

nvmm-x86: hide more CPUID flags, mostly related to perf monitors

nvmm: misc improvements
 - use mach->ncpus to get the number of vcpus, now that we have it
 - don't forget to decrement mach->ncpus when a machine gets killed
 - add more __predict_false()

nvmm-x86-svm: don't forget to intercept INVD
INVD executed in the guest can be dangerous for the host, due to CPU
caches being flushed without write-back.

nvmm: slightly clarify

nvmm: explicitly include atomic.h

Revision 1.5 / (download) - annotate - [select for diffs], Tue Aug 11 15:48:42 2020 UTC (3 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.4: +3 -3 lines
Diff to previous 1.4 (colored)

Micro-optimize: use pushq instead of pushw. To avoid LCP stalls and
unaligned stack accesses.

Revision 1.4 / (download) - annotate - [select for diffs], Sun Jul 19 06:36:37 2020 UTC (3 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.3: +2 -13 lines
Diff to previous 1.3 (colored)

The TLB flush IPIs do not respect the IPL, so enforcing IPL_HIGH has no
effect. Disable interrupts earlier instead. This prevents a possible race
against such IPIs.

Revision 1.3.2.2 / (download) - annotate - [select for diffs], Mon Jun 10 22:07:14 2019 UTC (4 years, 10 months ago) by christos
Branch: phil-wifi
Changes since 1.3.2.1: +260 -0 lines
Diff to previous 1.3.2.1 (colored) to branchpoint 1.3 (colored) next main 1.4 (colored)

Sync with HEAD

Revision 1.3.2.1, Sat Apr 27 08:16:19 2019 UTC (4 years, 11 months ago) by christos
Branch: phil-wifi
Changes since 1.3: +0 -260 lines
FILE REMOVED

file nvmm_x86_vmxfunc.S was added on branch phil-wifi on 2019-06-10 22:07:14 +0000

Revision 1.3 / (download) - annotate - [select for diffs], Sat Apr 27 08:16:19 2019 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20200421, phil-wifi-20200411, phil-wifi-20200406, phil-wifi-20191119, phil-wifi-20190609, netbsd-9-base, netbsd-9-0-RELEASE, netbsd-9-0-RC2, netbsd-9-0-RC1, is-mlppp-base, is-mlppp, bouyer-xenpvh-base2, bouyer-xenpvh-base1, bouyer-xenpvh-base, bouyer-xenpvh, ad-namecache-base3, ad-namecache-base2, ad-namecache-base1, ad-namecache-base, ad-namecache
Branch point for: phil-wifi, netbsd-9
Changes since 1.2: +18 -115 lines
Diff to previous 1.2 (colored)

Optimize nvmm-intel, use inlined GCC assembly rather than function calls.

Revision 1.2 / (download) - annotate - [select for diffs], Wed Apr 24 18:45:15 2019 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.1: +10 -10 lines
Diff to previous 1.1 (colored)

Match the structure order, for better cache utilization.

Revision 1.1 / (download) - annotate - [select for diffs], Wed Feb 13 16:03:16 2019 UTC (5 years, 2 months ago) by maxv
Branch: MAIN
CVS Tags: isaki-audio2-base, isaki-audio2

Add Intel-VMX support in NVMM. This allows us to run hardware-accelerated
VMs on Intel CPUs. Overall this implementation is fast and reliable, I am
able to run NetBSD VMs with many VCPUs on a quad-core Intel i5.

NVMM-Intel applies several optimizations already present in NVMM-AMD, and
has a code structure similar to it. No change was needed in the NVMM MI
frontend, or in libnvmm.

Some differences exist against AMD:

 - On Intel the ASID space is big, so we don't fall back to a shared ASID
   when there are more VCPUs executing than available ASIDs in the host,
   contrary to AMD. There are enough ASIDs for the maximum number of VCPUs
   supported by NVMM.

 - On Intel there are two TLBs we need to take care of, one for the host
   (EPT) and one for the guest (VPID). Changes in EPT paging flush the
   host TLB, changes to the guest mode flush the guest TLB.

 - On Intel there is no easy way to set/fetch the VTPR, so we intercept
   reads/writes to CR8 and maintain a software TPR, that we give to the
   virtualizer as if it was the effective TPR in the guest.

 - On Intel, because of SVS, the host CR4 and LSTAR are not static, so
   we're forced to save them on each VMENTRY.

 - There is extra Intel weirdness we need to take care of, for example the
   reserved bits in CR0 and CR4 when accesses trap.

While this implementation is functional and can already run many OSes, we
likely have a problem on 32bit-PAE guests, because they require special
care on Intel CPUs, and currently we don't handle that correctly; such
guests may misbehave for now (without altering the host stability). I
expect to fix that soon.

This form allows you to request diff's between any two revisions of a file. You may select a symbolic revision name using the selection box or you may type in a numeric name using the type-in text box.




CVSweb <webmaster@jp.NetBSD.org>