CVS log for src/sys/dev/mii/igphyreg.h

Up to [cvs.NetBSD.org] / src / sys / dev / mii

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Pull up the following revisions, requested by msaitoh in ticket #1594:

	sys/dev/pci/if_wm.c			1.655-1.658, 1.660,
						1.662, 1.664-1.668,
						1.671-1.674, 1.678,
						1.680-1.685 via patch
	sys/dev/pci/if_wmreg.c			1.118-1.119 via patch
	sys/dev/pci/if_wmvar.c			1.45 via patch
	sys/dev/mii/igphy.c			1.35-1.36 via patch
	sys/dev/mii/igphyreg.h			1.12-1.13
	sys/dev/mii/makphy.c			1.66 via patch
	sys/dev/mii/makphyreg.h			1.11

- Add SFP support. Module insertion/removal is not supported yet.
  Currently, SFP detection is only done in the driver's attach phase.
- Detect the Media Auto Sense feature. Not supported yet.
- Fix SFF_SFP_ETH_FLAGS_100FX. It's not 0x10 but 0x20.
- Add extra delay in wm_serdes_power_up_link_82575().
- Add Intel I219 LM10-LM15 and V10-V14.
- wm(4) can use workqueue as deferred Rx/Tx handler).
  Set hw.wm*.txrx_workqueue=1 to use workqueue instead of softint.
  The default value of hw.wm*.txrx_workqueue is 0 which use softint
  as before.
- Unset RSS UDP flags like ixg(4) and other OSes. To handle IP
  fragmented UDP, first packet and second packet should be processed
  in the same Rx queue.
- It's useless to not to set PCI_PMCSR_PME_STS bit when writing because
  the bit is W1C. Instead, always write PCI_PMCSR_PME_STS bit to clear
  in case it's already set.
- Actually writing always the checksum offload context descriptor
  makes the HW do extra processing, avoid doing that if possible.
- Fix a bug that the WMREG_EEARBC_I210 register is incorrectly set if
  the system uses iNVM.
- "wmX: 0" on 82542 is difficult to understand, so don't print it.
- Explicitly cast from uint16_t to uint32_t before shifting 16bit left
  when printing Image Unique ID to avoid undefined behavior.
- Set if_baudrate for non-MII device.
- Rename some macros and function.
- KNF. Add comment.

Pull up following revision(s) (requested by msaitoh in ticket #1040):

	sys/dev/mii/igphy.c: revision 1.35
	sys/dev/mii/igphy.c: revision 1.36
	sys/dev/mii/igphyreg.h: revision 1.12
	sys/dev/mii/igphyreg.h: revision 1.13
	sys/dev/mii/makphyreg.h: revision 1.11
	sys/dev/pci/if_wm.c: revision 1.682
	sys/dev/pci/if_wm.c: revision 1.683
	sys/dev/pci/if_wm.c: revision 1.684
	sys/dev/pci/if_wm.c: revision 1.685
	sys/dev/mii/makphy.c: revision 1.66

s/MII_IGPHY_/IGPHY_/. No functional change.

Rename PSSR_* to MAKPHY_PSSR_* and IGPHY_PSSR_* to avoid conflict.
No functional change.

  Setup PCS and SGMII for SFP correctly. It still doesn't support SFP
insertion/removal.

Copper:
wm2: SGMII(SFP)
wm2: 0x1043c440<SPI,IOH_VALID,PCIE,SGMII,NEWQUEUE,ASF_FIRM,EEE,SFP>
makphy0 at wm2 phy 6: Marvell 88E1111 Gigabit PHY, rev. 1

Fiber:
wm3: SERDES(SFP)
wm3: 0x10034440<SPI,IOH_VALID,PCIE,NEWQUEUE,ASF_FIRM,SFP>
wm3: 1000baseSX, 1000baseSX-FDX, auto

  Explicitly cast from uint16_t to uint32_t before shifting 16bit left
when printing Image Unique ID. Found by kUBSan.

  Set if_baudrate for non-MII device. Before this commit, it was 0.

Rename PSSR_* to MAKPHY_PSSR_* and IGPHY_PSSR_* to avoid conflict.
No functional change.

s/MII_IGPHY_/IGPHY_/. No functional change.

Sync with HEAD

Sync with HEAD

 Change MII PHY read/write API from:

	int (*mii_readreg_t)(device_t, int, int);
	void (*mii_writereg_t)(device_t, int, int, int);
to:

	int (*mii_readreg_t)(device_t, int, int, uint16_t *);
	int (*mii_writereg_t)(device_t, int, int, uint16_t);

Now we can test if a read/write operation failed or not by the return value.

 In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.

 Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:

	arm/at91/at91emac.c
	arm/ep93xx/epe.c
	arm/omap/omapl1x_emac.c
	mips/ralink/ralink_eth.c
	arch/powerpc/booke/dev/pq3etsec.c(read)
	dev/cadence/if_cemac.c <- hkenken
	dev/ic/lan9118.c


Tested with the following device:

	axe+ukphy
	axe+rgephy
	axen+rgephy	(tested by Andrius V)
	wm+atphy
	wm+ukphy
	wm+igphy
	wm+ihphy
	wm+makphy
	sk+makphy
	sk+brgphy
	sk+gentbi
	msk+makphy
	sip+icsphy
	sip+ukphy
	re+rgephy
	bge+brgphy
	bnx+brgphy
	gsip+gphyter
	rtk+rlphy
	fxp+inphy	(tested by Andrius V)
	tlp+acphy
	ex+exphy
	epic+qsphy
	vge+ciphy	(tested by Andrius V)
	vr+ukphy	(tested by Andrius V)
	vte+ukphy	(tested by Andrius V)

Not tested (MAC):
	arm:at91emac
	arm:cemac
	arm:epe
	arm:geminigmac
	arm:enet
	arm:cpsw
	arm:emac(omac)
	arm:emac(sunxi)
	arm:npe
	evbppc:temac
	macppc:bm
	macppc:gm
	mips:aumac
	mips:ae
	mips:cnmac
	mips:reth
	mips:sbmac
	playstation2:smap
	powerpc:tsec
	powerpc:emac(ibm4xx)
	sgimips:mec
	sparc:be
	sf
	ne(ax88190, dl10019)
	awge
	ep
	gem
	hme
	smsh
	mtd
	sm
	age
	alc
	ale
	bce
	cas
	et
	jme
	lii
	nfe
	pcn
	ste
	stge
	tl
	xi
	aue
	mue
	smsc
	udav
	url

Not tested (PHY):
	amhphy
	bmtphy
	dmphy
	etphy
	glxtphy
	ikphy
	iophy
	lxtphy
	nsphyter
	pnaphy
	rdcphy
	sqphy
	tlphy
	tqphy
	urlphy

update from HEAD

Sync with netbsd-5

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

Pull up following revision(s) (requested by msaitoh in ticket #1302):
	sys/dev/mii/igphyreg.h: revisions 1.7-1.10
	sys/dev/mii/ikphyreg.h: revisions 1.3
	sys/dev/mii/inbmphyreg.h: revisions 1.4-1.9
	sys/dev/mii/mii.h: revisions 1.19-1.20
	sys/dev/pci/if_wm.c: revisions 1.390, 1.392-1.395, 1.397, 1.419-1.425, 1.427-1.428, 1.430-1.435, 1.437-1.453 via patch
	sys/dev/pci/if_wmreg.: revisions 1.89-1.93 via patch
	sys/dev/pci/if_wmvar.h: revisions 1.31-1.32
Update wm(4) up to if_wm.c rev. 1.453 except MSI/MSI-X, multiqueue and
NET_MPSAFE:
- Add I219 support. It's not stable so it's disabled by default.
- wm_gate_hw_phy_config_ich8lan() is for younger than PCH2.
- Drop the host wakeup bit after resetting PHY on PCH and newer
  devices.
- Increase delay while toggling LANPHYPC
- Move call of wm_reset() in wm_attach() after setting PHY and NVM
  related flags because those flags are used in wm_reset().
- Use mutex for NVM access on ICH8 and newer devices. Same as FreeBSD.
- Rewrite PHY related lock stuff. Almost the same as FreeBSD.
  This change will fix a bug that PHY read/write fail on some cases.
- Increase delay in wm_phy_resetisblocked(). Same as FreeBSD.
- Use semaphore in wm_hv_phy_workaround_ich8lan() and
  wm_k1_gig_workaround_hv()
- Use wm_gii_mdic_readreg/writereg() in wm_access_phy_wakeup_reg_bm()
  because these functions are called with taking lock.
- 82567V_3 is BME1000_E_2(bm). Tested with Advantech AIMB-212 1st
  Ethernet port.
- Use wm_gmii_82544_{read,write}reg() on non-82567 ICH8, 9 and 10.
- Remove an 82578 workaround which was for PCH rev < 3. FreeBSD
  removed this workaround in r228386.
- Add an 82578 workaround which is for PHY rev < 2. From FreeBSD and
  Linux.
- Fix wm(4) input drop packet counter. WMREG_RNBC is incremented when
  there is no available buffers in host memory. However, ethernet
  controller can receive packets in such case if there is space in
  phy's FIFO. That is, ethernet controller drops packet only if there
  is no available buffers *and* there is no space in phy's FIFO. So,
  the number of dropped packets should be added WMREG_MPC only.
- Use MII_ADDRMASK.
- Define WMPHY_I217, WMPHY_VF and WMPHY_210.
- Use BME1000_PHY_PAGE_SELECT in wm_gmii_bm_{read,write}reg(). This
  change has no effect because GG82563_PHY_PAGE_SELECT and
  BME1000_PHY_PAGE_SELECT have the same value.
- Fix PHY access on  82567(ICH8 or ICH10), 82574 and 82583:
  - Use wm_gmii_bm_{read,write}reg() on 82574 and 82573.
  - Issue page select correctly on BM PHYs.
- Fix workaround which did dummy read BM_WUC register. This code was
  changed to drop BM_WUC_HOST_WU_BIT of BM_PROT_GEN_CFG register in
  FreeBSD r228386. The code was added rev. 1.149, but the location was
  not the best.
- wm_gmii_hv_{read/write}reg*(): USE PHY address 1 for some special
  registers.
- Add check code for an 82578 workaround. Not completed yet.
- wm_release_hw_control(): Remove extra line. No any effect.
- Add "10/100" into non-gigabit devices' name.
- Call wm_enable_wakeup() in wm_detach() and wm_suspend(). Now wake on
  lan works on Thinkpad X61(ICH8).
- Fix wm_access_phy_wakeup_reg_bm(). This change has no effect because
  this function is used for WUC register and our driver currenlty
  doesn't access to it.
- Call wm_enable_phy_wakeup() on PCH2 and newer, too. Now these devices
  can do WOL. Tested with Thinkpad X220(PCH2).
- Set CTRL_MEHE correctly (PCH_{LPT,SPT} only).
- Add three workarounds for PCH_{LPT,SPT}.
- Fix a bug that 8257[56], 82580, I35[04] and I21[01] didn't use
  wm_{get,release}_hw_control() correctly.
- Sync wm_smbustopci() with Linux and FreeBSD. This change effects PCH
  and newer devices.
- Move the location of wm_smbustopci() call.
- Fix flag check in wm_get_wakeup()
  - 8254[17]* and 8257[124] should not set WM_F_ARC_SUBSYS_VALID.
  - Add missing WM_T_82541_2 and WM_T_82547_2.
- Fix WOL related setting of the WUC register for other than PCH* in
  wm_enable_wakeup(). Tested with 82567V(ICH8) and 82583V.
- Use common MII_ADDRMASK.
- igphy(4): No binary change:
  - s/IGPPHY/IGPHY/
  - Fix the definition of PLHR_VALID_CHANNEL_*
  - Fix the definition of MSE_CHANNEL_*
  - Add MII_IGPHY_POWER_MGMT.
- Add some KASSERT.
- Add comment. Modify comment.
- Add debug code.

Sync with HEAD

Fix previous (s/MII_MAXREGADDR/MII_ADDRMASK/).

Sync with HEAD

- Use MII_ADDRMASK.
- Remove debug printf().

Sync with HEAD (as of 26th Dec)

No binary change:
 - s/IGPPHY/IGPHY/
 - Fix the definition of PLHR_VALID_CHANNEL_*
 - Fix the definition of MSE_CHANNEL_*
 - Add MII_IGPHY_POWER_MGMT

- PSCR_TP_LOOPBACK is not bit 0 but bit 4. No binary change because
  this macro is not used.
- Rename MII_IGPPHY_PORT_CONFIG's bit definitions from PSCR_ to PSCFR_
  to avoid confusion. PSCR_ is for MII_IGPHY_PORT_CTRL.

Pullup the following revisions via patch, requested by msaitoh in ticket #1850:
	sys/dev/pci/if_wm.c			1.201, 1.203-1.204,
						1.207-1.212, 1.215,
						1.217-1.218, 1.220-1.223,
						1.228, 1.232-245
	sys/dev/pci/if_wmreg.h			1.40-1.45, 1.47-1.48
	sys/dev/pci/if_wmvar.h			1.11-1.13
	sys/dev/pci/pcidevs			1.1074, 1.1077, 1.1117
	sys/dev/pci/pcidevs.h			regen
	sys/dev/pci/pcidevs_data.h		regen
	sys/dev/mii/igphyreg.h			1.6
	sys/dev/mii/ihphy.c			1.1-1.2
	sys/dev/mii/ihphyreg.h			1.1
	sys/dev/mii/inbmphyreg.h		1.3
	sys/dev/mii/files.mii			1.47 via patch
	sys/dev/mii/miidevs			1.97 and 1.100
	sys/dev/mii/miidevs.h			regen
	sys/dev/mii/miidevs_data.h		regen
	sys/arch/i386/conf/ALL			1.280
	sys/arch/i386/conf/GENERIC		1.1001
	sys/arch/i386/conf/INSTALL_FLOPPY	1.11
	sys/arch/i386/conf/XEN2_DOM0		patch
	sys/arch/amd64/conf/GENERIC		1.293
	sys/arch/amd64/conf/XEN3_DOM0		1.61
	share/man/man4/wm.4			1.21-1.24

Apply almost all fixes and improvements from netbsd-6 except for
the rev. 1.196's iqdrops' change.

- Add the detach code.
- Add code for WOL, ASF, IPMI and Intel AMT. WOL is disabled by default
- Add Yet another workaround for ICH8.
- 82576 is dual port, so check the FUNCID and increment the MAC address for
  the 2nd port.
- Fix the names of 82577L[MC] LAN controllers (for mobile).
- Fix CTRL_EXT_SWDPIN() and CTRL_EXT_SWDPIO() macros. The bit order of the
  SW definable pin is not 6543 but 3654!!!
- Rewrite the code to read MAC address from eeprom.
- Add 82580 support.
- 82571 quirk. Only 82571 shares port 0 of EEMNGCTL_CFGDONE.
- The document says that the TDH register must be set after
  TCL.EN is set on 82575 and newer devices.
- Fix some register names. No functional change.
- Omit U+00AE "REGISTERED SIGN" in a product name due to its non-ASCII nature.
- Stop wm(4) from needlessly resetting when you add or delete a vlan(4).
- Fix MAC address check on 8257[156] and 80003 case. Some cards have non 0xffff
  pointer but those don't use alternative MAC address in reality. So we check
  whether the broadcast bit is set or not like Intel's e1000 driver.
  Fixes PR kern/44072 reported by Jean-Yves Moulin.
- Add PCH2(and 82579) support. Fixes PR#46487
- Add yet another 82567V support.
- Add ICH10+HANKSVILL support.
- Add support Intel I350 Ethernet.
- Make vlan and all ip/ip6 checksum offload work for the I350.
- Fix compile error with  WM_DEBUG.
- Fix a bug that PHY isn't set to low-power mode on PCH and PCH2.
- Add WM_DEBUG_NVM. If WM_DEBUG_NVM is enabled, dump the FLASH ROM data.
- Skip 64bit BAR correctly.
- Fix RAL_TABSIZE for ICH8, 82576, 82580 and I350.
- Use 82580(and I350) specific PHY read/write functions. Fixes PR#47542.
- Style fix. Fix typo in comment. Fix comments. Add comments.

Sync with HEAD.

sync to netbsd-5

sync with head

- Add code for WOL, ASF, IPMI and Intel AMT.
    - wm_enable_wakeup() is disabled by default. If you want to use WOL with
      the Magic Packet, define WM_WOL.
    - Add the following flags:
        WM_F_ASF_FIRMWARE_PRESENT
        WM_F_ARC_SUBSYSTEM_VALID
        WM_F_HAS_AMT
        WM_F_HAS_MANAGE
        WM_F_WOL
    - Add wm_suspend() and wm_resume(). Give/get the control to/from the
      firmware.
    - Need more work for PCH. See wm_enable_phy_wakeup().
- Enable wm_get_hw_control() for 82574 and 82583.
- Add Yet another workaround for ICH8.
    - Add wm_igp3_phy_powerdown_workaround_ich8lan() for power down problem
      on D3.

Pull up the following revisions(s) (requested by msaitoh in ticket #1277):
sys/dev/pci/if_wm.c		1.184-1.192, 1.194
sys/dev/pci/if_wmreg.h		1.29-1.35
sys/dev/pci/if_wmvar.h		1.5-1.8
sys/dev/pci/pcidevs		1.1006,1.1009-1.1010, 1.1012-1.1013 via patch
sys/dev/pci/pcidevs.h		regen
sys/dev/pci/pcidevs_data.h	regen
sys/dev/mii/igphyreg.h		1.5
sys/dev/mii/inbmphyreg.h	1.1

- Add support for i82583V.
- Add some ICH9 and ICH10 devices.
- Add support for PCH.
- Fix the bug that ICH9 can't found a PHY. Fixes PR#42237
- Fix an incorrect test for WM_F_EEPROM_INVALID since rev. 1.183. Some old
  chips don't set EECD_EE_PRES.
- Fix a bug that both WM_F_EEPROM_SPI and WM_F_EEPROM_FLASH are set.
- Add a missing decrement for a timeout reported by Wolfgang Stukenbrock
  in PR#42422.
- PBA setting for i82574 is not 12K but 20K.
- Enable checking the management mode on 82574.
- Fix the length of the delay() in wm_gmii_reset(). It fixed the problem that
  sometimes the driver misunderstood PHYs in mii_attach(). It was reported
  by MATSUI Yoshihiro. We observed it on ICH9.
- Fix the checking of jumbo frame function
- Remove the extra macro definition for the offset 0x1a in EEPROM.
- Add missing break in wm_reset()...
- Fix the offset of WMREG_PBS...
- Make wm_reset() and wm_gmii_reset() close to e1000 driver.
  At least, this change make wm_attach() stable on ICH9.
- Reset GMII interface after wm_reset() in wm_init().
- Rework for assigning mii_{read,write}reg(). Use PCI product ID to identify
  the PHY.
- Add code about LPLU(Low Power Link Up) function. It seems that we have to
  do the same work for ICH9.
- Fixes the rx stall problem on 82578 by MANY workaround code. We need more
  work for 82577.

Add some macros

merge ktrace-lwp.

sync with -current

sync with head.  xen and whitespace.  xen part is not finished.

Sync with HEAD.

Hi Perry!

nuke trailing whitespace

Pull up revision 1.2 (requested by thorpej in ticket #897)

Enable the SmartSpeed work-around code for the IGP phy, with some
minor adjustments.

Pull up revision 1.2 (requested by thorpej in ticket #897)

Enable the SmartSpeed work-around code for the IGP phy, with some
minor adjustments.

Sync with HEAD

Enable the SmartSpeed work-around code for the IGP phy, with some
minor adjustments.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

file igphyreg.h was added on branch ktrace-lwp on 2004-08-03 10:48:49 +0000

Add a driver for the Intel IGPE1000 PHY as found on 82541 and 82547 chips.
Not yet enabled anywhere.