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Revision 1.3, Mon Jan 22 22:28:47 2001 UTC (16 years, 8 months ago) by bjh21
Branch: MAIN
CVS Tags: yamt-x86pmap-base4, yamt-x86pmap-base3, yamt-x86pmap-base2, yamt-x86pmap-base, yamt-x86pmap, yamt-vop-base3, yamt-vop-base2, yamt-vop-base, yamt-vop, yamt-uio_vmspace-base5, yamt-uio_vmspace, yamt-splraiseipl-base5, yamt-splraiseipl-base4, yamt-splraiseipl-base3, yamt-splraiseipl-base2, yamt-splraiseipl-base, yamt-splraiseipl, yamt-readahead-pervnode, yamt-readahead-perfile, yamt-readahead-base3, yamt-readahead-base2, yamt-readahead-base, yamt-readahead, yamt-pf42-baseX, yamt-pf42-base4, yamt-pf42-base3, yamt-pf42-base2, yamt-pf42-base, yamt-pf42, yamt-pdpolicy-base9, yamt-pdpolicy-base8, yamt-pdpolicy-base7, yamt-pdpolicy-base6, yamt-pdpolicy-base5, yamt-pdpolicy-base4, yamt-pdpolicy-base3, yamt-pdpolicy-base2, yamt-pdpolicy-base, yamt-pdpolicy, yamt-pagecache-tag8, yamt-pagecache-base9, yamt-pagecache-base8, yamt-pagecache-base7, yamt-pagecache-base6, yamt-pagecache-base5, yamt-pagecache-base4, yamt-pagecache-base3, yamt-pagecache-base2, yamt-pagecache-base, yamt-pagecache, yamt-nfs-mp-base9, yamt-nfs-mp-base8, yamt-nfs-mp-base7, yamt-nfs-mp-base6, yamt-nfs-mp-base5, yamt-nfs-mp-base4, yamt-nfs-mp-base3, yamt-nfs-mp-base2, yamt-nfs-mp-base11, yamt-nfs-mp-base10, yamt-nfs-mp-base, yamt-nfs-mp, yamt-lazymbuf-base15, yamt-lazymbuf-base14, yamt-lazymbuf, yamt-kmem-base3, yamt-kmem-base2, yamt-kmem-base, yamt-kmem, yamt-km-base4, yamt-km-base3, yamt-km-base2, yamt-km-base, yamt-km, yamt-idlelwp-base8, yamt-idlelwp, wrstuden-revivesa-base-4, wrstuden-revivesa-base-3, wrstuden-revivesa-base-2, wrstuden-revivesa-base-1, wrstuden-revivesa-base, wrstuden-revivesa, wrstuden-fixsa-newbase, wrstuden-fixsa-base-1, wrstuden-fixsa-base, wrstuden-fixsa, vmlocking2-base3, vmlocking2-base2, vmlocking2-base1, vmlocking2, vmlocking-nbase, vmlocking-base, vmlocking, uebayasi-xip-base4, uebayasi-xip-base3, uebayasi-xip-base2, uebayasi-xip-base1, uebayasi-xip-base, uebayasi-xip, tls-maxphys-base, tls-maxphys, tls-earlyentropy-base, tls-earlyentropy, thorpej_scsipi_nbase, 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pgoyette-localcount-20170320, pgoyette-localcount-20170107, pgoyette-localcount-20161104, pgoyette-localcount-20160806, pgoyette-localcount-20160726, pgoyette-localcount, peter-altq-base, peter-altq, perseant-stdc-iso10646-base, perseant-stdc-iso10646, nick-nhusb-base-20170825, nick-nhusb-base-20170204, nick-nhusb-base-20161204, nick-nhusb-base-20161004, nick-nhusb-base-20160907, nick-nhusb-base-20160529, nick-nhusb-base-20160422, nick-nhusb-base-20160319, nick-nhusb-base-20151226, nick-nhusb-base-20150921, nick-nhusb-base-20150606, nick-nhusb-base-20150406, nick-nhusb-base, nick-nhusb, nick-net80211-sync-base, nick-net80211-sync, nick-hppapmap-base4, nick-hppapmap-base3, nick-hppapmap-base2, nick-hppapmap-base, nick-hppapmap, nick-csl-alignment-base5, nick-csl-alignment-base, nick-csl-alignment, newlock2-nbase, newlock2-base, newlock2, newlock-base, newlock, netbsd-8-base, netbsd-8, netbsd-7-nhusb-base-20170116, netbsd-7-nhusb-base, netbsd-7-nhusb, netbsd-7-base, netbsd-7-1-RELEASE, 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netbsd-1-6-RC2, netbsd-1-6-RC1, netbsd-1-6-PATCH002-RELEASE, netbsd-1-6-PATCH002-RC4, netbsd-1-6-PATCH002-RC3, netbsd-1-6-PATCH002-RC2, netbsd-1-6-PATCH002-RC1, netbsd-1-6-PATCH002, netbsd-1-6-PATCH001-RELEASE, netbsd-1-6-PATCH001-RC3, netbsd-1-6-PATCH001-RC2, netbsd-1-6-PATCH001-RC1, netbsd-1-6-PATCH001, netbsd-1-6, nathanw_sa_end, nathanw_sa_before_merge, nathanw_sa_base, nathanw_sa, mjf-ufs-trans-base, mjf-ufs-trans, mjf-devfs2-base, mjf-devfs2, mjf-devfs-base, mjf-devfs, matt-premerge-20091211, matt-nb6-plus-nbase, matt-nb6-plus-base, matt-nb6-plus, matt-nb5-pq3-base, matt-nb5-pq3, matt-nb5-mips64-u2-k2-k4-k7-k8-k9, matt-nb5-mips64-u1-k1-k5, matt-nb5-mips64-premerge-20101231, matt-nb5-mips64-premerge-20091211, matt-nb5-mips64-k15, matt-nb5-mips64, matt-nb4-mips64-k7-u2a-k9b, matt-nb4-arm-base, matt-nb4-arm, matt-mips64-premerge-20101231, matt-mips64-base2, matt-mips64-base, matt-mips64, matt-armv6-prevmlocking, matt-armv6-nbase, matt-armv6-base, matt-armv6, localcount-20160914, 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gdamore-uart-base, gdamore-uart, fvdl_fs64_base, elad-kernelauth-base, elad-kernelauth, eeh-devprop-base, eeh-devprop, cube-autoconf-base, cube-autoconf, cherry-xenmp-base, cherry-xenmp, chap-midi-nbase, chap-midi-base, chap-midi, bouyer-xeni386-nbase, bouyer-xeni386-merge1, bouyer-xeni386-base, bouyer-xeni386, bouyer-xenamd64-base2, bouyer-xenamd64-base, bouyer-xenamd64, bouyer-socketcan-base1, bouyer-socketcan-base, bouyer-socketcan, bouyer-quota2-nbase, bouyer-quota2-base, bouyer-quota2, agc-symver-base, agc-symver, ad-socklock-base1, ad-audiomp2-base, ad-audiomp2, ad-audiomp-base, ad-audiomp, abandoned-netbsd-4-base, abandoned-netbsd-4, HEAD
Changes since 1.2: +7 -1 lines

Patch from PR kern/8001, submitted by Rafal Boni.

This adds support for EtherExpress/16 cards with 16k of RAM, and in the
process adds general support for PIO mode on these cards.  This entails
changing the way the i82586 driver handles bus barriers, since it doesn't
allow for strange cases like this.

This has been tested on the i386 port with the 'ix' driver in both
16KB (which was the source of the problem) and 32KB modes, as well
as with the 'ef' driver.  I've tested it (briefly) with 'ei' on arm26
as well.  In theory, drivers other than 'ix' should follow precisely the
same code paths as before.

/*	$NetBSD: if_ixreg.h,v 1.3 2001/01/22 22:28:47 bjh21 Exp $	*/

/*
 * Copyright (c) 1993, 1994, 1995
 *	Rodney W. Grimes, Milwaukie, Oregon  97222.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer as
 *    the first lines of this file unmodified.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Rodney W. Grimes.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY RODNEY W. GRIMES ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL RODNEY W. GRIMES BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/*
 * Definitions for EtherExpress 16
 */

#define IX_IOSIZE	16	/* card has 16 registers in IO space */

#define IX_DATAPORT  		0x00	/* shared memory data port */
#define IX_WRITEPTR  		0x02	/* shared memory write pointer */
#define IX_READPTR  		0x04	/* shared memory read pointer */

#define IX_ATTN			0x06	/* channel attention control */
#define IX_IRQ			0x07	/* IRQ configuration */
#define IX_IRQ_ENABLE		0x08	/* enable board interrupts */

#define IX_SHADOWPTR  		0x08	/* shadow memory pointer */

#define IX_MEMDEC		0x0a	/* memory decode */
#define IX_MCTRL		0x0b	/* memory control */
#define IX_MCTRL_FMCS16		0x10	/* MEMCS16- for F000 */

#define IX_MPCTRL		0x0c	/* memory page control */
#define IX_CONFIG		0x0d	/* config register */
#define IX_BART_LOOPBACK	0x02	/* loopback, 0=none, 1=loopback */
#define IX_BART_IOCHRDY_LATE	0x10	/* iochrdy late control bit */
#define IX_BART_IO_TEST_EN	0x20	/* enable iochrdy timing test */
#define IX_BART_IO_RESULT	0x40	/* result of the iochrdy test */
#define IX_BART_MCS16_TEST	0x80	/* enable memcs16 select test */

#define IX_ECTRL		0x0e	/* eeprom control */
#define IX_ECTRL_EESK		0x01	/* EEPROM clock bit */
#define IX_ECTRL_EECS		0x02	/* EEPROM chip select */
#define IX_ECTRL_EEDI		0x04	/* EEPROM data in bit */
#define IX_ECTRL_EEDO		0x08	/* EEPROM data out bit */
#define IX_RESET_ASIC		0x40	/* reset ASIC (bart) pin */
#define IX_RESET_586		0x80	/* reset 82586 pin */
#define IX_ECTRL_MASK		0xb2	/* and'ed with ECTRL to enable read  */

#define IX_MECTRL		0x0f	/* memory control, 0xe000 seg 'W' */
#define IX_ID_PORT		0x0f	/* auto-id port 'R' */

#define IX_ID			0xbaba	/* known id of EE16 */

#define IX_EEPROM_READ	0x06	/* EEPROM read opcode */
#define IX_EEPROM_OPSIZE1	0x03	/* size of EEPROM opcodes */
#define IX_EEPROM_ADDR_SIZE	0x06	/* size of EEPROM address */

/* Locations in the EEPROM */
#define IX_EEPROM_CONFIG1	0x00	/* Configuration register 1 */
#define IX_EEPROM_MEDIA_EXT	0x1000	/* Using external transceiver */

#define IX_EEPROM_IRQ		0xE000	/* Encoded IRQ */
#define IX_EEPROM_IRQ_SHIFT	13	/* To shift IRQ to lower bits */
#define IX_EEPROM_LOCK_ADDR	0x01	/* contains the lock bit */
#define IX_EEPROM_LOCKED	0x01	/* means that it is locked */

#define IX_EEPROM_ENET_LOW	0x02	/* Ethernet address, low word */
#define IX_EEPROM_ENET_MID	0x03	/* Ethernet address, middle word */
#define IX_EEPROM_ENET_HIGH	0x04	/* Ethernet address, high word */

#define IX_EEPROM_MEDIA		0x05	/* Selects between TP/BNC */
#define IX_EEPROM_MEDIA_TP	0x01	/* if ON, using TP, else BNC */