version 1.19.6.1, 2005/02/12 18:17:45 |
version 1.19.6.2, 2005/03/19 08:34:33 |
Line 298 ix_copyin (sc, dst, offset, size) |
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Line 298 ix_copyin (sc, dst, offset, size) |
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wptr++; |
wptr++; |
} |
} |
} else { |
} else { |
bus_space_read_region_2(sc->bt, sc->bh, offset, |
bus_space_read_region_2(sc->bt, sc->bh, offset, |
(u_int16_t *) bptr, size / 2); |
(u_int16_t *) bptr, size / 2); |
} |
} |
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Line 330 ix_copyout (sc, src, offset, size) |
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Line 330 ix_copyout (sc, src, offset, size) |
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if (isc->use_pio) { |
if (isc->use_pio) { |
/* Reset write pointer to the specified offset */ |
/* Reset write pointer to the specified offset */ |
bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); |
bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); |
bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, |
bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
} |
} |
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Line 351 ix_copyout (sc, src, offset, size) |
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Line 351 ix_copyout (sc, src, offset, size) |
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wptr++; |
wptr++; |
} |
} |
} else { |
} else { |
bus_space_write_region_2(sc->bt, sc->bh, offset, |
bus_space_write_region_2(sc->bt, sc->bh, offset, |
(u_int16_t *)bptr, size / 2); |
(u_int16_t *)bptr, size / 2); |
} |
} |
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Line 366 ix_copyout (sc, src, offset, size) |
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Line 366 ix_copyout (sc, src, offset, size) |
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} |
} |
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if (isc->use_pio) |
if (isc->use_pio) |
bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, |
bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
else |
else |
bus_space_barrier(sc->bt, sc->bh, ooffset, osize, |
bus_space_barrier(sc->bt, sc->bh, ooffset, osize, |
Line 399 ix_read_16 (sc, offset) |
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Line 399 ix_read_16 (sc, offset) |
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/* Reset read pointer to the specified offset */ |
/* Reset read pointer to the specified offset */ |
bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); |
bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); |
bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, |
bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
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return bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); |
return bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); |
} else { |
} else { |
bus_space_barrier(sc->bt, sc->bh, offset, 2, |
bus_space_barrier(sc->bt, sc->bh, offset, 2, |
BUS_SPACE_BARRIER_READ); |
BUS_SPACE_BARRIER_READ); |
return bus_space_read_2(sc->bt, sc->bh, offset); |
return bus_space_read_2(sc->bt, sc->bh, offset); |
} |
} |
Line 421 ix_write_16 (sc, offset, value) |
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Line 421 ix_write_16 (sc, offset, value) |
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if (isc->use_pio) { |
if (isc->use_pio) { |
/* Reset write pointer to the specified offset */ |
/* Reset write pointer to the specified offset */ |
bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); |
bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); |
bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, |
bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
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bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, value); |
bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, value); |
bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, |
bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
} else { |
} else { |
bus_space_write_2(sc->bt, sc->bh, offset, value); |
bus_space_write_2(sc->bt, sc->bh, offset, value); |
bus_space_barrier(sc->bt, sc->bh, offset, 2, |
bus_space_barrier(sc->bt, sc->bh, offset, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
} |
} |
} |
} |
Line 446 ix_write_24 (sc, offset, addr) |
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Line 446 ix_write_24 (sc, offset, addr) |
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if (isc->use_pio) { |
if (isc->use_pio) { |
/* Reset write pointer to the specified offset */ |
/* Reset write pointer to the specified offset */ |
bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); |
bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); |
bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, |
bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
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ptr = (char*) &val; |
ptr = (char*) &val; |
bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, |
bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, |
*((u_int16_t *)ptr)); |
*((u_int16_t *)ptr)); |
bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, |
bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, |
*((u_int16_t *)(ptr + 2))); |
*((u_int16_t *)(ptr + 2))); |
bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, |
bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
} else { |
} else { |
bus_space_write_4(sc->bt, sc->bh, offset, val); |
bus_space_write_4(sc->bt, sc->bh, offset, val); |
bus_space_barrier(sc->bt, sc->bh, offset, 4, |
bus_space_barrier(sc->bt, sc->bh, offset, 4, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
} |
} |
} |
} |
Line 475 ix_zeromem(sc, offset, count) |
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Line 475 ix_zeromem(sc, offset, count) |
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if (isc->use_pio) { |
if (isc->use_pio) { |
/* Reset write pointer to the specified offset */ |
/* Reset write pointer to the specified offset */ |
bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); |
bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); |
bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, |
bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
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if (offset % 2) { |
if (offset % 2) { |
Line 490 ix_zeromem(sc, offset, count) |
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Line 490 ix_zeromem(sc, offset, count) |
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if (dribble) |
if (dribble) |
bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); |
bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); |
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bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, |
bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
} else { |
} else { |
bus_space_set_region_1(sc->bt, sc->bh, offset, 0, count); |
bus_space_set_region_1(sc->bt, sc->bh, offset, 0, count); |
bus_space_barrier(sc->bt, sc->bh, offset, count, |
bus_space_barrier(sc->bt, sc->bh, offset, count, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
} |
} |
} |
} |
Line 654 ix_match(parent, cf, aux) |
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Line 654 ix_match(parent, cf, aux) |
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} |
} |
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/* |
/* |
* Only do the following bit if using memory-mapped access. For |
* Only do the following bit if using memory-mapped access. For |
* boards with no mapped memory, we use PIO. We also use PIO for |
* boards with no mapped memory, we use PIO. We also use PIO for |
* boards with 16K of mapped memory, as those setups don't seem |
* boards with 16K of mapped memory, as those setups don't seem |
* to work otherwise. |
* to work otherwise. |
Line 670 ix_match(parent, cf, aux) |
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Line 670 ix_match(parent, cf, aux) |
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bus_space_write_1(iot, ioh, IX_MPCTRL, (~decode & 0xFF)); |
bus_space_write_1(iot, ioh, IX_MPCTRL, (~decode & 0xFF)); |
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/* XXX disable Exxx */ |
/* XXX disable Exxx */ |
bus_space_write_1(iot, ioh, IX_MECTRL, edecode); |
bus_space_write_1(iot, ioh, IX_MECTRL, edecode); |
} |
} |
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/* |
/* |
Line 741 ix_attach(parent, self, aux) |
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Line 741 ix_attach(parent, self, aux) |
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iot = ia->ia_iot; |
iot = ia->ia_iot; |
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/* |
/* |
* Shared memory access seems to fail on 16K mapped boards, so |
* Shared memory access seems to fail on 16K mapped boards, so |
* disable shared memory access if the board is in 16K mode. If |
* disable shared memory access if the board is in 16K mode. If |
* no memory is mapped, we have no choice but to use PIO |
* no memory is mapped, we have no choice but to use PIO |
*/ |
*/ |
isc->use_pio = (ia->ia_iomem[0].ir_size <= (16 * 1024)); |
isc->use_pio = (ia->ia_iomem[0].ir_size <= (16 * 1024)); |
Line 814 ix_attach(parent, self, aux) |
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Line 814 ix_attach(parent, self, aux) |
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sc->bt = iot; |
sc->bt = iot; |
sc->bh = ioh; |
sc->bh = ioh; |
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/* |
/* |
* If using PIO, the memory size is bounded by on-card memory, |
* If using PIO, the memory size is bounded by on-card memory, |
* not by how much is mapped into the memory-mapped region, so |
* not by how much is mapped into the memory-mapped region, so |
* determine how much total memory we have to play with here. |
* determine how much total memory we have to play with here. |
*/ |
*/ |
for(memsize = 64 * 1024; memsize; memsize -= 16 * 1024) { |
for(memsize = 64 * 1024; memsize; memsize -= 16 * 1024) { |
/* warm up shared memory, the zero it all out */ |
/* warm up shared memory, the zero it all out */ |
Line 826 ix_attach(parent, self, aux) |
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Line 826 ix_attach(parent, self, aux) |
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/* Reset write pointer to the start of RAM */ |
/* Reset write pointer to the start of RAM */ |
bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); |
bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); |
bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, |
bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
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/* write test pattern */ |
/* write test pattern */ |
Line 836 ix_attach(parent, self, aux) |
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Line 836 ix_attach(parent, self, aux) |
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} |
} |
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/* Flush all reads & writes to data port */ |
/* Flush all reads & writes to data port */ |
bus_space_barrier(iot, ioh, IX_DATAPORT, 2, |
bus_space_barrier(iot, ioh, IX_DATAPORT, 2, |
BUS_SPACE_BARRIER_READ | |
BUS_SPACE_BARRIER_READ | |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
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/* Reset read pointer to beginning of card RAM */ |
/* Reset read pointer to beginning of card RAM */ |
bus_space_write_2(iot, ioh, IX_READPTR, 0); |
bus_space_write_2(iot, ioh, IX_READPTR, 0); |
bus_space_barrier(iot, ioh, IX_READPTR, 2, |
bus_space_barrier(iot, ioh, IX_READPTR, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
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/* read and verify test pattern */ |
/* read and verify test pattern */ |
Line 865 ix_attach(parent, self, aux) |
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Line 865 ix_attach(parent, self, aux) |
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/* Reset write pointer to start of card RAM */ |
/* Reset write pointer to start of card RAM */ |
bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); |
bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); |
bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, |
bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
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/* write out test pattern */ |
/* write out test pattern */ |
Line 875 ix_attach(parent, self, aux) |
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Line 875 ix_attach(parent, self, aux) |
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} |
} |
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/* Flush all reads & writes to data port */ |
/* Flush all reads & writes to data port */ |
bus_space_barrier(iot, ioh, IX_DATAPORT, 2, |
bus_space_barrier(iot, ioh, IX_DATAPORT, 2, |
BUS_SPACE_BARRIER_READ | |
BUS_SPACE_BARRIER_READ | |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
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/* Reset read pointer to beginning of card RAM */ |
/* Reset read pointer to beginning of card RAM */ |
bus_space_write_2(iot, ioh, IX_READPTR, 0); |
bus_space_write_2(iot, ioh, IX_READPTR, 0); |
bus_space_barrier(iot, ioh, IX_READPTR, 2, |
bus_space_barrier(iot, ioh, IX_READPTR, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
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/* read and verify test pattern */ |
/* read and verify test pattern */ |
Line 892 ix_attach(parent, self, aux) |
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Line 892 ix_attach(parent, self, aux) |
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bpat += 3; |
bpat += 3; |
} |
} |
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/* If we got through all of memory, we're done! */ |
/* If we got through all of memory, we're done! */ |
if (i == memsize) |
if (i == memsize) |
break; |
break; |
} |
} |
Line 935 ix_attach(parent, self, aux) |
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Line 935 ix_attach(parent, self, aux) |
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/* set card to 16-bit bus mode */ |
/* set card to 16-bit bus mode */ |
if (isc->use_pio) { |
if (isc->use_pio) { |
bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, |
bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, |
IE_SCP_BUS_USE((u_long)sc->scp)); |
IE_SCP_BUS_USE((u_long)sc->scp)); |
bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, |
bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, |
BUS_SPACE_BARRIER_WRITE); |
BUS_SPACE_BARRIER_WRITE); |
Line 943 ix_attach(parent, self, aux) |
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Line 943 ix_attach(parent, self, aux) |
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bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, |
bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, |
IE_SYSBUS_16BIT); |
IE_SYSBUS_16BIT); |
} else { |
} else { |
bus_space_write_1(sc->bt, sc->bh, |
bus_space_write_1(sc->bt, sc->bh, |
IE_SCP_BUS_USE((u_long)sc->scp), |
IE_SCP_BUS_USE((u_long)sc->scp), |
IE_SYSBUS_16BIT); |
IE_SYSBUS_16BIT); |
} |
} |