Annotation of src/sys/dev/isa/esp_isa.c, Revision 1.27.6.3
1.27.6.3! skrll 1: /* $NetBSD: esp_isa.c,v 1.27.6.2 2004/09/21 13:29:43 skrll Exp $ */
1.2 thorpej 2:
1.5 thorpej 3: /*-
1.12 mycroft 4: * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
1.1 pk 5: * All rights reserved.
6: *
1.5 thorpej 7: * This code is derived from software contributed to The NetBSD Foundation
1.13 mycroft 8: * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
9: * Simulation Facility, NASA Ames Research Center.
1.5 thorpej 10: *
1.1 pk 11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
1.5 thorpej 21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
1.1 pk 26: *
1.5 thorpej 27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
1.1 pk 38: */
39:
40: /*
41: * Copyright (c) 1994 Peter Galbavy
42: * All rights reserved.
43: *
44: * Redistribution and use in source and binary forms, with or without
45: * modification, are permitted provided that the following conditions
46: * are met:
47: * 1. Redistributions of source code must retain the above copyright
48: * notice, this list of conditions and the following disclaimer.
49: * 2. Redistributions in binary form must reproduce the above copyright
50: * notice, this list of conditions and the following disclaimer in the
51: * documentation and/or other materials provided with the distribution.
52: * 3. All advertising materials mentioning features or use of this software
53: * must display the following acknowledgement:
54: * This product includes software developed by Peter Galbavy
55: * 4. The name of the author may not be used to endorse or promote products
56: * derived from this software without specific prior written permission.
57: *
58: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
59: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
60: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
61: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
62: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
63: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
64: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
65: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
66: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
67: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
68: * POSSIBILITY OF SUCH DAMAGE.
69: */
70:
71: /*
72: * Based on aic6360 by Jarle Greipsland
73: *
74: * Acknowledgements: Many of the algorithms used in this driver are
75: * inspired by the work of Julian Elischer (julian@tfs.com) and
76: * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
77: */
78:
79: /*
80: * Initial m68k mac support from Allen Briggs <briggs@macbsd.com>
81: * (basically consisting of the match, a bit of the attach, and the
82: * "DMA" glue functions).
83: */
84:
85: /*
86: * Copyright (c) 1997 Eric S. Hvozda (hvozda@netcom.com)
87: * All rights reserved.
88: *
89: * Redistribution and use in source and binary forms, with or without
90: * modification, are permitted provided that the following conditions
91: * are met:
92: * 1. Redistributions of source code must retain the above copyright
93: * notice, this list of conditions and the following disclaimer.
94: * 2. Redistributions in binary form must reproduce the above copyright
95: * notice, this list of conditions and the following disclaimer in the
96: * documentation and/or other materials provided with the distribution.
97: * 3. All advertising materials mentioning features or use of this software
98: * must display the following acknowledgement:
99: * This product includes software developed by Eric S. Hvozda.
100: * 4. The name of Eric S. Hvozda may not be used to endorse or promote products
101: * derived from this software without specific prior written permission.
102: *
103: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
104: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
105: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
106: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
107: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
108: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
109: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
110: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
111: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
112: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
113: */
1.23 lukem 114:
115: #include <sys/cdefs.h>
1.27.6.3! skrll 116: __KERNEL_RCSID(0, "$NetBSD: esp_isa.c,v 1.27.6.2 2004/09/21 13:29:43 skrll Exp $");
1.1 pk 117:
118: #include <sys/param.h>
119: #include <sys/systm.h>
120: #include <sys/device.h>
121: #include <sys/buf.h>
122:
123: #include <machine/bus.h>
124: #include <machine/intr.h>
125:
1.22 bouyer 126: #include <dev/scsipi/scsipi_all.h>
1.4 bouyer 127: #include <dev/scsipi/scsi_all.h>
128: #include <dev/scsipi/scsiconf.h>
1.1 pk 129:
130: #include <dev/isa/isavar.h>
131: #include <dev/isa/isadmavar.h>
132:
133: #include <dev/ic/ncr53c9xreg.h>
134: #include <dev/ic/ncr53c9xvar.h>
135:
1.18 mycroft 136: #include <dev/isa/esp_isavar.h>
1.1 pk 137:
1.27.6.3! skrll 138: int esp_isa_match(struct device *, struct cfdata *, void *);
! 139: void esp_isa_attach(struct device *, struct device *, void *);
1.1 pk 140:
1.26 thorpej 141: CFATTACH_DECL(esp_isa, sizeof(struct esp_isa_softc),
1.27 thorpej 142: esp_isa_match, esp_isa_attach, NULL, NULL);
1.1 pk 143:
1.17 mycroft 144: int esp_isa_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */
1.1 pk 145:
146: /*
147: * Functions and the switch for the MI code.
148: */
1.27.6.3! skrll 149: u_char esp_isa_read_reg(struct ncr53c9x_softc *, int);
! 150: void esp_isa_write_reg(struct ncr53c9x_softc *, int, u_char);
! 151: int esp_isa_dma_isintr(struct ncr53c9x_softc *);
! 152: void esp_isa_dma_reset(struct ncr53c9x_softc *);
! 153: int esp_isa_dma_intr(struct ncr53c9x_softc *);
! 154: int esp_isa_dma_setup(struct ncr53c9x_softc *, caddr_t *,
! 155: size_t *, int, size_t *);
! 156: void esp_isa_dma_go(struct ncr53c9x_softc *);
! 157: void esp_isa_dma_stop(struct ncr53c9x_softc *);
! 158: int esp_isa_dma_isactive(struct ncr53c9x_softc *);
1.17 mycroft 159:
160: struct ncr53c9x_glue esp_isa_glue = {
161: esp_isa_read_reg,
162: esp_isa_write_reg,
163: esp_isa_dma_isintr,
164: esp_isa_dma_reset,
165: esp_isa_dma_intr,
166: esp_isa_dma_setup,
167: esp_isa_dma_go,
168: esp_isa_dma_stop,
169: esp_isa_dma_isactive,
1.1 pk 170: NULL, /* gl_clear_latched_intr */
171: };
172:
173: /*
174: * Look for the board
175: */
176: int
1.17 mycroft 177: esp_isa_find(iot, ioh, epd)
1.1 pk 178: bus_space_tag_t iot;
179: bus_space_handle_t ioh;
1.17 mycroft 180: struct esp_isa_probe_data *epd;
1.1 pk 181: {
182: u_int vers;
183: u_int p1;
184: u_int p2;
185: u_int jmp;
186:
1.17 mycroft 187: ESP_TRACE(("[esp_isa_find] "));
1.1 pk 188:
189: /* reset card before we probe? */
190:
1.19 mycroft 191: epd->sc_cfg4 = NCRCFG4_ACTNEG;
192: epd->sc_cfg5 = NCRCFG5_CRS1 | NCRCFG5_AADDR | NCRCFG5_PTRINC;
193:
1.1 pk 194: /*
195: * Switch to the PIO regs and look for the bit pattern
196: * we expect...
197: */
1.19 mycroft 198: bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5);
1.1 pk 199:
200: #define SIG_MASK 0x87
201: #define REV_MASK 0x70
202: #define M1 0x02
203: #define M2 0x05
204: #define ISNCR 0x80
205: #define ISESP406 0x40
206:
207: vers = bus_space_read_1(iot, ioh, NCR_SIGNTR);
208: p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK;
209: p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK;
210:
1.17 mycroft 211: ESP_MISC(("esp_isa_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2));
1.1 pk 212:
213: if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1)))
214: return 0;
215:
216: /* Ok, what is it? */
217: epd->sc_isncr = (vers & ISNCR);
218: epd->sc_rev = ((vers & REV_MASK) == ISESP406) ?
219: NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408;
220:
221: /* What do the jumpers tell us? */
222: jmp = bus_space_read_1(iot, ioh, NCR_JMP);
223:
224: epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000;
225: epd->sc_parity = jmp & NCRJMP_J2;
226: epd->sc_sync = jmp & NCRJMP_J4;
227: epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6;
228: switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) {
229: case NCRJMP_J0 | NCRJMP_J1:
230: epd->sc_irq = 11;
231: break;
232: case NCRJMP_J0:
233: epd->sc_irq = 10;
234: break;
235: case NCRJMP_J1:
236: epd->sc_irq = 15;
237: break;
238: default:
239: epd->sc_irq = 12;
240: break;
241: }
242:
1.19 mycroft 243: bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5);
1.1 pk 244:
245: /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support
246: * NCRESPCFG3_FCLK even though it is documented. A bad
247: * batch of chips perhaps?
248: */
249: bus_space_write_1(iot, ioh, NCR_ESPCFG3,
250: bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK);
251: epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3)
252: & NCRESPCFG3_FCLK;
253:
254: return 1;
255: }
256:
257: void
1.17 mycroft 258: esp_isa_init(esc, epd)
259: struct esp_isa_softc *esc;
260: struct esp_isa_probe_data *epd;
1.1 pk 261: {
262: struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
263:
1.17 mycroft 264: ESP_TRACE(("[esp_isa_init] "));
1.1 pk 265:
266: /*
267: * Set up the glue for MI code early; we use some of it here.
268: */
1.17 mycroft 269: sc->sc_glue = &esp_isa_glue;
1.1 pk 270:
271: sc->sc_rev = epd->sc_rev;
272: sc->sc_id = epd->sc_id;
273:
274: /* If we could set NCRESPCFG3_FCLK earlier, we can really move */
275: sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3);
276: if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) {
277: sc->sc_freq = 40;
278: sc->sc_cfg3 |= NCRESPCFG3_FCLK;
1.19 mycroft 279: } else
1.1 pk 280: sc->sc_freq = 24;
281:
282: /* Setup the register defaults */
283: sc->sc_cfg1 = sc->sc_id;
284: if (epd->sc_parity)
285: sc->sc_cfg1 |= NCRCFG1_PARENB;
286: sc->sc_cfg2 = NCRCFG2_SCSI2;
287: sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI;
1.19 mycroft 288: sc->sc_cfg4 = epd->sc_cfg4;
289: sc->sc_cfg5 = epd->sc_cfg5;
1.1 pk 290:
291: /*
292: * This is the value used to start sync negotiations
293: * Note that the NCR register "SYNCTP" is programmed
294: * in "clocks per byte", and has a minimum value of 4.
295: * The SCSI period used in negotiation is one-fourth
296: * of the time (in nanoseconds) needed to transfer one byte.
297: * Since the chip's clock is given in MHz, we have the following
298: * formula: 4 * period = (1000 / freq) * 4
299: */
300: if (epd->sc_sync)
301: {
302: #ifdef DIAGNOSTIC
303: printf("%s: sync requested, but not supported; will do async\n",
304: sc->sc_dev.dv_xname);
305: #endif
306: epd->sc_sync = 0;
307: }
308:
309: sc->sc_minsync = 0;
310:
311: /* Really no limit, but since we want to fit into the TCR... */
312: sc->sc_maxxfer = 64 * 1024;
313: }
314:
315: /*
316: * Check the slots looking for a board we recognise
317: * If we find one, note it's address (slot) and call
318: * the actual probe routine to check it out.
319: */
320: int
321: esp_isa_match(parent, match, aux)
322: struct device *parent;
1.8 drochner 323: struct cfdata *match;
324: void *aux;
1.1 pk 325: {
326: struct isa_attach_args *ia = aux;
327: bus_space_tag_t iot = ia->ia_iot;
328: bus_space_handle_t ioh;
1.17 mycroft 329: struct esp_isa_probe_data epd;
1.1 pk 330: int rv;
331:
1.24 christos 332: if (ia->ia_nio < 1)
333: return (0);
334: if (ia->ia_nirq < 1)
335: return (0);
336: if (ia->ia_ndrq < 1)
337: return (0);
338:
339: if (ISA_DIRECT_CONFIG(ia))
340: return (0);
341:
1.1 pk 342: ESP_TRACE(("[esp_isa_match] "));
343:
1.27.6.1 skrll 344: if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
1.1 pk 345: return 0;
346:
1.24 christos 347: if (bus_space_map(iot, ia->ia_io[0].ir_addr, ESP_ISA_IOSIZE, 0, &ioh))
1.1 pk 348: return 0;
349:
1.17 mycroft 350: rv = esp_isa_find(iot, ioh, &epd);
1.1 pk 351:
352: bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE);
353:
354: if (rv) {
1.27.6.1 skrll 355: if (ia->ia_irq[0].ir_irq != ISA_UNKNOWN_IRQ &&
1.24 christos 356: ia->ia_irq[0].ir_irq != epd.sc_irq) {
1.1 pk 357: #ifdef DIAGNOSTIC
1.8 drochner 358: printf("esp_isa_match: configured IRQ (%0d) does not "
359: "match board IRQ (%0d), device not configured\n",
1.24 christos 360: ia->ia_irq[0].ir_irq, epd.sc_irq);
1.1 pk 361: #endif
362: return 0;
363: }
1.24 christos 364: ia->ia_irq[0].ir_irq = epd.sc_irq;
365: ia->ia_iomem[0].ir_size = 0;
366: ia->ia_io[0].ir_size = ESP_ISA_IOSIZE;
1.1 pk 367: }
368: return (rv);
369: }
370:
371: /*
372: * Attach this instance, and then all the sub-devices
373: */
374: void
375: esp_isa_attach(parent, self, aux)
376: struct device *parent, *self;
377: void *aux;
378: {
379: struct isa_attach_args *ia = aux;
1.17 mycroft 380: struct esp_isa_softc *esc = (void *)self;
1.1 pk 381: struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
382: bus_space_tag_t iot = ia->ia_iot;
383: bus_space_handle_t ioh;
1.17 mycroft 384: struct esp_isa_probe_data epd;
1.1 pk 385: isa_chipset_tag_t ic = ia->ia_ic;
1.11 thorpej 386: int error;
1.1 pk 387:
388: printf("\n");
389: ESP_TRACE(("[esp_isa_attach] "));
390:
1.24 christos 391: if (bus_space_map(iot, ia->ia_io[0].ir_addr, ESP_ISA_IOSIZE, 0, &ioh)) {
1.6 thorpej 392: printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname);
393: return;
394: }
1.1 pk 395:
1.17 mycroft 396: if (!esp_isa_find(iot, ioh, &epd)) {
397: printf("%s: esp_isa_find failed\n", sc->sc_dev.dv_xname);
1.6 thorpej 398: return;
399: }
1.1 pk 400:
1.27.6.1 skrll 401: if (ia->ia_drq[0].ir_drq != ISA_UNKNOWN_DRQ) {
1.24 christos 402: if ((error = isa_dmacascade(ic, ia->ia_drq[0].ir_drq)) != 0) {
1.11 thorpej 403: printf("%s: unable to cascade DRQ, error = %d\n",
404: sc->sc_dev.dv_xname, error);
405: return;
406: }
407: }
1.1 pk 408:
1.24 christos 409: esc->sc_ih = isa_intr_establish(ic, ia->ia_irq[0].ir_irq, IST_EDGE,
410: IPL_BIO, ncr53c9x_intr, esc);
1.1 pk 411: if (esc->sc_ih == NULL) {
412: printf("%s: couldn't establish interrupt\n",
413: sc->sc_dev.dv_xname);
414: return;
415: }
416:
417: esc->sc_ioh = ioh;
418: esc->sc_iot = iot;
1.17 mycroft 419: esp_isa_init(esc, &epd);
1.1 pk 420:
421: printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname,
422: epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no ");
423: printf("%s", sc->sc_dev.dv_xname);
424:
425: /*
426: * Now try to attach all the sub-devices
427: */
1.22 bouyer 428: sc->sc_adapter.adapt_minphys = minphys;
429: sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
430: ncr53c9x_attach(sc);
1.1 pk 431: }
432:
433: /*
434: * Glue functions.
435: */
436: u_char
1.17 mycroft 437: esp_isa_read_reg(sc, reg)
1.1 pk 438: struct ncr53c9x_softc *sc;
439: int reg;
440: {
1.17 mycroft 441: struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
1.1 pk 442: u_char v;
443:
444: v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg);
445:
1.17 mycroft 446: ESP_REGS(("[esp_isa_read_reg CRS%c 0x%02x=0x%02x] ",
1.1 pk 447: (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) &
448: NCRCFG4_CRS1) ? '1' : '0', reg, v));
449:
450: return v;
451: }
452:
453: void
1.17 mycroft 454: esp_isa_write_reg(sc, reg, val)
1.1 pk 455: struct ncr53c9x_softc *sc;
456: int reg;
457: u_char val;
458: {
1.17 mycroft 459: struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
1.1 pk 460: u_char v = val;
461:
462: if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) {
463: v = NCRCMD_TRANS;
464: }
465:
1.17 mycroft 466: ESP_REGS(("[esp_isa_write_reg CRS%c 0x%02x=0x%02x] ",
1.1 pk 467: (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) &
468: NCRCFG4_CRS1) ? '1' : '0', reg, v));
469:
470: bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v);
471: }
472:
473: int
1.17 mycroft 474: esp_isa_dma_isintr(sc)
1.1 pk 475: struct ncr53c9x_softc *sc;
476: {
1.17 mycroft 477: ESP_TRACE(("[esp_isa_dma_isintr] "));
1.1 pk 478:
479: return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT;
480: }
481:
482: void
1.17 mycroft 483: esp_isa_dma_reset(sc)
1.1 pk 484: struct ncr53c9x_softc *sc;
485: {
1.17 mycroft 486: struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
1.1 pk 487:
1.17 mycroft 488: ESP_TRACE(("[esp_isa_dma_reset] "));
1.1 pk 489:
490: esc->sc_active = 0;
491: esc->sc_tc = 0;
492: }
493:
494: int
1.17 mycroft 495: esp_isa_dma_intr(sc)
1.1 pk 496: struct ncr53c9x_softc *sc;
497: {
1.17 mycroft 498: struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
1.1 pk 499: u_char *p;
500: u_int espphase, espstat, espintr;
501: int cnt;
502:
1.17 mycroft 503: ESP_TRACE(("[esp_isa_dma_intr] "));
1.1 pk 504:
505: if (esc->sc_active == 0) {
506: printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname);
507: return -1;
508: }
509:
510: if ((sc->sc_espintr & NCRINTR_BS) == 0) {
511: esc->sc_active = 0;
512: return 0;
513: }
514:
515: cnt = *esc->sc_pdmalen;
516: if (*esc->sc_pdmalen == 0) {
517: printf("%s: data interrupt, but no count left\n",
518: sc->sc_dev.dv_xname);
519: }
520:
521: p = *esc->sc_dmaaddr;
522: espphase = sc->sc_phase;
523: espstat = (u_int) sc->sc_espstat;
524: espintr = (u_int) sc->sc_espintr;
525: do {
526: if (esc->sc_datain) {
527: *p++ = NCR_READ_REG(sc, NCR_FIFO);
528: cnt--;
529: if (espphase == DATA_IN_PHASE) {
530: NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS);
531: } else {
532: esc->sc_active = 0;
533: }
534: } else {
535: if ( (espphase == DATA_OUT_PHASE)
536: || (espphase == MESSAGE_OUT_PHASE)) {
537: NCR_WRITE_REG(sc, NCR_FIFO, *p++);
538: cnt--;
539: NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS);
540: } else {
541: esc->sc_active = 0;
542: }
543: }
544:
545: if (esc->sc_active) {
1.20 tsutsui 546: while (!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT));
1.1 pk 547: espstat = NCR_READ_REG(sc, NCR_STAT);
548: espintr = NCR_READ_REG(sc, NCR_INTR);
549: espphase = (espintr & NCRINTR_DIS)
550: ? /* Disconnected */ BUSFREE_PHASE
551: : espstat & PHASE_MASK;
552: }
553: } while (esc->sc_active && espintr);
554: sc->sc_phase = espphase;
555: sc->sc_espstat = (u_char) espstat;
556: sc->sc_espintr = (u_char) espintr;
557: *esc->sc_dmaaddr = p;
558: *esc->sc_pdmalen = cnt;
559:
560: if (*esc->sc_pdmalen == 0) {
561: esc->sc_tc = NCRSTAT_TC;
562: }
563: sc->sc_espstat |= esc->sc_tc;
564: return 0;
565: }
566:
567: int
1.17 mycroft 568: esp_isa_dma_setup(sc, addr, len, datain, dmasize)
1.1 pk 569: struct ncr53c9x_softc *sc;
570: caddr_t *addr;
571: size_t *len;
572: int datain;
573: size_t *dmasize;
574: {
1.17 mycroft 575: struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
1.1 pk 576:
1.17 mycroft 577: ESP_TRACE(("[esp_isa_dma_setup] "));
1.1 pk 578:
579: esc->sc_dmaaddr = addr;
580: esc->sc_pdmalen = len;
581: esc->sc_datain = datain;
582: esc->sc_dmasize = *dmasize;
583: esc->sc_tc = 0;
584:
585: return 0;
586: }
587:
588: void
1.17 mycroft 589: esp_isa_dma_go(sc)
1.1 pk 590: struct ncr53c9x_softc *sc;
591: {
1.17 mycroft 592: struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
1.1 pk 593:
1.17 mycroft 594: ESP_TRACE(("[esp_isa_dma_go] "));
1.1 pk 595:
596: esc->sc_active = 1;
597: }
598:
599: void
1.17 mycroft 600: esp_isa_dma_stop(sc)
1.1 pk 601: struct ncr53c9x_softc *sc;
602: {
1.17 mycroft 603: ESP_TRACE(("[esp_isa_dma_stop] "));
1.1 pk 604: }
605:
606: int
1.17 mycroft 607: esp_isa_dma_isactive(sc)
1.1 pk 608: struct ncr53c9x_softc *sc;
609: {
1.17 mycroft 610: struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
1.1 pk 611:
1.17 mycroft 612: ESP_TRACE(("[esp_isa_dma_isactive] "));
1.1 pk 613:
614: return esc->sc_active;
615: }
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