Annotation of src/sys/dev/ic/wdc.c, Revision 1.49
1.49 ! bouyer 1: /* $NetBSD: wdc.c,v 1.48 1998/12/02 10:52:25 bouyer Exp $ */
1.31 bouyer 2:
3:
4: /*
5: * Copyright (c) 1998 Manuel Bouyer. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Manuel Bouyer.
18: * 4. The name of the author may not be used to endorse or promote products
19: * derived from this software without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31: */
1.2 bouyer 32:
1.27 mycroft 33: /*-
34: * Copyright (c) 1998 The NetBSD Foundation, Inc.
35: * All rights reserved.
1.2 bouyer 36: *
1.27 mycroft 37: * This code is derived from software contributed to The NetBSD Foundation
38: * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
1.12 cgd 39: *
1.2 bouyer 40: * Redistribution and use in source and binary forms, with or without
41: * modification, are permitted provided that the following conditions
42: * are met:
43: * 1. Redistributions of source code must retain the above copyright
44: * notice, this list of conditions and the following disclaimer.
45: * 2. Redistributions in binary form must reproduce the above copyright
46: * notice, this list of conditions and the following disclaimer in the
47: * documentation and/or other materials provided with the distribution.
48: * 3. All advertising materials mentioning features or use of this software
49: * must display the following acknowledgement:
1.27 mycroft 50: * This product includes software developed by the NetBSD
51: * Foundation, Inc. and its contributors.
52: * 4. Neither the name of The NetBSD Foundation nor the names of its
53: * contributors may be used to endorse or promote products derived
54: * from this software without specific prior written permission.
1.2 bouyer 55: *
1.27 mycroft 56: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
57: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
58: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
59: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
60: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
61: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
62: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
63: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
64: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
65: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
66: * POSSIBILITY OF SUCH DAMAGE.
1.2 bouyer 67: */
68:
1.12 cgd 69: /*
70: * CODE UNTESTED IN THE CURRENT REVISION:
1.31 bouyer 71: *
1.12 cgd 72: */
73:
1.31 bouyer 74: #define WDCDEBUG
75:
1.2 bouyer 76: #include <sys/param.h>
77: #include <sys/systm.h>
78: #include <sys/kernel.h>
79: #include <sys/conf.h>
80: #include <sys/buf.h>
1.31 bouyer 81: #include <sys/device.h>
1.2 bouyer 82: #include <sys/malloc.h>
83: #include <sys/syslog.h>
84: #include <sys/proc.h>
85:
86: #include <vm/vm.h>
87:
88: #include <machine/intr.h>
89: #include <machine/bus.h>
90:
1.17 sakamoto 91: #ifndef __BUS_SPACE_HAS_STREAM_METHODS
1.31 bouyer 92: #define bus_space_write_multi_stream_2 bus_space_write_multi_2
93: #define bus_space_write_multi_stream_4 bus_space_write_multi_4
94: #define bus_space_read_multi_stream_2 bus_space_read_multi_2
95: #define bus_space_read_multi_stream_4 bus_space_read_multi_4
1.17 sakamoto 96: #endif /* __BUS_SPACE_HAS_STREAM_METHODS */
1.16 sakamoto 97:
1.31 bouyer 98: #include <dev/ata/atavar.h>
99: #include <dev/ata/atareg.h>
1.12 cgd 100: #include <dev/ic/wdcreg.h>
101: #include <dev/ic/wdcvar.h>
1.31 bouyer 102:
1.2 bouyer 103: #include "atapibus.h"
104:
1.31 bouyer 105: #define WDCDELAY 100 /* 100 microseconds */
106: #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY)
1.2 bouyer 107: #if 0
1.31 bouyer 108: /* If you enable this, it will report any delays more than WDCDELAY * N long. */
1.2 bouyer 109: #define WDCNDELAY_DEBUG 50
110: #endif
111:
112: LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list;
113:
1.31 bouyer 114: static void __wdcerror __P((struct channel_softc*, char *));
115: static int __wdcwait_reset __P((struct channel_softc *, int));
116: void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *));
117: void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *));
118: int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *));
119: int wdprint __P((void *, const char *));
120:
121:
122: #define DEBUG_INTR 0x01
123: #define DEBUG_XFERS 0x02
124: #define DEBUG_STATUS 0x04
125: #define DEBUG_FUNCS 0x08
126: #define DEBUG_PROBE 0x10
127: #ifdef WDCDEBUG
1.32 bouyer 128: int wdcdebug_mask = 0;
1.31 bouyer 129: int wdc_nxfer = 0;
130: #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args
1.2 bouyer 131: #else
1.31 bouyer 132: #define WDCDEBUG_PRINT(args, level)
1.2 bouyer 133: #endif
134:
1.31 bouyer 135: int
136: wdprint(aux, pnp)
137: void *aux;
138: const char *pnp;
139: {
140: struct ata_atapi_attach *aa_link = aux;
141: if (pnp)
142: printf("drive at %s", pnp);
143: printf(" channel %d drive %d", aa_link->aa_channel,
144: aa_link->aa_drv_data->drive);
145: return (UNCONF);
146: }
1.2 bouyer 147:
1.31 bouyer 148: int
149: atapi_print(aux, pnp)
150: void *aux;
151: const char *pnp;
152: {
153: struct ata_atapi_attach *aa_link = aux;
154: if (pnp)
155: printf("atapibus at %s", pnp);
156: printf(" channel %d", aa_link->aa_channel);
157: return (UNCONF);
158: }
159:
160: /* Test to see controller with at last one attached drive is there.
161: * Returns a bit for each possible drive found (0x01 for drive 0,
162: * 0x02 for drive 1).
163: * Logic:
164: * - If a status register is at 0xff, assume there is no drive here
165: * (ISA has pull-up resistors). If no drive at all -> return.
166: * - reset the controller, wait for it to complete (may take up to 31s !).
167: * If timeout -> return.
168: * - test ATA/ATAPI signatures. If at last one drive found -> return.
169: * - try an ATA command on the master.
1.12 cgd 170: */
1.31 bouyer 171:
1.2 bouyer 172: int
1.31 bouyer 173: wdcprobe(chp)
174: struct channel_softc *chp;
1.12 cgd 175: {
1.31 bouyer 176: u_int8_t st0, st1, sc, sn, cl, ch;
177: u_int8_t ret_value = 0x03;
178: u_int8_t drive;
179:
180: /*
181: * Sanity check to see if the wdc channel responds at all.
182: */
183:
1.43 kenh 184: if (chp->wdc == NULL ||
185: (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) {
186: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
187: WDSD_IBM);
188: delay(1);
189: st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
190: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
191: WDSD_IBM | 0x10);
192: delay(1);
193: st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
194:
195: WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n",
196: chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
197: chp->channel, st0, st1), DEBUG_PROBE);
198:
199: if (st0 == 0xff)
200: ret_value &= ~0x01;
201: if (st1 == 0xff)
202: ret_value &= ~0x02;
203: if (ret_value == 0)
204: return 0;
205: }
1.42 thorpej 206:
1.31 bouyer 207: /* assert SRST, wait for reset to complete */
208: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
209: WDSD_IBM);
210: delay(1);
211: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
212: WDCTL_RST | WDCTL_IDS);
213: DELAY(1000);
214: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
215: WDCTL_IDS);
216: delay(1000);
217: (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error);
218: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
219: delay(1);
220:
221: ret_value = __wdcwait_reset(chp, ret_value);
222: WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n",
223: chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel,
224: ret_value), DEBUG_PROBE);
1.26 drochner 225:
1.31 bouyer 226: /* if reset failed, there's nothing here */
227: if (ret_value == 0)
228: return 0;
1.2 bouyer 229:
1.31 bouyer 230: /*
231: * Test presence of drives. First test register signatures looking for
232: * ATAPI devices , then rescan and try an ATA command, in case it's an
233: * old drive.
234: * Fill in drive_flags accordingly
235: */
236: for (drive = 0; drive < 2; drive++) {
237: if ((ret_value & (0x01 << drive)) == 0)
238: continue;
239: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
240: WDSD_IBM | (drive << 4));
241: delay(1);
242: /* Save registers contents */
243: sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt);
244: sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector);
245: cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo);
246: ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi);
247:
248: WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x "
249: "cl=0x%x ch=0x%x\n",
250: chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
251: chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE);
252: if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) {
253: chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI;
254: }
255: }
256: for (drive = 0; drive < 2; drive++) {
257: if ((ret_value & (0x01 << drive)) == 0 ||
258: (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0)
259: continue;
260: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
261: WDSD_IBM | (drive << 4));
262: delay(1);
1.2 bouyer 263: /*
1.31 bouyer 264: * Maybe it's an old device, so don't rely on ATA sig.
265: * Test registers writability (Error register not writable,
266: * but cyllo is), then try an ATA command.
1.2 bouyer 267: */
1.31 bouyer 268: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58);
269: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5);
270: if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) ==
271: 0x58 ||
272: bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) !=
273: 0xa5) {
274: WDCDEBUG_PRINT(("%s:%d:%d: register writability "
275: "failed\n",
276: chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
277: chp->channel, drive), DEBUG_PROBE);
278: ret_value &= ~(0x01 << drive);
279: continue;
280: }
281: if (wait_for_ready(chp, 10000) != 0) {
282: WDCDEBUG_PRINT(("%s:%d:%d: not ready\n",
283: chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
284: chp->channel, drive), DEBUG_PROBE);
285: ret_value &= ~(0x01 << drive);
286: continue;
287: }
288: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command,
289: WDCC_DIAGNOSE);
290: if (wait_for_ready(chp, 10000) == 0) {
291: chp->ch_drive[drive].drive_flags |=
292: DRIVE_ATA;
1.7 bouyer 293: } else {
1.31 bouyer 294: WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n",
295: chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
296: chp->channel, drive), DEBUG_PROBE);
297: ret_value &= ~(0x01 << drive);
1.2 bouyer 298: }
1.7 bouyer 299: }
1.31 bouyer 300: return (ret_value);
301: }
302:
303: void
304: wdcattach(chp)
305: struct channel_softc *chp;
306: {
1.44 thorpej 307: int channel_flags, ctrl_flags, i, error;
1.31 bouyer 308: struct ata_atapi_attach aa_link;
309:
310: LIST_INIT(&xfer_free_list);
311: for (i = 0; i < 2; i++) {
312: chp->ch_drive[i].chnl_softc = chp;
313: chp->ch_drive[i].drive = i;
314: /* If controller can't do 16bit flag the drives as 32bit */
315: if ((chp->wdc->cap &
316: (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
317: WDC_CAPABILITY_DATA32)
318: chp->ch_drive[i].drive_flags |= DRIVE_CAP32;
319: }
320:
1.44 thorpej 321: if ((error = wdc_addref(chp)) != 0) {
322: printf("%s: unable to enable controller\n",
323: chp->wdc->sc_dev.dv_xname);
324: return;
325: }
326:
327: if (wdcprobe(chp) == 0) {
328: /* If no drives, abort attach here. */
329: wdc_delref(chp);
330: return;
331: }
1.31 bouyer 332:
333: TAILQ_INIT(&chp->ch_queue->sc_xfer);
334: ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags;
335: channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff;
336:
337: WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n",
338: chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags),
339: DEBUG_PROBE);
1.12 cgd 340:
341: /*
1.31 bouyer 342: * Attach an ATAPI bus, if needed.
1.12 cgd 343: */
1.31 bouyer 344: if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) ||
345: (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) {
346: #if NATAPIBUS > 0
347: wdc_atapibus_attach(chp);
348: #else
349: /*
350: * Fills in a fake aa_link and call config_found, so that
351: * the config machinery will print
352: * "atapibus at xxx not configured"
353: */
354: memset(&aa_link, 0, sizeof(struct ata_atapi_attach));
355: aa_link.aa_type = T_ATAPI;
356: aa_link.aa_channel = chp->channel;
357: aa_link.aa_openings = 1;
358: aa_link.aa_drv_data = 0;
359: aa_link.aa_bus_private = NULL;
360: (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link,
361: atapi_print);
362: #endif
363: }
364:
365: for (i = 0; i < 2; i++) {
366: if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) {
367: continue;
368: }
369: memset(&aa_link, 0, sizeof(struct ata_atapi_attach));
370: aa_link.aa_type = T_ATA;
371: aa_link.aa_channel = chp->channel;
372: aa_link.aa_openings = 1;
373: aa_link.aa_drv_data = &chp->ch_drive[i];
374: if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint))
375: wdc_probe_caps(&chp->ch_drive[i]);
1.32 bouyer 376: }
377:
378: /*
379: * reset drive_flags for unnatached devices, reset state for attached
380: * ones
381: */
382: for (i = 0; i < 2; i++) {
383: if (chp->ch_drive[i].drv_softc == NULL)
384: chp->ch_drive[i].drive_flags = 0;
385: else
386: chp->ch_drive[i].state = 0;
1.2 bouyer 387: }
1.12 cgd 388:
389: /*
1.31 bouyer 390: * Reset channel. The probe, with some combinations of ATA/ATAPI
391: * devices keep it in a mostly working, but strange state (with busy
392: * led on)
1.12 cgd 393: */
1.31 bouyer 394: if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) {
395: wdcreset(chp, VERBOSE);
396: /*
397: * Read status registers to avoid spurious interrupts.
398: */
399: for (i = 1; i >= 0; i--) {
400: if (chp->ch_drive[i].drive_flags & DRIVE) {
401: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh,
402: wd_sdh, WDSD_IBM | (i << 4));
403: if (wait_for_unbusy(chp, 10000) < 0)
404: printf("%s:%d:%d: device busy\n",
405: chp->wdc->sc_dev.dv_xname,
406: chp->channel, i);
407: }
408: }
409: }
1.44 thorpej 410: wdc_delref(chp);
1.31 bouyer 411: }
412:
413: /*
414: * Start I/O on a controller, for the given channel.
415: * The first xfer may be not for our channel if the channel queues
416: * are shared.
417: */
418: void
1.45 drochner 419: wdcstart(chp)
420: struct channel_softc *chp;
1.31 bouyer 421: {
422: struct wdc_xfer *xfer;
1.38 bouyer 423:
424: #ifdef WDC_DIAGNOSTIC
425: int spl1, spl2;
426:
427: spl1 = splbio();
428: spl2 = splbio();
429: if (spl2 != spl1) {
430: printf("wdcstart: not at splbio()\n");
431: panic("wdcstart");
432: }
433: splx(spl2);
434: splx(spl1);
435: #endif /* WDC_DIAGNOSTIC */
1.12 cgd 436:
1.31 bouyer 437: /* is there a xfer ? */
1.45 drochner 438: if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL)
1.31 bouyer 439: return;
1.47 bouyer 440:
441: /* adjust chp, in case we have a shared queue */
1.49 ! bouyer 442: chp = xfer->chp;
1.47 bouyer 443:
1.31 bouyer 444: if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) {
445: return; /* channel aleady active */
446: }
447: #ifdef DIAGNOSTIC
448: if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0)
449: panic("wdcstart: channel waiting for irq\n");
450: #endif
1.45 drochner 451: if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK)
452: if (!(*chp->wdc->claim_hw)(chp, 0))
1.31 bouyer 453: return;
1.12 cgd 454:
1.31 bouyer 455: WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer,
1.49 ! bouyer 456: chp->channel, xfer->drive), DEBUG_XFERS);
1.31 bouyer 457: chp->ch_flags |= WDCF_ACTIVE;
1.37 bouyer 458: if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) {
459: chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET;
460: chp->ch_drive[xfer->drive].state = 0;
461: }
1.31 bouyer 462: xfer->c_start(chp, xfer);
463: }
1.2 bouyer 464:
1.31 bouyer 465: /* restart an interrupted I/O */
466: void
467: wdcrestart(v)
468: void *v;
469: {
470: struct channel_softc *chp = v;
471: int s;
1.2 bouyer 472:
1.31 bouyer 473: s = splbio();
1.45 drochner 474: wdcstart(chp);
1.31 bouyer 475: splx(s);
1.2 bouyer 476: }
1.31 bouyer 477:
1.2 bouyer 478:
1.31 bouyer 479: /*
480: * Interrupt routine for the controller. Acknowledge the interrupt, check for
481: * errors on the current operation, mark it done if necessary, and start the
482: * next request. Also check for a partially done transfer, and continue with
483: * the next chunk if so.
484: */
1.12 cgd 485: int
1.31 bouyer 486: wdcintr(arg)
487: void *arg;
1.12 cgd 488: {
1.31 bouyer 489: struct channel_softc *chp = arg;
490: struct wdc_xfer *xfer;
1.12 cgd 491:
1.31 bouyer 492: if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) {
493: #if 0
494: /* Clear the pending interrupt and abort. */
495: u_int8_t s =
496: bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
497: #ifdef WDCDEBUG
498: u_int8_t e =
499: bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error);
500: u_int8_t i =
501: bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt);
502: #else
503: bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error);
504: bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt);
505: #endif
1.12 cgd 506:
1.31 bouyer 507: WDCDEBUG_PRINT(("wdcintr: inactive controller, "
508: "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR);
509:
510: if (s & WDCS_DRQ) {
511: int len;
512: len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
513: wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot,
514: chp->cmd_ioh, wd_cyl_hi);
515: WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n",
516: len), DEBUG_INTR);
517: wdcbit_bucket (chp, len);
518: }
519: #else
520: WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR);
521: #endif
522: return 0;
523: }
1.12 cgd 524:
1.31 bouyer 525: WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR);
526: untimeout(wdctimeout, chp);
527: chp->ch_flags &= ~WDCF_IRQ_WAIT;
528: xfer = chp->ch_queue->sc_xfer.tqh_first;
529: return xfer->c_intr(chp, xfer);
1.12 cgd 530: }
531:
1.31 bouyer 532: /* Put all disk in RESET state */
533: void wdc_reset_channel(drvp)
534: struct ata_drive_datas *drvp;
1.2 bouyer 535: {
1.31 bouyer 536: struct channel_softc *chp = drvp->chnl_softc;
1.2 bouyer 537: int drive;
1.34 bouyer 538: WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n",
539: chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive),
540: DEBUG_FUNCS);
1.31 bouyer 541: (void) wdcreset(chp, VERBOSE);
542: for (drive = 0; drive < 2; drive++) {
543: chp->ch_drive[drive].state = 0;
1.12 cgd 544: }
1.31 bouyer 545: }
1.12 cgd 546:
1.31 bouyer 547: int
548: wdcreset(chp, verb)
549: struct channel_softc *chp;
550: int verb;
551: {
552: int drv_mask1, drv_mask2;
1.2 bouyer 553:
1.31 bouyer 554: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
555: WDSD_IBM); /* master */
556: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
557: WDCTL_RST | WDCTL_IDS);
558: delay(1000);
559: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
560: WDCTL_IDS);
561: delay(1000);
562: (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error);
563: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
564: WDCTL_4BIT);
1.2 bouyer 565:
1.31 bouyer 566: drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00;
567: drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00;
568: drv_mask2 = __wdcwait_reset(chp, drv_mask1);
569: if (verb && drv_mask2 != drv_mask1) {
570: printf("%s channel %d: reset failed for",
571: chp->wdc->sc_dev.dv_xname, chp->channel);
572: if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0)
573: printf(" drive 0");
574: if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0)
575: printf(" drive 1");
576: printf("\n");
577: }
578: return (drv_mask1 != drv_mask2) ? 1 : 0;
579: }
580:
581: static int
582: __wdcwait_reset(chp, drv_mask)
583: struct channel_softc *chp;
584: int drv_mask;
585: {
586: int timeout;
587: u_int8_t st0, st1;
588: /* wait for BSY to deassert */
589: for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) {
590: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
591: WDSD_IBM); /* master */
592: delay(1);
593: st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
594: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
595: WDSD_IBM | 0x10); /* slave */
596: delay(1);
597: st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
598:
599: if ((drv_mask & 0x01) == 0) {
600: /* no master */
601: if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) {
602: /* No master, slave is ready, it's done */
603: return drv_mask;
604: }
605: } else if ((drv_mask & 0x02) == 0) {
606: /* no slave */
607: if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) {
608: /* No slave, master is ready, it's done */
609: return drv_mask;
610: }
1.2 bouyer 611: } else {
1.31 bouyer 612: /* Wait for both master and slave to be ready */
613: if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) {
614: return drv_mask;
1.2 bouyer 615: }
616: }
1.31 bouyer 617: delay(WDCDELAY);
1.2 bouyer 618: }
1.31 bouyer 619: /* Reset timed out. Maybe it's because drv_mask was not rigth */
620: if (st0 & WDCS_BSY)
621: drv_mask &= ~0x01;
622: if (st1 & WDCS_BSY)
623: drv_mask &= ~0x02;
624: return drv_mask;
1.2 bouyer 625: }
626:
627: /*
1.31 bouyer 628: * Wait for a drive to be !BSY, and have mask in its status register.
629: * return -1 for a timeout after "timeout" ms.
1.2 bouyer 630: */
1.31 bouyer 631: int
632: wdcwait(chp, mask, bits, timeout)
633: struct channel_softc *chp;
634: int mask, bits, timeout;
1.2 bouyer 635: {
1.31 bouyer 636: u_char status;
637: int time = 0;
638: #ifdef WDCNDELAY_DEBUG
639: extern int cold;
640: #endif
1.34 bouyer 641: WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname,
642: chp->channel), DEBUG_STATUS);
1.31 bouyer 643: chp->ch_error = 0;
644:
645: timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */
1.2 bouyer 646:
1.31 bouyer 647: for (;;) {
648: chp->ch_status = status =
649: bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
650: if ((status & WDCS_BSY) == 0 && (status & mask) == bits)
651: break;
652: if (++time > timeout) {
653: WDCDEBUG_PRINT(("wdcwait: timeout, status %x "
654: "error %x\n", status,
655: bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
656: wd_error)),
657: DEBUG_STATUS);
658: return -1;
659: }
660: delay(WDCDELAY);
1.2 bouyer 661: }
1.31 bouyer 662: if (status & WDCS_ERR)
663: chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
664: wd_error);
665: #ifdef WDCNDELAY_DEBUG
666: /* After autoconfig, there should be no long delays. */
667: if (!cold && time > WDCNDELAY_DEBUG) {
668: struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first;
669: if (xfer == NULL)
670: printf("%s channel %d: warning: busy-wait took %dus\n",
671: chp->wdc->sc_dev.dv_xname, chp->channel,
672: WDCDELAY * time);
673: else
674: printf("%s:%d:%d: warning: busy-wait took %dus\n",
1.49 ! bouyer 675: chp->wdc->sc_dev.dv_xname, chp->channel,
1.31 bouyer 676: xfer->drive,
677: WDCDELAY * time);
1.2 bouyer 678: }
679: #endif
1.31 bouyer 680: return 0;
1.2 bouyer 681: }
682:
1.31 bouyer 683: void
684: wdctimeout(arg)
685: void *arg;
1.2 bouyer 686: {
1.31 bouyer 687: struct channel_softc *chp = (struct channel_softc *)arg;
688: struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first;
689: int s;
1.2 bouyer 690:
1.31 bouyer 691: WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS);
692:
693: s = splbio();
694: if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) {
695: __wdcerror(chp, "lost interrupt");
696: printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ?
697: "atapi":"ata");
698: printf("\tc_bcount: %d\n", xfer->c_bcount);
699: printf("\tc_skip: %d\n", xfer->c_skip);
700: /*
701: * Call the interrupt routine. If we just missed and interrupt,
702: * it will do what's needed. Else, it will take the needed
703: * action (reset the device).
704: */
705: xfer->c_flags |= C_TIMEOU;
706: chp->ch_flags &= ~WDCF_IRQ_WAIT;
707: xfer->c_intr(chp, xfer);
708: } else
709: __wdcerror(chp, "missing untimeout");
710: splx(s);
1.2 bouyer 711: }
712:
1.31 bouyer 713: /*
714: * Probe drive's capabilites, for use by the controller later
715: * Assumes drvp points to an existing drive.
716: * XXX this should be a controller-indep function
717: */
1.2 bouyer 718: void
1.31 bouyer 719: wdc_probe_caps(drvp)
720: struct ata_drive_datas *drvp;
1.2 bouyer 721: {
1.31 bouyer 722: struct ataparams params, params2;
723: struct channel_softc *chp = drvp->chnl_softc;
724: struct device *drv_dev = drvp->drv_softc;
725: struct wdc_softc *wdc = chp->wdc;
726: int i, printed;
727: char *sep = "";
1.48 bouyer 728: int cf_flags;
1.31 bouyer 729:
730: if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) {
731: /* IDENTIFY failed. Can't tell more about the device */
1.2 bouyer 732: return;
733: }
1.31 bouyer 734: if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
735: (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) {
1.2 bouyer 736: /*
1.39 bouyer 737: * Controller claims 16 and 32 bit transfers.
738: * Re-do an IDENTIFY with 32-bit transfers,
1.31 bouyer 739: * and compare results.
1.2 bouyer 740: */
1.31 bouyer 741: drvp->drive_flags |= DRIVE_CAP32;
742: ata_get_params(drvp, AT_POLL, ¶ms2);
743: if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) {
744: /* Not good. fall back to 16bits */
745: drvp->drive_flags &= ~DRIVE_CAP32;
746: } else {
1.39 bouyer 747: printf("%s: 32-bits data port\n", drv_dev->dv_xname);
1.2 bouyer 748: }
749: }
750:
1.31 bouyer 751: /* An ATAPI device is at last PIO mode 3 */
752: if (drvp->drive_flags & DRIVE_ATAPI)
753: drvp->PIO_mode = 3;
1.2 bouyer 754:
755: /*
1.31 bouyer 756: * It's not in the specs, but it seems that some drive
757: * returns 0xffff in atap_extensions when this field is invalid
1.2 bouyer 758: */
1.31 bouyer 759: if (params.atap_extensions != 0xffff &&
760: (params.atap_extensions & WDC_EXT_MODES)) {
761: printed = 0;
762: /*
763: * XXX some drives report something wrong here (they claim to
764: * support PIO mode 8 !). As mode is coded on 3 bits in
765: * SET FEATURE, limit it to 7 (so limit i to 4).
1.39 bouyer 766: * If higther mode than 7 is found, abort.
1.31 bouyer 767: */
1.39 bouyer 768: for (i = 7; i >= 0; i--) {
1.31 bouyer 769: if ((params.atap_piomode_supp & (1 << i)) == 0)
770: continue;
1.39 bouyer 771: if (i > 4)
772: return;
1.31 bouyer 773: /*
774: * See if mode is accepted.
775: * If the controller can't set its PIO mode,
776: * assume the defaults are good, so don't try
777: * to set it
778: */
779: if ((wdc->cap & WDC_CAPABILITY_MODE) != 0)
780: if (ata_set_mode(drvp, 0x08 | (i + 3),
781: AT_POLL) != CMD_OK)
1.2 bouyer 782: continue;
1.31 bouyer 783: if (!printed) {
1.39 bouyer 784: printf("%s: drive supports PIO mode %d",
785: drv_dev->dv_xname, i + 3);
1.31 bouyer 786: sep = ",";
787: printed = 1;
788: }
789: /*
790: * If controller's driver can't set its PIO mode,
791: * get the highter one for the drive.
792: */
793: if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 ||
794: wdc->pio_mode >= i + 3) {
795: drvp->PIO_mode = i + 3;
1.48 bouyer 796: drvp->PIO_cap = i + 3;
1.2 bouyer 797: break;
798: }
799: }
1.31 bouyer 800: if (!printed) {
801: /*
802: * We didn't find a valid PIO mode.
803: * Assume the values returned for DMA are buggy too
804: */
805: return;
1.2 bouyer 806: }
1.35 bouyer 807: drvp->drive_flags |= DRIVE_MODE;
1.31 bouyer 808: printed = 0;
809: for (i = 7; i >= 0; i--) {
810: if ((params.atap_dmamode_supp & (1 << i)) == 0)
811: continue;
812: if ((wdc->cap & WDC_CAPABILITY_DMA) &&
813: (wdc->cap & WDC_CAPABILITY_MODE))
814: if (ata_set_mode(drvp, 0x20 | i, AT_POLL)
815: != CMD_OK)
816: continue;
817: if (!printed) {
818: printf("%s DMA mode %d", sep, i);
819: sep = ",";
820: printed = 1;
821: }
822: if (wdc->cap & WDC_CAPABILITY_DMA) {
823: if ((wdc->cap & WDC_CAPABILITY_MODE) &&
824: wdc->dma_mode < i)
825: continue;
826: drvp->DMA_mode = i;
1.48 bouyer 827: drvp->DMA_cap = i;
1.31 bouyer 828: drvp->drive_flags |= DRIVE_DMA;
829: }
1.2 bouyer 830: break;
831: }
1.31 bouyer 832: if (params.atap_extensions & WDC_EXT_UDMA_MODES) {
833: for (i = 7; i >= 0; i--) {
834: if ((params.atap_udmamode_supp & (1 << i))
835: == 0)
836: continue;
837: if ((wdc->cap & WDC_CAPABILITY_MODE) &&
838: (wdc->cap & WDC_CAPABILITY_UDMA))
839: if (ata_set_mode(drvp, 0x40 | i,
840: AT_POLL) != CMD_OK)
841: continue;
842: printf("%s UDMA mode %d", sep, i);
843: sep = ",";
844: /*
845: * ATA-4 specs says if a mode is supported,
846: * all lower modes shall be supported.
847: * No need to look further.
848: */
849: if (wdc->cap & WDC_CAPABILITY_UDMA) {
850: drvp->UDMA_mode = i;
1.48 bouyer 851: drvp->UDMA_cap = i;
1.31 bouyer 852: drvp->drive_flags |= DRIVE_UDMA;
853: }
854: break;
855: }
856: }
857: printf("\n");
1.48 bouyer 858: }
859: cf_flags = drv_dev->dv_cfdata->cf_flags;
860: if (cf_flags & ATA_CONFIG_PIO_SET) {
861: drvp->PIO_mode =
862: (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF;
863: drvp->drive_flags |= DRIVE_MODE;
864: }
865: if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) {
866: /* don't care about DMA modes */
867: return;
868: }
869: if (cf_flags & ATA_CONFIG_DMA_SET) {
870: if ((cf_flags & ATA_CONFIG_DMA_MODES) ==
871: ATA_CONFIG_DMA_DISABLE) {
872: drvp->drive_flags &= ~DRIVE_DMA;
873: } else {
874: drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >>
875: ATA_CONFIG_DMA_OFF;
876: drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE;
877: }
878: }
879: if (cf_flags & ATA_CONFIG_UDMA_SET) {
880: if ((cf_flags & ATA_CONFIG_UDMA_MODES) ==
881: ATA_CONFIG_UDMA_DISABLE) {
882: drvp->drive_flags &= ~DRIVE_UDMA;
883: } else {
884: drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >>
885: ATA_CONFIG_UDMA_OFF;
886: drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE;
887: }
1.2 bouyer 888: }
889: }
890:
891: int
1.31 bouyer 892: wdc_exec_command(drvp, wdc_c)
893: struct ata_drive_datas *drvp;
894: struct wdc_command *wdc_c;
895: {
896: struct channel_softc *chp = drvp->chnl_softc;
1.2 bouyer 897: struct wdc_xfer *xfer;
1.31 bouyer 898: int s, ret;
1.2 bouyer 899:
1.34 bouyer 900: WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n",
901: chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive),
902: DEBUG_FUNCS);
1.2 bouyer 903:
1.31 bouyer 904: /* set up an xfer and queue. Wait for completion */
905: xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP :
906: WDC_NOSLEEP);
907: if (xfer == NULL) {
908: return WDC_TRY_AGAIN;
909: }
1.2 bouyer 910:
1.31 bouyer 911: if (wdc_c->flags & AT_POLL)
912: xfer->c_flags |= C_POLL;
913: xfer->drive = drvp->drive;
914: xfer->databuf = wdc_c->data;
915: xfer->c_bcount = wdc_c->bcount;
916: xfer->cmd = wdc_c;
917: xfer->c_start = __wdccommand_start;
918: xfer->c_intr = __wdccommand_intr;
1.2 bouyer 919:
1.31 bouyer 920: s = splbio();
921: wdc_exec_xfer(chp, xfer);
922: #ifdef DIAGNOSTIC
923: if ((wdc_c->flags & AT_POLL) != 0 &&
924: (wdc_c->flags & AT_DONE) == 0)
925: panic("wdc_exec_command: polled command not done\n");
1.2 bouyer 926: #endif
1.31 bouyer 927: if (wdc_c->flags & AT_DONE) {
928: ret = WDC_COMPLETE;
929: } else {
930: if (wdc_c->flags & AT_WAIT) {
931: tsleep(wdc_c, PRIBIO, "wdccmd", 0);
932: ret = WDC_COMPLETE;
933: } else {
934: ret = WDC_QUEUED;
1.2 bouyer 935: }
936: }
1.31 bouyer 937: splx(s);
938: return ret;
1.2 bouyer 939: }
940:
941: void
1.31 bouyer 942: __wdccommand_start(chp, xfer)
943: struct channel_softc *chp;
1.2 bouyer 944: struct wdc_xfer *xfer;
1.31 bouyer 945: {
946: int drive = xfer->drive;
947: struct wdc_command *wdc_c = xfer->cmd;
948:
1.34 bouyer 949: WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n",
950: chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive),
951: DEBUG_FUNCS);
1.31 bouyer 952:
953: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
954: WDSD_IBM | (drive << 4));
955: if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask,
956: wdc_c->timeout) != 0) {
957: wdc_c->flags |= AT_TIMEOU;
958: __wdccommand_done(chp, xfer);
959: }
960: wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head,
961: wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp);
962: if ((wdc_c->flags & AT_POLL) == 0) {
963: chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */
964: timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz);
965: return;
1.2 bouyer 966: }
967: /*
1.31 bouyer 968: * Polled command. Wait for drive ready or drq. Done in intr().
969: * Wait for at last 400ns for status bit to be valid.
1.2 bouyer 970: */
1.31 bouyer 971: delay(10);
972: if (__wdccommand_intr(chp, xfer) == 0) {
973: wdc_c->flags |= AT_TIMEOU;
974: __wdccommand_done(chp, xfer);
1.2 bouyer 975: }
976: }
977:
978: int
1.31 bouyer 979: __wdccommand_intr(chp, xfer)
980: struct channel_softc *chp;
981: struct wdc_xfer *xfer;
1.2 bouyer 982: {
1.31 bouyer 983: struct wdc_command *wdc_c = xfer->cmd;
984: int bcount = wdc_c->bcount;
985: char *data = wdc_c->data;
986:
1.34 bouyer 987: WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n",
988: chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR);
1.31 bouyer 989: if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask,
990: wdc_c->timeout)) {
991: wdc_c->flags |= AT_ERROR;
992: __wdccommand_done(chp, xfer);
1.2 bouyer 993: return 1;
994: }
1.31 bouyer 995: if (wdc_c->flags & AT_READ) {
996: if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) {
997: bus_space_read_multi_4(chp->data32iot, chp->data32ioh,
998: 0, (u_int32_t*)data, bcount >> 2);
999: data += bcount & 0xfffffffc;
1000: bcount = bcount & 0x03;
1001: }
1002: if (bcount > 0)
1003: bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh,
1004: wd_data, (u_int16_t *)data, bcount >> 1);
1005: } else if (wdc_c->flags & AT_WRITE) {
1006: if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) {
1007: bus_space_write_multi_4(chp->data32iot, chp->data32ioh,
1008: 0, (u_int32_t*)data, bcount >> 2);
1009: data += bcount & 0xfffffffc;
1010: bcount = bcount & 0x03;
1011: }
1012: if (bcount > 0)
1013: bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh,
1014: wd_data, (u_int16_t *)data, bcount >> 1);
1.2 bouyer 1015: }
1.31 bouyer 1016: __wdccommand_done(chp, xfer);
1017: return 1;
1.2 bouyer 1018: }
1019:
1020: void
1.31 bouyer 1021: __wdccommand_done(chp, xfer)
1022: struct channel_softc *chp;
1023: struct wdc_xfer *xfer;
1.2 bouyer 1024: {
1.31 bouyer 1025: int needdone = xfer->c_flags & C_NEEDDONE;
1026: struct wdc_command *wdc_c = xfer->cmd;
1.2 bouyer 1027:
1.34 bouyer 1028: WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n",
1029: chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS);
1.31 bouyer 1030: if (chp->ch_status & WDCS_DWF)
1031: wdc_c->flags |= AT_DF;
1032: if (chp->ch_status & WDCS_ERR) {
1033: wdc_c->flags |= AT_ERROR;
1034: wdc_c->r_error = chp->ch_error;
1035: }
1036: wdc_c->flags |= AT_DONE;
1.46 kenh 1037: if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF))
1038: == 0) {
1039: wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1040: wd_sdh);
1041: wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1042: wd_cyl_hi) << 8;
1043: wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1044: wd_cyl_lo);
1045: wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1046: wd_sector);
1047: wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1048: wd_seccnt);
1049: wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1050: wd_error);
1051: wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1052: wd_precomp);
1053: }
1.31 bouyer 1054: wdc_free_xfer(chp, xfer);
1055: if (needdone) {
1056: if (wdc_c->flags & AT_WAIT)
1057: wakeup(wdc_c);
1058: else
1059: wdc_c->callback(wdc_c->callback_arg);
1.2 bouyer 1060: }
1.45 drochner 1061: wdcstart(chp);
1.31 bouyer 1062: return;
1.2 bouyer 1063: }
1064:
1065: /*
1.31 bouyer 1066: * Send a command. The drive should be ready.
1.2 bouyer 1067: * Assumes interrupts are blocked.
1068: */
1.31 bouyer 1069: void
1070: wdccommand(chp, drive, command, cylin, head, sector, count, precomp)
1071: struct channel_softc *chp;
1072: u_int8_t drive;
1073: u_int8_t command;
1074: u_int16_t cylin;
1075: u_int8_t head, sector, count, precomp;
1076: {
1077: WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d "
1078: "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname,
1079: chp->channel, drive, command, cylin, head, sector, count, precomp),
1080: DEBUG_FUNCS);
1081:
1082: /* Select drive, head, and addressing mode. */
1083: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
1084: WDSD_IBM | (drive << 4) | head);
1085: /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */
1086: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp,
1087: precomp);
1088: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin);
1089: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8);
1090: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector);
1091: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count);
1.2 bouyer 1092:
1.31 bouyer 1093: /* Send command. */
1094: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command);
1095: return;
1.2 bouyer 1096: }
1097:
1098: /*
1.31 bouyer 1099: * Simplified version of wdccommand(). Unbusy/ready/drq must be
1100: * tested by the caller.
1.2 bouyer 1101: */
1.31 bouyer 1102: void
1103: wdccommandshort(chp, drive, command)
1104: struct channel_softc *chp;
1105: int drive;
1106: int command;
1.2 bouyer 1107: {
1108:
1.31 bouyer 1109: WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n",
1110: chp->wdc->sc_dev.dv_xname, chp->channel, drive, command),
1111: DEBUG_FUNCS);
1.2 bouyer 1112:
1.31 bouyer 1113: /* Select drive. */
1114: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
1115: WDSD_IBM | (drive << 4));
1.2 bouyer 1116:
1.31 bouyer 1117: bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command);
1118: }
1.2 bouyer 1119:
1.31 bouyer 1120: /* Add a command to the queue and start controller. Must be called at splbio */
1.2 bouyer 1121:
1122: void
1.31 bouyer 1123: wdc_exec_xfer(chp, xfer)
1124: struct channel_softc *chp;
1.2 bouyer 1125: struct wdc_xfer *xfer;
1126: {
1.33 bouyer 1127: WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer,
1128: chp->channel, xfer->drive), DEBUG_XFERS);
1.2 bouyer 1129:
1.31 bouyer 1130: /* complete xfer setup */
1.49 ! bouyer 1131: xfer->chp = chp;
1.2 bouyer 1132:
1.31 bouyer 1133: /*
1134: * If we are a polled command, and the list is not empty,
1135: * we are doing a dump. Drop the list to allow the polled command
1136: * to complete, we're going to reboot soon anyway.
1137: */
1138: if ((xfer->c_flags & C_POLL) != 0 &&
1139: chp->ch_queue->sc_xfer.tqh_first != NULL) {
1140: TAILQ_INIT(&chp->ch_queue->sc_xfer);
1141: }
1.2 bouyer 1142: /* insert at the end of command list */
1.31 bouyer 1143: TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain);
1144: WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n",
1.33 bouyer 1145: chp->ch_flags), DEBUG_XFERS);
1.45 drochner 1146: wdcstart(chp);
1.2 bouyer 1147: xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */
1.31 bouyer 1148: }
1.2 bouyer 1149:
1150: struct wdc_xfer *
1151: wdc_get_xfer(flags)
1152: int flags;
1153: {
1154: struct wdc_xfer *xfer;
1155: int s;
1156:
1157: s = splbio();
1158: if ((xfer = xfer_free_list.lh_first) != NULL) {
1159: LIST_REMOVE(xfer, free_list);
1160: splx(s);
1161: #ifdef DIAGNOSTIC
1162: if ((xfer->c_flags & C_INUSE) != 0)
1163: panic("wdc_get_xfer: xfer already in use\n");
1164: #endif
1165: } else {
1166: splx(s);
1.31 bouyer 1167: WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS);
1.2 bouyer 1168: xfer = malloc(sizeof(*xfer), M_DEVBUF,
1.31 bouyer 1169: ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK));
1.2 bouyer 1170: if (xfer == NULL)
1171: return 0;
1172: #ifdef DIAGNOSTIC
1173: xfer->c_flags &= ~C_INUSE;
1174: #endif
1.31 bouyer 1175: #ifdef WDCDEBUG
1.2 bouyer 1176: wdc_nxfer++;
1177: #endif
1178: }
1179: #ifdef DIAGNOSTIC
1180: if ((xfer->c_flags & C_INUSE) != 0)
1181: panic("wdc_get_xfer: xfer already in use\n");
1182: #endif
1.31 bouyer 1183: memset(xfer, 0, sizeof(struct wdc_xfer));
1.2 bouyer 1184: xfer->c_flags = C_INUSE;
1185: return xfer;
1186: }
1187:
1188: void
1.31 bouyer 1189: wdc_free_xfer(chp, xfer)
1190: struct channel_softc *chp;
1.2 bouyer 1191: struct wdc_xfer *xfer;
1192: {
1.31 bouyer 1193: struct wdc_softc *wdc = chp->wdc;
1.2 bouyer 1194: int s;
1195:
1.31 bouyer 1196: if (wdc->cap & WDC_CAPABILITY_HWLOCK)
1197: (*wdc->free_hw)(chp);
1.2 bouyer 1198: s = splbio();
1.31 bouyer 1199: chp->ch_flags &= ~WDCF_ACTIVE;
1200: TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain);
1.2 bouyer 1201: xfer->c_flags &= ~C_INUSE;
1202: LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list);
1203: splx(s);
1204: }
1205:
1.31 bouyer 1206: static void
1207: __wdcerror(chp, msg)
1208: struct channel_softc *chp;
1.2 bouyer 1209: char *msg;
1210: {
1.31 bouyer 1211: struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first;
1.2 bouyer 1212: if (xfer == NULL)
1.31 bouyer 1213: printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel,
1214: msg);
1.2 bouyer 1215: else
1.31 bouyer 1216: printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname,
1.49 ! bouyer 1217: chp->channel, xfer->drive, msg);
1.2 bouyer 1218: }
1219:
1220: /*
1221: * the bit bucket
1222: */
1223: void
1.31 bouyer 1224: wdcbit_bucket(chp, size)
1225: struct channel_softc *chp;
1.2 bouyer 1226: int size;
1227: {
1228:
1.12 cgd 1229: for (; size >= 2; size -= 2)
1.31 bouyer 1230: (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data);
1.12 cgd 1231: if (size)
1.31 bouyer 1232: (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data);
1.44 thorpej 1233: }
1234:
1235: int
1236: wdc_addref(chp)
1237: struct channel_softc *chp;
1238: {
1239: struct wdc_softc *wdc = chp->wdc;
1240: struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter;
1241: int s, error = 0;
1242:
1243: s = splbio();
1244: if (adapter->scsipi_refcnt++ == 0 &&
1245: adapter->scsipi_enable != NULL) {
1246: error = (*adapter->scsipi_enable)(wdc, 1);
1247: if (error)
1248: adapter->scsipi_refcnt--;
1249: }
1250: splx(s);
1251: return (error);
1252: }
1253:
1254: void
1255: wdc_delref(chp)
1256: struct channel_softc *chp;
1257: {
1258: struct wdc_softc *wdc = chp->wdc;
1259: struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter;
1260: int s;
1261:
1262: s = splbio();
1263: if (adapter->scsipi_refcnt-- == 1 &&
1264: adapter->scsipi_enable != NULL)
1265: (void) (*adapter->scsipi_enable)(wdc, 0);
1266: splx(s);
1.2 bouyer 1267: }
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