Annotation of src/sys/dev/ic/wdc.c, Revision 1.180
1.180 ! mycroft 1: /* $NetBSD: wdc.c,v 1.179 2004/05/27 16:47:35 mycroft Exp $ */
1.31 bouyer 2:
3: /*
1.137 bouyer 4: * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved.
1.31 bouyer 5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: * 3. All advertising materials mentioning features or use of this software
15: * must display the following acknowledgement:
16: * This product includes software developed by Manuel Bouyer.
17: * 4. The name of the author may not be used to endorse or promote products
18: * derived from this software without specific prior written permission.
19: *
20: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30: */
1.2 bouyer 31:
1.27 mycroft 32: /*-
1.125 mycroft 33: * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
1.27 mycroft 34: * All rights reserved.
1.2 bouyer 35: *
1.27 mycroft 36: * This code is derived from software contributed to The NetBSD Foundation
37: * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
1.12 cgd 38: *
1.2 bouyer 39: * Redistribution and use in source and binary forms, with or without
40: * modification, are permitted provided that the following conditions
41: * are met:
42: * 1. Redistributions of source code must retain the above copyright
43: * notice, this list of conditions and the following disclaimer.
44: * 2. Redistributions in binary form must reproduce the above copyright
45: * notice, this list of conditions and the following disclaimer in the
46: * documentation and/or other materials provided with the distribution.
47: * 3. All advertising materials mentioning features or use of this software
48: * must display the following acknowledgement:
1.27 mycroft 49: * This product includes software developed by the NetBSD
50: * Foundation, Inc. and its contributors.
51: * 4. Neither the name of The NetBSD Foundation nor the names of its
52: * contributors may be used to endorse or promote products derived
53: * from this software without specific prior written permission.
1.2 bouyer 54: *
1.27 mycroft 55: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
56: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
57: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
58: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
59: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
60: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
61: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
62: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
63: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
64: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
65: * POSSIBILITY OF SUCH DAMAGE.
1.2 bouyer 66: */
67:
1.12 cgd 68: /*
69: * CODE UNTESTED IN THE CURRENT REVISION:
70: */
1.100 lukem 71:
72: #include <sys/cdefs.h>
1.180 ! mycroft 73: __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.179 2004/05/27 16:47:35 mycroft Exp $");
1.12 cgd 74:
1.59 hubertf 75: #ifndef WDCDEBUG
1.31 bouyer 76: #define WDCDEBUG
1.59 hubertf 77: #endif /* WDCDEBUG */
1.31 bouyer 78:
1.2 bouyer 79: #include <sys/param.h>
80: #include <sys/systm.h>
81: #include <sys/kernel.h>
82: #include <sys/conf.h>
83: #include <sys/buf.h>
1.31 bouyer 84: #include <sys/device.h>
1.2 bouyer 85: #include <sys/malloc.h>
1.71 bouyer 86: #include <sys/pool.h>
1.2 bouyer 87: #include <sys/syslog.h>
88: #include <sys/proc.h>
89:
90: #include <machine/intr.h>
91: #include <machine/bus.h>
92:
1.17 sakamoto 93: #ifndef __BUS_SPACE_HAS_STREAM_METHODS
1.31 bouyer 94: #define bus_space_write_multi_stream_2 bus_space_write_multi_2
95: #define bus_space_write_multi_stream_4 bus_space_write_multi_4
96: #define bus_space_read_multi_stream_2 bus_space_read_multi_2
97: #define bus_space_read_multi_stream_4 bus_space_read_multi_4
1.17 sakamoto 98: #endif /* __BUS_SPACE_HAS_STREAM_METHODS */
1.16 sakamoto 99:
1.103 bouyer 100: #include <dev/ata/atavar.h>
1.31 bouyer 101: #include <dev/ata/atareg.h>
1.12 cgd 102: #include <dev/ic/wdcreg.h>
103: #include <dev/ic/wdcvar.h>
1.31 bouyer 104:
1.137 bouyer 105: #include "locators.h"
106:
1.122 thorpej 107: #include "ataraid.h"
1.2 bouyer 108: #include "atapibus.h"
1.106 bouyer 109: #include "wd.h"
1.2 bouyer 110:
1.122 thorpej 111: #if NATARAID > 0
112: #include <dev/ata/ata_raidvar.h>
113: #endif
114:
1.31 bouyer 115: #define WDCDELAY 100 /* 100 microseconds */
116: #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY)
1.2 bouyer 117: #if 0
1.31 bouyer 118: /* If you enable this, it will report any delays more than WDCDELAY * N long. */
1.2 bouyer 119: #define WDCNDELAY_DEBUG 50
120: #endif
121:
1.137 bouyer 122: /* When polling wait that much and then tsleep for 1/hz seconds */
123: #define WDCDELAY_POLL 1 /* ms */
124:
125: /* timeout for the control commands */
126: #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */
127:
1.71 bouyer 128: struct pool wdc_xfer_pool;
1.2 bouyer 129:
1.106 bouyer 130: #if NWD > 0
1.103 bouyer 131: extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */
1.106 bouyer 132: #else
133: /* A fake one, the autoconfig will print "wd at foo ... not configured */
134: const struct ata_bustype wdc_ata_bustype = {
135: SCSIPI_BUSTYPE_ATA,
136: NULL,
137: NULL,
138: NULL,
139: NULL,
140: NULL,
141: NULL,
142: NULL
143: };
144: #endif
1.102 bouyer 145:
1.168 thorpej 146: static int wdcprobe1(struct wdc_channel*, int);
147: static void __wdcerror(struct wdc_channel*, char *);
148: static int __wdcwait_reset(struct wdc_channel *, int, int);
149: static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *);
150: static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *);
151: static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *,
1.167 thorpej 152: int);
1.168 thorpej 153: static int __wdcwait(struct wdc_channel *, int, int, int);
1.31 bouyer 154:
155: #define DEBUG_INTR 0x01
156: #define DEBUG_XFERS 0x02
157: #define DEBUG_STATUS 0x04
158: #define DEBUG_FUNCS 0x08
159: #define DEBUG_PROBE 0x10
1.74 enami 160: #define DEBUG_DETACH 0x20
1.87 bouyer 161: #define DEBUG_DELAY 0x40
1.31 bouyer 162: #ifdef WDCDEBUG
1.32 bouyer 163: int wdcdebug_mask = 0;
1.31 bouyer 164: int wdc_nxfer = 0;
165: #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args
1.2 bouyer 166: #else
1.31 bouyer 167: #define WDCDEBUG_PRINT(args, level)
1.2 bouyer 168: #endif
169:
1.162 thorpej 170: /*
171: * A queue of atabus instances, used to ensure the same bus probe order
172: * for a given hardware configuration at each boot.
173: */
174: struct atabus_initq_head atabus_initq_head =
175: TAILQ_HEAD_INITIALIZER(atabus_initq_head);
176: struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER;
1.137 bouyer 177:
1.176 thorpej 178: /*
179: * Initialize the "shadow register" handles for a standard wdc controller.
180: */
181: void
182: wdc_init_shadow_regs(struct wdc_channel *chp)
183: {
184:
185: chp->cmd_iohs[wd_status] = chp->cmd_iohs[wd_command];
186: chp->cmd_iohs[wd_features] = chp->cmd_iohs[wd_error];
187: }
188:
1.162 thorpej 189: /* Test to see controller with at last one attached drive is there.
190: * Returns a bit for each possible drive found (0x01 for drive 0,
191: * 0x02 for drive 1).
192: * Logic:
193: * - If a status register is at 0xff, assume there is no drive here
194: * (ISA has pull-up resistors). Similarly if the status register has
195: * the value we last wrote to the bus (for IDE interfaces without pullups).
196: * If no drive at all -> return.
197: * - reset the controller, wait for it to complete (may take up to 31s !).
198: * If timeout -> return.
199: * - test ATA/ATAPI signatures. If at last one drive found -> return.
200: * - try an ATA command on the master.
201: */
1.137 bouyer 202:
1.164 thorpej 203: static void
1.168 thorpej 204: wdc_drvprobe(struct wdc_channel *chp)
1.137 bouyer 205: {
206: struct ataparams params;
1.169 thorpej 207: struct wdc_softc *wdc = chp->ch_wdc;
1.145 christos 208: u_int8_t st0 = 0, st1 = 0;
1.164 thorpej 209: int i, error;
1.137 bouyer 210:
1.164 thorpej 211: if (wdcprobe1(chp, 0) == 0) {
212: /* No drives, abort the attach here. */
213: return;
1.161 thorpej 214: }
1.137 bouyer 215:
216: /* for ATA/OLD drives, wait for DRDY, 3s timeout */
217: for (i = 0; i < mstohz(3000); i++) {
1.174 bouyer 218: if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) {
219: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
220: wdc->select(chp,0);
221: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
222: 0, WDSD_IBM);
223: delay(10); /* 400ns delay */
224: st0 = bus_space_read_1(chp->cmd_iot,
225: chp->cmd_iohs[wd_status], 0);
226: }
1.137 bouyer 227:
1.174 bouyer 228: if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) {
229: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
230: wdc->select(chp,1);
231: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
232: 0, WDSD_IBM | 0x10);
233: delay(10); /* 400ns delay */
234: st1 = bus_space_read_1(chp->cmd_iot,
235: chp->cmd_iohs[wd_status], 0);
236: }
1.137 bouyer 237:
238: if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD))
239: == 0 ||
240: (st0 & WDCS_DRDY)) &&
241: ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD))
242: == 0 ||
243: (st1 & WDCS_DRDY)))
244: break;
1.164 thorpej 245: tsleep(¶ms, PRIBIO, "atadrdy", 1);
1.137 bouyer 246: }
247: if ((st0 & WDCS_DRDY) == 0)
248: chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD);
249: if ((st1 & WDCS_DRDY) == 0)
250: chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD);
251:
252: WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n",
1.169 thorpej 253: wdc->sc_dev.dv_xname,
254: chp->ch_channel, st0, st1), DEBUG_PROBE);
1.137 bouyer 255:
256: /* Wait a bit, some devices are weird just after a reset. */
257: delay(5000);
258:
259: for (i = 0; i < 2; i++) {
1.171 thorpej 260: /* XXX This should be done by other code. */
1.137 bouyer 261: chp->ch_drive[i].chnl_softc = chp;
262: chp->ch_drive[i].drive = i;
1.171 thorpej 263:
1.137 bouyer 264: /*
265: * Init error counter so that an error withing the first xfers
266: * will trigger a downgrade
267: */
268: chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1;
269:
270: /* If controller can't do 16bit flag the drives as 32bit */
1.169 thorpej 271: if ((wdc->cap &
1.137 bouyer 272: (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
273: WDC_CAPABILITY_DATA32)
274: chp->ch_drive[i].drive_flags |= DRIVE_CAP32;
275: if ((chp->ch_drive[i].drive_flags & DRIVE) == 0)
276: continue;
277:
1.144 briggs 278: /* Shortcut in case we've been shutdown */
279: if (chp->ch_flags & WDCF_SHUTDOWN)
1.164 thorpej 280: return;
1.144 briggs 281:
1.137 bouyer 282: /* issue an identify, to try to detect ghosts */
283: error = ata_get_params(&chp->ch_drive[i],
284: AT_WAIT | AT_POLL, ¶ms);
285: if (error != CMD_OK) {
1.164 thorpej 286: tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000));
1.144 briggs 287:
288: /* Shortcut in case we've been shutdown */
289: if (chp->ch_flags & WDCF_SHUTDOWN)
1.164 thorpej 290: return;
1.144 briggs 291:
1.137 bouyer 292: error = ata_get_params(&chp->ch_drive[i],
293: AT_WAIT | AT_POLL, ¶ms);
294: }
295: if (error == CMD_OK) {
1.152 wiz 296: /* If IDENTIFY succeeded, this is not an OLD ctrl */
1.137 bouyer 297: chp->ch_drive[0].drive_flags &= ~DRIVE_OLD;
298: chp->ch_drive[1].drive_flags &= ~DRIVE_OLD;
299: } else {
1.155 bouyer 300: chp->ch_drive[i].drive_flags &=
1.137 bouyer 301: ~(DRIVE_ATA | DRIVE_ATAPI);
302: WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n",
1.169 thorpej 303: wdc->sc_dev.dv_xname,
304: chp->ch_channel, i, error), DEBUG_PROBE);
1.137 bouyer 305: if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0)
306: continue;
307: /*
308: * Pre-ATA drive ?
309: * Test registers writability (Error register not
310: * writable, but cyllo is), then try an ATA command.
311: */
1.169 thorpej 312: if (wdc->cap & WDC_CAPABILITY_SELECT)
313: wdc->select(chp,i);
1.157 fvdl 314: bus_space_write_1(chp->cmd_iot,
315: chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4));
1.137 bouyer 316: delay(10); /* 400ns delay */
1.157 fvdl 317: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error],
318: 0, 0x58);
319: bus_space_write_1(chp->cmd_iot,
320: chp->cmd_iohs[wd_cyl_lo], 0, 0xa5);
321: if (bus_space_read_1(chp->cmd_iot,
322: chp->cmd_iohs[wd_error], 0) == 0x58 ||
323: bus_space_read_1(chp->cmd_iot,
324: chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) {
1.137 bouyer 325: WDCDEBUG_PRINT(("%s:%d:%d: register "
326: "writability failed\n",
1.169 thorpej 327: wdc->sc_dev.dv_xname,
328: chp->ch_channel, i), DEBUG_PROBE);
1.137 bouyer 329: chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
1.155 bouyer 330: continue;
1.137 bouyer 331: }
1.166 thorpej 332: if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) {
1.137 bouyer 333: WDCDEBUG_PRINT(("%s:%d:%d: not ready\n",
1.169 thorpej 334: wdc->sc_dev.dv_xname,
335: chp->ch_channel, i), DEBUG_PROBE);
1.137 bouyer 336: chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
337: continue;
338: }
1.157 fvdl 339: bus_space_write_1(chp->cmd_iot,
340: chp->cmd_iohs[wd_command], 0, WDCC_RECAL);
1.137 bouyer 341: delay(10); /* 400ns delay */
1.166 thorpej 342: if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) {
1.137 bouyer 343: WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n",
1.169 thorpej 344: wdc->sc_dev.dv_xname,
345: chp->ch_channel, i), DEBUG_PROBE);
1.137 bouyer 346: chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
1.155 bouyer 347: } else {
348: chp->ch_drive[0].drive_flags &=
349: ~(DRIVE_ATA | DRIVE_ATAPI);
350: chp->ch_drive[1].drive_flags &=
351: ~(DRIVE_ATA | DRIVE_ATAPI);
1.137 bouyer 352: }
353: }
354: }
1.164 thorpej 355: }
356:
357: void
358: atabusconfig(struct atabus_softc *atabus_sc)
359: {
1.168 thorpej 360: struct wdc_channel *chp = atabus_sc->sc_chan;
1.169 thorpej 361: struct wdc_softc *wdc = chp->ch_wdc;
1.164 thorpej 362: int i, error, need_delref = 0;
363: struct atabus_initq *atabus_initq = NULL;
364:
365: if ((error = wdc_addref(chp)) != 0) {
366: aprint_error("%s: unable to enable controller\n",
1.169 thorpej 367: wdc->sc_dev.dv_xname);
1.164 thorpej 368: goto out;
369: }
370: need_delref = 1;
371:
372: /* Probe for the drives. */
1.169 thorpej 373: (*wdc->drv_probe)(chp);
1.137 bouyer 374:
375: WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n",
376: chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags),
377: DEBUG_PROBE);
378:
379: /* If no drives, abort here */
380: if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 &&
381: (chp->ch_drive[1].drive_flags & DRIVE) == 0)
382: goto out;
383:
1.164 thorpej 384: /* Shortcut in case we've been shutdown */
385: if (chp->ch_flags & WDCF_SHUTDOWN)
386: goto out;
387:
1.137 bouyer 388: /* Make sure the devices probe in atabus order to avoid jitter. */
389: simple_lock(&atabus_interlock);
390: while(1) {
391: atabus_initq = TAILQ_FIRST(&atabus_initq_head);
392: if (atabus_initq->atabus_sc == atabus_sc)
393: break;
394: ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0,
395: &atabus_interlock);
396: }
397: simple_unlock(&atabus_interlock);
398:
399: /*
400: * Attach an ATAPI bus, if needed.
401: */
402: if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) ||
403: (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) {
404: #if NATAPIBUS > 0
405: wdc_atapibus_attach(atabus_sc);
406: #else
407: /*
408: * Fake the autoconfig "not configured" message
409: */
410: aprint_normal("atapibus at %s not configured\n",
1.169 thorpej 411: wdc->sc_dev.dv_xname);
1.137 bouyer 412: chp->atapibus = NULL;
1.141 bouyer 413: chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI;
414: chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI;
1.137 bouyer 415: #endif
416: }
417:
418: for (i = 0; i < 2; i++) {
419: struct ata_device adev;
420: if ((chp->ch_drive[i].drive_flags &
421: (DRIVE_ATA | DRIVE_OLD)) == 0) {
422: continue;
423: }
424: memset(&adev, 0, sizeof(struct ata_device));
425: adev.adev_bustype = &wdc_ata_bustype;
1.169 thorpej 426: adev.adev_channel = chp->ch_channel;
1.137 bouyer 427: adev.adev_openings = 1;
428: adev.adev_drv_data = &chp->ch_drive[i];
429: chp->ata_drives[i] = config_found(&atabus_sc->sc_dev,
1.162 thorpej 430: &adev, ataprint);
1.141 bouyer 431: if (chp->ata_drives[i] != NULL)
1.137 bouyer 432: wdc_probe_caps(&chp->ch_drive[i]);
1.141 bouyer 433: else
434: chp->ch_drive[i].drive_flags &=
435: ~(DRIVE_ATA | DRIVE_OLD);
1.137 bouyer 436: }
437:
438: /* now that we know the drives, the controller can set its modes */
1.169 thorpej 439: if (wdc->cap & WDC_CAPABILITY_MODE) {
440: wdc->set_modes(chp);
1.137 bouyer 441: wdc_print_modes(chp);
442: }
443: #if NATARAID > 0
1.169 thorpej 444: if (wdc->cap & WDC_CAPABILITY_RAID)
1.137 bouyer 445: for (i = 0; i < 2; i++)
446: if (chp->ata_drives[i] != NULL)
447: ata_raid_check_component(chp->ata_drives[i]);
448: #endif /* NATARAID > 0 */
449:
450: /*
1.152 wiz 451: * reset drive_flags for unattached devices, reset state for attached
1.137 bouyer 452: * ones
453: */
454: for (i = 0; i < 2; i++) {
455: if (chp->ch_drive[i].drv_softc == NULL)
456: chp->ch_drive[i].drive_flags = 0;
457: else
458: chp->ch_drive[i].state = 0;
459: }
460:
1.163 thorpej 461: out:
1.137 bouyer 462: if (atabus_initq == NULL) {
463: simple_lock(&atabus_interlock);
464: while(1) {
465: atabus_initq = TAILQ_FIRST(&atabus_initq_head);
466: if (atabus_initq->atabus_sc == atabus_sc)
467: break;
468: ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0,
469: &atabus_interlock);
470: }
471: simple_unlock(&atabus_interlock);
472: }
473: simple_lock(&atabus_interlock);
474: TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq);
475: simple_unlock(&atabus_interlock);
476:
477: free(atabus_initq, M_DEVBUF);
478: wakeup(&atabus_initq_head);
479:
480: config_pending_decr();
1.144 briggs 481: if (need_delref)
482: wdc_delref(chp);
1.137 bouyer 483: }
484:
1.2 bouyer 485: int
1.168 thorpej 486: wdcprobe(struct wdc_channel *chp)
1.12 cgd 487: {
1.163 thorpej 488:
489: return (wdcprobe1(chp, 1));
1.137 bouyer 490: }
491:
1.167 thorpej 492: static int
1.168 thorpej 493: wdcprobe1(struct wdc_channel *chp, int poll)
1.137 bouyer 494: {
1.169 thorpej 495: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 496: u_int8_t st0, st1, sc, sn, cl, ch;
497: u_int8_t ret_value = 0x03;
498: u_int8_t drive;
1.156 bouyer 499: int s;
1.31 bouyer 500:
501: /*
502: * Sanity check to see if the wdc channel responds at all.
503: */
504:
1.174 bouyer 505: s = splbio();
1.169 thorpej 506: if (wdc == NULL ||
507: (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) {
1.107 dbj 508:
1.169 thorpej 509: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
510: wdc->select(chp,0);
1.137 bouyer 511:
1.157 fvdl 512: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.43 kenh 513: WDSD_IBM);
1.131 mycroft 514: delay(10); /* 400ns delay */
1.157 fvdl 515: st0 = bus_space_read_1(chp->cmd_iot,
516: chp->cmd_iohs[wd_status], 0);
1.107 dbj 517:
1.169 thorpej 518: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
519: wdc->select(chp,1);
1.137 bouyer 520:
1.157 fvdl 521: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.43 kenh 522: WDSD_IBM | 0x10);
1.131 mycroft 523: delay(10); /* 400ns delay */
1.157 fvdl 524: st1 = bus_space_read_1(chp->cmd_iot,
525: chp->cmd_iohs[wd_status], 0);
1.43 kenh 526:
527: WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n",
1.169 thorpej 528: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
529: chp->ch_channel, st0, st1), DEBUG_PROBE);
1.43 kenh 530:
1.142 bouyer 531: if (st0 == 0xff || st0 == WDSD_IBM)
1.43 kenh 532: ret_value &= ~0x01;
1.142 bouyer 533: if (st1 == 0xff || st1 == (WDSD_IBM | 0x10))
1.43 kenh 534: ret_value &= ~0x02;
1.125 mycroft 535: /* Register writability test, drive 0. */
536: if (ret_value & 0x01) {
1.169 thorpej 537: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
538: wdc->select(chp,0);
1.157 fvdl 539: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
540: 0, WDSD_IBM);
541: bus_space_write_1(chp->cmd_iot,
542: chp->cmd_iohs[wd_cyl_lo], 0, 0x02);
1.174 bouyer 543: cl = bus_space_read_1(chp->cmd_iot,
544: chp->cmd_iohs[wd_cyl_lo], 0);
545: if (cl != 0x02) {
546: WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: "
547: "got 0x%x != 0x02\n",
548: wdc != NULL ?
549: wdc->sc_dev.dv_xname : "wdcprobe",
550: chp->ch_channel, cl),
551: DEBUG_PROBE);
1.125 mycroft 552: ret_value &= ~0x01;
1.174 bouyer 553: }
1.157 fvdl 554: bus_space_write_1(chp->cmd_iot,
555: chp->cmd_iohs[wd_cyl_lo], 0, 0x01);
1.174 bouyer 556: cl = bus_space_read_1(chp->cmd_iot,
557: chp->cmd_iohs[wd_cyl_lo], 0);
558: if (cl != 0x01) {
559: WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: "
560: "got 0x%x != 0x01\n",
561: wdc != NULL ?
562: wdc->sc_dev.dv_xname : "wdcprobe",
563: chp->ch_channel, cl),
564: DEBUG_PROBE);
1.125 mycroft 565: ret_value &= ~0x01;
1.174 bouyer 566: }
1.167 thorpej 567: bus_space_write_1(chp->cmd_iot,
568: chp->cmd_iohs[wd_sector], 0, 0x01);
1.174 bouyer 569: cl = bus_space_read_1(chp->cmd_iot,
570: chp->cmd_iohs[wd_sector], 0);
571: if (cl != 0x01) {
572: WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: "
573: "got 0x%x != 0x01\n",
574: wdc != NULL ?
575: wdc->sc_dev.dv_xname : "wdcprobe",
576: chp->ch_channel, cl),
577: DEBUG_PROBE);
1.125 mycroft 578: ret_value &= ~0x01;
1.174 bouyer 579: }
1.157 fvdl 580: bus_space_write_1(chp->cmd_iot,
581: chp->cmd_iohs[wd_sector], 0, 0x02);
1.174 bouyer 582: cl = bus_space_read_1(chp->cmd_iot,
583: chp->cmd_iohs[wd_sector], 0);
584: if (cl != 0x02) {
585: WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: "
586: "got 0x%x != 0x02\n",
587: wdc != NULL ?
588: wdc->sc_dev.dv_xname : "wdcprobe",
589: chp->ch_channel, cl),
590: DEBUG_PROBE);
1.125 mycroft 591: ret_value &= ~0x01;
1.174 bouyer 592: }
593: cl = bus_space_read_1(chp->cmd_iot,
594: chp->cmd_iohs[wd_cyl_lo], 0);
595: if (cl != 0x01) {
596: WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): "
597: "got 0x%x != 0x01\n",
598: wdc != NULL ?
599: wdc->sc_dev.dv_xname : "wdcprobe",
600: chp->ch_channel, cl),
601: DEBUG_PROBE);
1.131 mycroft 602: ret_value &= ~0x01;
1.174 bouyer 603: }
1.125 mycroft 604: }
605: /* Register writability test, drive 1. */
606: if (ret_value & 0x02) {
1.169 thorpej 607: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
608: wdc->select(chp,1);
1.157 fvdl 609: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
610: 0, WDSD_IBM | 0x10);
1.167 thorpej 611: bus_space_write_1(chp->cmd_iot,
612: chp->cmd_iohs[wd_cyl_lo], 0, 0x02);
1.174 bouyer 613: cl = bus_space_read_1(chp->cmd_iot,
614: chp->cmd_iohs[wd_cyl_lo], 0);
615: if (cl != 0x02) {
616: WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: "
617: "got 0x%x != 0x02\n",
618: wdc != NULL ?
619: wdc->sc_dev.dv_xname : "wdcprobe",
620: chp->ch_channel, cl),
621: DEBUG_PROBE);
1.125 mycroft 622: ret_value &= ~0x02;
1.174 bouyer 623: }
1.157 fvdl 624: bus_space_write_1(chp->cmd_iot,
625: chp->cmd_iohs[wd_cyl_lo], 0, 0x01);
1.174 bouyer 626: cl = bus_space_read_1(chp->cmd_iot,
627: chp->cmd_iohs[wd_cyl_lo], 0);
628: if (cl != 0x01) {
629: WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: "
630: "got 0x%x != 0x01\n",
631: wdc != NULL ?
632: wdc->sc_dev.dv_xname : "wdcprobe",
633: chp->ch_channel, cl),
634: DEBUG_PROBE);
1.125 mycroft 635: ret_value &= ~0x02;
1.174 bouyer 636: }
1.157 fvdl 637: bus_space_write_1(chp->cmd_iot,
638: chp->cmd_iohs[wd_sector], 0, 0x01);
1.174 bouyer 639: cl = bus_space_read_1(chp->cmd_iot,
640: chp->cmd_iohs[wd_sector], 0);
641: if (cl != 0x01) {
642: WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: "
643: "got 0x%x != 0x01\n",
644: wdc != NULL ?
645: wdc->sc_dev.dv_xname : "wdcprobe",
646: chp->ch_channel, cl),
647: DEBUG_PROBE);
1.125 mycroft 648: ret_value &= ~0x02;
1.174 bouyer 649: }
1.167 thorpej 650: bus_space_write_1(chp->cmd_iot,
651: chp->cmd_iohs[wd_sector], 0, 0x02);
1.174 bouyer 652: cl = bus_space_read_1(chp->cmd_iot,
653: chp->cmd_iohs[wd_sector], 0);
654: if (cl != 0x02) {
655: WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: "
656: "got 0x%x != 0x02\n",
657: wdc != NULL ?
658: wdc->sc_dev.dv_xname : "wdcprobe",
659: chp->ch_channel, cl),
660: DEBUG_PROBE);
1.125 mycroft 661: ret_value &= ~0x02;
1.174 bouyer 662: }
663: cl = bus_space_read_1(chp->cmd_iot,
664: chp->cmd_iohs[wd_cyl_lo], 0);
665: if (cl != 0x01) {
666: WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): "
667: "got 0x%x != 0x01\n",
668: wdc != NULL ?
669: wdc->sc_dev.dv_xname : "wdcprobe",
670: chp->ch_channel, cl),
671: DEBUG_PROBE);
1.131 mycroft 672: ret_value &= ~0x02;
1.174 bouyer 673: }
1.125 mycroft 674: }
1.137 bouyer 675:
1.174 bouyer 676: if (ret_value == 0) {
677: splx(s);
1.137 bouyer 678: return 0;
1.174 bouyer 679: }
1.62 bouyer 680: }
1.31 bouyer 681:
1.174 bouyer 682:
683: /*
684: * reset bus. Also send an ATAPI_RESET to devices, in case there are
685: * ATAPI device out there which don't react to the bus reset
686: */
687: if (ret_value & 0x01) {
688: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
689: wdc->select(chp,0);
690: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
691: 0, WDSD_IBM);
692: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0,
693: ATAPI_SOFT_RESET);
694: }
695: if (ret_value & 0x02) {
696: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
697: wdc->select(chp,0);
698: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
699: 0, WDSD_IBM | 0x10);
700: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0,
701: ATAPI_SOFT_RESET);
702: }
1.156 bouyer 703:
1.175 bouyer 704: delay(5000);
705:
1.169 thorpej 706: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
707: wdc->select(chp,0);
1.157 fvdl 708: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM);
1.137 bouyer 709: delay(10); /* 400ns delay */
1.174 bouyer 710: /* assert SRST, wait for reset to complete */
1.137 bouyer 711: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
712: WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
1.172 bouyer 713: DELAY(1000);
714: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
715: WDCTL_IDS | WDCTL_4BIT);
1.137 bouyer 716: DELAY(2000);
1.157 fvdl 717: (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0);
1.137 bouyer 718: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
719: delay(10); /* 400ns delay */
1.156 bouyer 720: /* ACK interrupt in case there is one pending left (Promise ATA100) */
1.169 thorpej 721: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK))
722: wdc->irqack(chp);
1.156 bouyer 723: splx(s);
1.137 bouyer 724:
725: ret_value = __wdcwait_reset(chp, ret_value, poll);
726: WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n",
1.169 thorpej 727: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel,
1.137 bouyer 728: ret_value), DEBUG_PROBE);
1.12 cgd 729:
1.137 bouyer 730: /* if reset failed, there's nothing here */
731: if (ret_value == 0)
732: return 0;
1.67 bouyer 733:
1.12 cgd 734: /*
1.167 thorpej 735: * Test presence of drives. First test register signatures looking
736: * for ATAPI devices. If it's not an ATAPI and reset said there may
737: * be something here assume it's ATA or OLD. Ghost will be killed
738: * later in attach routine.
1.12 cgd 739: */
1.137 bouyer 740: for (drive = 0; drive < 2; drive++) {
741: if ((ret_value & (0x01 << drive)) == 0)
742: continue;
1.169 thorpej 743: if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT)
744: wdc->select(chp,drive);
1.157 fvdl 745: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.137 bouyer 746: WDSD_IBM | (drive << 4));
747: delay(10); /* 400ns delay */
748: /* Save registers contents */
1.157 fvdl 749: sc = bus_space_read_1(chp->cmd_iot,
750: chp->cmd_iohs[wd_seccnt], 0);
751: sn = bus_space_read_1(chp->cmd_iot,
752: chp->cmd_iohs[wd_sector], 0);
753: cl = bus_space_read_1(chp->cmd_iot,
754: chp->cmd_iohs[wd_cyl_lo], 0);
755: ch = bus_space_read_1(chp->cmd_iot,
756: chp->cmd_iohs[wd_cyl_hi], 0);
1.137 bouyer 757:
758: WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x "
759: "cl=0x%x ch=0x%x\n",
1.169 thorpej 760: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
761: chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE);
1.31 bouyer 762: /*
1.137 bouyer 763: * sc & sn are supposted to be 0x1 for ATAPI but in some cases
764: * we get wrong values here, so ignore it.
1.31 bouyer 765: */
1.137 bouyer 766: if (cl == 0x14 && ch == 0xeb) {
767: chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI;
768: } else {
769: chp->ch_drive[drive].drive_flags |= DRIVE_ATA;
1.169 thorpej 770: if (wdc == NULL ||
771: (wdc->cap & WDC_CAPABILITY_PREATA) != 0)
1.137 bouyer 772: chp->ch_drive[drive].drive_flags |= DRIVE_OLD;
773: }
1.31 bouyer 774: }
1.137 bouyer 775: return (ret_value);
776: }
1.31 bouyer 777:
1.137 bouyer 778: void
1.168 thorpej 779: wdcattach(struct wdc_channel *chp)
1.137 bouyer 780: {
1.169 thorpej 781: struct wdc_softc *wdc = chp->ch_wdc;
1.137 bouyer 782: static int inited = 0;
1.32 bouyer 783:
1.137 bouyer 784: if (chp->ch_flags & WDCF_DISABLED)
785: return;
1.74 enami 786:
1.137 bouyer 787: /* initialise global data */
788: callout_init(&chp->ch_callout);
1.169 thorpej 789: if (wdc->drv_probe == NULL)
790: wdc->drv_probe = wdc_drvprobe;
1.137 bouyer 791: if (inited == 0) {
1.165 thorpej 792: /* Initialize the ata_xfer pool. */
793: pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0,
1.137 bouyer 794: 0, 0, "wdcspl", NULL);
795: inited++;
1.133 bouyer 796: }
1.165 thorpej 797: TAILQ_INIT(&chp->ch_queue->queue_xfer);
1.148 bouyer 798: chp->ch_queue->queue_freeze = 0;
1.126 enami 799:
1.169 thorpej 800: chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint);
1.74 enami 801: }
802:
1.163 thorpej 803: int
804: wdcactivate(struct device *self, enum devact act)
1.137 bouyer 805: {
806: struct wdc_softc *wdc = (struct wdc_softc *)self;
807: int s, i, error = 0;
808:
809: s = splbio();
810: switch (act) {
811: case DVACT_ACTIVATE:
812: error = EOPNOTSUPP;
813: break;
814:
815: case DVACT_DEACTIVATE:
816: for (i = 0; i < wdc->nchannels; i++) {
817: error = config_deactivate(wdc->channels[i]->atabus);
818: if (error)
819: break;
820: }
821: break;
822: }
823: splx(s);
824: return (error);
825: }
826:
827: int
1.163 thorpej 828: wdcdetach(struct device *self, int flags)
1.137 bouyer 829: {
830: struct wdc_softc *wdc = (struct wdc_softc *)self;
1.168 thorpej 831: struct wdc_channel *chp;
1.137 bouyer 832: int i, error = 0;
833:
834: for (i = 0; i < wdc->nchannels; i++) {
835: chp = wdc->channels[i];
836: WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n",
837: wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH);
838: error = config_detach(chp->atabus, flags);
839: if (error)
840: break;
841: }
842: return (error);
843: }
844:
1.31 bouyer 845: /*
846: * Start I/O on a controller, for the given channel.
847: * The first xfer may be not for our channel if the channel queues
848: * are shared.
849: */
850: void
1.168 thorpej 851: wdcstart(struct wdc_channel *chp)
1.31 bouyer 852: {
1.169 thorpej 853: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 854: struct ata_xfer *xfer;
1.38 bouyer 855:
856: #ifdef WDC_DIAGNOSTIC
857: int spl1, spl2;
858:
859: spl1 = splbio();
860: spl2 = splbio();
861: if (spl2 != spl1) {
862: printf("wdcstart: not at splbio()\n");
863: panic("wdcstart");
864: }
865: splx(spl2);
866: splx(spl1);
867: #endif /* WDC_DIAGNOSTIC */
1.12 cgd 868:
1.31 bouyer 869: /* is there a xfer ? */
1.165 thorpej 870: if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL)
1.31 bouyer 871: return;
1.47 bouyer 872:
873: /* adjust chp, in case we have a shared queue */
1.165 thorpej 874: chp = xfer->c_chp;
1.47 bouyer 875:
1.31 bouyer 876: if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) {
877: return; /* channel aleady active */
878: }
1.148 bouyer 879: if (__predict_false(chp->ch_queue->queue_freeze > 0)) {
1.147 bouyer 880: return; /* queue froozen */
1.137 bouyer 881: }
1.31 bouyer 882: #ifdef DIAGNOSTIC
883: if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0)
1.118 provos 884: panic("wdcstart: channel waiting for irq");
1.31 bouyer 885: #endif
1.169 thorpej 886: if (wdc->cap & WDC_CAPABILITY_HWLOCK)
887: if (!(*wdc->claim_hw)(chp, 0))
1.31 bouyer 888: return;
1.12 cgd 889:
1.31 bouyer 890: WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer,
1.169 thorpej 891: chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
1.31 bouyer 892: chp->ch_flags |= WDCF_ACTIVE;
1.165 thorpej 893: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) {
894: chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET;
895: chp->ch_drive[xfer->c_drive].state = 0;
1.37 bouyer 896: }
1.169 thorpej 897: if (wdc->cap & WDC_CAPABILITY_NOIRQ)
1.98 bjh21 898: KASSERT(xfer->c_flags & C_POLL);
1.31 bouyer 899: xfer->c_start(chp, xfer);
900: }
1.2 bouyer 901:
1.31 bouyer 902: /* restart an interrupted I/O */
903: void
1.163 thorpej 904: wdcrestart(void *v)
1.31 bouyer 905: {
1.168 thorpej 906: struct wdc_channel *chp = v;
1.31 bouyer 907: int s;
1.2 bouyer 908:
1.31 bouyer 909: s = splbio();
1.45 drochner 910: wdcstart(chp);
1.31 bouyer 911: splx(s);
1.2 bouyer 912: }
1.31 bouyer 913:
1.2 bouyer 914:
1.31 bouyer 915: /*
916: * Interrupt routine for the controller. Acknowledge the interrupt, check for
917: * errors on the current operation, mark it done if necessary, and start the
918: * next request. Also check for a partially done transfer, and continue with
919: * the next chunk if so.
920: */
1.12 cgd 921: int
1.163 thorpej 922: wdcintr(void *arg)
1.12 cgd 923: {
1.168 thorpej 924: struct wdc_channel *chp = arg;
1.169 thorpej 925: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 926: struct ata_xfer *xfer;
1.76 bouyer 927: int ret;
1.12 cgd 928:
1.169 thorpej 929: if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) {
1.80 enami 930: WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"),
931: DEBUG_INTR);
932: return (0);
933: }
1.31 bouyer 934: if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) {
935: WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR);
1.113 bouyer 936: /* try to clear the pending interrupt anyway */
1.157 fvdl 937: (void)bus_space_read_1(chp->cmd_iot,
938: chp->cmd_iohs[wd_status], 0);
1.80 enami 939: return (0);
1.31 bouyer 940: }
1.12 cgd 941:
1.31 bouyer 942: WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR);
1.165 thorpej 943: xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.84 bouyer 944: if (chp->ch_flags & WDCF_DMA_WAIT) {
1.169 thorpej 945: wdc->dma_status =
946: (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel,
1.165 thorpej 947: xfer->c_drive, 0);
1.169 thorpej 948: if (wdc->dma_status & WDC_DMAST_NOIRQ) {
1.84 bouyer 949: /* IRQ not for us, not detected by DMA engine */
950: return 0;
951: }
952: chp->ch_flags &= ~WDCF_DMA_WAIT;
953: }
1.31 bouyer 954: chp->ch_flags &= ~WDCF_IRQ_WAIT;
1.76 bouyer 955: ret = xfer->c_intr(chp, xfer, 1);
956: if (ret == 0) /* irq was not for us, still waiting for irq */
957: chp->ch_flags |= WDCF_IRQ_WAIT;
958: return (ret);
1.12 cgd 959: }
960:
1.31 bouyer 961: /* Put all disk in RESET state */
1.125 mycroft 962: void
1.163 thorpej 963: wdc_reset_channel(struct ata_drive_datas *drvp, int flags)
1.2 bouyer 964: {
1.168 thorpej 965: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 966: struct wdc_softc *wdc = chp->ch_wdc;
1.2 bouyer 967: int drive;
1.163 thorpej 968:
1.34 bouyer 969: WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n",
1.169 thorpej 970: wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive),
1.34 bouyer 971: DEBUG_FUNCS);
1.147 bouyer 972: if ((flags & AT_POLL) == 0) {
1.153 bouyer 973: if (chp->ch_flags & WDCF_TH_RESET) {
974: /* no need to schedule a reset more than one time */
975: return;
976: }
1.137 bouyer 977: chp->ch_flags |= WDCF_TH_RESET;
1.148 bouyer 978: chp->ch_queue->queue_freeze++;
1.170 thorpej 979: wakeup(&chp->ch_thread);
1.137 bouyer 980: return;
981: }
1.147 bouyer 982: (void) wdcreset(chp, RESET_POLL);
1.31 bouyer 983: for (drive = 0; drive < 2; drive++) {
984: chp->ch_drive[drive].state = 0;
1.12 cgd 985: }
1.31 bouyer 986: }
1.12 cgd 987:
1.31 bouyer 988: int
1.168 thorpej 989: wdcreset(struct wdc_channel *chp, int poll)
1.31 bouyer 990: {
1.169 thorpej 991: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 992: int drv_mask1, drv_mask2;
1.156 bouyer 993: int s = 0;
1.2 bouyer 994:
1.169 thorpej 995: if (wdc->cap & WDC_CAPABILITY_SELECT)
996: wdc->select(chp,0);
1.156 bouyer 997: if (poll != RESET_SLEEP)
998: s = splbio();
1.157 fvdl 999: /* master */
1000: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM);
1.131 mycroft 1001: delay(10); /* 400ns delay */
1.31 bouyer 1002: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
1.131 mycroft 1003: WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
1004: delay(2000);
1.157 fvdl 1005: (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0);
1.137 bouyer 1006: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
1007: WDCTL_4BIT | WDCTL_IDS);
1.131 mycroft 1008: delay(10); /* 400ns delay */
1.156 bouyer 1009: if (poll != RESET_SLEEP) {
1.169 thorpej 1010: if (wdc->cap & WDC_CAPABILITY_IRQACK)
1011: wdc->irqack(chp);
1.156 bouyer 1012: splx(s);
1013: }
1.2 bouyer 1014:
1.31 bouyer 1015: drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00;
1016: drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00;
1.137 bouyer 1017: drv_mask2 = __wdcwait_reset(chp, drv_mask1,
1018: (poll == RESET_SLEEP) ? 0 : 1);
1019: if (drv_mask2 != drv_mask1) {
1.31 bouyer 1020: printf("%s channel %d: reset failed for",
1.169 thorpej 1021: wdc->sc_dev.dv_xname, chp->ch_channel);
1.31 bouyer 1022: if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0)
1023: printf(" drive 0");
1024: if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0)
1025: printf(" drive 1");
1026: printf("\n");
1027: }
1.137 bouyer 1028: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
1.31 bouyer 1029: return (drv_mask1 != drv_mask2) ? 1 : 0;
1030: }
1031:
1032: static int
1.168 thorpej 1033: __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll)
1.31 bouyer 1034: {
1.169 thorpej 1035: struct wdc_softc *wdc = chp->ch_wdc;
1.137 bouyer 1036: int timeout, nloop;
1.149 bouyer 1037: u_int8_t st0 = 0, st1 = 0;
1.70 bouyer 1038: #ifdef WDCDEBUG
1.146 christos 1039: u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0;
1040: u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0;
1.70 bouyer 1041: #endif
1.137 bouyer 1042:
1043: if (poll)
1044: nloop = WDCNDELAY_RST;
1045: else
1046: nloop = WDC_RESET_WAIT * hz / 1000;
1.31 bouyer 1047: /* wait for BSY to deassert */
1.137 bouyer 1048: for (timeout = 0; timeout < nloop; timeout++) {
1.174 bouyer 1049: if ((drv_mask & 0x01) != 0) {
1050: if (wdc && wdc->cap & WDC_CAPABILITY_SELECT)
1051: wdc->select(chp,0);
1052: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
1053: 0, WDSD_IBM); /* master */
1054: delay(10);
1055: st0 = bus_space_read_1(chp->cmd_iot,
1056: chp->cmd_iohs[wd_status], 0);
1.70 bouyer 1057: #ifdef WDCDEBUG
1.174 bouyer 1058: sc0 = bus_space_read_1(chp->cmd_iot,
1059: chp->cmd_iohs[wd_seccnt], 0);
1060: sn0 = bus_space_read_1(chp->cmd_iot,
1061: chp->cmd_iohs[wd_sector], 0);
1062: cl0 = bus_space_read_1(chp->cmd_iot,
1063: chp->cmd_iohs[wd_cyl_lo], 0);
1064: ch0 = bus_space_read_1(chp->cmd_iot,
1065: chp->cmd_iohs[wd_cyl_hi], 0);
1.70 bouyer 1066: #endif
1.174 bouyer 1067: }
1068: if ((drv_mask & 0x02) != 0) {
1069: if (wdc && wdc->cap & WDC_CAPABILITY_SELECT)
1070: wdc->select(chp,1);
1071: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
1072: 0, WDSD_IBM | 0x10); /* slave */
1073: delay(10);
1074: st1 = bus_space_read_1(chp->cmd_iot,
1075: chp->cmd_iohs[wd_status], 0);
1.70 bouyer 1076: #ifdef WDCDEBUG
1.174 bouyer 1077: sc1 = bus_space_read_1(chp->cmd_iot,
1078: chp->cmd_iohs[wd_seccnt], 0);
1079: sn1 = bus_space_read_1(chp->cmd_iot,
1080: chp->cmd_iohs[wd_sector], 0);
1081: cl1 = bus_space_read_1(chp->cmd_iot,
1082: chp->cmd_iohs[wd_cyl_lo], 0);
1083: ch1 = bus_space_read_1(chp->cmd_iot,
1084: chp->cmd_iohs[wd_cyl_hi], 0);
1.70 bouyer 1085: #endif
1.174 bouyer 1086: }
1.31 bouyer 1087:
1088: if ((drv_mask & 0x01) == 0) {
1089: /* no master */
1090: if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) {
1091: /* No master, slave is ready, it's done */
1.65 bouyer 1092: goto end;
1.31 bouyer 1093: }
1094: } else if ((drv_mask & 0x02) == 0) {
1095: /* no slave */
1096: if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) {
1097: /* No slave, master is ready, it's done */
1.65 bouyer 1098: goto end;
1.31 bouyer 1099: }
1.2 bouyer 1100: } else {
1.31 bouyer 1101: /* Wait for both master and slave to be ready */
1102: if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) {
1.65 bouyer 1103: goto end;
1.2 bouyer 1104: }
1105: }
1.137 bouyer 1106: if (poll)
1107: delay(WDCDELAY);
1108: else
1109: tsleep(&nloop, PRIBIO, "atarst", 1);
1.2 bouyer 1110: }
1.116 wiz 1111: /* Reset timed out. Maybe it's because drv_mask was not right */
1.31 bouyer 1112: if (st0 & WDCS_BSY)
1113: drv_mask &= ~0x01;
1114: if (st1 & WDCS_BSY)
1115: drv_mask &= ~0x02;
1.65 bouyer 1116: end:
1.70 bouyer 1117: WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x "
1118: "cl=0x%x ch=0x%x\n",
1.169 thorpej 1119: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
1120: chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE);
1.70 bouyer 1121: WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x "
1122: "cl=0x%x ch=0x%x\n",
1.169 thorpej 1123: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
1124: chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE);
1.70 bouyer 1125:
1.149 bouyer 1126: WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n",
1.169 thorpej 1127: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel,
1.149 bouyer 1128: st0, st1), DEBUG_PROBE);
1.65 bouyer 1129:
1.31 bouyer 1130: return drv_mask;
1.2 bouyer 1131: }
1132:
1133: /*
1.31 bouyer 1134: * Wait for a drive to be !BSY, and have mask in its status register.
1135: * return -1 for a timeout after "timeout" ms.
1.2 bouyer 1136: */
1.167 thorpej 1137: static int
1.168 thorpej 1138: __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout)
1.2 bouyer 1139: {
1.169 thorpej 1140: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 1141: u_char status;
1142: int time = 0;
1.60 abs 1143:
1.169 thorpej 1144: WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ?
1145: wdc->sc_dev.dv_xname : "none",
1146: chp->ch_channel), DEBUG_STATUS);
1.31 bouyer 1147: chp->ch_error = 0;
1148:
1149: timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */
1.2 bouyer 1150:
1.31 bouyer 1151: for (;;) {
1152: chp->ch_status = status =
1.157 fvdl 1153: bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0);
1.131 mycroft 1154: if ((status & (WDCS_BSY | mask)) == bits)
1.31 bouyer 1155: break;
1156: if (++time > timeout) {
1.137 bouyer 1157: WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), "
1.87 bouyer 1158: "status %x error %x (mask 0x%x bits 0x%x)\n",
1159: time, status,
1.157 fvdl 1160: bus_space_read_1(chp->cmd_iot,
1161: chp->cmd_iohs[wd_error], 0), mask, bits),
1.87 bouyer 1162: DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY);
1.137 bouyer 1163: return(WDCWAIT_TOUT);
1.31 bouyer 1164: }
1165: delay(WDCDELAY);
1.2 bouyer 1166: }
1.87 bouyer 1167: #ifdef WDCDEBUG
1168: if (time > 0 && (wdcdebug_mask & DEBUG_DELAY))
1.137 bouyer 1169: printf("__wdcwait: did busy-wait, time=%d\n", time);
1.87 bouyer 1170: #endif
1.31 bouyer 1171: if (status & WDCS_ERR)
1.157 fvdl 1172: chp->ch_error = bus_space_read_1(chp->cmd_iot,
1173: chp->cmd_iohs[wd_error], 0);
1.31 bouyer 1174: #ifdef WDCNDELAY_DEBUG
1175: /* After autoconfig, there should be no long delays. */
1176: if (!cold && time > WDCNDELAY_DEBUG) {
1.165 thorpej 1177: struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.31 bouyer 1178: if (xfer == NULL)
1179: printf("%s channel %d: warning: busy-wait took %dus\n",
1.169 thorpej 1180: wdc->sc_dev.dv_xname, chp->ch_channel,
1.31 bouyer 1181: WDCDELAY * time);
1182: else
1183: printf("%s:%d:%d: warning: busy-wait took %dus\n",
1.169 thorpej 1184: wdc->sc_dev.dv_xname, chp->ch_channel,
1.31 bouyer 1185: xfer->drive,
1186: WDCDELAY * time);
1.2 bouyer 1187: }
1188: #endif
1.137 bouyer 1189: return(WDCWAIT_OK);
1190: }
1191:
1192: /*
1193: * Call __wdcwait(), polling using tsleep() or waking up the kernel
1194: * thread if possible
1195: */
1196: int
1.168 thorpej 1197: wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags)
1.137 bouyer 1198: {
1199: int error, i, timeout_hz = mstohz(timeout);
1200:
1201: if (timeout_hz == 0 ||
1202: (flags & (AT_WAIT | AT_POLL)) == AT_POLL)
1203: error = __wdcwait(chp, mask, bits, timeout);
1204: else {
1205: error = __wdcwait(chp, mask, bits, WDCDELAY_POLL);
1206: if (error != 0) {
1.147 bouyer 1207: if ((chp->ch_flags & WDCF_TH_RUN) ||
1208: (flags & AT_WAIT)) {
1.137 bouyer 1209: /*
1.147 bouyer 1210: * we're running in the channel thread
1211: * or some userland thread context
1.137 bouyer 1212: */
1213: for (i = 0; i < timeout_hz; i++) {
1214: if (__wdcwait(chp, mask, bits,
1215: WDCDELAY_POLL) == 0) {
1216: error = 0;
1217: break;
1218: }
1219: tsleep(&chp, PRIBIO, "atapoll", 1);
1220: }
1221: } else {
1222: /*
1223: * we're probably in interrupt context,
1224: * ask the thread to come back here
1225: */
1.147 bouyer 1226: #ifdef DIAGNOSTIC
1.148 bouyer 1227: if (chp->ch_queue->queue_freeze > 0)
1228: panic("wdcwait: queue_freeze");
1.147 bouyer 1229: #endif
1.148 bouyer 1230: chp->ch_queue->queue_freeze++;
1.170 thorpej 1231: wakeup(&chp->ch_thread);
1.137 bouyer 1232: return(WDCWAIT_THR);
1233: }
1234: }
1235: }
1.163 thorpej 1236: return (error);
1.2 bouyer 1237: }
1238:
1.137 bouyer 1239:
1.84 bouyer 1240: /*
1241: * Busy-wait for DMA to complete
1242: */
1243: int
1.168 thorpej 1244: wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout)
1.84 bouyer 1245: {
1.169 thorpej 1246: struct wdc_softc *wdc = chp->ch_wdc;
1.84 bouyer 1247: int time;
1.169 thorpej 1248:
1.84 bouyer 1249: for (time = 0; time < timeout * 1000 / WDCDELAY; time++) {
1.169 thorpej 1250: wdc->dma_status =
1251: (*wdc->dma_finish)(wdc->dma_arg,
1252: chp->ch_channel, xfer->c_drive, 0);
1253: if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0)
1.84 bouyer 1254: return 0;
1255: delay(WDCDELAY);
1256: }
1257: /* timeout, force a DMA halt */
1.169 thorpej 1258: wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg,
1259: chp->ch_channel, xfer->c_drive, 1);
1.84 bouyer 1260: return 1;
1261: }
1262:
1.31 bouyer 1263: void
1.163 thorpej 1264: wdctimeout(void *arg)
1.2 bouyer 1265: {
1.168 thorpej 1266: struct wdc_channel *chp = (struct wdc_channel *)arg;
1.169 thorpej 1267: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1268: struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.31 bouyer 1269: int s;
1.2 bouyer 1270:
1.31 bouyer 1271: WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS);
1272:
1273: s = splbio();
1274: if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) {
1275: __wdcerror(chp, "lost interrupt");
1.88 mrg 1276: printf("\ttype: %s tc_bcount: %d tc_skip: %d\n",
1277: (xfer->c_flags & C_ATAPI) ? "atapi" : "ata",
1278: xfer->c_bcount,
1279: xfer->c_skip);
1.84 bouyer 1280: if (chp->ch_flags & WDCF_DMA_WAIT) {
1.169 thorpej 1281: wdc->dma_status =
1282: (*wdc->dma_finish)(wdc->dma_arg,
1283: chp->ch_channel, xfer->c_drive, 1);
1.84 bouyer 1284: chp->ch_flags &= ~WDCF_DMA_WAIT;
1285: }
1.31 bouyer 1286: /*
1.119 drochner 1287: * Call the interrupt routine. If we just missed an interrupt,
1.31 bouyer 1288: * it will do what's needed. Else, it will take the needed
1289: * action (reset the device).
1.70 bouyer 1290: * Before that we need to reinstall the timeout callback,
1291: * in case it will miss another irq while in this transfer
1292: * We arbitray chose it to be 1s
1.31 bouyer 1293: */
1.81 thorpej 1294: callout_reset(&chp->ch_callout, hz, wdctimeout, chp);
1.31 bouyer 1295: xfer->c_flags |= C_TIMEOU;
1296: chp->ch_flags &= ~WDCF_IRQ_WAIT;
1.66 bouyer 1297: xfer->c_intr(chp, xfer, 1);
1.31 bouyer 1298: } else
1299: __wdcerror(chp, "missing untimeout");
1300: splx(s);
1.2 bouyer 1301: }
1302:
1.31 bouyer 1303: /*
1.152 wiz 1304: * Probe drive's capabilities, for use by the controller later
1.31 bouyer 1305: * Assumes drvp points to an existing drive.
1306: * XXX this should be a controller-indep function
1307: */
1.2 bouyer 1308: void
1.163 thorpej 1309: wdc_probe_caps(struct ata_drive_datas *drvp)
1.2 bouyer 1310: {
1.31 bouyer 1311: struct ataparams params, params2;
1.168 thorpej 1312: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 1313: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 1314: struct device *drv_dev = drvp->drv_softc;
1315: int i, printed;
1316: char *sep = "";
1.48 bouyer 1317: int cf_flags;
1.31 bouyer 1318:
1.125 mycroft 1319: if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) {
1.31 bouyer 1320: /* IDENTIFY failed. Can't tell more about the device */
1.2 bouyer 1321: return;
1322: }
1.31 bouyer 1323: if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
1324: (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) {
1.2 bouyer 1325: /*
1.39 bouyer 1326: * Controller claims 16 and 32 bit transfers.
1327: * Re-do an IDENTIFY with 32-bit transfers,
1.31 bouyer 1328: * and compare results.
1.2 bouyer 1329: */
1.31 bouyer 1330: drvp->drive_flags |= DRIVE_CAP32;
1.125 mycroft 1331: ata_get_params(drvp, AT_WAIT, ¶ms2);
1.31 bouyer 1332: if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) {
1333: /* Not good. fall back to 16bits */
1334: drvp->drive_flags &= ~DRIVE_CAP32;
1335: } else {
1.125 mycroft 1336: aprint_normal("%s: 32-bit data port\n",
1.123 thorpej 1337: drv_dev->dv_xname);
1.2 bouyer 1338: }
1339: }
1.55 bouyer 1340: #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */
1341: if (params.atap_ata_major > 0x01 &&
1342: params.atap_ata_major != 0xffff) {
1343: for (i = 14; i > 0; i--) {
1344: if (params.atap_ata_major & (1 << i)) {
1.125 mycroft 1345: aprint_normal("%s: ATA version %d\n",
1346: drv_dev->dv_xname, i);
1.55 bouyer 1347: drvp->ata_vers = i;
1348: break;
1349: }
1350: }
1.125 mycroft 1351: }
1.55 bouyer 1352: #endif
1.2 bouyer 1353:
1.31 bouyer 1354: /* An ATAPI device is at last PIO mode 3 */
1355: if (drvp->drive_flags & DRIVE_ATAPI)
1356: drvp->PIO_mode = 3;
1.2 bouyer 1357:
1358: /*
1.31 bouyer 1359: * It's not in the specs, but it seems that some drive
1360: * returns 0xffff in atap_extensions when this field is invalid
1.2 bouyer 1361: */
1.31 bouyer 1362: if (params.atap_extensions != 0xffff &&
1363: (params.atap_extensions & WDC_EXT_MODES)) {
1364: printed = 0;
1365: /*
1366: * XXX some drives report something wrong here (they claim to
1367: * support PIO mode 8 !). As mode is coded on 3 bits in
1368: * SET FEATURE, limit it to 7 (so limit i to 4).
1.116 wiz 1369: * If higher mode than 7 is found, abort.
1.31 bouyer 1370: */
1.39 bouyer 1371: for (i = 7; i >= 0; i--) {
1.31 bouyer 1372: if ((params.atap_piomode_supp & (1 << i)) == 0)
1373: continue;
1.39 bouyer 1374: if (i > 4)
1375: return;
1.31 bouyer 1376: /*
1377: * See if mode is accepted.
1378: * If the controller can't set its PIO mode,
1379: * assume the defaults are good, so don't try
1380: * to set it
1381: */
1382: if ((wdc->cap & WDC_CAPABILITY_MODE) != 0)
1.137 bouyer 1383: /*
1384: * It's OK to pool here, it's fast enouth
1385: * to not bother waiting for interrupt
1386: */
1.31 bouyer 1387: if (ata_set_mode(drvp, 0x08 | (i + 3),
1.125 mycroft 1388: AT_WAIT) != CMD_OK)
1.2 bouyer 1389: continue;
1.31 bouyer 1390: if (!printed) {
1.123 thorpej 1391: aprint_normal("%s: drive supports PIO mode %d",
1.39 bouyer 1392: drv_dev->dv_xname, i + 3);
1.31 bouyer 1393: sep = ",";
1394: printed = 1;
1395: }
1396: /*
1397: * If controller's driver can't set its PIO mode,
1398: * get the highter one for the drive.
1399: */
1400: if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 ||
1.52 bouyer 1401: wdc->PIO_cap >= i + 3) {
1.31 bouyer 1402: drvp->PIO_mode = i + 3;
1.48 bouyer 1403: drvp->PIO_cap = i + 3;
1.2 bouyer 1404: break;
1405: }
1406: }
1.31 bouyer 1407: if (!printed) {
1408: /*
1409: * We didn't find a valid PIO mode.
1410: * Assume the values returned for DMA are buggy too
1411: */
1412: return;
1.2 bouyer 1413: }
1.35 bouyer 1414: drvp->drive_flags |= DRIVE_MODE;
1.31 bouyer 1415: printed = 0;
1416: for (i = 7; i >= 0; i--) {
1417: if ((params.atap_dmamode_supp & (1 << i)) == 0)
1418: continue;
1419: if ((wdc->cap & WDC_CAPABILITY_DMA) &&
1420: (wdc->cap & WDC_CAPABILITY_MODE))
1.125 mycroft 1421: if (ata_set_mode(drvp, 0x20 | i, AT_WAIT)
1.31 bouyer 1422: != CMD_OK)
1423: continue;
1424: if (!printed) {
1.123 thorpej 1425: aprint_normal("%s DMA mode %d", sep, i);
1.31 bouyer 1426: sep = ",";
1427: printed = 1;
1428: }
1429: if (wdc->cap & WDC_CAPABILITY_DMA) {
1430: if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1.52 bouyer 1431: wdc->DMA_cap < i)
1.31 bouyer 1432: continue;
1433: drvp->DMA_mode = i;
1.48 bouyer 1434: drvp->DMA_cap = i;
1.31 bouyer 1435: drvp->drive_flags |= DRIVE_DMA;
1436: }
1.2 bouyer 1437: break;
1438: }
1.31 bouyer 1439: if (params.atap_extensions & WDC_EXT_UDMA_MODES) {
1.71 bouyer 1440: printed = 0;
1.31 bouyer 1441: for (i = 7; i >= 0; i--) {
1442: if ((params.atap_udmamode_supp & (1 << i))
1443: == 0)
1444: continue;
1445: if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1446: (wdc->cap & WDC_CAPABILITY_UDMA))
1447: if (ata_set_mode(drvp, 0x40 | i,
1.125 mycroft 1448: AT_WAIT) != CMD_OK)
1.31 bouyer 1449: continue;
1.71 bouyer 1450: if (!printed) {
1.123 thorpej 1451: aprint_normal("%s Ultra-DMA mode %d",
1452: sep, i);
1.93 wrstuden 1453: if (i == 2)
1.123 thorpej 1454: aprint_normal(" (Ultra/33)");
1.93 wrstuden 1455: else if (i == 4)
1.123 thorpej 1456: aprint_normal(" (Ultra/66)");
1.93 wrstuden 1457: else if (i == 5)
1.123 thorpej 1458: aprint_normal(" (Ultra/100)");
1.117 bouyer 1459: else if (i == 6)
1.123 thorpej 1460: aprint_normal(" (Ultra/133)");
1.71 bouyer 1461: sep = ",";
1462: printed = 1;
1463: }
1.31 bouyer 1464: if (wdc->cap & WDC_CAPABILITY_UDMA) {
1.50 bouyer 1465: if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1.52 bouyer 1466: wdc->UDMA_cap < i)
1.50 bouyer 1467: continue;
1.31 bouyer 1468: drvp->UDMA_mode = i;
1.48 bouyer 1469: drvp->UDMA_cap = i;
1.31 bouyer 1470: drvp->drive_flags |= DRIVE_UDMA;
1471: }
1472: break;
1473: }
1474: }
1.123 thorpej 1475: aprint_normal("\n");
1.55 bouyer 1476: }
1477:
1478: /* Try to guess ATA version here, if it didn't get reported */
1479: if (drvp->ata_vers == 0) {
1480: if (drvp->drive_flags & DRIVE_UDMA)
1481: drvp->ata_vers = 4; /* should be at last ATA-4 */
1482: else if (drvp->PIO_cap > 2)
1483: drvp->ata_vers = 2; /* should be at last ATA-2 */
1.48 bouyer 1484: }
1485: cf_flags = drv_dev->dv_cfdata->cf_flags;
1486: if (cf_flags & ATA_CONFIG_PIO_SET) {
1487: drvp->PIO_mode =
1488: (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF;
1489: drvp->drive_flags |= DRIVE_MODE;
1490: }
1491: if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) {
1492: /* don't care about DMA modes */
1493: return;
1494: }
1495: if (cf_flags & ATA_CONFIG_DMA_SET) {
1496: if ((cf_flags & ATA_CONFIG_DMA_MODES) ==
1497: ATA_CONFIG_DMA_DISABLE) {
1498: drvp->drive_flags &= ~DRIVE_DMA;
1499: } else {
1500: drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >>
1501: ATA_CONFIG_DMA_OFF;
1502: drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE;
1503: }
1.101 bouyer 1504: }
1505: if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) {
1506: /* don't care about UDMA modes */
1507: return;
1.48 bouyer 1508: }
1509: if (cf_flags & ATA_CONFIG_UDMA_SET) {
1510: if ((cf_flags & ATA_CONFIG_UDMA_MODES) ==
1511: ATA_CONFIG_UDMA_DISABLE) {
1512: drvp->drive_flags &= ~DRIVE_UDMA;
1513: } else {
1514: drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >>
1515: ATA_CONFIG_UDMA_OFF;
1516: drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE;
1517: }
1.2 bouyer 1518: }
1.54 bouyer 1519: }
1520:
1521: /*
1.56 bouyer 1522: * downgrade the transfer mode of a drive after an error. return 1 if
1.54 bouyer 1523: * downgrade was possible, 0 otherwise.
1524: */
1525: int
1.163 thorpej 1526: wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags)
1.54 bouyer 1527: {
1.168 thorpej 1528: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 1529: struct wdc_softc *wdc = chp->ch_wdc;
1.54 bouyer 1530: struct device *drv_dev = drvp->drv_softc;
1531: int cf_flags = drv_dev->dv_cfdata->cf_flags;
1532:
1533: /* if drive or controller don't know its mode, we can't do much */
1534: if ((drvp->drive_flags & DRIVE_MODE) == 0 ||
1535: (wdc->cap & WDC_CAPABILITY_MODE) == 0)
1536: return 0;
1537: /* current drive mode was set by a config flag, let it this way */
1538: if ((cf_flags & ATA_CONFIG_PIO_SET) ||
1539: (cf_flags & ATA_CONFIG_DMA_SET) ||
1540: (cf_flags & ATA_CONFIG_UDMA_SET))
1541: return 0;
1542:
1.61 bouyer 1543: /*
1.180 ! mycroft 1544: * If we were using Ultra-DMA mode, downgrade to the next lower mode.
1.73 bouyer 1545: */
1.78 bouyer 1546: if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) {
1.180 ! mycroft 1547: drvp->UDMA_mode--;
1.78 bouyer 1548: printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n",
1.73 bouyer 1549: drv_dev->dv_xname, drvp->UDMA_mode);
1550: }
1551:
1552: /*
1.180 ! mycroft 1553: * If we were using ultra-DMA, don't downgrade to multiword DMA.
1.61 bouyer 1554: */
1.180 ! mycroft 1555: else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
1.61 bouyer 1556: drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
1.54 bouyer 1557: drvp->PIO_mode = drvp->PIO_cap;
1.56 bouyer 1558: printf("%s: transfer error, downgrading to PIO mode %d\n",
1.54 bouyer 1559: drv_dev->dv_xname, drvp->PIO_mode);
1560: } else /* already using PIO, can't downgrade */
1561: return 0;
1562:
1563: wdc->set_modes(chp);
1.137 bouyer 1564: wdc_print_modes(chp);
1565: /* reset the channel, which will shedule all drives for setup */
1566: wdc_reset_channel(drvp, flags);
1.54 bouyer 1567: return 1;
1.2 bouyer 1568: }
1569:
1570: int
1.163 thorpej 1571: wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c)
1.31 bouyer 1572: {
1.168 thorpej 1573: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 1574: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1575: struct ata_xfer *xfer;
1.31 bouyer 1576: int s, ret;
1.2 bouyer 1577:
1.34 bouyer 1578: WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n",
1.169 thorpej 1579: wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive),
1.34 bouyer 1580: DEBUG_FUNCS);
1.2 bouyer 1581:
1.31 bouyer 1582: /* set up an xfer and queue. Wait for completion */
1583: xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP :
1584: WDC_NOSLEEP);
1585: if (xfer == NULL) {
1586: return WDC_TRY_AGAIN;
1587: }
1.2 bouyer 1588:
1.169 thorpej 1589: if (wdc->cap & WDC_CAPABILITY_NOIRQ)
1.98 bjh21 1590: wdc_c->flags |= AT_POLL;
1.31 bouyer 1591: if (wdc_c->flags & AT_POLL)
1592: xfer->c_flags |= C_POLL;
1.165 thorpej 1593: xfer->c_drive = drvp->drive;
1594: xfer->c_databuf = wdc_c->data;
1.31 bouyer 1595: xfer->c_bcount = wdc_c->bcount;
1.165 thorpej 1596: xfer->c_cmd = wdc_c;
1.31 bouyer 1597: xfer->c_start = __wdccommand_start;
1598: xfer->c_intr = __wdccommand_intr;
1.75 enami 1599: xfer->c_kill_xfer = __wdccommand_done;
1.2 bouyer 1600:
1.31 bouyer 1601: s = splbio();
1602: wdc_exec_xfer(chp, xfer);
1603: #ifdef DIAGNOSTIC
1604: if ((wdc_c->flags & AT_POLL) != 0 &&
1605: (wdc_c->flags & AT_DONE) == 0)
1.118 provos 1606: panic("wdc_exec_command: polled command not done");
1.2 bouyer 1607: #endif
1.31 bouyer 1608: if (wdc_c->flags & AT_DONE) {
1609: ret = WDC_COMPLETE;
1610: } else {
1611: if (wdc_c->flags & AT_WAIT) {
1.69 bouyer 1612: while ((wdc_c->flags & AT_DONE) == 0) {
1613: tsleep(wdc_c, PRIBIO, "wdccmd", 0);
1614: }
1.31 bouyer 1615: ret = WDC_COMPLETE;
1616: } else {
1617: ret = WDC_QUEUED;
1.2 bouyer 1618: }
1619: }
1.31 bouyer 1620: splx(s);
1621: return ret;
1.2 bouyer 1622: }
1623:
1.167 thorpej 1624: static void
1.168 thorpej 1625: __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer)
1.31 bouyer 1626: {
1.169 thorpej 1627: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1628: int drive = xfer->c_drive;
1629: struct wdc_command *wdc_c = xfer->c_cmd;
1.31 bouyer 1630:
1.34 bouyer 1631: WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n",
1.169 thorpej 1632: wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive),
1.34 bouyer 1633: DEBUG_FUNCS);
1.31 bouyer 1634:
1.169 thorpej 1635: if (wdc->cap & WDC_CAPABILITY_SELECT)
1636: wdc->select(chp,drive);
1.157 fvdl 1637: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.31 bouyer 1638: WDSD_IBM | (drive << 4));
1.137 bouyer 1639: switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ,
1640: wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) {
1641: case WDCWAIT_OK:
1642: break;
1643: case WDCWAIT_TOUT:
1.31 bouyer 1644: wdc_c->flags |= AT_TIMEOU;
1645: __wdccommand_done(chp, xfer);
1.53 bouyer 1646: return;
1.137 bouyer 1647: case WDCWAIT_THR:
1648: return;
1.31 bouyer 1649: }
1.135 bouyer 1650: if (wdc_c->flags & AT_POLL) {
1651: /* polled command, disable interrupts */
1652: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
1653: WDCTL_4BIT | WDCTL_IDS);
1654: }
1.31 bouyer 1655: wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head,
1.178 thorpej 1656: wdc_c->r_sector, wdc_c->r_count, wdc_c->r_features);
1.139 bouyer 1657:
1.31 bouyer 1658: if ((wdc_c->flags & AT_POLL) == 0) {
1659: chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */
1.81 thorpej 1660: callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz,
1661: wdctimeout, chp);
1.31 bouyer 1662: return;
1.2 bouyer 1663: }
1664: /*
1.31 bouyer 1665: * Polled command. Wait for drive ready or drq. Done in intr().
1666: * Wait for at last 400ns for status bit to be valid.
1.2 bouyer 1667: */
1.134 mycroft 1668: delay(10); /* 400ns delay */
1.66 bouyer 1669: __wdccommand_intr(chp, xfer, 0);
1.2 bouyer 1670: }
1671:
1.167 thorpej 1672: static int
1.168 thorpej 1673: __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq)
1.2 bouyer 1674: {
1.169 thorpej 1675: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1676: struct wdc_command *wdc_c = xfer->c_cmd;
1.31 bouyer 1677: int bcount = wdc_c->bcount;
1678: char *data = wdc_c->data;
1.137 bouyer 1679: int wflags;
1680:
1681: if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) {
1682: /* both wait and poll, we can tsleep here */
1.147 bouyer 1683: wflags = AT_WAIT | AT_POLL;
1.137 bouyer 1684: } else {
1685: wflags = AT_POLL;
1686: }
1.31 bouyer 1687:
1.163 thorpej 1688: again:
1.34 bouyer 1689: WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n",
1.169 thorpej 1690: wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive),
1.165 thorpej 1691: DEBUG_INTR);
1.137 bouyer 1692: /*
1693: * after a ATAPI_SOFT_RESET, the device will have released the bus.
1694: * Reselect again, it doesn't hurt for others commands, and the time
1695: * penalty for the extra regiter write is acceptable,
1696: * wdc_exec_command() isn't called often (mosly for autoconfig)
1697: */
1.157 fvdl 1698: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.165 thorpej 1699: WDSD_IBM | (xfer->c_drive << 4));
1.114 bouyer 1700: if ((wdc_c->flags & AT_XFDONE) != 0) {
1701: /*
1702: * We have completed a data xfer. The drive should now be
1703: * in its initial state
1704: */
1705: if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ,
1.137 bouyer 1706: wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0,
1707: wflags) == WDCWAIT_TOUT) {
1.114 bouyer 1708: if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1709: return 0; /* IRQ was not for us */
1710: wdc_c->flags |= AT_TIMEOU;
1711: }
1.131 mycroft 1712: goto out;
1.114 bouyer 1713: }
1.31 bouyer 1714: if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask,
1.137 bouyer 1715: (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) {
1.66 bouyer 1716: if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1.63 bouyer 1717: return 0; /* IRQ was not for us */
1718: wdc_c->flags |= AT_TIMEOU;
1.131 mycroft 1719: goto out;
1.2 bouyer 1720: }
1.169 thorpej 1721: if (wdc->cap & WDC_CAPABILITY_IRQACK)
1722: wdc->irqack(chp);
1.31 bouyer 1723: if (wdc_c->flags & AT_READ) {
1.131 mycroft 1724: if ((chp->ch_status & WDCS_DRQ) == 0) {
1725: wdc_c->flags |= AT_TIMEOU;
1726: goto out;
1727: }
1.165 thorpej 1728: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) {
1.31 bouyer 1729: bus_space_read_multi_4(chp->data32iot, chp->data32ioh,
1730: 0, (u_int32_t*)data, bcount >> 2);
1731: data += bcount & 0xfffffffc;
1732: bcount = bcount & 0x03;
1733: }
1734: if (bcount > 0)
1.157 fvdl 1735: bus_space_read_multi_2(chp->cmd_iot,
1736: chp->cmd_iohs[wd_data], 0,
1737: (u_int16_t *)data, bcount >> 1);
1.114 bouyer 1738: /* at this point the drive should be in its initial state */
1739: wdc_c->flags |= AT_XFDONE;
1.137 bouyer 1740: /* XXX should read status register here ? */
1.131 mycroft 1741: } else if (wdc_c->flags & AT_WRITE) {
1742: if ((chp->ch_status & WDCS_DRQ) == 0) {
1.114 bouyer 1743: wdc_c->flags |= AT_TIMEOU;
1.131 mycroft 1744: goto out;
1745: }
1.165 thorpej 1746: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) {
1.31 bouyer 1747: bus_space_write_multi_4(chp->data32iot, chp->data32ioh,
1748: 0, (u_int32_t*)data, bcount >> 2);
1749: data += bcount & 0xfffffffc;
1750: bcount = bcount & 0x03;
1751: }
1752: if (bcount > 0)
1.157 fvdl 1753: bus_space_write_multi_2(chp->cmd_iot,
1754: chp->cmd_iohs[wd_data], 0,
1755: (u_int16_t *)data, bcount >> 1);
1.114 bouyer 1756: wdc_c->flags |= AT_XFDONE;
1757: if ((wdc_c->flags & AT_POLL) == 0) {
1758: chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */
1759: callout_reset(&chp->ch_callout,
1760: wdc_c->timeout / 1000 * hz, wdctimeout, chp);
1761: return 1;
1762: } else {
1763: goto again;
1764: }
1.2 bouyer 1765: }
1.163 thorpej 1766: out:
1.31 bouyer 1767: __wdccommand_done(chp, xfer);
1768: return 1;
1.2 bouyer 1769: }
1770:
1.167 thorpej 1771: static void
1.168 thorpej 1772: __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer)
1.2 bouyer 1773: {
1.169 thorpej 1774: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1775: struct wdc_command *wdc_c = xfer->c_cmd;
1.2 bouyer 1776:
1.34 bouyer 1777: WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n",
1.169 thorpej 1778: wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive),
1.165 thorpej 1779: DEBUG_FUNCS);
1.70 bouyer 1780:
1.81 thorpej 1781: callout_stop(&chp->ch_callout);
1.70 bouyer 1782:
1.31 bouyer 1783: if (chp->ch_status & WDCS_DWF)
1784: wdc_c->flags |= AT_DF;
1785: if (chp->ch_status & WDCS_ERR) {
1786: wdc_c->flags |= AT_ERROR;
1787: wdc_c->r_error = chp->ch_error;
1788: }
1789: wdc_c->flags |= AT_DONE;
1.80 enami 1790: if ((wdc_c->flags & AT_READREG) != 0 &&
1.169 thorpej 1791: (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 &&
1.75 enami 1792: (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) {
1.157 fvdl 1793: wdc_c->r_head = bus_space_read_1(chp->cmd_iot,
1794: chp->cmd_iohs[wd_sdh], 0);
1.179 mycroft 1795: wdc_c->r_count = bus_space_read_1(chp->cmd_iot,
1796: chp->cmd_iohs[wd_seccnt], 0);
1797: wdc_c->r_sector = bus_space_read_1(chp->cmd_iot,
1798: chp->cmd_iohs[wd_sector], 0);
1799: wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot,
1800: chp->cmd_iohs[wd_cyl_lo], 0);
1.157 fvdl 1801: wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot,
1802: chp->cmd_iohs[wd_cyl_hi], 0) << 8;
1803: wdc_c->r_error = bus_space_read_1(chp->cmd_iot,
1804: chp->cmd_iohs[wd_error], 0);
1.178 thorpej 1805: wdc_c->r_features = bus_space_read_1(chp->cmd_iot,
1806: chp->cmd_iohs[wd_features], 0);
1.135 bouyer 1807: }
1.137 bouyer 1808:
1.135 bouyer 1809: if (wdc_c->flags & AT_POLL) {
1810: /* enable interrupts */
1811: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
1812: WDCTL_4BIT);
1.173 bouyer 1813: delay(10); /* some drives need a little delay here */
1.46 kenh 1814: }
1.31 bouyer 1815: wdc_free_xfer(chp, xfer);
1.71 bouyer 1816: if (wdc_c->flags & AT_WAIT)
1817: wakeup(wdc_c);
1818: else if (wdc_c->callback)
1819: wdc_c->callback(wdc_c->callback_arg);
1.45 drochner 1820: wdcstart(chp);
1.31 bouyer 1821: return;
1.2 bouyer 1822: }
1823:
1824: /*
1.31 bouyer 1825: * Send a command. The drive should be ready.
1.2 bouyer 1826: * Assumes interrupts are blocked.
1827: */
1.31 bouyer 1828: void
1.168 thorpej 1829: wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command,
1.163 thorpej 1830: u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count,
1.178 thorpej 1831: u_int8_t features)
1.31 bouyer 1832: {
1.169 thorpej 1833: struct wdc_softc *wdc = chp->ch_wdc;
1.163 thorpej 1834:
1.31 bouyer 1835: WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d "
1.178 thorpej 1836: "sector=%d count=%d features=%d\n", wdc->sc_dev.dv_xname,
1.169 thorpej 1837: chp->ch_channel, drive, command, cylin, head, sector, count,
1.178 thorpej 1838: features), DEBUG_FUNCS);
1.31 bouyer 1839:
1.169 thorpej 1840: if (wdc->cap & WDC_CAPABILITY_SELECT)
1841: wdc->select(chp,drive);
1.107 dbj 1842:
1.31 bouyer 1843: /* Select drive, head, and addressing mode. */
1.157 fvdl 1844: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.31 bouyer 1845: WDSD_IBM | (drive << 4) | head);
1.177 thorpej 1846: /* Load parameters into the wd_features register. */
1847: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0,
1.178 thorpej 1848: features);
1.179 mycroft 1849: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count);
1850: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector);
1.157 fvdl 1851: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin);
1852: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi],
1853: 0, cylin >> 8);
1.108 christos 1854:
1855: /* Send command. */
1.157 fvdl 1856: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command);
1.108 christos 1857: return;
1858: }
1859:
1860: /*
1861: * Send a 48-bit addressing command. The drive should be ready.
1862: * Assumes interrupts are blocked.
1863: */
1864: void
1.168 thorpej 1865: wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command,
1.163 thorpej 1866: u_int64_t blkno, u_int16_t count)
1.108 christos 1867: {
1.169 thorpej 1868: struct wdc_softc *wdc = chp->ch_wdc;
1.163 thorpej 1869:
1.108 christos 1870: WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d "
1.169 thorpej 1871: "count=%d\n", wdc->sc_dev.dv_xname,
1872: chp->ch_channel, drive, command, (u_int32_t) blkno, count),
1.108 christos 1873: DEBUG_FUNCS);
1874:
1.169 thorpej 1875: if (wdc->cap & WDC_CAPABILITY_SELECT)
1876: wdc->select(chp,drive);
1.108 christos 1877:
1878: /* Select drive, head, and addressing mode. */
1.157 fvdl 1879: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.108 christos 1880: (drive << 4) | WDSD_LBA);
1881:
1882: /* previous */
1.157 fvdl 1883: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0);
1884: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt],
1885: 0, count >> 8);
1.179 mycroft 1886: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo],
1887: 0, blkno >> 24);
1888: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi],
1889: 0, blkno >> 32);
1.157 fvdl 1890: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi],
1891: 0, blkno >> 40);
1.108 christos 1892:
1893: /* current */
1.157 fvdl 1894: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0);
1895: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count);
1.179 mycroft 1896: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno);
1897: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi],
1898: 0, blkno >> 8);
1.157 fvdl 1899: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi],
1900: 0, blkno >> 16);
1.2 bouyer 1901:
1.31 bouyer 1902: /* Send command. */
1.157 fvdl 1903: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command);
1.31 bouyer 1904: return;
1.2 bouyer 1905: }
1906:
1907: /*
1.31 bouyer 1908: * Simplified version of wdccommand(). Unbusy/ready/drq must be
1909: * tested by the caller.
1.2 bouyer 1910: */
1.31 bouyer 1911: void
1.168 thorpej 1912: wdccommandshort(struct wdc_channel *chp, int drive, int command)
1.2 bouyer 1913: {
1.169 thorpej 1914: struct wdc_softc *wdc = chp->ch_wdc;
1.2 bouyer 1915:
1.31 bouyer 1916: WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n",
1.169 thorpej 1917: wdc->sc_dev.dv_xname, chp->ch_channel, drive, command),
1.31 bouyer 1918: DEBUG_FUNCS);
1.107 dbj 1919:
1.169 thorpej 1920: if (wdc->cap & WDC_CAPABILITY_SELECT)
1921: wdc->select(chp,drive);
1.2 bouyer 1922:
1.31 bouyer 1923: /* Select drive. */
1.157 fvdl 1924: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.31 bouyer 1925: WDSD_IBM | (drive << 4));
1.2 bouyer 1926:
1.157 fvdl 1927: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command);
1.31 bouyer 1928: }
1.2 bouyer 1929:
1.31 bouyer 1930: /* Add a command to the queue and start controller. Must be called at splbio */
1.2 bouyer 1931: void
1.168 thorpej 1932: wdc_exec_xfer(struct wdc_channel *chp, struct ata_xfer *xfer)
1.2 bouyer 1933: {
1.163 thorpej 1934:
1.33 bouyer 1935: WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer,
1.169 thorpej 1936: chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
1.2 bouyer 1937:
1.31 bouyer 1938: /* complete xfer setup */
1.165 thorpej 1939: xfer->c_chp = chp;
1.2 bouyer 1940:
1.31 bouyer 1941: /*
1942: * If we are a polled command, and the list is not empty,
1943: * we are doing a dump. Drop the list to allow the polled command
1944: * to complete, we're going to reboot soon anyway.
1945: */
1946: if ((xfer->c_flags & C_POLL) != 0 &&
1.165 thorpej 1947: TAILQ_FIRST(&chp->ch_queue->queue_xfer) != NULL) {
1948: TAILQ_INIT(&chp->ch_queue->queue_xfer);
1.31 bouyer 1949: }
1.2 bouyer 1950: /* insert at the end of command list */
1.165 thorpej 1951: TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
1.31 bouyer 1952: WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n",
1.33 bouyer 1953: chp->ch_flags), DEBUG_XFERS);
1.45 drochner 1954: wdcstart(chp);
1.31 bouyer 1955: }
1.2 bouyer 1956:
1.165 thorpej 1957: struct ata_xfer *
1.163 thorpej 1958: wdc_get_xfer(int flags)
1.2 bouyer 1959: {
1.165 thorpej 1960: struct ata_xfer *xfer;
1.72 bouyer 1961: int s;
1.2 bouyer 1962:
1.72 bouyer 1963: s = splbio();
1.71 bouyer 1964: xfer = pool_get(&wdc_xfer_pool,
1965: ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK));
1.72 bouyer 1966: splx(s);
1.99 chs 1967: if (xfer != NULL) {
1.165 thorpej 1968: memset(xfer, 0, sizeof(struct ata_xfer));
1.99 chs 1969: }
1.2 bouyer 1970: return xfer;
1971: }
1972:
1973: void
1.168 thorpej 1974: wdc_free_xfer(struct wdc_channel *chp, struct ata_xfer *xfer)
1.2 bouyer 1975: {
1.169 thorpej 1976: struct wdc_softc *wdc = chp->ch_wdc;
1.2 bouyer 1977: int s;
1978:
1.31 bouyer 1979: if (wdc->cap & WDC_CAPABILITY_HWLOCK)
1980: (*wdc->free_hw)(chp);
1.2 bouyer 1981: s = splbio();
1.31 bouyer 1982: chp->ch_flags &= ~WDCF_ACTIVE;
1.165 thorpej 1983: TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
1.72 bouyer 1984: pool_put(&wdc_xfer_pool, xfer);
1.2 bouyer 1985: splx(s);
1.75 enami 1986: }
1987:
1988: /*
1.168 thorpej 1989: * Kill off all pending xfers for a wdc_channel.
1.75 enami 1990: *
1991: * Must be called at splbio().
1992: */
1993: void
1.168 thorpej 1994: wdc_kill_pending(struct wdc_channel *chp)
1.75 enami 1995: {
1.165 thorpej 1996: struct ata_xfer *xfer;
1.75 enami 1997:
1.165 thorpej 1998: while ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) != NULL) {
1999: chp = xfer->c_chp;
1.75 enami 2000: (*xfer->c_kill_xfer)(chp, xfer);
2001: }
1.2 bouyer 2002: }
2003:
1.31 bouyer 2004: static void
1.168 thorpej 2005: __wdcerror(struct wdc_channel *chp, char *msg)
1.2 bouyer 2006: {
1.169 thorpej 2007: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 2008: struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.88 mrg 2009:
1.2 bouyer 2010: if (xfer == NULL)
1.169 thorpej 2011: printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel,
1.31 bouyer 2012: msg);
1.2 bouyer 2013: else
1.169 thorpej 2014: printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname,
2015: chp->ch_channel, xfer->c_drive, msg);
1.2 bouyer 2016: }
2017:
2018: /*
2019: * the bit bucket
2020: */
2021: void
1.168 thorpej 2022: wdcbit_bucket(struct wdc_channel *chp, int size)
1.2 bouyer 2023: {
2024:
1.12 cgd 2025: for (; size >= 2; size -= 2)
1.157 fvdl 2026: (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0);
1.12 cgd 2027: if (size)
1.157 fvdl 2028: (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0);
1.44 thorpej 2029: }
2030:
2031: int
1.168 thorpej 2032: wdc_addref(struct wdc_channel *chp)
1.44 thorpej 2033: {
1.169 thorpej 2034: struct wdc_softc *wdc = chp->ch_wdc;
1.96 bouyer 2035: struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic;
1.44 thorpej 2036: int s, error = 0;
2037:
2038: s = splbio();
1.96 bouyer 2039: if (adapt->adapt_refcnt++ == 0 &&
2040: adapt->adapt_enable != NULL) {
2041: error = (*adapt->adapt_enable)(&wdc->sc_dev, 1);
1.44 thorpej 2042: if (error)
1.96 bouyer 2043: adapt->adapt_refcnt--;
1.44 thorpej 2044: }
2045: splx(s);
2046: return (error);
2047: }
2048:
2049: void
1.168 thorpej 2050: wdc_delref(struct wdc_channel *chp)
1.44 thorpej 2051: {
1.169 thorpej 2052: struct wdc_softc *wdc = chp->ch_wdc;
1.96 bouyer 2053: struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic;
1.44 thorpej 2054: int s;
2055:
2056: s = splbio();
1.96 bouyer 2057: if (adapt->adapt_refcnt-- == 1 &&
2058: adapt->adapt_enable != NULL)
2059: (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0);
1.44 thorpej 2060: splx(s);
1.93 wrstuden 2061: }
2062:
2063: void
1.168 thorpej 2064: wdc_print_modes(struct wdc_channel *chp)
1.93 wrstuden 2065: {
1.169 thorpej 2066: struct wdc_softc *wdc = chp->ch_wdc;
1.93 wrstuden 2067: int drive;
2068: struct ata_drive_datas *drvp;
2069:
2070: for (drive = 0; drive < 2; drive++) {
2071: drvp = &chp->ch_drive[drive];
2072: if ((drvp->drive_flags & DRIVE) == 0)
2073: continue;
1.123 thorpej 2074: aprint_normal("%s(%s:%d:%d): using PIO mode %d",
1.93 wrstuden 2075: drvp->drv_softc->dv_xname,
1.169 thorpej 2076: wdc->sc_dev.dv_xname,
2077: chp->ch_channel, drive, drvp->PIO_mode);
1.93 wrstuden 2078: if (drvp->drive_flags & DRIVE_DMA)
1.123 thorpej 2079: aprint_normal(", DMA mode %d", drvp->DMA_mode);
1.93 wrstuden 2080: if (drvp->drive_flags & DRIVE_UDMA) {
1.123 thorpej 2081: aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode);
1.93 wrstuden 2082: if (drvp->UDMA_mode == 2)
1.123 thorpej 2083: aprint_normal(" (Ultra/33)");
1.93 wrstuden 2084: else if (drvp->UDMA_mode == 4)
1.123 thorpej 2085: aprint_normal(" (Ultra/66)");
1.93 wrstuden 2086: else if (drvp->UDMA_mode == 5)
1.123 thorpej 2087: aprint_normal(" (Ultra/100)");
2088: else if (drvp->UDMA_mode == 6)
2089: aprint_normal(" (Ultra/133)");
1.93 wrstuden 2090: }
2091: if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA))
1.123 thorpej 2092: aprint_normal(" (using DMA data transfers)");
2093: aprint_normal("\n");
1.93 wrstuden 2094: }
1.2 bouyer 2095: }
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