Annotation of src/sys/dev/ic/wdc.c, Revision 1.173
1.173 ! bouyer 1: /* $NetBSD: wdc.c,v 1.172 2004/03/25 19:45:09 bouyer Exp $ */
1.31 bouyer 2:
3: /*
1.137 bouyer 4: * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved.
1.31 bouyer 5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: * 3. All advertising materials mentioning features or use of this software
15: * must display the following acknowledgement:
16: * This product includes software developed by Manuel Bouyer.
17: * 4. The name of the author may not be used to endorse or promote products
18: * derived from this software without specific prior written permission.
19: *
20: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30: */
1.2 bouyer 31:
1.27 mycroft 32: /*-
1.125 mycroft 33: * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
1.27 mycroft 34: * All rights reserved.
1.2 bouyer 35: *
1.27 mycroft 36: * This code is derived from software contributed to The NetBSD Foundation
37: * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
1.12 cgd 38: *
1.2 bouyer 39: * Redistribution and use in source and binary forms, with or without
40: * modification, are permitted provided that the following conditions
41: * are met:
42: * 1. Redistributions of source code must retain the above copyright
43: * notice, this list of conditions and the following disclaimer.
44: * 2. Redistributions in binary form must reproduce the above copyright
45: * notice, this list of conditions and the following disclaimer in the
46: * documentation and/or other materials provided with the distribution.
47: * 3. All advertising materials mentioning features or use of this software
48: * must display the following acknowledgement:
1.27 mycroft 49: * This product includes software developed by the NetBSD
50: * Foundation, Inc. and its contributors.
51: * 4. Neither the name of The NetBSD Foundation nor the names of its
52: * contributors may be used to endorse or promote products derived
53: * from this software without specific prior written permission.
1.2 bouyer 54: *
1.27 mycroft 55: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
56: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
57: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
58: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
59: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
60: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
61: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
62: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
63: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
64: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
65: * POSSIBILITY OF SUCH DAMAGE.
1.2 bouyer 66: */
67:
1.12 cgd 68: /*
69: * CODE UNTESTED IN THE CURRENT REVISION:
70: */
1.100 lukem 71:
72: #include <sys/cdefs.h>
1.173 ! bouyer 73: __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.172 2004/03/25 19:45:09 bouyer Exp $");
1.12 cgd 74:
1.59 hubertf 75: #ifndef WDCDEBUG
1.31 bouyer 76: #define WDCDEBUG
1.59 hubertf 77: #endif /* WDCDEBUG */
1.31 bouyer 78:
1.2 bouyer 79: #include <sys/param.h>
80: #include <sys/systm.h>
81: #include <sys/kernel.h>
82: #include <sys/conf.h>
83: #include <sys/buf.h>
1.31 bouyer 84: #include <sys/device.h>
1.2 bouyer 85: #include <sys/malloc.h>
1.71 bouyer 86: #include <sys/pool.h>
1.2 bouyer 87: #include <sys/syslog.h>
88: #include <sys/proc.h>
89:
90: #include <machine/intr.h>
91: #include <machine/bus.h>
92:
1.17 sakamoto 93: #ifndef __BUS_SPACE_HAS_STREAM_METHODS
1.31 bouyer 94: #define bus_space_write_multi_stream_2 bus_space_write_multi_2
95: #define bus_space_write_multi_stream_4 bus_space_write_multi_4
96: #define bus_space_read_multi_stream_2 bus_space_read_multi_2
97: #define bus_space_read_multi_stream_4 bus_space_read_multi_4
1.17 sakamoto 98: #endif /* __BUS_SPACE_HAS_STREAM_METHODS */
1.16 sakamoto 99:
1.103 bouyer 100: #include <dev/ata/atavar.h>
1.31 bouyer 101: #include <dev/ata/atareg.h>
1.12 cgd 102: #include <dev/ic/wdcreg.h>
103: #include <dev/ic/wdcvar.h>
1.31 bouyer 104:
1.137 bouyer 105: #include "locators.h"
106:
1.122 thorpej 107: #include "ataraid.h"
1.2 bouyer 108: #include "atapibus.h"
1.106 bouyer 109: #include "wd.h"
1.2 bouyer 110:
1.122 thorpej 111: #if NATARAID > 0
112: #include <dev/ata/ata_raidvar.h>
113: #endif
114:
1.31 bouyer 115: #define WDCDELAY 100 /* 100 microseconds */
116: #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY)
1.2 bouyer 117: #if 0
1.31 bouyer 118: /* If you enable this, it will report any delays more than WDCDELAY * N long. */
1.2 bouyer 119: #define WDCNDELAY_DEBUG 50
120: #endif
121:
1.137 bouyer 122: /* When polling wait that much and then tsleep for 1/hz seconds */
123: #define WDCDELAY_POLL 1 /* ms */
124:
125: /* timeout for the control commands */
126: #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */
127:
1.71 bouyer 128: struct pool wdc_xfer_pool;
1.2 bouyer 129:
1.106 bouyer 130: #if NWD > 0
1.103 bouyer 131: extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */
1.106 bouyer 132: #else
133: /* A fake one, the autoconfig will print "wd at foo ... not configured */
134: const struct ata_bustype wdc_ata_bustype = {
135: SCSIPI_BUSTYPE_ATA,
136: NULL,
137: NULL,
138: NULL,
139: NULL,
140: NULL,
141: NULL,
142: NULL
143: };
144: #endif
1.102 bouyer 145:
1.168 thorpej 146: static int wdcprobe1(struct wdc_channel*, int);
147: static void __wdcerror(struct wdc_channel*, char *);
148: static int __wdcwait_reset(struct wdc_channel *, int, int);
149: static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *);
150: static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *);
151: static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *,
1.167 thorpej 152: int);
1.168 thorpej 153: static int __wdcwait(struct wdc_channel *, int, int, int);
1.31 bouyer 154:
155: #define DEBUG_INTR 0x01
156: #define DEBUG_XFERS 0x02
157: #define DEBUG_STATUS 0x04
158: #define DEBUG_FUNCS 0x08
159: #define DEBUG_PROBE 0x10
1.74 enami 160: #define DEBUG_DETACH 0x20
1.87 bouyer 161: #define DEBUG_DELAY 0x40
1.31 bouyer 162: #ifdef WDCDEBUG
1.32 bouyer 163: int wdcdebug_mask = 0;
1.31 bouyer 164: int wdc_nxfer = 0;
165: #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args
1.2 bouyer 166: #else
1.31 bouyer 167: #define WDCDEBUG_PRINT(args, level)
1.2 bouyer 168: #endif
169:
1.162 thorpej 170: /*
171: * A queue of atabus instances, used to ensure the same bus probe order
172: * for a given hardware configuration at each boot.
173: */
174: struct atabus_initq_head atabus_initq_head =
175: TAILQ_HEAD_INITIALIZER(atabus_initq_head);
176: struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER;
1.137 bouyer 177:
1.162 thorpej 178: /* Test to see controller with at last one attached drive is there.
179: * Returns a bit for each possible drive found (0x01 for drive 0,
180: * 0x02 for drive 1).
181: * Logic:
182: * - If a status register is at 0xff, assume there is no drive here
183: * (ISA has pull-up resistors). Similarly if the status register has
184: * the value we last wrote to the bus (for IDE interfaces without pullups).
185: * If no drive at all -> return.
186: * - reset the controller, wait for it to complete (may take up to 31s !).
187: * If timeout -> return.
188: * - test ATA/ATAPI signatures. If at last one drive found -> return.
189: * - try an ATA command on the master.
190: */
1.137 bouyer 191:
1.164 thorpej 192: static void
1.168 thorpej 193: wdc_drvprobe(struct wdc_channel *chp)
1.137 bouyer 194: {
195: struct ataparams params;
1.169 thorpej 196: struct wdc_softc *wdc = chp->ch_wdc;
1.145 christos 197: u_int8_t st0 = 0, st1 = 0;
1.164 thorpej 198: int i, error;
1.137 bouyer 199:
1.164 thorpej 200: if (wdcprobe1(chp, 0) == 0) {
201: /* No drives, abort the attach here. */
202: return;
1.161 thorpej 203: }
1.137 bouyer 204:
205: /* for ATA/OLD drives, wait for DRDY, 3s timeout */
206: for (i = 0; i < mstohz(3000); i++) {
1.169 thorpej 207: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
208: wdc->select(chp,0);
1.157 fvdl 209: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.137 bouyer 210: WDSD_IBM);
211: delay(10); /* 400ns delay */
1.157 fvdl 212: st0 = bus_space_read_1(chp->cmd_iot,
213: chp->cmd_iohs[wd_status], 0);
1.137 bouyer 214:
1.169 thorpej 215: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
216: wdc->select(chp,1);
1.157 fvdl 217: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.137 bouyer 218: WDSD_IBM | 0x10);
219: delay(10); /* 400ns delay */
1.157 fvdl 220: st1 = bus_space_read_1(chp->cmd_iot,
221: chp->cmd_iohs[wd_status], 0);
1.137 bouyer 222:
223: if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD))
224: == 0 ||
225: (st0 & WDCS_DRDY)) &&
226: ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD))
227: == 0 ||
228: (st1 & WDCS_DRDY)))
229: break;
1.164 thorpej 230: tsleep(¶ms, PRIBIO, "atadrdy", 1);
1.137 bouyer 231: }
232: if ((st0 & WDCS_DRDY) == 0)
233: chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD);
234: if ((st1 & WDCS_DRDY) == 0)
235: chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD);
236:
237: WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n",
1.169 thorpej 238: wdc->sc_dev.dv_xname,
239: chp->ch_channel, st0, st1), DEBUG_PROBE);
1.137 bouyer 240:
241: /* Wait a bit, some devices are weird just after a reset. */
242: delay(5000);
243:
244: for (i = 0; i < 2; i++) {
1.171 thorpej 245: /* XXX This should be done by other code. */
1.137 bouyer 246: chp->ch_drive[i].chnl_softc = chp;
247: chp->ch_drive[i].drive = i;
1.171 thorpej 248:
1.137 bouyer 249: /*
250: * Init error counter so that an error withing the first xfers
251: * will trigger a downgrade
252: */
253: chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1;
254:
255: /* If controller can't do 16bit flag the drives as 32bit */
1.169 thorpej 256: if ((wdc->cap &
1.137 bouyer 257: (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
258: WDC_CAPABILITY_DATA32)
259: chp->ch_drive[i].drive_flags |= DRIVE_CAP32;
260: if ((chp->ch_drive[i].drive_flags & DRIVE) == 0)
261: continue;
262:
1.144 briggs 263: /* Shortcut in case we've been shutdown */
264: if (chp->ch_flags & WDCF_SHUTDOWN)
1.164 thorpej 265: return;
1.144 briggs 266:
1.137 bouyer 267: /* issue an identify, to try to detect ghosts */
268: error = ata_get_params(&chp->ch_drive[i],
269: AT_WAIT | AT_POLL, ¶ms);
270: if (error != CMD_OK) {
1.164 thorpej 271: tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000));
1.144 briggs 272:
273: /* Shortcut in case we've been shutdown */
274: if (chp->ch_flags & WDCF_SHUTDOWN)
1.164 thorpej 275: return;
1.144 briggs 276:
1.137 bouyer 277: error = ata_get_params(&chp->ch_drive[i],
278: AT_WAIT | AT_POLL, ¶ms);
279: }
280: if (error == CMD_OK) {
1.152 wiz 281: /* If IDENTIFY succeeded, this is not an OLD ctrl */
1.137 bouyer 282: chp->ch_drive[0].drive_flags &= ~DRIVE_OLD;
283: chp->ch_drive[1].drive_flags &= ~DRIVE_OLD;
284: } else {
1.155 bouyer 285: chp->ch_drive[i].drive_flags &=
1.137 bouyer 286: ~(DRIVE_ATA | DRIVE_ATAPI);
287: WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n",
1.169 thorpej 288: wdc->sc_dev.dv_xname,
289: chp->ch_channel, i, error), DEBUG_PROBE);
1.137 bouyer 290: if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0)
291: continue;
292: /*
293: * Pre-ATA drive ?
294: * Test registers writability (Error register not
295: * writable, but cyllo is), then try an ATA command.
296: */
1.169 thorpej 297: if (wdc->cap & WDC_CAPABILITY_SELECT)
298: wdc->select(chp,i);
1.157 fvdl 299: bus_space_write_1(chp->cmd_iot,
300: chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4));
1.137 bouyer 301: delay(10); /* 400ns delay */
1.157 fvdl 302: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error],
303: 0, 0x58);
304: bus_space_write_1(chp->cmd_iot,
305: chp->cmd_iohs[wd_cyl_lo], 0, 0xa5);
306: if (bus_space_read_1(chp->cmd_iot,
307: chp->cmd_iohs[wd_error], 0) == 0x58 ||
308: bus_space_read_1(chp->cmd_iot,
309: chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) {
1.137 bouyer 310: WDCDEBUG_PRINT(("%s:%d:%d: register "
311: "writability failed\n",
1.169 thorpej 312: wdc->sc_dev.dv_xname,
313: chp->ch_channel, i), DEBUG_PROBE);
1.137 bouyer 314: chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
1.155 bouyer 315: continue;
1.137 bouyer 316: }
1.166 thorpej 317: if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) {
1.137 bouyer 318: WDCDEBUG_PRINT(("%s:%d:%d: not ready\n",
1.169 thorpej 319: wdc->sc_dev.dv_xname,
320: chp->ch_channel, i), DEBUG_PROBE);
1.137 bouyer 321: chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
322: continue;
323: }
1.157 fvdl 324: bus_space_write_1(chp->cmd_iot,
325: chp->cmd_iohs[wd_command], 0, WDCC_RECAL);
1.137 bouyer 326: delay(10); /* 400ns delay */
1.166 thorpej 327: if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) {
1.137 bouyer 328: WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n",
1.169 thorpej 329: wdc->sc_dev.dv_xname,
330: chp->ch_channel, i), DEBUG_PROBE);
1.137 bouyer 331: chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
1.155 bouyer 332: } else {
333: chp->ch_drive[0].drive_flags &=
334: ~(DRIVE_ATA | DRIVE_ATAPI);
335: chp->ch_drive[1].drive_flags &=
336: ~(DRIVE_ATA | DRIVE_ATAPI);
1.137 bouyer 337: }
338: }
339: }
1.164 thorpej 340: }
341:
342: void
343: atabusconfig(struct atabus_softc *atabus_sc)
344: {
1.168 thorpej 345: struct wdc_channel *chp = atabus_sc->sc_chan;
1.169 thorpej 346: struct wdc_softc *wdc = chp->ch_wdc;
1.164 thorpej 347: int i, error, need_delref = 0;
348: struct atabus_initq *atabus_initq = NULL;
349:
350: if ((error = wdc_addref(chp)) != 0) {
351: aprint_error("%s: unable to enable controller\n",
1.169 thorpej 352: wdc->sc_dev.dv_xname);
1.164 thorpej 353: goto out;
354: }
355: need_delref = 1;
356:
357: /* Probe for the drives. */
1.169 thorpej 358: (*wdc->drv_probe)(chp);
1.137 bouyer 359:
360: WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n",
361: chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags),
362: DEBUG_PROBE);
363:
364: /* If no drives, abort here */
365: if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 &&
366: (chp->ch_drive[1].drive_flags & DRIVE) == 0)
367: goto out;
368:
1.164 thorpej 369: /* Shortcut in case we've been shutdown */
370: if (chp->ch_flags & WDCF_SHUTDOWN)
371: goto out;
372:
1.137 bouyer 373: /* Make sure the devices probe in atabus order to avoid jitter. */
374: simple_lock(&atabus_interlock);
375: while(1) {
376: atabus_initq = TAILQ_FIRST(&atabus_initq_head);
377: if (atabus_initq->atabus_sc == atabus_sc)
378: break;
379: ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0,
380: &atabus_interlock);
381: }
382: simple_unlock(&atabus_interlock);
383:
384: /*
385: * Attach an ATAPI bus, if needed.
386: */
387: if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) ||
388: (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) {
389: #if NATAPIBUS > 0
390: wdc_atapibus_attach(atabus_sc);
391: #else
392: /*
393: * Fake the autoconfig "not configured" message
394: */
395: aprint_normal("atapibus at %s not configured\n",
1.169 thorpej 396: wdc->sc_dev.dv_xname);
1.137 bouyer 397: chp->atapibus = NULL;
1.141 bouyer 398: chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI;
399: chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI;
1.137 bouyer 400: #endif
401: }
402:
403: for (i = 0; i < 2; i++) {
404: struct ata_device adev;
405: if ((chp->ch_drive[i].drive_flags &
406: (DRIVE_ATA | DRIVE_OLD)) == 0) {
407: continue;
408: }
409: memset(&adev, 0, sizeof(struct ata_device));
410: adev.adev_bustype = &wdc_ata_bustype;
1.169 thorpej 411: adev.adev_channel = chp->ch_channel;
1.137 bouyer 412: adev.adev_openings = 1;
413: adev.adev_drv_data = &chp->ch_drive[i];
414: chp->ata_drives[i] = config_found(&atabus_sc->sc_dev,
1.162 thorpej 415: &adev, ataprint);
1.141 bouyer 416: if (chp->ata_drives[i] != NULL)
1.137 bouyer 417: wdc_probe_caps(&chp->ch_drive[i]);
1.141 bouyer 418: else
419: chp->ch_drive[i].drive_flags &=
420: ~(DRIVE_ATA | DRIVE_OLD);
1.137 bouyer 421: }
422:
423: /* now that we know the drives, the controller can set its modes */
1.169 thorpej 424: if (wdc->cap & WDC_CAPABILITY_MODE) {
425: wdc->set_modes(chp);
1.137 bouyer 426: wdc_print_modes(chp);
427: }
428: #if NATARAID > 0
1.169 thorpej 429: if (wdc->cap & WDC_CAPABILITY_RAID)
1.137 bouyer 430: for (i = 0; i < 2; i++)
431: if (chp->ata_drives[i] != NULL)
432: ata_raid_check_component(chp->ata_drives[i]);
433: #endif /* NATARAID > 0 */
434:
435: /*
1.152 wiz 436: * reset drive_flags for unattached devices, reset state for attached
1.137 bouyer 437: * ones
438: */
439: for (i = 0; i < 2; i++) {
440: if (chp->ch_drive[i].drv_softc == NULL)
441: chp->ch_drive[i].drive_flags = 0;
442: else
443: chp->ch_drive[i].state = 0;
444: }
445:
1.163 thorpej 446: out:
1.137 bouyer 447: if (atabus_initq == NULL) {
448: simple_lock(&atabus_interlock);
449: while(1) {
450: atabus_initq = TAILQ_FIRST(&atabus_initq_head);
451: if (atabus_initq->atabus_sc == atabus_sc)
452: break;
453: ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0,
454: &atabus_interlock);
455: }
456: simple_unlock(&atabus_interlock);
457: }
458: simple_lock(&atabus_interlock);
459: TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq);
460: simple_unlock(&atabus_interlock);
461:
462: free(atabus_initq, M_DEVBUF);
463: wakeup(&atabus_initq_head);
464:
465: config_pending_decr();
1.144 briggs 466: if (need_delref)
467: wdc_delref(chp);
1.137 bouyer 468: }
469:
1.2 bouyer 470: int
1.168 thorpej 471: wdcprobe(struct wdc_channel *chp)
1.12 cgd 472: {
1.163 thorpej 473:
474: return (wdcprobe1(chp, 1));
1.137 bouyer 475: }
476:
1.167 thorpej 477: static int
1.168 thorpej 478: wdcprobe1(struct wdc_channel *chp, int poll)
1.137 bouyer 479: {
1.169 thorpej 480: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 481: u_int8_t st0, st1, sc, sn, cl, ch;
482: u_int8_t ret_value = 0x03;
483: u_int8_t drive;
1.156 bouyer 484: int s;
1.31 bouyer 485:
486: /*
487: * Sanity check to see if the wdc channel responds at all.
488: */
489:
1.169 thorpej 490: if (wdc == NULL ||
491: (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) {
1.107 dbj 492:
1.169 thorpej 493: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
494: wdc->select(chp,0);
1.137 bouyer 495:
1.157 fvdl 496: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.43 kenh 497: WDSD_IBM);
1.131 mycroft 498: delay(10); /* 400ns delay */
1.157 fvdl 499: st0 = bus_space_read_1(chp->cmd_iot,
500: chp->cmd_iohs[wd_status], 0);
1.107 dbj 501:
1.169 thorpej 502: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
503: wdc->select(chp,1);
1.137 bouyer 504:
1.157 fvdl 505: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.43 kenh 506: WDSD_IBM | 0x10);
1.131 mycroft 507: delay(10); /* 400ns delay */
1.157 fvdl 508: st1 = bus_space_read_1(chp->cmd_iot,
509: chp->cmd_iohs[wd_status], 0);
1.43 kenh 510:
511: WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n",
1.169 thorpej 512: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
513: chp->ch_channel, st0, st1), DEBUG_PROBE);
1.43 kenh 514:
1.142 bouyer 515: if (st0 == 0xff || st0 == WDSD_IBM)
1.43 kenh 516: ret_value &= ~0x01;
1.142 bouyer 517: if (st1 == 0xff || st1 == (WDSD_IBM | 0x10))
1.43 kenh 518: ret_value &= ~0x02;
1.125 mycroft 519: /* Register writability test, drive 0. */
520: if (ret_value & 0x01) {
1.169 thorpej 521: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
522: wdc->select(chp,0);
1.157 fvdl 523: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
524: 0, WDSD_IBM);
525: bus_space_write_1(chp->cmd_iot,
526: chp->cmd_iohs[wd_cyl_lo], 0, 0x02);
527: if (bus_space_read_1(chp->cmd_iot,
528: chp->cmd_iohs[wd_cyl_lo], 0) != 0x02)
1.125 mycroft 529: ret_value &= ~0x01;
1.157 fvdl 530: bus_space_write_1(chp->cmd_iot,
531: chp->cmd_iohs[wd_cyl_lo], 0, 0x01);
532: if (bus_space_read_1(chp->cmd_iot,
533: chp->cmd_iohs[wd_cyl_lo], 0) != 0x01)
1.125 mycroft 534: ret_value &= ~0x01;
1.167 thorpej 535: bus_space_write_1(chp->cmd_iot,
536: chp->cmd_iohs[wd_sector], 0, 0x01);
1.157 fvdl 537: if (bus_space_read_1(chp->cmd_iot,
538: chp->cmd_iohs[wd_sector], 0) != 0x01)
1.125 mycroft 539: ret_value &= ~0x01;
1.157 fvdl 540: bus_space_write_1(chp->cmd_iot,
541: chp->cmd_iohs[wd_sector], 0, 0x02);
542: if (bus_space_read_1(chp->cmd_iot,
543: chp->cmd_iohs[wd_sector], 0) != 0x02)
1.125 mycroft 544: ret_value &= ~0x01;
1.157 fvdl 545: if (bus_space_read_1(chp->cmd_iot,
546: chp->cmd_iohs[wd_cyl_lo], 0) != 0x01)
1.131 mycroft 547: ret_value &= ~0x01;
1.125 mycroft 548: }
549: /* Register writability test, drive 1. */
550: if (ret_value & 0x02) {
1.169 thorpej 551: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
552: wdc->select(chp,1);
1.157 fvdl 553: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
554: 0, WDSD_IBM | 0x10);
1.167 thorpej 555: bus_space_write_1(chp->cmd_iot,
556: chp->cmd_iohs[wd_cyl_lo], 0, 0x02);
1.157 fvdl 557: if (bus_space_read_1(chp->cmd_iot,
558: chp->cmd_iohs[wd_cyl_lo], 0) != 0x02)
1.125 mycroft 559: ret_value &= ~0x02;
1.157 fvdl 560: bus_space_write_1(chp->cmd_iot,
561: chp->cmd_iohs[wd_cyl_lo], 0, 0x01);
562: if (bus_space_read_1(chp->cmd_iot,
563: chp->cmd_iohs[wd_cyl_lo], 0) != 0x01)
1.125 mycroft 564: ret_value &= ~0x02;
1.157 fvdl 565: bus_space_write_1(chp->cmd_iot,
566: chp->cmd_iohs[wd_sector], 0, 0x01);
567: if (bus_space_read_1(chp->cmd_iot,
568: chp->cmd_iohs[wd_sector], 0) != 0x01)
1.125 mycroft 569: ret_value &= ~0x02;
1.167 thorpej 570: bus_space_write_1(chp->cmd_iot,
571: chp->cmd_iohs[wd_sector], 0, 0x02);
1.157 fvdl 572: if (bus_space_read_1(chp->cmd_iot,
573: chp->cmd_iohs[wd_sector], 0) != 0x02)
1.125 mycroft 574: ret_value &= ~0x02;
1.157 fvdl 575: if (bus_space_read_1(chp->cmd_iot,
576: chp->cmd_iohs[wd_cyl_lo], 0) != 0x01)
1.131 mycroft 577: ret_value &= ~0x02;
1.125 mycroft 578: }
1.137 bouyer 579:
580: if (ret_value == 0)
581: return 0;
1.62 bouyer 582: }
1.31 bouyer 583:
1.156 bouyer 584: s = splbio();
585:
1.169 thorpej 586: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
587: wdc->select(chp,0);
1.137 bouyer 588: /* assert SRST, wait for reset to complete */
1.157 fvdl 589: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM);
1.137 bouyer 590: delay(10); /* 400ns delay */
591: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
592: WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
1.172 bouyer 593: DELAY(1000);
594: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
595: WDCTL_IDS | WDCTL_4BIT);
1.137 bouyer 596: DELAY(2000);
1.157 fvdl 597: (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0);
1.137 bouyer 598: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
599: delay(10); /* 400ns delay */
1.156 bouyer 600: /* ACK interrupt in case there is one pending left (Promise ATA100) */
1.169 thorpej 601: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK))
602: wdc->irqack(chp);
1.156 bouyer 603: splx(s);
1.137 bouyer 604:
605: ret_value = __wdcwait_reset(chp, ret_value, poll);
606: WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n",
1.169 thorpej 607: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel,
1.137 bouyer 608: ret_value), DEBUG_PROBE);
1.12 cgd 609:
1.137 bouyer 610: /* if reset failed, there's nothing here */
611: if (ret_value == 0)
612: return 0;
1.67 bouyer 613:
1.12 cgd 614: /*
1.167 thorpej 615: * Test presence of drives. First test register signatures looking
616: * for ATAPI devices. If it's not an ATAPI and reset said there may
617: * be something here assume it's ATA or OLD. Ghost will be killed
618: * later in attach routine.
1.12 cgd 619: */
1.137 bouyer 620: for (drive = 0; drive < 2; drive++) {
621: if ((ret_value & (0x01 << drive)) == 0)
622: continue;
1.169 thorpej 623: if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT)
624: wdc->select(chp,drive);
1.157 fvdl 625: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.137 bouyer 626: WDSD_IBM | (drive << 4));
627: delay(10); /* 400ns delay */
628: /* Save registers contents */
1.157 fvdl 629: sc = bus_space_read_1(chp->cmd_iot,
630: chp->cmd_iohs[wd_seccnt], 0);
631: sn = bus_space_read_1(chp->cmd_iot,
632: chp->cmd_iohs[wd_sector], 0);
633: cl = bus_space_read_1(chp->cmd_iot,
634: chp->cmd_iohs[wd_cyl_lo], 0);
635: ch = bus_space_read_1(chp->cmd_iot,
636: chp->cmd_iohs[wd_cyl_hi], 0);
1.137 bouyer 637:
638: WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x "
639: "cl=0x%x ch=0x%x\n",
1.169 thorpej 640: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
641: chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE);
1.31 bouyer 642: /*
1.137 bouyer 643: * sc & sn are supposted to be 0x1 for ATAPI but in some cases
644: * we get wrong values here, so ignore it.
1.31 bouyer 645: */
1.137 bouyer 646: if (cl == 0x14 && ch == 0xeb) {
647: chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI;
648: } else {
649: chp->ch_drive[drive].drive_flags |= DRIVE_ATA;
1.169 thorpej 650: if (wdc == NULL ||
651: (wdc->cap & WDC_CAPABILITY_PREATA) != 0)
1.137 bouyer 652: chp->ch_drive[drive].drive_flags |= DRIVE_OLD;
653: }
1.31 bouyer 654: }
1.137 bouyer 655: return (ret_value);
656: }
1.31 bouyer 657:
1.137 bouyer 658: void
1.168 thorpej 659: wdcattach(struct wdc_channel *chp)
1.137 bouyer 660: {
1.169 thorpej 661: struct wdc_softc *wdc = chp->ch_wdc;
1.137 bouyer 662: static int inited = 0;
1.32 bouyer 663:
1.137 bouyer 664: if (chp->ch_flags & WDCF_DISABLED)
665: return;
1.74 enami 666:
1.137 bouyer 667: /* initialise global data */
668: callout_init(&chp->ch_callout);
1.169 thorpej 669: if (wdc->drv_probe == NULL)
670: wdc->drv_probe = wdc_drvprobe;
1.137 bouyer 671: if (inited == 0) {
1.165 thorpej 672: /* Initialize the ata_xfer pool. */
673: pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0,
1.137 bouyer 674: 0, 0, "wdcspl", NULL);
675: inited++;
1.133 bouyer 676: }
1.165 thorpej 677: TAILQ_INIT(&chp->ch_queue->queue_xfer);
1.148 bouyer 678: chp->ch_queue->queue_freeze = 0;
1.126 enami 679:
1.169 thorpej 680: chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint);
1.74 enami 681: }
682:
1.163 thorpej 683: int
684: wdcactivate(struct device *self, enum devact act)
1.137 bouyer 685: {
686: struct wdc_softc *wdc = (struct wdc_softc *)self;
687: int s, i, error = 0;
688:
689: s = splbio();
690: switch (act) {
691: case DVACT_ACTIVATE:
692: error = EOPNOTSUPP;
693: break;
694:
695: case DVACT_DEACTIVATE:
696: for (i = 0; i < wdc->nchannels; i++) {
697: error = config_deactivate(wdc->channels[i]->atabus);
698: if (error)
699: break;
700: }
701: break;
702: }
703: splx(s);
704: return (error);
705: }
706:
707: int
1.163 thorpej 708: wdcdetach(struct device *self, int flags)
1.137 bouyer 709: {
710: struct wdc_softc *wdc = (struct wdc_softc *)self;
1.168 thorpej 711: struct wdc_channel *chp;
1.137 bouyer 712: int i, error = 0;
713:
714: for (i = 0; i < wdc->nchannels; i++) {
715: chp = wdc->channels[i];
716: WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n",
717: wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH);
718: error = config_detach(chp->atabus, flags);
719: if (error)
720: break;
721: }
722: return (error);
723: }
724:
1.31 bouyer 725: /*
726: * Start I/O on a controller, for the given channel.
727: * The first xfer may be not for our channel if the channel queues
728: * are shared.
729: */
730: void
1.168 thorpej 731: wdcstart(struct wdc_channel *chp)
1.31 bouyer 732: {
1.169 thorpej 733: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 734: struct ata_xfer *xfer;
1.38 bouyer 735:
736: #ifdef WDC_DIAGNOSTIC
737: int spl1, spl2;
738:
739: spl1 = splbio();
740: spl2 = splbio();
741: if (spl2 != spl1) {
742: printf("wdcstart: not at splbio()\n");
743: panic("wdcstart");
744: }
745: splx(spl2);
746: splx(spl1);
747: #endif /* WDC_DIAGNOSTIC */
1.12 cgd 748:
1.31 bouyer 749: /* is there a xfer ? */
1.165 thorpej 750: if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL)
1.31 bouyer 751: return;
1.47 bouyer 752:
753: /* adjust chp, in case we have a shared queue */
1.165 thorpej 754: chp = xfer->c_chp;
1.47 bouyer 755:
1.31 bouyer 756: if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) {
757: return; /* channel aleady active */
758: }
1.148 bouyer 759: if (__predict_false(chp->ch_queue->queue_freeze > 0)) {
1.147 bouyer 760: return; /* queue froozen */
1.137 bouyer 761: }
1.31 bouyer 762: #ifdef DIAGNOSTIC
763: if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0)
1.118 provos 764: panic("wdcstart: channel waiting for irq");
1.31 bouyer 765: #endif
1.169 thorpej 766: if (wdc->cap & WDC_CAPABILITY_HWLOCK)
767: if (!(*wdc->claim_hw)(chp, 0))
1.31 bouyer 768: return;
1.12 cgd 769:
1.31 bouyer 770: WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer,
1.169 thorpej 771: chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
1.31 bouyer 772: chp->ch_flags |= WDCF_ACTIVE;
1.165 thorpej 773: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) {
774: chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET;
775: chp->ch_drive[xfer->c_drive].state = 0;
1.37 bouyer 776: }
1.169 thorpej 777: if (wdc->cap & WDC_CAPABILITY_NOIRQ)
1.98 bjh21 778: KASSERT(xfer->c_flags & C_POLL);
1.31 bouyer 779: xfer->c_start(chp, xfer);
780: }
1.2 bouyer 781:
1.31 bouyer 782: /* restart an interrupted I/O */
783: void
1.163 thorpej 784: wdcrestart(void *v)
1.31 bouyer 785: {
1.168 thorpej 786: struct wdc_channel *chp = v;
1.31 bouyer 787: int s;
1.2 bouyer 788:
1.31 bouyer 789: s = splbio();
1.45 drochner 790: wdcstart(chp);
1.31 bouyer 791: splx(s);
1.2 bouyer 792: }
1.31 bouyer 793:
1.2 bouyer 794:
1.31 bouyer 795: /*
796: * Interrupt routine for the controller. Acknowledge the interrupt, check for
797: * errors on the current operation, mark it done if necessary, and start the
798: * next request. Also check for a partially done transfer, and continue with
799: * the next chunk if so.
800: */
1.12 cgd 801: int
1.163 thorpej 802: wdcintr(void *arg)
1.12 cgd 803: {
1.168 thorpej 804: struct wdc_channel *chp = arg;
1.169 thorpej 805: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 806: struct ata_xfer *xfer;
1.76 bouyer 807: int ret;
1.12 cgd 808:
1.169 thorpej 809: if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) {
1.80 enami 810: WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"),
811: DEBUG_INTR);
812: return (0);
813: }
1.31 bouyer 814: if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) {
815: WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR);
1.113 bouyer 816: /* try to clear the pending interrupt anyway */
1.157 fvdl 817: (void)bus_space_read_1(chp->cmd_iot,
818: chp->cmd_iohs[wd_status], 0);
1.80 enami 819: return (0);
1.31 bouyer 820: }
1.12 cgd 821:
1.31 bouyer 822: WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR);
1.165 thorpej 823: xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.84 bouyer 824: if (chp->ch_flags & WDCF_DMA_WAIT) {
1.169 thorpej 825: wdc->dma_status =
826: (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel,
1.165 thorpej 827: xfer->c_drive, 0);
1.169 thorpej 828: if (wdc->dma_status & WDC_DMAST_NOIRQ) {
1.84 bouyer 829: /* IRQ not for us, not detected by DMA engine */
830: return 0;
831: }
832: chp->ch_flags &= ~WDCF_DMA_WAIT;
833: }
1.31 bouyer 834: chp->ch_flags &= ~WDCF_IRQ_WAIT;
1.76 bouyer 835: ret = xfer->c_intr(chp, xfer, 1);
836: if (ret == 0) /* irq was not for us, still waiting for irq */
837: chp->ch_flags |= WDCF_IRQ_WAIT;
838: return (ret);
1.12 cgd 839: }
840:
1.31 bouyer 841: /* Put all disk in RESET state */
1.125 mycroft 842: void
1.163 thorpej 843: wdc_reset_channel(struct ata_drive_datas *drvp, int flags)
1.2 bouyer 844: {
1.168 thorpej 845: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 846: struct wdc_softc *wdc = chp->ch_wdc;
1.2 bouyer 847: int drive;
1.163 thorpej 848:
1.34 bouyer 849: WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n",
1.169 thorpej 850: wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive),
1.34 bouyer 851: DEBUG_FUNCS);
1.147 bouyer 852: if ((flags & AT_POLL) == 0) {
1.153 bouyer 853: if (chp->ch_flags & WDCF_TH_RESET) {
854: /* no need to schedule a reset more than one time */
855: return;
856: }
1.137 bouyer 857: chp->ch_flags |= WDCF_TH_RESET;
1.148 bouyer 858: chp->ch_queue->queue_freeze++;
1.170 thorpej 859: wakeup(&chp->ch_thread);
1.137 bouyer 860: return;
861: }
1.147 bouyer 862: (void) wdcreset(chp, RESET_POLL);
1.31 bouyer 863: for (drive = 0; drive < 2; drive++) {
864: chp->ch_drive[drive].state = 0;
1.12 cgd 865: }
1.31 bouyer 866: }
1.12 cgd 867:
1.31 bouyer 868: int
1.168 thorpej 869: wdcreset(struct wdc_channel *chp, int poll)
1.31 bouyer 870: {
1.169 thorpej 871: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 872: int drv_mask1, drv_mask2;
1.156 bouyer 873: int s = 0;
1.2 bouyer 874:
1.169 thorpej 875: if (wdc->cap & WDC_CAPABILITY_SELECT)
876: wdc->select(chp,0);
1.156 bouyer 877: if (poll != RESET_SLEEP)
878: s = splbio();
1.157 fvdl 879: /* master */
880: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM);
1.131 mycroft 881: delay(10); /* 400ns delay */
1.31 bouyer 882: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
1.131 mycroft 883: WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
884: delay(2000);
1.157 fvdl 885: (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0);
1.137 bouyer 886: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
887: WDCTL_4BIT | WDCTL_IDS);
1.131 mycroft 888: delay(10); /* 400ns delay */
1.156 bouyer 889: if (poll != RESET_SLEEP) {
1.169 thorpej 890: if (wdc->cap & WDC_CAPABILITY_IRQACK)
891: wdc->irqack(chp);
1.156 bouyer 892: splx(s);
893: }
1.2 bouyer 894:
1.31 bouyer 895: drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00;
896: drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00;
1.137 bouyer 897: drv_mask2 = __wdcwait_reset(chp, drv_mask1,
898: (poll == RESET_SLEEP) ? 0 : 1);
899: if (drv_mask2 != drv_mask1) {
1.31 bouyer 900: printf("%s channel %d: reset failed for",
1.169 thorpej 901: wdc->sc_dev.dv_xname, chp->ch_channel);
1.31 bouyer 902: if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0)
903: printf(" drive 0");
904: if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0)
905: printf(" drive 1");
906: printf("\n");
907: }
1.137 bouyer 908: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
1.31 bouyer 909: return (drv_mask1 != drv_mask2) ? 1 : 0;
910: }
911:
912: static int
1.168 thorpej 913: __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll)
1.31 bouyer 914: {
1.169 thorpej 915: struct wdc_softc *wdc = chp->ch_wdc;
1.137 bouyer 916: int timeout, nloop;
1.149 bouyer 917: u_int8_t st0 = 0, st1 = 0;
1.70 bouyer 918: #ifdef WDCDEBUG
1.146 christos 919: u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0;
920: u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0;
1.70 bouyer 921: #endif
1.137 bouyer 922:
923: if (poll)
924: nloop = WDCNDELAY_RST;
925: else
926: nloop = WDC_RESET_WAIT * hz / 1000;
1.31 bouyer 927: /* wait for BSY to deassert */
1.137 bouyer 928: for (timeout = 0; timeout < nloop; timeout++) {
1.169 thorpej 929: if (wdc && wdc->cap & WDC_CAPABILITY_SELECT)
930: wdc->select(chp,0);
1.157 fvdl 931: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.31 bouyer 932: WDSD_IBM); /* master */
1.65 bouyer 933: delay(10);
1.157 fvdl 934: st0 = bus_space_read_1(chp->cmd_iot,
935: chp->cmd_iohs[wd_status], 0);
1.70 bouyer 936: #ifdef WDCDEBUG
1.157 fvdl 937: sc0 = bus_space_read_1(chp->cmd_iot,
938: chp->cmd_iohs[wd_seccnt], 0);
939: sn0 = bus_space_read_1(chp->cmd_iot,
940: chp->cmd_iohs[wd_sector], 0);
941: cl0 = bus_space_read_1(chp->cmd_iot,
942: chp->cmd_iohs[wd_cyl_lo], 0);
943: ch0 = bus_space_read_1(chp->cmd_iot,
944: chp->cmd_iohs[wd_cyl_hi], 0);
1.70 bouyer 945: #endif
1.169 thorpej 946: if (wdc && wdc->cap & WDC_CAPABILITY_SELECT)
947: wdc->select(chp,1);
1.157 fvdl 948: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.31 bouyer 949: WDSD_IBM | 0x10); /* slave */
1.65 bouyer 950: delay(10);
1.157 fvdl 951: st1 = bus_space_read_1(chp->cmd_iot,
952: chp->cmd_iohs[wd_status], 0);
1.70 bouyer 953: #ifdef WDCDEBUG
1.157 fvdl 954: sc1 = bus_space_read_1(chp->cmd_iot,
955: chp->cmd_iohs[wd_seccnt], 0);
956: sn1 = bus_space_read_1(chp->cmd_iot,
957: chp->cmd_iohs[wd_sector], 0);
958: cl1 = bus_space_read_1(chp->cmd_iot,
959: chp->cmd_iohs[wd_cyl_lo], 0);
960: ch1 = bus_space_read_1(chp->cmd_iot,
961: chp->cmd_iohs[wd_cyl_hi], 0);
1.70 bouyer 962: #endif
1.31 bouyer 963:
964: if ((drv_mask & 0x01) == 0) {
965: /* no master */
966: if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) {
967: /* No master, slave is ready, it's done */
1.65 bouyer 968: goto end;
1.31 bouyer 969: }
970: } else if ((drv_mask & 0x02) == 0) {
971: /* no slave */
972: if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) {
973: /* No slave, master is ready, it's done */
1.65 bouyer 974: goto end;
1.31 bouyer 975: }
1.2 bouyer 976: } else {
1.31 bouyer 977: /* Wait for both master and slave to be ready */
978: if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) {
1.65 bouyer 979: goto end;
1.2 bouyer 980: }
981: }
1.137 bouyer 982: if (poll)
983: delay(WDCDELAY);
984: else
985: tsleep(&nloop, PRIBIO, "atarst", 1);
1.2 bouyer 986: }
1.116 wiz 987: /* Reset timed out. Maybe it's because drv_mask was not right */
1.31 bouyer 988: if (st0 & WDCS_BSY)
989: drv_mask &= ~0x01;
990: if (st1 & WDCS_BSY)
991: drv_mask &= ~0x02;
1.65 bouyer 992: end:
1.70 bouyer 993: WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x "
994: "cl=0x%x ch=0x%x\n",
1.169 thorpej 995: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
996: chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE);
1.70 bouyer 997: WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x "
998: "cl=0x%x ch=0x%x\n",
1.169 thorpej 999: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
1000: chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE);
1.70 bouyer 1001:
1.149 bouyer 1002: WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n",
1.169 thorpej 1003: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel,
1.149 bouyer 1004: st0, st1), DEBUG_PROBE);
1.65 bouyer 1005:
1.31 bouyer 1006: return drv_mask;
1.2 bouyer 1007: }
1008:
1009: /*
1.31 bouyer 1010: * Wait for a drive to be !BSY, and have mask in its status register.
1011: * return -1 for a timeout after "timeout" ms.
1.2 bouyer 1012: */
1.167 thorpej 1013: static int
1.168 thorpej 1014: __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout)
1.2 bouyer 1015: {
1.169 thorpej 1016: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 1017: u_char status;
1018: int time = 0;
1.60 abs 1019:
1.169 thorpej 1020: WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ?
1021: wdc->sc_dev.dv_xname : "none",
1022: chp->ch_channel), DEBUG_STATUS);
1.31 bouyer 1023: chp->ch_error = 0;
1024:
1025: timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */
1.2 bouyer 1026:
1.31 bouyer 1027: for (;;) {
1028: chp->ch_status = status =
1.157 fvdl 1029: bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0);
1.131 mycroft 1030: if ((status & (WDCS_BSY | mask)) == bits)
1.31 bouyer 1031: break;
1032: if (++time > timeout) {
1.137 bouyer 1033: WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), "
1.87 bouyer 1034: "status %x error %x (mask 0x%x bits 0x%x)\n",
1035: time, status,
1.157 fvdl 1036: bus_space_read_1(chp->cmd_iot,
1037: chp->cmd_iohs[wd_error], 0), mask, bits),
1.87 bouyer 1038: DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY);
1.137 bouyer 1039: return(WDCWAIT_TOUT);
1.31 bouyer 1040: }
1041: delay(WDCDELAY);
1.2 bouyer 1042: }
1.87 bouyer 1043: #ifdef WDCDEBUG
1044: if (time > 0 && (wdcdebug_mask & DEBUG_DELAY))
1.137 bouyer 1045: printf("__wdcwait: did busy-wait, time=%d\n", time);
1.87 bouyer 1046: #endif
1.31 bouyer 1047: if (status & WDCS_ERR)
1.157 fvdl 1048: chp->ch_error = bus_space_read_1(chp->cmd_iot,
1049: chp->cmd_iohs[wd_error], 0);
1.31 bouyer 1050: #ifdef WDCNDELAY_DEBUG
1051: /* After autoconfig, there should be no long delays. */
1052: if (!cold && time > WDCNDELAY_DEBUG) {
1.165 thorpej 1053: struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.31 bouyer 1054: if (xfer == NULL)
1055: printf("%s channel %d: warning: busy-wait took %dus\n",
1.169 thorpej 1056: wdc->sc_dev.dv_xname, chp->ch_channel,
1.31 bouyer 1057: WDCDELAY * time);
1058: else
1059: printf("%s:%d:%d: warning: busy-wait took %dus\n",
1.169 thorpej 1060: wdc->sc_dev.dv_xname, chp->ch_channel,
1.31 bouyer 1061: xfer->drive,
1062: WDCDELAY * time);
1.2 bouyer 1063: }
1064: #endif
1.137 bouyer 1065: return(WDCWAIT_OK);
1066: }
1067:
1068: /*
1069: * Call __wdcwait(), polling using tsleep() or waking up the kernel
1070: * thread if possible
1071: */
1072: int
1.168 thorpej 1073: wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags)
1.137 bouyer 1074: {
1075: int error, i, timeout_hz = mstohz(timeout);
1076:
1077: if (timeout_hz == 0 ||
1078: (flags & (AT_WAIT | AT_POLL)) == AT_POLL)
1079: error = __wdcwait(chp, mask, bits, timeout);
1080: else {
1081: error = __wdcwait(chp, mask, bits, WDCDELAY_POLL);
1082: if (error != 0) {
1.147 bouyer 1083: if ((chp->ch_flags & WDCF_TH_RUN) ||
1084: (flags & AT_WAIT)) {
1.137 bouyer 1085: /*
1.147 bouyer 1086: * we're running in the channel thread
1087: * or some userland thread context
1.137 bouyer 1088: */
1089: for (i = 0; i < timeout_hz; i++) {
1090: if (__wdcwait(chp, mask, bits,
1091: WDCDELAY_POLL) == 0) {
1092: error = 0;
1093: break;
1094: }
1095: tsleep(&chp, PRIBIO, "atapoll", 1);
1096: }
1097: } else {
1098: /*
1099: * we're probably in interrupt context,
1100: * ask the thread to come back here
1101: */
1.147 bouyer 1102: #ifdef DIAGNOSTIC
1.148 bouyer 1103: if (chp->ch_queue->queue_freeze > 0)
1104: panic("wdcwait: queue_freeze");
1.147 bouyer 1105: #endif
1.148 bouyer 1106: chp->ch_queue->queue_freeze++;
1.170 thorpej 1107: wakeup(&chp->ch_thread);
1.137 bouyer 1108: return(WDCWAIT_THR);
1109: }
1110: }
1111: }
1.163 thorpej 1112: return (error);
1.2 bouyer 1113: }
1114:
1.137 bouyer 1115:
1.84 bouyer 1116: /*
1117: * Busy-wait for DMA to complete
1118: */
1119: int
1.168 thorpej 1120: wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout)
1.84 bouyer 1121: {
1.169 thorpej 1122: struct wdc_softc *wdc = chp->ch_wdc;
1.84 bouyer 1123: int time;
1.169 thorpej 1124:
1.84 bouyer 1125: for (time = 0; time < timeout * 1000 / WDCDELAY; time++) {
1.169 thorpej 1126: wdc->dma_status =
1127: (*wdc->dma_finish)(wdc->dma_arg,
1128: chp->ch_channel, xfer->c_drive, 0);
1129: if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0)
1.84 bouyer 1130: return 0;
1131: delay(WDCDELAY);
1132: }
1133: /* timeout, force a DMA halt */
1.169 thorpej 1134: wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg,
1135: chp->ch_channel, xfer->c_drive, 1);
1.84 bouyer 1136: return 1;
1137: }
1138:
1.31 bouyer 1139: void
1.163 thorpej 1140: wdctimeout(void *arg)
1.2 bouyer 1141: {
1.168 thorpej 1142: struct wdc_channel *chp = (struct wdc_channel *)arg;
1.169 thorpej 1143: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1144: struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.31 bouyer 1145: int s;
1.2 bouyer 1146:
1.31 bouyer 1147: WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS);
1148:
1149: s = splbio();
1150: if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) {
1151: __wdcerror(chp, "lost interrupt");
1.88 mrg 1152: printf("\ttype: %s tc_bcount: %d tc_skip: %d\n",
1153: (xfer->c_flags & C_ATAPI) ? "atapi" : "ata",
1154: xfer->c_bcount,
1155: xfer->c_skip);
1.84 bouyer 1156: if (chp->ch_flags & WDCF_DMA_WAIT) {
1.169 thorpej 1157: wdc->dma_status =
1158: (*wdc->dma_finish)(wdc->dma_arg,
1159: chp->ch_channel, xfer->c_drive, 1);
1.84 bouyer 1160: chp->ch_flags &= ~WDCF_DMA_WAIT;
1161: }
1.31 bouyer 1162: /*
1.119 drochner 1163: * Call the interrupt routine. If we just missed an interrupt,
1.31 bouyer 1164: * it will do what's needed. Else, it will take the needed
1165: * action (reset the device).
1.70 bouyer 1166: * Before that we need to reinstall the timeout callback,
1167: * in case it will miss another irq while in this transfer
1168: * We arbitray chose it to be 1s
1.31 bouyer 1169: */
1.81 thorpej 1170: callout_reset(&chp->ch_callout, hz, wdctimeout, chp);
1.31 bouyer 1171: xfer->c_flags |= C_TIMEOU;
1172: chp->ch_flags &= ~WDCF_IRQ_WAIT;
1.66 bouyer 1173: xfer->c_intr(chp, xfer, 1);
1.31 bouyer 1174: } else
1175: __wdcerror(chp, "missing untimeout");
1176: splx(s);
1.2 bouyer 1177: }
1178:
1.31 bouyer 1179: /*
1.152 wiz 1180: * Probe drive's capabilities, for use by the controller later
1.31 bouyer 1181: * Assumes drvp points to an existing drive.
1182: * XXX this should be a controller-indep function
1183: */
1.2 bouyer 1184: void
1.163 thorpej 1185: wdc_probe_caps(struct ata_drive_datas *drvp)
1.2 bouyer 1186: {
1.31 bouyer 1187: struct ataparams params, params2;
1.168 thorpej 1188: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 1189: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 1190: struct device *drv_dev = drvp->drv_softc;
1191: int i, printed;
1192: char *sep = "";
1.48 bouyer 1193: int cf_flags;
1.31 bouyer 1194:
1.125 mycroft 1195: if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) {
1.31 bouyer 1196: /* IDENTIFY failed. Can't tell more about the device */
1.2 bouyer 1197: return;
1198: }
1.31 bouyer 1199: if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
1200: (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) {
1.2 bouyer 1201: /*
1.39 bouyer 1202: * Controller claims 16 and 32 bit transfers.
1203: * Re-do an IDENTIFY with 32-bit transfers,
1.31 bouyer 1204: * and compare results.
1.2 bouyer 1205: */
1.31 bouyer 1206: drvp->drive_flags |= DRIVE_CAP32;
1.125 mycroft 1207: ata_get_params(drvp, AT_WAIT, ¶ms2);
1.31 bouyer 1208: if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) {
1209: /* Not good. fall back to 16bits */
1210: drvp->drive_flags &= ~DRIVE_CAP32;
1211: } else {
1.125 mycroft 1212: aprint_normal("%s: 32-bit data port\n",
1.123 thorpej 1213: drv_dev->dv_xname);
1.2 bouyer 1214: }
1215: }
1.55 bouyer 1216: #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */
1217: if (params.atap_ata_major > 0x01 &&
1218: params.atap_ata_major != 0xffff) {
1219: for (i = 14; i > 0; i--) {
1220: if (params.atap_ata_major & (1 << i)) {
1.125 mycroft 1221: aprint_normal("%s: ATA version %d\n",
1222: drv_dev->dv_xname, i);
1.55 bouyer 1223: drvp->ata_vers = i;
1224: break;
1225: }
1226: }
1.125 mycroft 1227: }
1.55 bouyer 1228: #endif
1.2 bouyer 1229:
1.31 bouyer 1230: /* An ATAPI device is at last PIO mode 3 */
1231: if (drvp->drive_flags & DRIVE_ATAPI)
1232: drvp->PIO_mode = 3;
1.2 bouyer 1233:
1234: /*
1.31 bouyer 1235: * It's not in the specs, but it seems that some drive
1236: * returns 0xffff in atap_extensions when this field is invalid
1.2 bouyer 1237: */
1.31 bouyer 1238: if (params.atap_extensions != 0xffff &&
1239: (params.atap_extensions & WDC_EXT_MODES)) {
1240: printed = 0;
1241: /*
1242: * XXX some drives report something wrong here (they claim to
1243: * support PIO mode 8 !). As mode is coded on 3 bits in
1244: * SET FEATURE, limit it to 7 (so limit i to 4).
1.116 wiz 1245: * If higher mode than 7 is found, abort.
1.31 bouyer 1246: */
1.39 bouyer 1247: for (i = 7; i >= 0; i--) {
1.31 bouyer 1248: if ((params.atap_piomode_supp & (1 << i)) == 0)
1249: continue;
1.39 bouyer 1250: if (i > 4)
1251: return;
1.31 bouyer 1252: /*
1253: * See if mode is accepted.
1254: * If the controller can't set its PIO mode,
1255: * assume the defaults are good, so don't try
1256: * to set it
1257: */
1258: if ((wdc->cap & WDC_CAPABILITY_MODE) != 0)
1.137 bouyer 1259: /*
1260: * It's OK to pool here, it's fast enouth
1261: * to not bother waiting for interrupt
1262: */
1.31 bouyer 1263: if (ata_set_mode(drvp, 0x08 | (i + 3),
1.125 mycroft 1264: AT_WAIT) != CMD_OK)
1.2 bouyer 1265: continue;
1.31 bouyer 1266: if (!printed) {
1.123 thorpej 1267: aprint_normal("%s: drive supports PIO mode %d",
1.39 bouyer 1268: drv_dev->dv_xname, i + 3);
1.31 bouyer 1269: sep = ",";
1270: printed = 1;
1271: }
1272: /*
1273: * If controller's driver can't set its PIO mode,
1274: * get the highter one for the drive.
1275: */
1276: if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 ||
1.52 bouyer 1277: wdc->PIO_cap >= i + 3) {
1.31 bouyer 1278: drvp->PIO_mode = i + 3;
1.48 bouyer 1279: drvp->PIO_cap = i + 3;
1.2 bouyer 1280: break;
1281: }
1282: }
1.31 bouyer 1283: if (!printed) {
1284: /*
1285: * We didn't find a valid PIO mode.
1286: * Assume the values returned for DMA are buggy too
1287: */
1288: return;
1.2 bouyer 1289: }
1.35 bouyer 1290: drvp->drive_flags |= DRIVE_MODE;
1.31 bouyer 1291: printed = 0;
1292: for (i = 7; i >= 0; i--) {
1293: if ((params.atap_dmamode_supp & (1 << i)) == 0)
1294: continue;
1295: if ((wdc->cap & WDC_CAPABILITY_DMA) &&
1296: (wdc->cap & WDC_CAPABILITY_MODE))
1.125 mycroft 1297: if (ata_set_mode(drvp, 0x20 | i, AT_WAIT)
1.31 bouyer 1298: != CMD_OK)
1299: continue;
1300: if (!printed) {
1.123 thorpej 1301: aprint_normal("%s DMA mode %d", sep, i);
1.31 bouyer 1302: sep = ",";
1303: printed = 1;
1304: }
1305: if (wdc->cap & WDC_CAPABILITY_DMA) {
1306: if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1.52 bouyer 1307: wdc->DMA_cap < i)
1.31 bouyer 1308: continue;
1309: drvp->DMA_mode = i;
1.48 bouyer 1310: drvp->DMA_cap = i;
1.31 bouyer 1311: drvp->drive_flags |= DRIVE_DMA;
1312: }
1.2 bouyer 1313: break;
1314: }
1.31 bouyer 1315: if (params.atap_extensions & WDC_EXT_UDMA_MODES) {
1.71 bouyer 1316: printed = 0;
1.31 bouyer 1317: for (i = 7; i >= 0; i--) {
1318: if ((params.atap_udmamode_supp & (1 << i))
1319: == 0)
1320: continue;
1321: if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1322: (wdc->cap & WDC_CAPABILITY_UDMA))
1323: if (ata_set_mode(drvp, 0x40 | i,
1.125 mycroft 1324: AT_WAIT) != CMD_OK)
1.31 bouyer 1325: continue;
1.71 bouyer 1326: if (!printed) {
1.123 thorpej 1327: aprint_normal("%s Ultra-DMA mode %d",
1328: sep, i);
1.93 wrstuden 1329: if (i == 2)
1.123 thorpej 1330: aprint_normal(" (Ultra/33)");
1.93 wrstuden 1331: else if (i == 4)
1.123 thorpej 1332: aprint_normal(" (Ultra/66)");
1.93 wrstuden 1333: else if (i == 5)
1.123 thorpej 1334: aprint_normal(" (Ultra/100)");
1.117 bouyer 1335: else if (i == 6)
1.123 thorpej 1336: aprint_normal(" (Ultra/133)");
1.71 bouyer 1337: sep = ",";
1338: printed = 1;
1339: }
1.31 bouyer 1340: if (wdc->cap & WDC_CAPABILITY_UDMA) {
1.50 bouyer 1341: if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1.52 bouyer 1342: wdc->UDMA_cap < i)
1.50 bouyer 1343: continue;
1.31 bouyer 1344: drvp->UDMA_mode = i;
1.48 bouyer 1345: drvp->UDMA_cap = i;
1.31 bouyer 1346: drvp->drive_flags |= DRIVE_UDMA;
1347: }
1348: break;
1349: }
1350: }
1.123 thorpej 1351: aprint_normal("\n");
1.55 bouyer 1352: }
1353:
1354: /* Try to guess ATA version here, if it didn't get reported */
1355: if (drvp->ata_vers == 0) {
1356: if (drvp->drive_flags & DRIVE_UDMA)
1357: drvp->ata_vers = 4; /* should be at last ATA-4 */
1358: else if (drvp->PIO_cap > 2)
1359: drvp->ata_vers = 2; /* should be at last ATA-2 */
1.48 bouyer 1360: }
1361: cf_flags = drv_dev->dv_cfdata->cf_flags;
1362: if (cf_flags & ATA_CONFIG_PIO_SET) {
1363: drvp->PIO_mode =
1364: (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF;
1365: drvp->drive_flags |= DRIVE_MODE;
1366: }
1367: if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) {
1368: /* don't care about DMA modes */
1369: return;
1370: }
1371: if (cf_flags & ATA_CONFIG_DMA_SET) {
1372: if ((cf_flags & ATA_CONFIG_DMA_MODES) ==
1373: ATA_CONFIG_DMA_DISABLE) {
1374: drvp->drive_flags &= ~DRIVE_DMA;
1375: } else {
1376: drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >>
1377: ATA_CONFIG_DMA_OFF;
1378: drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE;
1379: }
1.101 bouyer 1380: }
1381: if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) {
1382: /* don't care about UDMA modes */
1383: return;
1.48 bouyer 1384: }
1385: if (cf_flags & ATA_CONFIG_UDMA_SET) {
1386: if ((cf_flags & ATA_CONFIG_UDMA_MODES) ==
1387: ATA_CONFIG_UDMA_DISABLE) {
1388: drvp->drive_flags &= ~DRIVE_UDMA;
1389: } else {
1390: drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >>
1391: ATA_CONFIG_UDMA_OFF;
1392: drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE;
1393: }
1.2 bouyer 1394: }
1.54 bouyer 1395: }
1396:
1397: /*
1.56 bouyer 1398: * downgrade the transfer mode of a drive after an error. return 1 if
1.54 bouyer 1399: * downgrade was possible, 0 otherwise.
1400: */
1401: int
1.163 thorpej 1402: wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags)
1.54 bouyer 1403: {
1.168 thorpej 1404: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 1405: struct wdc_softc *wdc = chp->ch_wdc;
1.54 bouyer 1406: struct device *drv_dev = drvp->drv_softc;
1407: int cf_flags = drv_dev->dv_cfdata->cf_flags;
1408:
1409: /* if drive or controller don't know its mode, we can't do much */
1410: if ((drvp->drive_flags & DRIVE_MODE) == 0 ||
1411: (wdc->cap & WDC_CAPABILITY_MODE) == 0)
1412: return 0;
1413: /* current drive mode was set by a config flag, let it this way */
1414: if ((cf_flags & ATA_CONFIG_PIO_SET) ||
1415: (cf_flags & ATA_CONFIG_DMA_SET) ||
1416: (cf_flags & ATA_CONFIG_UDMA_SET))
1417: return 0;
1418:
1.61 bouyer 1419: /*
1.73 bouyer 1420: * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first.
1421: * Maybe we didn't properly notice the cable type
1.78 bouyer 1422: * If we were using Ultra-DMA mode 2, downgrade to mode 1 first.
1423: * It helps in some cases.
1.73 bouyer 1424: */
1.78 bouyer 1425: if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) {
1426: drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2;
1427: printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n",
1.73 bouyer 1428: drv_dev->dv_xname, drvp->UDMA_mode);
1429: }
1430:
1431: /*
1.61 bouyer 1432: * If we were using ultra-DMA, don't downgrade to multiword DMA
1433: * if we noticed a CRC error. It has been noticed that CRC errors
1434: * in ultra-DMA lead to silent data corruption in multiword DMA.
1435: * Data corruption is less likely to occur in PIO mode.
1436: */
1.73 bouyer 1437: else if ((drvp->drive_flags & DRIVE_UDMA) &&
1.61 bouyer 1438: (drvp->drive_flags & DRIVE_DMAERR) == 0) {
1.54 bouyer 1439: drvp->drive_flags &= ~DRIVE_UDMA;
1440: drvp->drive_flags |= DRIVE_DMA;
1441: drvp->DMA_mode = drvp->DMA_cap;
1.56 bouyer 1442: printf("%s: transfer error, downgrading to DMA mode %d\n",
1.54 bouyer 1443: drv_dev->dv_xname, drvp->DMA_mode);
1.61 bouyer 1444: } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
1445: drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
1.54 bouyer 1446: drvp->PIO_mode = drvp->PIO_cap;
1.56 bouyer 1447: printf("%s: transfer error, downgrading to PIO mode %d\n",
1.54 bouyer 1448: drv_dev->dv_xname, drvp->PIO_mode);
1449: } else /* already using PIO, can't downgrade */
1450: return 0;
1451:
1452: wdc->set_modes(chp);
1.137 bouyer 1453: wdc_print_modes(chp);
1454: /* reset the channel, which will shedule all drives for setup */
1455: wdc_reset_channel(drvp, flags);
1.54 bouyer 1456: return 1;
1.2 bouyer 1457: }
1458:
1459: int
1.163 thorpej 1460: wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c)
1.31 bouyer 1461: {
1.168 thorpej 1462: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 1463: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1464: struct ata_xfer *xfer;
1.31 bouyer 1465: int s, ret;
1.2 bouyer 1466:
1.34 bouyer 1467: WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n",
1.169 thorpej 1468: wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive),
1.34 bouyer 1469: DEBUG_FUNCS);
1.2 bouyer 1470:
1.31 bouyer 1471: /* set up an xfer and queue. Wait for completion */
1472: xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP :
1473: WDC_NOSLEEP);
1474: if (xfer == NULL) {
1475: return WDC_TRY_AGAIN;
1476: }
1.2 bouyer 1477:
1.169 thorpej 1478: if (wdc->cap & WDC_CAPABILITY_NOIRQ)
1.98 bjh21 1479: wdc_c->flags |= AT_POLL;
1.31 bouyer 1480: if (wdc_c->flags & AT_POLL)
1481: xfer->c_flags |= C_POLL;
1.165 thorpej 1482: xfer->c_drive = drvp->drive;
1483: xfer->c_databuf = wdc_c->data;
1.31 bouyer 1484: xfer->c_bcount = wdc_c->bcount;
1.165 thorpej 1485: xfer->c_cmd = wdc_c;
1.31 bouyer 1486: xfer->c_start = __wdccommand_start;
1487: xfer->c_intr = __wdccommand_intr;
1.75 enami 1488: xfer->c_kill_xfer = __wdccommand_done;
1.2 bouyer 1489:
1.31 bouyer 1490: s = splbio();
1491: wdc_exec_xfer(chp, xfer);
1492: #ifdef DIAGNOSTIC
1493: if ((wdc_c->flags & AT_POLL) != 0 &&
1494: (wdc_c->flags & AT_DONE) == 0)
1.118 provos 1495: panic("wdc_exec_command: polled command not done");
1.2 bouyer 1496: #endif
1.31 bouyer 1497: if (wdc_c->flags & AT_DONE) {
1498: ret = WDC_COMPLETE;
1499: } else {
1500: if (wdc_c->flags & AT_WAIT) {
1.69 bouyer 1501: while ((wdc_c->flags & AT_DONE) == 0) {
1502: tsleep(wdc_c, PRIBIO, "wdccmd", 0);
1503: }
1.31 bouyer 1504: ret = WDC_COMPLETE;
1505: } else {
1506: ret = WDC_QUEUED;
1.2 bouyer 1507: }
1508: }
1.31 bouyer 1509: splx(s);
1510: return ret;
1.2 bouyer 1511: }
1512:
1.167 thorpej 1513: static void
1.168 thorpej 1514: __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer)
1.31 bouyer 1515: {
1.169 thorpej 1516: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1517: int drive = xfer->c_drive;
1518: struct wdc_command *wdc_c = xfer->c_cmd;
1.31 bouyer 1519:
1.34 bouyer 1520: WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n",
1.169 thorpej 1521: wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive),
1.34 bouyer 1522: DEBUG_FUNCS);
1.31 bouyer 1523:
1.169 thorpej 1524: if (wdc->cap & WDC_CAPABILITY_SELECT)
1525: wdc->select(chp,drive);
1.157 fvdl 1526: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.31 bouyer 1527: WDSD_IBM | (drive << 4));
1.137 bouyer 1528: switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ,
1529: wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) {
1530: case WDCWAIT_OK:
1531: break;
1532: case WDCWAIT_TOUT:
1.31 bouyer 1533: wdc_c->flags |= AT_TIMEOU;
1534: __wdccommand_done(chp, xfer);
1.53 bouyer 1535: return;
1.137 bouyer 1536: case WDCWAIT_THR:
1537: return;
1.31 bouyer 1538: }
1.135 bouyer 1539: if (wdc_c->flags & AT_POLL) {
1540: /* polled command, disable interrupts */
1541: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
1542: WDCTL_4BIT | WDCTL_IDS);
1543: }
1.31 bouyer 1544: wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head,
1545: wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp);
1.139 bouyer 1546:
1.31 bouyer 1547: if ((wdc_c->flags & AT_POLL) == 0) {
1548: chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */
1.81 thorpej 1549: callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz,
1550: wdctimeout, chp);
1.31 bouyer 1551: return;
1.2 bouyer 1552: }
1553: /*
1.31 bouyer 1554: * Polled command. Wait for drive ready or drq. Done in intr().
1555: * Wait for at last 400ns for status bit to be valid.
1.2 bouyer 1556: */
1.134 mycroft 1557: delay(10); /* 400ns delay */
1.66 bouyer 1558: __wdccommand_intr(chp, xfer, 0);
1.2 bouyer 1559: }
1560:
1.167 thorpej 1561: static int
1.168 thorpej 1562: __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq)
1.2 bouyer 1563: {
1.169 thorpej 1564: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1565: struct wdc_command *wdc_c = xfer->c_cmd;
1.31 bouyer 1566: int bcount = wdc_c->bcount;
1567: char *data = wdc_c->data;
1.137 bouyer 1568: int wflags;
1569:
1570: if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) {
1571: /* both wait and poll, we can tsleep here */
1.147 bouyer 1572: wflags = AT_WAIT | AT_POLL;
1.137 bouyer 1573: } else {
1574: wflags = AT_POLL;
1575: }
1.31 bouyer 1576:
1.163 thorpej 1577: again:
1.34 bouyer 1578: WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n",
1.169 thorpej 1579: wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive),
1.165 thorpej 1580: DEBUG_INTR);
1.137 bouyer 1581: /*
1582: * after a ATAPI_SOFT_RESET, the device will have released the bus.
1583: * Reselect again, it doesn't hurt for others commands, and the time
1584: * penalty for the extra regiter write is acceptable,
1585: * wdc_exec_command() isn't called often (mosly for autoconfig)
1586: */
1.157 fvdl 1587: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.165 thorpej 1588: WDSD_IBM | (xfer->c_drive << 4));
1.114 bouyer 1589: if ((wdc_c->flags & AT_XFDONE) != 0) {
1590: /*
1591: * We have completed a data xfer. The drive should now be
1592: * in its initial state
1593: */
1594: if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ,
1.137 bouyer 1595: wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0,
1596: wflags) == WDCWAIT_TOUT) {
1.114 bouyer 1597: if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1598: return 0; /* IRQ was not for us */
1599: wdc_c->flags |= AT_TIMEOU;
1600: }
1.131 mycroft 1601: goto out;
1.114 bouyer 1602: }
1.31 bouyer 1603: if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask,
1.137 bouyer 1604: (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) {
1.66 bouyer 1605: if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1.63 bouyer 1606: return 0; /* IRQ was not for us */
1607: wdc_c->flags |= AT_TIMEOU;
1.131 mycroft 1608: goto out;
1.2 bouyer 1609: }
1.169 thorpej 1610: if (wdc->cap & WDC_CAPABILITY_IRQACK)
1611: wdc->irqack(chp);
1.31 bouyer 1612: if (wdc_c->flags & AT_READ) {
1.131 mycroft 1613: if ((chp->ch_status & WDCS_DRQ) == 0) {
1614: wdc_c->flags |= AT_TIMEOU;
1615: goto out;
1616: }
1.165 thorpej 1617: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) {
1.31 bouyer 1618: bus_space_read_multi_4(chp->data32iot, chp->data32ioh,
1619: 0, (u_int32_t*)data, bcount >> 2);
1620: data += bcount & 0xfffffffc;
1621: bcount = bcount & 0x03;
1622: }
1623: if (bcount > 0)
1.157 fvdl 1624: bus_space_read_multi_2(chp->cmd_iot,
1625: chp->cmd_iohs[wd_data], 0,
1626: (u_int16_t *)data, bcount >> 1);
1.114 bouyer 1627: /* at this point the drive should be in its initial state */
1628: wdc_c->flags |= AT_XFDONE;
1.137 bouyer 1629: /* XXX should read status register here ? */
1.131 mycroft 1630: } else if (wdc_c->flags & AT_WRITE) {
1631: if ((chp->ch_status & WDCS_DRQ) == 0) {
1.114 bouyer 1632: wdc_c->flags |= AT_TIMEOU;
1.131 mycroft 1633: goto out;
1634: }
1.165 thorpej 1635: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) {
1.31 bouyer 1636: bus_space_write_multi_4(chp->data32iot, chp->data32ioh,
1637: 0, (u_int32_t*)data, bcount >> 2);
1638: data += bcount & 0xfffffffc;
1639: bcount = bcount & 0x03;
1640: }
1641: if (bcount > 0)
1.157 fvdl 1642: bus_space_write_multi_2(chp->cmd_iot,
1643: chp->cmd_iohs[wd_data], 0,
1644: (u_int16_t *)data, bcount >> 1);
1.114 bouyer 1645: wdc_c->flags |= AT_XFDONE;
1646: if ((wdc_c->flags & AT_POLL) == 0) {
1647: chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */
1648: callout_reset(&chp->ch_callout,
1649: wdc_c->timeout / 1000 * hz, wdctimeout, chp);
1650: return 1;
1651: } else {
1652: goto again;
1653: }
1.2 bouyer 1654: }
1.163 thorpej 1655: out:
1.31 bouyer 1656: __wdccommand_done(chp, xfer);
1657: return 1;
1.2 bouyer 1658: }
1659:
1.167 thorpej 1660: static void
1.168 thorpej 1661: __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer)
1.2 bouyer 1662: {
1.169 thorpej 1663: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1664: struct wdc_command *wdc_c = xfer->c_cmd;
1.2 bouyer 1665:
1.34 bouyer 1666: WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n",
1.169 thorpej 1667: wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive),
1.165 thorpej 1668: DEBUG_FUNCS);
1.70 bouyer 1669:
1.81 thorpej 1670: callout_stop(&chp->ch_callout);
1.70 bouyer 1671:
1.31 bouyer 1672: if (chp->ch_status & WDCS_DWF)
1673: wdc_c->flags |= AT_DF;
1674: if (chp->ch_status & WDCS_ERR) {
1675: wdc_c->flags |= AT_ERROR;
1676: wdc_c->r_error = chp->ch_error;
1677: }
1678: wdc_c->flags |= AT_DONE;
1.80 enami 1679: if ((wdc_c->flags & AT_READREG) != 0 &&
1.169 thorpej 1680: (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 &&
1.75 enami 1681: (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) {
1.157 fvdl 1682: wdc_c->r_head = bus_space_read_1(chp->cmd_iot,
1683: chp->cmd_iohs[wd_sdh], 0);
1684: wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot,
1685: chp->cmd_iohs[wd_cyl_hi], 0) << 8;
1686: wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot,
1687: chp->cmd_iohs[wd_cyl_lo], 0);
1688: wdc_c->r_sector = bus_space_read_1(chp->cmd_iot,
1689: chp->cmd_iohs[wd_sector], 0);
1690: wdc_c->r_count = bus_space_read_1(chp->cmd_iot,
1691: chp->cmd_iohs[wd_seccnt], 0);
1692: wdc_c->r_error = bus_space_read_1(chp->cmd_iot,
1693: chp->cmd_iohs[wd_error], 0);
1694: wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot,
1695: chp->cmd_iohs[wd_precomp], 0);
1.135 bouyer 1696: }
1.137 bouyer 1697:
1.135 bouyer 1698: if (wdc_c->flags & AT_POLL) {
1699: /* enable interrupts */
1700: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
1701: WDCTL_4BIT);
1.173 ! bouyer 1702: delay(10); /* some drives need a little delay here */
1.46 kenh 1703: }
1.31 bouyer 1704: wdc_free_xfer(chp, xfer);
1.71 bouyer 1705: if (wdc_c->flags & AT_WAIT)
1706: wakeup(wdc_c);
1707: else if (wdc_c->callback)
1708: wdc_c->callback(wdc_c->callback_arg);
1.45 drochner 1709: wdcstart(chp);
1.31 bouyer 1710: return;
1.2 bouyer 1711: }
1712:
1713: /*
1.31 bouyer 1714: * Send a command. The drive should be ready.
1.2 bouyer 1715: * Assumes interrupts are blocked.
1716: */
1.31 bouyer 1717: void
1.168 thorpej 1718: wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command,
1.163 thorpej 1719: u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count,
1720: u_int8_t precomp)
1.31 bouyer 1721: {
1.169 thorpej 1722: struct wdc_softc *wdc = chp->ch_wdc;
1.163 thorpej 1723:
1.31 bouyer 1724: WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d "
1.169 thorpej 1725: "sector=%d count=%d precomp=%d\n", wdc->sc_dev.dv_xname,
1726: chp->ch_channel, drive, command, cylin, head, sector, count,
1727: precomp), DEBUG_FUNCS);
1.31 bouyer 1728:
1.169 thorpej 1729: if (wdc->cap & WDC_CAPABILITY_SELECT)
1730: wdc->select(chp,drive);
1.107 dbj 1731:
1.31 bouyer 1732: /* Select drive, head, and addressing mode. */
1.157 fvdl 1733: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.31 bouyer 1734: WDSD_IBM | (drive << 4) | head);
1735: /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */
1.157 fvdl 1736: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0,
1.31 bouyer 1737: precomp);
1.157 fvdl 1738: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin);
1739: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi],
1740: 0, cylin >> 8);
1741: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector);
1742: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count);
1.108 christos 1743:
1744: /* Send command. */
1.157 fvdl 1745: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command);
1.108 christos 1746: return;
1747: }
1748:
1749: /*
1750: * Send a 48-bit addressing command. The drive should be ready.
1751: * Assumes interrupts are blocked.
1752: */
1753: void
1.168 thorpej 1754: wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command,
1.163 thorpej 1755: u_int64_t blkno, u_int16_t count)
1.108 christos 1756: {
1.169 thorpej 1757: struct wdc_softc *wdc = chp->ch_wdc;
1.163 thorpej 1758:
1.108 christos 1759: WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d "
1.169 thorpej 1760: "count=%d\n", wdc->sc_dev.dv_xname,
1761: chp->ch_channel, drive, command, (u_int32_t) blkno, count),
1.108 christos 1762: DEBUG_FUNCS);
1763:
1.169 thorpej 1764: if (wdc->cap & WDC_CAPABILITY_SELECT)
1765: wdc->select(chp,drive);
1.108 christos 1766:
1767: /* Select drive, head, and addressing mode. */
1.157 fvdl 1768: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.108 christos 1769: (drive << 4) | WDSD_LBA);
1770:
1771: /* previous */
1.157 fvdl 1772: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0);
1773: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt],
1774: 0, count >> 8);
1775: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi],
1776: 0, blkno >> 40);
1777: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi],
1778: 0, blkno >> 32);
1779: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo],
1780: 0, blkno >> 24);
1.108 christos 1781:
1782: /* current */
1.157 fvdl 1783: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0);
1784: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count);
1785: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi],
1786: 0, blkno >> 16);
1787: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi],
1788: 0, blkno >> 8);
1789: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno);
1.2 bouyer 1790:
1.31 bouyer 1791: /* Send command. */
1.157 fvdl 1792: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command);
1.31 bouyer 1793: return;
1.2 bouyer 1794: }
1795:
1796: /*
1.31 bouyer 1797: * Simplified version of wdccommand(). Unbusy/ready/drq must be
1798: * tested by the caller.
1.2 bouyer 1799: */
1.31 bouyer 1800: void
1.168 thorpej 1801: wdccommandshort(struct wdc_channel *chp, int drive, int command)
1.2 bouyer 1802: {
1.169 thorpej 1803: struct wdc_softc *wdc = chp->ch_wdc;
1.2 bouyer 1804:
1.31 bouyer 1805: WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n",
1.169 thorpej 1806: wdc->sc_dev.dv_xname, chp->ch_channel, drive, command),
1.31 bouyer 1807: DEBUG_FUNCS);
1.107 dbj 1808:
1.169 thorpej 1809: if (wdc->cap & WDC_CAPABILITY_SELECT)
1810: wdc->select(chp,drive);
1.2 bouyer 1811:
1.31 bouyer 1812: /* Select drive. */
1.157 fvdl 1813: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.31 bouyer 1814: WDSD_IBM | (drive << 4));
1.2 bouyer 1815:
1.157 fvdl 1816: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command);
1.31 bouyer 1817: }
1.2 bouyer 1818:
1.31 bouyer 1819: /* Add a command to the queue and start controller. Must be called at splbio */
1.2 bouyer 1820: void
1.168 thorpej 1821: wdc_exec_xfer(struct wdc_channel *chp, struct ata_xfer *xfer)
1.2 bouyer 1822: {
1.163 thorpej 1823:
1.33 bouyer 1824: WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer,
1.169 thorpej 1825: chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
1.2 bouyer 1826:
1.31 bouyer 1827: /* complete xfer setup */
1.165 thorpej 1828: xfer->c_chp = chp;
1.2 bouyer 1829:
1.31 bouyer 1830: /*
1831: * If we are a polled command, and the list is not empty,
1832: * we are doing a dump. Drop the list to allow the polled command
1833: * to complete, we're going to reboot soon anyway.
1834: */
1835: if ((xfer->c_flags & C_POLL) != 0 &&
1.165 thorpej 1836: TAILQ_FIRST(&chp->ch_queue->queue_xfer) != NULL) {
1837: TAILQ_INIT(&chp->ch_queue->queue_xfer);
1.31 bouyer 1838: }
1.2 bouyer 1839: /* insert at the end of command list */
1.165 thorpej 1840: TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
1.31 bouyer 1841: WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n",
1.33 bouyer 1842: chp->ch_flags), DEBUG_XFERS);
1.45 drochner 1843: wdcstart(chp);
1.31 bouyer 1844: }
1.2 bouyer 1845:
1.165 thorpej 1846: struct ata_xfer *
1.163 thorpej 1847: wdc_get_xfer(int flags)
1.2 bouyer 1848: {
1.165 thorpej 1849: struct ata_xfer *xfer;
1.72 bouyer 1850: int s;
1.2 bouyer 1851:
1.72 bouyer 1852: s = splbio();
1.71 bouyer 1853: xfer = pool_get(&wdc_xfer_pool,
1854: ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK));
1.72 bouyer 1855: splx(s);
1.99 chs 1856: if (xfer != NULL) {
1.165 thorpej 1857: memset(xfer, 0, sizeof(struct ata_xfer));
1.99 chs 1858: }
1.2 bouyer 1859: return xfer;
1860: }
1861:
1862: void
1.168 thorpej 1863: wdc_free_xfer(struct wdc_channel *chp, struct ata_xfer *xfer)
1.2 bouyer 1864: {
1.169 thorpej 1865: struct wdc_softc *wdc = chp->ch_wdc;
1.2 bouyer 1866: int s;
1867:
1.31 bouyer 1868: if (wdc->cap & WDC_CAPABILITY_HWLOCK)
1869: (*wdc->free_hw)(chp);
1.2 bouyer 1870: s = splbio();
1.31 bouyer 1871: chp->ch_flags &= ~WDCF_ACTIVE;
1.165 thorpej 1872: TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
1.72 bouyer 1873: pool_put(&wdc_xfer_pool, xfer);
1.2 bouyer 1874: splx(s);
1.75 enami 1875: }
1876:
1877: /*
1.168 thorpej 1878: * Kill off all pending xfers for a wdc_channel.
1.75 enami 1879: *
1880: * Must be called at splbio().
1881: */
1882: void
1.168 thorpej 1883: wdc_kill_pending(struct wdc_channel *chp)
1.75 enami 1884: {
1.165 thorpej 1885: struct ata_xfer *xfer;
1.75 enami 1886:
1.165 thorpej 1887: while ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) != NULL) {
1888: chp = xfer->c_chp;
1.75 enami 1889: (*xfer->c_kill_xfer)(chp, xfer);
1890: }
1.2 bouyer 1891: }
1892:
1.31 bouyer 1893: static void
1.168 thorpej 1894: __wdcerror(struct wdc_channel *chp, char *msg)
1.2 bouyer 1895: {
1.169 thorpej 1896: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1897: struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.88 mrg 1898:
1.2 bouyer 1899: if (xfer == NULL)
1.169 thorpej 1900: printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel,
1.31 bouyer 1901: msg);
1.2 bouyer 1902: else
1.169 thorpej 1903: printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname,
1904: chp->ch_channel, xfer->c_drive, msg);
1.2 bouyer 1905: }
1906:
1907: /*
1908: * the bit bucket
1909: */
1910: void
1.168 thorpej 1911: wdcbit_bucket(struct wdc_channel *chp, int size)
1.2 bouyer 1912: {
1913:
1.12 cgd 1914: for (; size >= 2; size -= 2)
1.157 fvdl 1915: (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0);
1.12 cgd 1916: if (size)
1.157 fvdl 1917: (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0);
1.44 thorpej 1918: }
1919:
1920: int
1.168 thorpej 1921: wdc_addref(struct wdc_channel *chp)
1.44 thorpej 1922: {
1.169 thorpej 1923: struct wdc_softc *wdc = chp->ch_wdc;
1.96 bouyer 1924: struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic;
1.44 thorpej 1925: int s, error = 0;
1926:
1927: s = splbio();
1.96 bouyer 1928: if (adapt->adapt_refcnt++ == 0 &&
1929: adapt->adapt_enable != NULL) {
1930: error = (*adapt->adapt_enable)(&wdc->sc_dev, 1);
1.44 thorpej 1931: if (error)
1.96 bouyer 1932: adapt->adapt_refcnt--;
1.44 thorpej 1933: }
1934: splx(s);
1935: return (error);
1936: }
1937:
1938: void
1.168 thorpej 1939: wdc_delref(struct wdc_channel *chp)
1.44 thorpej 1940: {
1.169 thorpej 1941: struct wdc_softc *wdc = chp->ch_wdc;
1.96 bouyer 1942: struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic;
1.44 thorpej 1943: int s;
1944:
1945: s = splbio();
1.96 bouyer 1946: if (adapt->adapt_refcnt-- == 1 &&
1947: adapt->adapt_enable != NULL)
1948: (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0);
1.44 thorpej 1949: splx(s);
1.93 wrstuden 1950: }
1951:
1952: void
1.168 thorpej 1953: wdc_print_modes(struct wdc_channel *chp)
1.93 wrstuden 1954: {
1.169 thorpej 1955: struct wdc_softc *wdc = chp->ch_wdc;
1.93 wrstuden 1956: int drive;
1957: struct ata_drive_datas *drvp;
1958:
1959: for (drive = 0; drive < 2; drive++) {
1960: drvp = &chp->ch_drive[drive];
1961: if ((drvp->drive_flags & DRIVE) == 0)
1962: continue;
1.123 thorpej 1963: aprint_normal("%s(%s:%d:%d): using PIO mode %d",
1.93 wrstuden 1964: drvp->drv_softc->dv_xname,
1.169 thorpej 1965: wdc->sc_dev.dv_xname,
1966: chp->ch_channel, drive, drvp->PIO_mode);
1.93 wrstuden 1967: if (drvp->drive_flags & DRIVE_DMA)
1.123 thorpej 1968: aprint_normal(", DMA mode %d", drvp->DMA_mode);
1.93 wrstuden 1969: if (drvp->drive_flags & DRIVE_UDMA) {
1.123 thorpej 1970: aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode);
1.93 wrstuden 1971: if (drvp->UDMA_mode == 2)
1.123 thorpej 1972: aprint_normal(" (Ultra/33)");
1.93 wrstuden 1973: else if (drvp->UDMA_mode == 4)
1.123 thorpej 1974: aprint_normal(" (Ultra/66)");
1.93 wrstuden 1975: else if (drvp->UDMA_mode == 5)
1.123 thorpej 1976: aprint_normal(" (Ultra/100)");
1977: else if (drvp->UDMA_mode == 6)
1978: aprint_normal(" (Ultra/133)");
1.93 wrstuden 1979: }
1980: if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA))
1.123 thorpej 1981: aprint_normal(" (using DMA data transfers)");
1982: aprint_normal("\n");
1.93 wrstuden 1983: }
1.2 bouyer 1984: }
CVSweb <webmaster@jp.NetBSD.org>
![[BACK]](/icons/back.gif){kind=icon}
Return to wdc.c CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [cvs.NetBSD.org] / src / sys / dev / ic