Annotation of src/sys/dev/ic/wdc.c, Revision 1.172.2.6
1.172.2.6! he 1: /* $NetBSD: wdc.c,v 1.172.2.5 2004/08/11 19:43:58 jmc Exp $ */
1.31 bouyer 2:
3: /*
1.137 bouyer 4: * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved.
1.31 bouyer 5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: * 3. All advertising materials mentioning features or use of this software
15: * must display the following acknowledgement:
16: * This product includes software developed by Manuel Bouyer.
17: * 4. The name of the author may not be used to endorse or promote products
18: * derived from this software without specific prior written permission.
19: *
20: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30: */
1.2 bouyer 31:
1.27 mycroft 32: /*-
1.125 mycroft 33: * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
1.27 mycroft 34: * All rights reserved.
1.2 bouyer 35: *
1.27 mycroft 36: * This code is derived from software contributed to The NetBSD Foundation
37: * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
1.12 cgd 38: *
1.2 bouyer 39: * Redistribution and use in source and binary forms, with or without
40: * modification, are permitted provided that the following conditions
41: * are met:
42: * 1. Redistributions of source code must retain the above copyright
43: * notice, this list of conditions and the following disclaimer.
44: * 2. Redistributions in binary form must reproduce the above copyright
45: * notice, this list of conditions and the following disclaimer in the
46: * documentation and/or other materials provided with the distribution.
47: * 3. All advertising materials mentioning features or use of this software
48: * must display the following acknowledgement:
1.27 mycroft 49: * This product includes software developed by the NetBSD
50: * Foundation, Inc. and its contributors.
51: * 4. Neither the name of The NetBSD Foundation nor the names of its
52: * contributors may be used to endorse or promote products derived
53: * from this software without specific prior written permission.
1.2 bouyer 54: *
1.27 mycroft 55: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
56: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
57: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
58: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
59: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
60: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
61: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
62: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
63: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
64: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
65: * POSSIBILITY OF SUCH DAMAGE.
1.2 bouyer 66: */
67:
1.12 cgd 68: /*
69: * CODE UNTESTED IN THE CURRENT REVISION:
70: */
1.100 lukem 71:
72: #include <sys/cdefs.h>
1.172.2.6! he 73: __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.172.2.5 2004/08/11 19:43:58 jmc Exp $");
1.12 cgd 74:
1.59 hubertf 75: #ifndef WDCDEBUG
1.31 bouyer 76: #define WDCDEBUG
1.59 hubertf 77: #endif /* WDCDEBUG */
1.31 bouyer 78:
1.2 bouyer 79: #include <sys/param.h>
80: #include <sys/systm.h>
81: #include <sys/kernel.h>
82: #include <sys/conf.h>
83: #include <sys/buf.h>
1.31 bouyer 84: #include <sys/device.h>
1.2 bouyer 85: #include <sys/malloc.h>
1.71 bouyer 86: #include <sys/pool.h>
1.2 bouyer 87: #include <sys/syslog.h>
88: #include <sys/proc.h>
89:
90: #include <machine/intr.h>
91: #include <machine/bus.h>
92:
1.17 sakamoto 93: #ifndef __BUS_SPACE_HAS_STREAM_METHODS
1.31 bouyer 94: #define bus_space_write_multi_stream_2 bus_space_write_multi_2
95: #define bus_space_write_multi_stream_4 bus_space_write_multi_4
96: #define bus_space_read_multi_stream_2 bus_space_read_multi_2
97: #define bus_space_read_multi_stream_4 bus_space_read_multi_4
1.17 sakamoto 98: #endif /* __BUS_SPACE_HAS_STREAM_METHODS */
1.16 sakamoto 99:
1.103 bouyer 100: #include <dev/ata/atavar.h>
1.31 bouyer 101: #include <dev/ata/atareg.h>
1.12 cgd 102: #include <dev/ic/wdcreg.h>
103: #include <dev/ic/wdcvar.h>
1.31 bouyer 104:
1.137 bouyer 105: #include "locators.h"
106:
1.122 thorpej 107: #include "ataraid.h"
1.2 bouyer 108: #include "atapibus.h"
1.106 bouyer 109: #include "wd.h"
1.2 bouyer 110:
1.122 thorpej 111: #if NATARAID > 0
112: #include <dev/ata/ata_raidvar.h>
113: #endif
114:
1.31 bouyer 115: #define WDCDELAY 100 /* 100 microseconds */
116: #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY)
1.2 bouyer 117: #if 0
1.31 bouyer 118: /* If you enable this, it will report any delays more than WDCDELAY * N long. */
1.2 bouyer 119: #define WDCNDELAY_DEBUG 50
120: #endif
121:
1.137 bouyer 122: /* When polling wait that much and then tsleep for 1/hz seconds */
123: #define WDCDELAY_POLL 1 /* ms */
124:
125: /* timeout for the control commands */
126: #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */
127:
1.71 bouyer 128: struct pool wdc_xfer_pool;
1.2 bouyer 129:
1.106 bouyer 130: #if NWD > 0
1.103 bouyer 131: extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */
1.106 bouyer 132: #else
133: /* A fake one, the autoconfig will print "wd at foo ... not configured */
134: const struct ata_bustype wdc_ata_bustype = {
135: SCSIPI_BUSTYPE_ATA,
136: NULL,
137: NULL,
138: NULL,
139: NULL,
140: NULL,
141: NULL,
142: NULL
143: };
144: #endif
1.102 bouyer 145:
1.168 thorpej 146: static int wdcprobe1(struct wdc_channel*, int);
147: static void __wdcerror(struct wdc_channel*, char *);
148: static int __wdcwait_reset(struct wdc_channel *, int, int);
1.172.2.5 jmc 149: static void __wdc_reset_channel(struct wdc_channel *, int);
1.168 thorpej 150: static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *);
1.172.2.5 jmc 151: static void __wdccommand_done_end(struct wdc_channel *, struct ata_xfer *);
152: static void __wdccommand_kill_xfer(struct wdc_channel *,
153: struct ata_xfer *, int);
1.168 thorpej 154: static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *);
1.172.2.5 jmc 155: static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *, int);
1.168 thorpej 156: static int __wdcwait(struct wdc_channel *, int, int, int);
1.31 bouyer 157:
158: #define DEBUG_INTR 0x01
159: #define DEBUG_XFERS 0x02
160: #define DEBUG_STATUS 0x04
161: #define DEBUG_FUNCS 0x08
162: #define DEBUG_PROBE 0x10
1.74 enami 163: #define DEBUG_DETACH 0x20
1.87 bouyer 164: #define DEBUG_DELAY 0x40
1.31 bouyer 165: #ifdef WDCDEBUG
1.32 bouyer 166: int wdcdebug_mask = 0;
1.31 bouyer 167: int wdc_nxfer = 0;
168: #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args
1.2 bouyer 169: #else
1.31 bouyer 170: #define WDCDEBUG_PRINT(args, level)
1.2 bouyer 171: #endif
172:
1.162 thorpej 173: /*
174: * A queue of atabus instances, used to ensure the same bus probe order
175: * for a given hardware configuration at each boot.
176: */
177: struct atabus_initq_head atabus_initq_head =
178: TAILQ_HEAD_INITIALIZER(atabus_initq_head);
179: struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER;
1.137 bouyer 180:
1.162 thorpej 181: /* Test to see controller with at last one attached drive is there.
182: * Returns a bit for each possible drive found (0x01 for drive 0,
183: * 0x02 for drive 1).
184: * Logic:
185: * - If a status register is at 0xff, assume there is no drive here
186: * (ISA has pull-up resistors). Similarly if the status register has
187: * the value we last wrote to the bus (for IDE interfaces without pullups).
188: * If no drive at all -> return.
189: * - reset the controller, wait for it to complete (may take up to 31s !).
190: * If timeout -> return.
191: * - test ATA/ATAPI signatures. If at last one drive found -> return.
192: * - try an ATA command on the master.
193: */
1.137 bouyer 194:
1.164 thorpej 195: static void
1.168 thorpej 196: wdc_drvprobe(struct wdc_channel *chp)
1.137 bouyer 197: {
198: struct ataparams params;
1.169 thorpej 199: struct wdc_softc *wdc = chp->ch_wdc;
1.145 christos 200: u_int8_t st0 = 0, st1 = 0;
1.164 thorpej 201: int i, error;
1.137 bouyer 202:
1.164 thorpej 203: if (wdcprobe1(chp, 0) == 0) {
204: /* No drives, abort the attach here. */
205: return;
1.161 thorpej 206: }
1.137 bouyer 207:
208: /* for ATA/OLD drives, wait for DRDY, 3s timeout */
209: for (i = 0; i < mstohz(3000); i++) {
1.172.2.2 tron 210: if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) {
211: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
212: wdc->select(chp,0);
213: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
214: 0, WDSD_IBM);
215: delay(10); /* 400ns delay */
216: st0 = bus_space_read_1(chp->cmd_iot,
217: chp->cmd_iohs[wd_status], 0);
218: }
1.137 bouyer 219:
1.172.2.2 tron 220: if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) {
221: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
222: wdc->select(chp,1);
223: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
224: 0, WDSD_IBM | 0x10);
225: delay(10); /* 400ns delay */
226: st1 = bus_space_read_1(chp->cmd_iot,
227: chp->cmd_iohs[wd_status], 0);
228: }
1.137 bouyer 229:
230: if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD))
231: == 0 ||
232: (st0 & WDCS_DRDY)) &&
233: ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD))
234: == 0 ||
235: (st1 & WDCS_DRDY)))
236: break;
1.164 thorpej 237: tsleep(¶ms, PRIBIO, "atadrdy", 1);
1.137 bouyer 238: }
239: if ((st0 & WDCS_DRDY) == 0)
240: chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD);
241: if ((st1 & WDCS_DRDY) == 0)
242: chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD);
243:
244: WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n",
1.169 thorpej 245: wdc->sc_dev.dv_xname,
246: chp->ch_channel, st0, st1), DEBUG_PROBE);
1.137 bouyer 247:
248: /* Wait a bit, some devices are weird just after a reset. */
249: delay(5000);
250:
251: for (i = 0; i < 2; i++) {
1.171 thorpej 252: /* XXX This should be done by other code. */
1.137 bouyer 253: chp->ch_drive[i].chnl_softc = chp;
254: chp->ch_drive[i].drive = i;
1.171 thorpej 255:
1.137 bouyer 256: /*
257: * Init error counter so that an error withing the first xfers
258: * will trigger a downgrade
259: */
260: chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1;
261:
262: /* If controller can't do 16bit flag the drives as 32bit */
1.169 thorpej 263: if ((wdc->cap &
1.137 bouyer 264: (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
265: WDC_CAPABILITY_DATA32)
266: chp->ch_drive[i].drive_flags |= DRIVE_CAP32;
267: if ((chp->ch_drive[i].drive_flags & DRIVE) == 0)
268: continue;
269:
1.144 briggs 270: /* Shortcut in case we've been shutdown */
271: if (chp->ch_flags & WDCF_SHUTDOWN)
1.164 thorpej 272: return;
1.144 briggs 273:
1.137 bouyer 274: /* issue an identify, to try to detect ghosts */
275: error = ata_get_params(&chp->ch_drive[i],
276: AT_WAIT | AT_POLL, ¶ms);
277: if (error != CMD_OK) {
1.164 thorpej 278: tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000));
1.144 briggs 279:
280: /* Shortcut in case we've been shutdown */
281: if (chp->ch_flags & WDCF_SHUTDOWN)
1.164 thorpej 282: return;
1.144 briggs 283:
1.137 bouyer 284: error = ata_get_params(&chp->ch_drive[i],
285: AT_WAIT | AT_POLL, ¶ms);
286: }
287: if (error == CMD_OK) {
1.152 wiz 288: /* If IDENTIFY succeeded, this is not an OLD ctrl */
1.137 bouyer 289: chp->ch_drive[0].drive_flags &= ~DRIVE_OLD;
290: chp->ch_drive[1].drive_flags &= ~DRIVE_OLD;
291: } else {
1.155 bouyer 292: chp->ch_drive[i].drive_flags &=
1.137 bouyer 293: ~(DRIVE_ATA | DRIVE_ATAPI);
294: WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n",
1.169 thorpej 295: wdc->sc_dev.dv_xname,
296: chp->ch_channel, i, error), DEBUG_PROBE);
1.137 bouyer 297: if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0)
298: continue;
299: /*
300: * Pre-ATA drive ?
301: * Test registers writability (Error register not
302: * writable, but cyllo is), then try an ATA command.
303: */
1.169 thorpej 304: if (wdc->cap & WDC_CAPABILITY_SELECT)
305: wdc->select(chp,i);
1.157 fvdl 306: bus_space_write_1(chp->cmd_iot,
307: chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4));
1.137 bouyer 308: delay(10); /* 400ns delay */
1.157 fvdl 309: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error],
310: 0, 0x58);
311: bus_space_write_1(chp->cmd_iot,
312: chp->cmd_iohs[wd_cyl_lo], 0, 0xa5);
313: if (bus_space_read_1(chp->cmd_iot,
314: chp->cmd_iohs[wd_error], 0) == 0x58 ||
315: bus_space_read_1(chp->cmd_iot,
316: chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) {
1.137 bouyer 317: WDCDEBUG_PRINT(("%s:%d:%d: register "
318: "writability failed\n",
1.169 thorpej 319: wdc->sc_dev.dv_xname,
320: chp->ch_channel, i), DEBUG_PROBE);
1.137 bouyer 321: chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
1.155 bouyer 322: continue;
1.137 bouyer 323: }
1.166 thorpej 324: if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) {
1.137 bouyer 325: WDCDEBUG_PRINT(("%s:%d:%d: not ready\n",
1.169 thorpej 326: wdc->sc_dev.dv_xname,
327: chp->ch_channel, i), DEBUG_PROBE);
1.137 bouyer 328: chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
329: continue;
330: }
1.157 fvdl 331: bus_space_write_1(chp->cmd_iot,
332: chp->cmd_iohs[wd_command], 0, WDCC_RECAL);
1.137 bouyer 333: delay(10); /* 400ns delay */
1.166 thorpej 334: if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) {
1.137 bouyer 335: WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n",
1.169 thorpej 336: wdc->sc_dev.dv_xname,
337: chp->ch_channel, i), DEBUG_PROBE);
1.137 bouyer 338: chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
1.155 bouyer 339: } else {
340: chp->ch_drive[0].drive_flags &=
341: ~(DRIVE_ATA | DRIVE_ATAPI);
342: chp->ch_drive[1].drive_flags &=
343: ~(DRIVE_ATA | DRIVE_ATAPI);
1.137 bouyer 344: }
345: }
346: }
1.164 thorpej 347: }
348:
349: void
350: atabusconfig(struct atabus_softc *atabus_sc)
351: {
1.168 thorpej 352: struct wdc_channel *chp = atabus_sc->sc_chan;
1.169 thorpej 353: struct wdc_softc *wdc = chp->ch_wdc;
1.164 thorpej 354: int i, error, need_delref = 0;
355: struct atabus_initq *atabus_initq = NULL;
356:
357: if ((error = wdc_addref(chp)) != 0) {
358: aprint_error("%s: unable to enable controller\n",
1.169 thorpej 359: wdc->sc_dev.dv_xname);
1.164 thorpej 360: goto out;
361: }
362: need_delref = 1;
363:
364: /* Probe for the drives. */
1.169 thorpej 365: (*wdc->drv_probe)(chp);
1.137 bouyer 366:
367: WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n",
368: chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags),
369: DEBUG_PROBE);
370:
371: /* If no drives, abort here */
372: if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 &&
373: (chp->ch_drive[1].drive_flags & DRIVE) == 0)
374: goto out;
375:
1.164 thorpej 376: /* Shortcut in case we've been shutdown */
377: if (chp->ch_flags & WDCF_SHUTDOWN)
378: goto out;
379:
1.137 bouyer 380: /* Make sure the devices probe in atabus order to avoid jitter. */
381: simple_lock(&atabus_interlock);
382: while(1) {
383: atabus_initq = TAILQ_FIRST(&atabus_initq_head);
384: if (atabus_initq->atabus_sc == atabus_sc)
385: break;
386: ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0,
387: &atabus_interlock);
388: }
389: simple_unlock(&atabus_interlock);
390:
391: /*
392: * Attach an ATAPI bus, if needed.
393: */
394: if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) ||
395: (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) {
396: #if NATAPIBUS > 0
397: wdc_atapibus_attach(atabus_sc);
398: #else
399: /*
400: * Fake the autoconfig "not configured" message
401: */
402: aprint_normal("atapibus at %s not configured\n",
1.169 thorpej 403: wdc->sc_dev.dv_xname);
1.137 bouyer 404: chp->atapibus = NULL;
1.141 bouyer 405: chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI;
406: chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI;
1.137 bouyer 407: #endif
408: }
409:
410: for (i = 0; i < 2; i++) {
411: struct ata_device adev;
412: if ((chp->ch_drive[i].drive_flags &
413: (DRIVE_ATA | DRIVE_OLD)) == 0) {
414: continue;
415: }
416: memset(&adev, 0, sizeof(struct ata_device));
417: adev.adev_bustype = &wdc_ata_bustype;
1.169 thorpej 418: adev.adev_channel = chp->ch_channel;
1.137 bouyer 419: adev.adev_openings = 1;
420: adev.adev_drv_data = &chp->ch_drive[i];
421: chp->ata_drives[i] = config_found(&atabus_sc->sc_dev,
1.162 thorpej 422: &adev, ataprint);
1.141 bouyer 423: if (chp->ata_drives[i] != NULL)
1.137 bouyer 424: wdc_probe_caps(&chp->ch_drive[i]);
1.141 bouyer 425: else
426: chp->ch_drive[i].drive_flags &=
427: ~(DRIVE_ATA | DRIVE_OLD);
1.137 bouyer 428: }
429:
430: /* now that we know the drives, the controller can set its modes */
1.169 thorpej 431: if (wdc->cap & WDC_CAPABILITY_MODE) {
432: wdc->set_modes(chp);
1.137 bouyer 433: wdc_print_modes(chp);
434: }
435: #if NATARAID > 0
1.169 thorpej 436: if (wdc->cap & WDC_CAPABILITY_RAID)
1.137 bouyer 437: for (i = 0; i < 2; i++)
438: if (chp->ata_drives[i] != NULL)
439: ata_raid_check_component(chp->ata_drives[i]);
440: #endif /* NATARAID > 0 */
441:
442: /*
1.152 wiz 443: * reset drive_flags for unattached devices, reset state for attached
1.137 bouyer 444: * ones
445: */
446: for (i = 0; i < 2; i++) {
447: if (chp->ch_drive[i].drv_softc == NULL)
448: chp->ch_drive[i].drive_flags = 0;
449: else
450: chp->ch_drive[i].state = 0;
451: }
452:
1.163 thorpej 453: out:
1.137 bouyer 454: if (atabus_initq == NULL) {
455: simple_lock(&atabus_interlock);
456: while(1) {
457: atabus_initq = TAILQ_FIRST(&atabus_initq_head);
458: if (atabus_initq->atabus_sc == atabus_sc)
459: break;
460: ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0,
461: &atabus_interlock);
462: }
463: simple_unlock(&atabus_interlock);
464: }
465: simple_lock(&atabus_interlock);
466: TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq);
467: simple_unlock(&atabus_interlock);
468:
469: free(atabus_initq, M_DEVBUF);
470: wakeup(&atabus_initq_head);
471:
472: config_pending_decr();
1.144 briggs 473: if (need_delref)
474: wdc_delref(chp);
1.137 bouyer 475: }
476:
1.2 bouyer 477: int
1.168 thorpej 478: wdcprobe(struct wdc_channel *chp)
1.12 cgd 479: {
1.163 thorpej 480:
481: return (wdcprobe1(chp, 1));
1.137 bouyer 482: }
483:
1.167 thorpej 484: static int
1.168 thorpej 485: wdcprobe1(struct wdc_channel *chp, int poll)
1.137 bouyer 486: {
1.169 thorpej 487: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 488: u_int8_t st0, st1, sc, sn, cl, ch;
489: u_int8_t ret_value = 0x03;
490: u_int8_t drive;
1.156 bouyer 491: int s;
1.31 bouyer 492:
493: /*
494: * Sanity check to see if the wdc channel responds at all.
495: */
496:
1.172.2.2 tron 497: s = splbio();
1.169 thorpej 498: if (wdc == NULL ||
499: (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) {
1.107 dbj 500:
1.169 thorpej 501: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
502: wdc->select(chp,0);
1.137 bouyer 503:
1.157 fvdl 504: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.43 kenh 505: WDSD_IBM);
1.131 mycroft 506: delay(10); /* 400ns delay */
1.157 fvdl 507: st0 = bus_space_read_1(chp->cmd_iot,
508: chp->cmd_iohs[wd_status], 0);
1.107 dbj 509:
1.169 thorpej 510: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
511: wdc->select(chp,1);
1.137 bouyer 512:
1.157 fvdl 513: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.43 kenh 514: WDSD_IBM | 0x10);
1.131 mycroft 515: delay(10); /* 400ns delay */
1.157 fvdl 516: st1 = bus_space_read_1(chp->cmd_iot,
517: chp->cmd_iohs[wd_status], 0);
1.43 kenh 518:
519: WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n",
1.169 thorpej 520: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
521: chp->ch_channel, st0, st1), DEBUG_PROBE);
1.43 kenh 522:
1.142 bouyer 523: if (st0 == 0xff || st0 == WDSD_IBM)
1.43 kenh 524: ret_value &= ~0x01;
1.142 bouyer 525: if (st1 == 0xff || st1 == (WDSD_IBM | 0x10))
1.43 kenh 526: ret_value &= ~0x02;
1.125 mycroft 527: /* Register writability test, drive 0. */
528: if (ret_value & 0x01) {
1.169 thorpej 529: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
530: wdc->select(chp,0);
1.157 fvdl 531: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
532: 0, WDSD_IBM);
533: bus_space_write_1(chp->cmd_iot,
534: chp->cmd_iohs[wd_cyl_lo], 0, 0x02);
1.172.2.2 tron 535: cl = bus_space_read_1(chp->cmd_iot,
536: chp->cmd_iohs[wd_cyl_lo], 0);
537: if (cl != 0x02) {
538: WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: "
539: "got 0x%x != 0x02\n",
540: wdc != NULL ?
541: wdc->sc_dev.dv_xname : "wdcprobe",
542: chp->ch_channel, cl),
543: DEBUG_PROBE);
1.125 mycroft 544: ret_value &= ~0x01;
1.172.2.2 tron 545: }
1.157 fvdl 546: bus_space_write_1(chp->cmd_iot,
547: chp->cmd_iohs[wd_cyl_lo], 0, 0x01);
1.172.2.2 tron 548: cl = bus_space_read_1(chp->cmd_iot,
549: chp->cmd_iohs[wd_cyl_lo], 0);
550: if (cl != 0x01) {
551: WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: "
552: "got 0x%x != 0x01\n",
553: wdc != NULL ?
554: wdc->sc_dev.dv_xname : "wdcprobe",
555: chp->ch_channel, cl),
556: DEBUG_PROBE);
1.125 mycroft 557: ret_value &= ~0x01;
1.172.2.2 tron 558: }
1.167 thorpej 559: bus_space_write_1(chp->cmd_iot,
560: chp->cmd_iohs[wd_sector], 0, 0x01);
1.172.2.2 tron 561: cl = bus_space_read_1(chp->cmd_iot,
562: chp->cmd_iohs[wd_sector], 0);
563: if (cl != 0x01) {
564: WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: "
565: "got 0x%x != 0x01\n",
566: wdc != NULL ?
567: wdc->sc_dev.dv_xname : "wdcprobe",
568: chp->ch_channel, cl),
569: DEBUG_PROBE);
1.125 mycroft 570: ret_value &= ~0x01;
1.172.2.2 tron 571: }
1.157 fvdl 572: bus_space_write_1(chp->cmd_iot,
573: chp->cmd_iohs[wd_sector], 0, 0x02);
1.172.2.2 tron 574: cl = bus_space_read_1(chp->cmd_iot,
575: chp->cmd_iohs[wd_sector], 0);
576: if (cl != 0x02) {
577: WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: "
578: "got 0x%x != 0x02\n",
579: wdc != NULL ?
580: wdc->sc_dev.dv_xname : "wdcprobe",
581: chp->ch_channel, cl),
582: DEBUG_PROBE);
1.125 mycroft 583: ret_value &= ~0x01;
1.172.2.2 tron 584: }
585: cl = bus_space_read_1(chp->cmd_iot,
586: chp->cmd_iohs[wd_cyl_lo], 0);
587: if (cl != 0x01) {
588: WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): "
589: "got 0x%x != 0x01\n",
590: wdc != NULL ?
591: wdc->sc_dev.dv_xname : "wdcprobe",
592: chp->ch_channel, cl),
593: DEBUG_PROBE);
1.131 mycroft 594: ret_value &= ~0x01;
1.172.2.2 tron 595: }
1.125 mycroft 596: }
597: /* Register writability test, drive 1. */
598: if (ret_value & 0x02) {
1.169 thorpej 599: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
600: wdc->select(chp,1);
1.157 fvdl 601: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
602: 0, WDSD_IBM | 0x10);
1.167 thorpej 603: bus_space_write_1(chp->cmd_iot,
604: chp->cmd_iohs[wd_cyl_lo], 0, 0x02);
1.172.2.2 tron 605: cl = bus_space_read_1(chp->cmd_iot,
606: chp->cmd_iohs[wd_cyl_lo], 0);
607: if (cl != 0x02) {
608: WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: "
609: "got 0x%x != 0x02\n",
610: wdc != NULL ?
611: wdc->sc_dev.dv_xname : "wdcprobe",
612: chp->ch_channel, cl),
613: DEBUG_PROBE);
1.125 mycroft 614: ret_value &= ~0x02;
1.172.2.2 tron 615: }
1.157 fvdl 616: bus_space_write_1(chp->cmd_iot,
617: chp->cmd_iohs[wd_cyl_lo], 0, 0x01);
1.172.2.2 tron 618: cl = bus_space_read_1(chp->cmd_iot,
619: chp->cmd_iohs[wd_cyl_lo], 0);
620: if (cl != 0x01) {
621: WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: "
622: "got 0x%x != 0x01\n",
623: wdc != NULL ?
624: wdc->sc_dev.dv_xname : "wdcprobe",
625: chp->ch_channel, cl),
626: DEBUG_PROBE);
1.125 mycroft 627: ret_value &= ~0x02;
1.172.2.2 tron 628: }
1.157 fvdl 629: bus_space_write_1(chp->cmd_iot,
630: chp->cmd_iohs[wd_sector], 0, 0x01);
1.172.2.2 tron 631: cl = bus_space_read_1(chp->cmd_iot,
632: chp->cmd_iohs[wd_sector], 0);
633: if (cl != 0x01) {
634: WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: "
635: "got 0x%x != 0x01\n",
636: wdc != NULL ?
637: wdc->sc_dev.dv_xname : "wdcprobe",
638: chp->ch_channel, cl),
639: DEBUG_PROBE);
1.125 mycroft 640: ret_value &= ~0x02;
1.172.2.2 tron 641: }
1.167 thorpej 642: bus_space_write_1(chp->cmd_iot,
643: chp->cmd_iohs[wd_sector], 0, 0x02);
1.172.2.2 tron 644: cl = bus_space_read_1(chp->cmd_iot,
645: chp->cmd_iohs[wd_sector], 0);
646: if (cl != 0x02) {
647: WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: "
648: "got 0x%x != 0x02\n",
649: wdc != NULL ?
650: wdc->sc_dev.dv_xname : "wdcprobe",
651: chp->ch_channel, cl),
652: DEBUG_PROBE);
1.125 mycroft 653: ret_value &= ~0x02;
1.172.2.2 tron 654: }
655: cl = bus_space_read_1(chp->cmd_iot,
656: chp->cmd_iohs[wd_cyl_lo], 0);
657: if (cl != 0x01) {
658: WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): "
659: "got 0x%x != 0x01\n",
660: wdc != NULL ?
661: wdc->sc_dev.dv_xname : "wdcprobe",
662: chp->ch_channel, cl),
663: DEBUG_PROBE);
1.131 mycroft 664: ret_value &= ~0x02;
1.172.2.2 tron 665: }
1.125 mycroft 666: }
1.137 bouyer 667:
1.172.2.2 tron 668: if (ret_value == 0) {
669: splx(s);
1.137 bouyer 670: return 0;
1.172.2.2 tron 671: }
1.62 bouyer 672: }
1.31 bouyer 673:
1.172.2.2 tron 674:
1.172.2.4 he 675: #if 0 /* XXX this break some ATA or ATAPI devices */
1.172.2.2 tron 676: /*
677: * reset bus. Also send an ATAPI_RESET to devices, in case there are
678: * ATAPI device out there which don't react to the bus reset
679: */
680: if (ret_value & 0x01) {
681: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
682: wdc->select(chp,0);
683: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
684: 0, WDSD_IBM);
685: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0,
686: ATAPI_SOFT_RESET);
687: }
688: if (ret_value & 0x02) {
689: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
690: wdc->select(chp,0);
691: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
692: 0, WDSD_IBM | 0x10);
693: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0,
694: ATAPI_SOFT_RESET);
695: }
1.156 bouyer 696:
1.172.2.3 tron 697: delay(5000);
1.172.2.4 he 698: #endif
1.172.2.3 tron 699:
1.169 thorpej 700: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT))
701: wdc->select(chp,0);
1.157 fvdl 702: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM);
1.137 bouyer 703: delay(10); /* 400ns delay */
1.172.2.2 tron 704: /* assert SRST, wait for reset to complete */
1.137 bouyer 705: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
706: WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
1.172 bouyer 707: DELAY(1000);
708: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
709: WDCTL_IDS | WDCTL_4BIT);
1.137 bouyer 710: DELAY(2000);
1.157 fvdl 711: (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0);
1.137 bouyer 712: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
713: delay(10); /* 400ns delay */
1.156 bouyer 714: /* ACK interrupt in case there is one pending left (Promise ATA100) */
1.169 thorpej 715: if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK))
716: wdc->irqack(chp);
1.156 bouyer 717: splx(s);
1.137 bouyer 718:
719: ret_value = __wdcwait_reset(chp, ret_value, poll);
720: WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n",
1.169 thorpej 721: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel,
1.137 bouyer 722: ret_value), DEBUG_PROBE);
1.12 cgd 723:
1.137 bouyer 724: /* if reset failed, there's nothing here */
725: if (ret_value == 0)
726: return 0;
1.67 bouyer 727:
1.12 cgd 728: /*
1.167 thorpej 729: * Test presence of drives. First test register signatures looking
730: * for ATAPI devices. If it's not an ATAPI and reset said there may
731: * be something here assume it's ATA or OLD. Ghost will be killed
732: * later in attach routine.
1.12 cgd 733: */
1.137 bouyer 734: for (drive = 0; drive < 2; drive++) {
735: if ((ret_value & (0x01 << drive)) == 0)
736: continue;
1.169 thorpej 737: if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT)
738: wdc->select(chp,drive);
1.157 fvdl 739: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.137 bouyer 740: WDSD_IBM | (drive << 4));
741: delay(10); /* 400ns delay */
742: /* Save registers contents */
1.157 fvdl 743: sc = bus_space_read_1(chp->cmd_iot,
744: chp->cmd_iohs[wd_seccnt], 0);
745: sn = bus_space_read_1(chp->cmd_iot,
746: chp->cmd_iohs[wd_sector], 0);
747: cl = bus_space_read_1(chp->cmd_iot,
748: chp->cmd_iohs[wd_cyl_lo], 0);
749: ch = bus_space_read_1(chp->cmd_iot,
750: chp->cmd_iohs[wd_cyl_hi], 0);
1.137 bouyer 751:
752: WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x "
753: "cl=0x%x ch=0x%x\n",
1.169 thorpej 754: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
755: chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE);
1.31 bouyer 756: /*
1.137 bouyer 757: * sc & sn are supposted to be 0x1 for ATAPI but in some cases
758: * we get wrong values here, so ignore it.
1.31 bouyer 759: */
1.137 bouyer 760: if (cl == 0x14 && ch == 0xeb) {
761: chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI;
762: } else {
763: chp->ch_drive[drive].drive_flags |= DRIVE_ATA;
1.169 thorpej 764: if (wdc == NULL ||
765: (wdc->cap & WDC_CAPABILITY_PREATA) != 0)
1.137 bouyer 766: chp->ch_drive[drive].drive_flags |= DRIVE_OLD;
767: }
1.31 bouyer 768: }
1.137 bouyer 769: return (ret_value);
770: }
1.31 bouyer 771:
1.137 bouyer 772: void
1.168 thorpej 773: wdcattach(struct wdc_channel *chp)
1.137 bouyer 774: {
1.169 thorpej 775: struct wdc_softc *wdc = chp->ch_wdc;
1.137 bouyer 776: static int inited = 0;
1.32 bouyer 777:
1.137 bouyer 778: if (chp->ch_flags & WDCF_DISABLED)
779: return;
1.74 enami 780:
1.137 bouyer 781: /* initialise global data */
782: callout_init(&chp->ch_callout);
1.169 thorpej 783: if (wdc->drv_probe == NULL)
784: wdc->drv_probe = wdc_drvprobe;
1.137 bouyer 785: if (inited == 0) {
1.165 thorpej 786: /* Initialize the ata_xfer pool. */
787: pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0,
1.137 bouyer 788: 0, 0, "wdcspl", NULL);
789: inited++;
1.133 bouyer 790: }
1.165 thorpej 791: TAILQ_INIT(&chp->ch_queue->queue_xfer);
1.148 bouyer 792: chp->ch_queue->queue_freeze = 0;
1.126 enami 793:
1.169 thorpej 794: chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint);
1.74 enami 795: }
796:
1.163 thorpej 797: int
798: wdcactivate(struct device *self, enum devact act)
1.137 bouyer 799: {
800: struct wdc_softc *wdc = (struct wdc_softc *)self;
801: int s, i, error = 0;
802:
803: s = splbio();
804: switch (act) {
805: case DVACT_ACTIVATE:
806: error = EOPNOTSUPP;
807: break;
808:
809: case DVACT_DEACTIVATE:
810: for (i = 0; i < wdc->nchannels; i++) {
811: error = config_deactivate(wdc->channels[i]->atabus);
812: if (error)
813: break;
814: }
815: break;
816: }
817: splx(s);
818: return (error);
819: }
820:
821: int
1.163 thorpej 822: wdcdetach(struct device *self, int flags)
1.137 bouyer 823: {
824: struct wdc_softc *wdc = (struct wdc_softc *)self;
1.168 thorpej 825: struct wdc_channel *chp;
1.137 bouyer 826: int i, error = 0;
827:
828: for (i = 0; i < wdc->nchannels; i++) {
829: chp = wdc->channels[i];
830: WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n",
831: wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH);
832: error = config_detach(chp->atabus, flags);
833: if (error)
834: break;
835: }
836: return (error);
837: }
838:
1.31 bouyer 839: /*
840: * Start I/O on a controller, for the given channel.
841: * The first xfer may be not for our channel if the channel queues
842: * are shared.
843: */
844: void
1.168 thorpej 845: wdcstart(struct wdc_channel *chp)
1.31 bouyer 846: {
1.169 thorpej 847: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 848: struct ata_xfer *xfer;
1.38 bouyer 849:
850: #ifdef WDC_DIAGNOSTIC
851: int spl1, spl2;
852:
853: spl1 = splbio();
854: spl2 = splbio();
855: if (spl2 != spl1) {
856: printf("wdcstart: not at splbio()\n");
857: panic("wdcstart");
858: }
859: splx(spl2);
860: splx(spl1);
861: #endif /* WDC_DIAGNOSTIC */
1.12 cgd 862:
1.31 bouyer 863: /* is there a xfer ? */
1.165 thorpej 864: if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL)
1.31 bouyer 865: return;
1.47 bouyer 866:
867: /* adjust chp, in case we have a shared queue */
1.165 thorpej 868: chp = xfer->c_chp;
1.47 bouyer 869:
1.31 bouyer 870: if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) {
871: return; /* channel aleady active */
872: }
1.148 bouyer 873: if (__predict_false(chp->ch_queue->queue_freeze > 0)) {
1.147 bouyer 874: return; /* queue froozen */
1.137 bouyer 875: }
1.31 bouyer 876: #ifdef DIAGNOSTIC
877: if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0)
1.118 provos 878: panic("wdcstart: channel waiting for irq");
1.31 bouyer 879: #endif
1.169 thorpej 880: if (wdc->cap & WDC_CAPABILITY_HWLOCK)
881: if (!(*wdc->claim_hw)(chp, 0))
1.31 bouyer 882: return;
1.12 cgd 883:
1.31 bouyer 884: WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer,
1.169 thorpej 885: chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
1.31 bouyer 886: chp->ch_flags |= WDCF_ACTIVE;
1.165 thorpej 887: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) {
888: chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET;
889: chp->ch_drive[xfer->c_drive].state = 0;
1.37 bouyer 890: }
1.169 thorpej 891: if (wdc->cap & WDC_CAPABILITY_NOIRQ)
1.98 bjh21 892: KASSERT(xfer->c_flags & C_POLL);
1.31 bouyer 893: xfer->c_start(chp, xfer);
894: }
1.2 bouyer 895:
1.31 bouyer 896: /* restart an interrupted I/O */
897: void
1.163 thorpej 898: wdcrestart(void *v)
1.31 bouyer 899: {
1.168 thorpej 900: struct wdc_channel *chp = v;
1.31 bouyer 901: int s;
1.2 bouyer 902:
1.31 bouyer 903: s = splbio();
1.45 drochner 904: wdcstart(chp);
1.31 bouyer 905: splx(s);
1.2 bouyer 906: }
1.31 bouyer 907:
1.2 bouyer 908:
1.31 bouyer 909: /*
910: * Interrupt routine for the controller. Acknowledge the interrupt, check for
911: * errors on the current operation, mark it done if necessary, and start the
912: * next request. Also check for a partially done transfer, and continue with
913: * the next chunk if so.
914: */
1.12 cgd 915: int
1.163 thorpej 916: wdcintr(void *arg)
1.12 cgd 917: {
1.168 thorpej 918: struct wdc_channel *chp = arg;
1.169 thorpej 919: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 920: struct ata_xfer *xfer;
1.76 bouyer 921: int ret;
1.12 cgd 922:
1.169 thorpej 923: if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) {
1.80 enami 924: WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"),
925: DEBUG_INTR);
926: return (0);
927: }
1.31 bouyer 928: if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) {
929: WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR);
1.113 bouyer 930: /* try to clear the pending interrupt anyway */
1.157 fvdl 931: (void)bus_space_read_1(chp->cmd_iot,
932: chp->cmd_iohs[wd_status], 0);
1.80 enami 933: return (0);
1.31 bouyer 934: }
1.12 cgd 935:
1.31 bouyer 936: WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR);
1.165 thorpej 937: xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.84 bouyer 938: if (chp->ch_flags & WDCF_DMA_WAIT) {
1.169 thorpej 939: wdc->dma_status =
940: (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel,
1.165 thorpej 941: xfer->c_drive, 0);
1.169 thorpej 942: if (wdc->dma_status & WDC_DMAST_NOIRQ) {
1.84 bouyer 943: /* IRQ not for us, not detected by DMA engine */
944: return 0;
945: }
946: chp->ch_flags &= ~WDCF_DMA_WAIT;
947: }
1.31 bouyer 948: chp->ch_flags &= ~WDCF_IRQ_WAIT;
1.76 bouyer 949: ret = xfer->c_intr(chp, xfer, 1);
950: if (ret == 0) /* irq was not for us, still waiting for irq */
951: chp->ch_flags |= WDCF_IRQ_WAIT;
952: return (ret);
1.12 cgd 953: }
954:
1.31 bouyer 955: /* Put all disk in RESET state */
1.125 mycroft 956: void
1.163 thorpej 957: wdc_reset_channel(struct ata_drive_datas *drvp, int flags)
1.2 bouyer 958: {
1.168 thorpej 959: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 960: struct wdc_softc *wdc = chp->ch_wdc;
1.34 bouyer 961: WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n",
1.169 thorpej 962: wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive),
1.34 bouyer 963: DEBUG_FUNCS);
1.172.2.5 jmc 964:
965:
966: __wdc_reset_channel(chp, flags);
967: }
968:
969: static void
970: __wdc_reset_channel(struct wdc_channel *chp, int flags)
971: {
972: struct ata_xfer *xfer;
973: int drive;
974:
975: /*
976: * look for pending xfers. If we have a shared queue, we'll also reset
977: * the other channel if the current xfer is running on it.
978: * Then we'll freese the queue, and dequeue only the xfers for this
979: * channel. xfer->c_kill_xfer() will reset any ATAPI device when
980: * needed.
981: */
982: chp->ch_queue->queue_freeze++;
983: if ((flags & AT_RST_NOCMD) == 0) {
984: xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
985: if (xfer && xfer->c_chp != chp)
986: __wdc_reset_channel(xfer->c_chp, flags);
987: for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
988: xfer != 0; ) {
989: if (xfer->c_chp != chp)
990: continue;
991: if ((flags & AT_RST_EMERG) == 0)
992: xfer->c_kill_xfer(chp, xfer, KILL_RESET);
993: }
994: }
1.147 bouyer 995: if ((flags & AT_POLL) == 0) {
1.153 bouyer 996: if (chp->ch_flags & WDCF_TH_RESET) {
997: /* no need to schedule a reset more than one time */
1.172.2.6! he 998: chp->ch_queue->queue_freeze--;
1.153 bouyer 999: return;
1000: }
1.137 bouyer 1001: chp->ch_flags |= WDCF_TH_RESET;
1.170 thorpej 1002: wakeup(&chp->ch_thread);
1.137 bouyer 1003: return;
1004: }
1.147 bouyer 1005: (void) wdcreset(chp, RESET_POLL);
1.31 bouyer 1006: for (drive = 0; drive < 2; drive++) {
1007: chp->ch_drive[drive].state = 0;
1.12 cgd 1008: }
1.172.2.5 jmc 1009: if ((flags & AT_RST_EMERG) == 0) {
1010: chp->ch_queue->queue_freeze--;
1011: wdcstart(chp);
1012: } else {
1013: /* make sure that we can use polled commands */
1014: TAILQ_INIT(&chp->ch_queue->queue_xfer);
1015: chp->ch_queue->queue_freeze = 0;
1016: }
1.31 bouyer 1017: }
1.12 cgd 1018:
1.31 bouyer 1019: int
1.168 thorpej 1020: wdcreset(struct wdc_channel *chp, int poll)
1.31 bouyer 1021: {
1.169 thorpej 1022: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 1023: int drv_mask1, drv_mask2;
1.156 bouyer 1024: int s = 0;
1.2 bouyer 1025:
1.169 thorpej 1026: if (wdc->cap & WDC_CAPABILITY_SELECT)
1027: wdc->select(chp,0);
1.156 bouyer 1028: if (poll != RESET_SLEEP)
1029: s = splbio();
1.157 fvdl 1030: /* master */
1031: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM);
1.131 mycroft 1032: delay(10); /* 400ns delay */
1.31 bouyer 1033: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
1.131 mycroft 1034: WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
1035: delay(2000);
1.157 fvdl 1036: (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0);
1.137 bouyer 1037: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
1038: WDCTL_4BIT | WDCTL_IDS);
1.131 mycroft 1039: delay(10); /* 400ns delay */
1.156 bouyer 1040: if (poll != RESET_SLEEP) {
1.169 thorpej 1041: if (wdc->cap & WDC_CAPABILITY_IRQACK)
1042: wdc->irqack(chp);
1.156 bouyer 1043: splx(s);
1044: }
1.2 bouyer 1045:
1.31 bouyer 1046: drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00;
1047: drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00;
1.137 bouyer 1048: drv_mask2 = __wdcwait_reset(chp, drv_mask1,
1049: (poll == RESET_SLEEP) ? 0 : 1);
1050: if (drv_mask2 != drv_mask1) {
1.31 bouyer 1051: printf("%s channel %d: reset failed for",
1.169 thorpej 1052: wdc->sc_dev.dv_xname, chp->ch_channel);
1.31 bouyer 1053: if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0)
1054: printf(" drive 0");
1055: if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0)
1056: printf(" drive 1");
1057: printf("\n");
1058: }
1.137 bouyer 1059: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
1.31 bouyer 1060: return (drv_mask1 != drv_mask2) ? 1 : 0;
1061: }
1062:
1063: static int
1.168 thorpej 1064: __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll)
1.31 bouyer 1065: {
1.169 thorpej 1066: struct wdc_softc *wdc = chp->ch_wdc;
1.137 bouyer 1067: int timeout, nloop;
1.149 bouyer 1068: u_int8_t st0 = 0, st1 = 0;
1.70 bouyer 1069: #ifdef WDCDEBUG
1.146 christos 1070: u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0;
1071: u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0;
1.70 bouyer 1072: #endif
1.137 bouyer 1073:
1074: if (poll)
1075: nloop = WDCNDELAY_RST;
1076: else
1077: nloop = WDC_RESET_WAIT * hz / 1000;
1.31 bouyer 1078: /* wait for BSY to deassert */
1.137 bouyer 1079: for (timeout = 0; timeout < nloop; timeout++) {
1.172.2.2 tron 1080: if ((drv_mask & 0x01) != 0) {
1081: if (wdc && wdc->cap & WDC_CAPABILITY_SELECT)
1082: wdc->select(chp,0);
1083: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
1084: 0, WDSD_IBM); /* master */
1085: delay(10);
1086: st0 = bus_space_read_1(chp->cmd_iot,
1087: chp->cmd_iohs[wd_status], 0);
1.70 bouyer 1088: #ifdef WDCDEBUG
1.172.2.2 tron 1089: sc0 = bus_space_read_1(chp->cmd_iot,
1090: chp->cmd_iohs[wd_seccnt], 0);
1091: sn0 = bus_space_read_1(chp->cmd_iot,
1092: chp->cmd_iohs[wd_sector], 0);
1093: cl0 = bus_space_read_1(chp->cmd_iot,
1094: chp->cmd_iohs[wd_cyl_lo], 0);
1095: ch0 = bus_space_read_1(chp->cmd_iot,
1096: chp->cmd_iohs[wd_cyl_hi], 0);
1.70 bouyer 1097: #endif
1.172.2.2 tron 1098: }
1099: if ((drv_mask & 0x02) != 0) {
1100: if (wdc && wdc->cap & WDC_CAPABILITY_SELECT)
1101: wdc->select(chp,1);
1102: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh],
1103: 0, WDSD_IBM | 0x10); /* slave */
1104: delay(10);
1105: st1 = bus_space_read_1(chp->cmd_iot,
1106: chp->cmd_iohs[wd_status], 0);
1.70 bouyer 1107: #ifdef WDCDEBUG
1.172.2.2 tron 1108: sc1 = bus_space_read_1(chp->cmd_iot,
1109: chp->cmd_iohs[wd_seccnt], 0);
1110: sn1 = bus_space_read_1(chp->cmd_iot,
1111: chp->cmd_iohs[wd_sector], 0);
1112: cl1 = bus_space_read_1(chp->cmd_iot,
1113: chp->cmd_iohs[wd_cyl_lo], 0);
1114: ch1 = bus_space_read_1(chp->cmd_iot,
1115: chp->cmd_iohs[wd_cyl_hi], 0);
1.70 bouyer 1116: #endif
1.172.2.2 tron 1117: }
1.31 bouyer 1118:
1119: if ((drv_mask & 0x01) == 0) {
1120: /* no master */
1121: if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) {
1122: /* No master, slave is ready, it's done */
1.65 bouyer 1123: goto end;
1.31 bouyer 1124: }
1125: } else if ((drv_mask & 0x02) == 0) {
1126: /* no slave */
1127: if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) {
1128: /* No slave, master is ready, it's done */
1.65 bouyer 1129: goto end;
1.31 bouyer 1130: }
1.2 bouyer 1131: } else {
1.31 bouyer 1132: /* Wait for both master and slave to be ready */
1133: if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) {
1.65 bouyer 1134: goto end;
1.2 bouyer 1135: }
1136: }
1.137 bouyer 1137: if (poll)
1138: delay(WDCDELAY);
1139: else
1140: tsleep(&nloop, PRIBIO, "atarst", 1);
1.2 bouyer 1141: }
1.116 wiz 1142: /* Reset timed out. Maybe it's because drv_mask was not right */
1.31 bouyer 1143: if (st0 & WDCS_BSY)
1144: drv_mask &= ~0x01;
1145: if (st1 & WDCS_BSY)
1146: drv_mask &= ~0x02;
1.65 bouyer 1147: end:
1.70 bouyer 1148: WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x "
1149: "cl=0x%x ch=0x%x\n",
1.169 thorpej 1150: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
1151: chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE);
1.70 bouyer 1152: WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x "
1153: "cl=0x%x ch=0x%x\n",
1.169 thorpej 1154: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe",
1155: chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE);
1.70 bouyer 1156:
1.149 bouyer 1157: WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n",
1.169 thorpej 1158: wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel,
1.149 bouyer 1159: st0, st1), DEBUG_PROBE);
1.65 bouyer 1160:
1.31 bouyer 1161: return drv_mask;
1.2 bouyer 1162: }
1163:
1164: /*
1.31 bouyer 1165: * Wait for a drive to be !BSY, and have mask in its status register.
1166: * return -1 for a timeout after "timeout" ms.
1.2 bouyer 1167: */
1.167 thorpej 1168: static int
1.168 thorpej 1169: __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout)
1.2 bouyer 1170: {
1.169 thorpej 1171: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 1172: u_char status;
1173: int time = 0;
1.60 abs 1174:
1.169 thorpej 1175: WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ?
1176: wdc->sc_dev.dv_xname : "none",
1177: chp->ch_channel), DEBUG_STATUS);
1.31 bouyer 1178: chp->ch_error = 0;
1179:
1180: timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */
1.2 bouyer 1181:
1.31 bouyer 1182: for (;;) {
1183: chp->ch_status = status =
1.157 fvdl 1184: bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0);
1.131 mycroft 1185: if ((status & (WDCS_BSY | mask)) == bits)
1.31 bouyer 1186: break;
1187: if (++time > timeout) {
1.137 bouyer 1188: WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), "
1.87 bouyer 1189: "status %x error %x (mask 0x%x bits 0x%x)\n",
1190: time, status,
1.157 fvdl 1191: bus_space_read_1(chp->cmd_iot,
1192: chp->cmd_iohs[wd_error], 0), mask, bits),
1.87 bouyer 1193: DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY);
1.137 bouyer 1194: return(WDCWAIT_TOUT);
1.31 bouyer 1195: }
1196: delay(WDCDELAY);
1.2 bouyer 1197: }
1.87 bouyer 1198: #ifdef WDCDEBUG
1199: if (time > 0 && (wdcdebug_mask & DEBUG_DELAY))
1.137 bouyer 1200: printf("__wdcwait: did busy-wait, time=%d\n", time);
1.87 bouyer 1201: #endif
1.31 bouyer 1202: if (status & WDCS_ERR)
1.157 fvdl 1203: chp->ch_error = bus_space_read_1(chp->cmd_iot,
1204: chp->cmd_iohs[wd_error], 0);
1.31 bouyer 1205: #ifdef WDCNDELAY_DEBUG
1206: /* After autoconfig, there should be no long delays. */
1207: if (!cold && time > WDCNDELAY_DEBUG) {
1.165 thorpej 1208: struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.31 bouyer 1209: if (xfer == NULL)
1210: printf("%s channel %d: warning: busy-wait took %dus\n",
1.169 thorpej 1211: wdc->sc_dev.dv_xname, chp->ch_channel,
1.31 bouyer 1212: WDCDELAY * time);
1213: else
1214: printf("%s:%d:%d: warning: busy-wait took %dus\n",
1.169 thorpej 1215: wdc->sc_dev.dv_xname, chp->ch_channel,
1.31 bouyer 1216: xfer->drive,
1217: WDCDELAY * time);
1.2 bouyer 1218: }
1219: #endif
1.137 bouyer 1220: return(WDCWAIT_OK);
1221: }
1222:
1223: /*
1224: * Call __wdcwait(), polling using tsleep() or waking up the kernel
1225: * thread if possible
1226: */
1227: int
1.168 thorpej 1228: wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags)
1.137 bouyer 1229: {
1230: int error, i, timeout_hz = mstohz(timeout);
1231:
1232: if (timeout_hz == 0 ||
1233: (flags & (AT_WAIT | AT_POLL)) == AT_POLL)
1234: error = __wdcwait(chp, mask, bits, timeout);
1235: else {
1236: error = __wdcwait(chp, mask, bits, WDCDELAY_POLL);
1237: if (error != 0) {
1.147 bouyer 1238: if ((chp->ch_flags & WDCF_TH_RUN) ||
1239: (flags & AT_WAIT)) {
1.137 bouyer 1240: /*
1.147 bouyer 1241: * we're running in the channel thread
1242: * or some userland thread context
1.137 bouyer 1243: */
1244: for (i = 0; i < timeout_hz; i++) {
1245: if (__wdcwait(chp, mask, bits,
1246: WDCDELAY_POLL) == 0) {
1247: error = 0;
1248: break;
1249: }
1250: tsleep(&chp, PRIBIO, "atapoll", 1);
1251: }
1252: } else {
1253: /*
1254: * we're probably in interrupt context,
1255: * ask the thread to come back here
1256: */
1.147 bouyer 1257: #ifdef DIAGNOSTIC
1.148 bouyer 1258: if (chp->ch_queue->queue_freeze > 0)
1259: panic("wdcwait: queue_freeze");
1.147 bouyer 1260: #endif
1.148 bouyer 1261: chp->ch_queue->queue_freeze++;
1.170 thorpej 1262: wakeup(&chp->ch_thread);
1.137 bouyer 1263: return(WDCWAIT_THR);
1264: }
1265: }
1266: }
1.163 thorpej 1267: return (error);
1.2 bouyer 1268: }
1269:
1.137 bouyer 1270:
1.84 bouyer 1271: /*
1272: * Busy-wait for DMA to complete
1273: */
1274: int
1.168 thorpej 1275: wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout)
1.84 bouyer 1276: {
1.169 thorpej 1277: struct wdc_softc *wdc = chp->ch_wdc;
1.84 bouyer 1278: int time;
1.169 thorpej 1279:
1.84 bouyer 1280: for (time = 0; time < timeout * 1000 / WDCDELAY; time++) {
1.169 thorpej 1281: wdc->dma_status =
1282: (*wdc->dma_finish)(wdc->dma_arg,
1283: chp->ch_channel, xfer->c_drive, 0);
1284: if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0)
1.84 bouyer 1285: return 0;
1286: delay(WDCDELAY);
1287: }
1288: /* timeout, force a DMA halt */
1.169 thorpej 1289: wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg,
1290: chp->ch_channel, xfer->c_drive, 1);
1.84 bouyer 1291: return 1;
1292: }
1293:
1.31 bouyer 1294: void
1.163 thorpej 1295: wdctimeout(void *arg)
1.2 bouyer 1296: {
1.168 thorpej 1297: struct wdc_channel *chp = (struct wdc_channel *)arg;
1.169 thorpej 1298: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1299: struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.31 bouyer 1300: int s;
1.2 bouyer 1301:
1.31 bouyer 1302: WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS);
1303:
1304: s = splbio();
1305: if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) {
1306: __wdcerror(chp, "lost interrupt");
1.88 mrg 1307: printf("\ttype: %s tc_bcount: %d tc_skip: %d\n",
1308: (xfer->c_flags & C_ATAPI) ? "atapi" : "ata",
1309: xfer->c_bcount,
1310: xfer->c_skip);
1.84 bouyer 1311: if (chp->ch_flags & WDCF_DMA_WAIT) {
1.169 thorpej 1312: wdc->dma_status =
1313: (*wdc->dma_finish)(wdc->dma_arg,
1314: chp->ch_channel, xfer->c_drive, 1);
1.84 bouyer 1315: chp->ch_flags &= ~WDCF_DMA_WAIT;
1316: }
1.31 bouyer 1317: /*
1.119 drochner 1318: * Call the interrupt routine. If we just missed an interrupt,
1.31 bouyer 1319: * it will do what's needed. Else, it will take the needed
1320: * action (reset the device).
1.70 bouyer 1321: * Before that we need to reinstall the timeout callback,
1322: * in case it will miss another irq while in this transfer
1323: * We arbitray chose it to be 1s
1.31 bouyer 1324: */
1.81 thorpej 1325: callout_reset(&chp->ch_callout, hz, wdctimeout, chp);
1.31 bouyer 1326: xfer->c_flags |= C_TIMEOU;
1327: chp->ch_flags &= ~WDCF_IRQ_WAIT;
1.66 bouyer 1328: xfer->c_intr(chp, xfer, 1);
1.31 bouyer 1329: } else
1330: __wdcerror(chp, "missing untimeout");
1331: splx(s);
1.2 bouyer 1332: }
1333:
1.31 bouyer 1334: /*
1.152 wiz 1335: * Probe drive's capabilities, for use by the controller later
1.31 bouyer 1336: * Assumes drvp points to an existing drive.
1337: * XXX this should be a controller-indep function
1338: */
1.2 bouyer 1339: void
1.163 thorpej 1340: wdc_probe_caps(struct ata_drive_datas *drvp)
1.2 bouyer 1341: {
1.31 bouyer 1342: struct ataparams params, params2;
1.168 thorpej 1343: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 1344: struct wdc_softc *wdc = chp->ch_wdc;
1.31 bouyer 1345: struct device *drv_dev = drvp->drv_softc;
1346: int i, printed;
1347: char *sep = "";
1.48 bouyer 1348: int cf_flags;
1.31 bouyer 1349:
1.125 mycroft 1350: if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) {
1.31 bouyer 1351: /* IDENTIFY failed. Can't tell more about the device */
1.2 bouyer 1352: return;
1353: }
1.31 bouyer 1354: if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
1355: (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) {
1.2 bouyer 1356: /*
1.39 bouyer 1357: * Controller claims 16 and 32 bit transfers.
1358: * Re-do an IDENTIFY with 32-bit transfers,
1.31 bouyer 1359: * and compare results.
1.2 bouyer 1360: */
1.31 bouyer 1361: drvp->drive_flags |= DRIVE_CAP32;
1.125 mycroft 1362: ata_get_params(drvp, AT_WAIT, ¶ms2);
1.31 bouyer 1363: if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) {
1364: /* Not good. fall back to 16bits */
1365: drvp->drive_flags &= ~DRIVE_CAP32;
1366: } else {
1.125 mycroft 1367: aprint_normal("%s: 32-bit data port\n",
1.123 thorpej 1368: drv_dev->dv_xname);
1.2 bouyer 1369: }
1370: }
1.55 bouyer 1371: #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */
1372: if (params.atap_ata_major > 0x01 &&
1373: params.atap_ata_major != 0xffff) {
1374: for (i = 14; i > 0; i--) {
1375: if (params.atap_ata_major & (1 << i)) {
1.125 mycroft 1376: aprint_normal("%s: ATA version %d\n",
1377: drv_dev->dv_xname, i);
1.55 bouyer 1378: drvp->ata_vers = i;
1379: break;
1380: }
1381: }
1.125 mycroft 1382: }
1.55 bouyer 1383: #endif
1.2 bouyer 1384:
1.31 bouyer 1385: /* An ATAPI device is at last PIO mode 3 */
1386: if (drvp->drive_flags & DRIVE_ATAPI)
1387: drvp->PIO_mode = 3;
1.2 bouyer 1388:
1389: /*
1.31 bouyer 1390: * It's not in the specs, but it seems that some drive
1391: * returns 0xffff in atap_extensions when this field is invalid
1.2 bouyer 1392: */
1.31 bouyer 1393: if (params.atap_extensions != 0xffff &&
1394: (params.atap_extensions & WDC_EXT_MODES)) {
1395: printed = 0;
1396: /*
1397: * XXX some drives report something wrong here (they claim to
1398: * support PIO mode 8 !). As mode is coded on 3 bits in
1399: * SET FEATURE, limit it to 7 (so limit i to 4).
1.116 wiz 1400: * If higher mode than 7 is found, abort.
1.31 bouyer 1401: */
1.39 bouyer 1402: for (i = 7; i >= 0; i--) {
1.31 bouyer 1403: if ((params.atap_piomode_supp & (1 << i)) == 0)
1404: continue;
1.39 bouyer 1405: if (i > 4)
1406: return;
1.31 bouyer 1407: /*
1408: * See if mode is accepted.
1409: * If the controller can't set its PIO mode,
1410: * assume the defaults are good, so don't try
1411: * to set it
1412: */
1413: if ((wdc->cap & WDC_CAPABILITY_MODE) != 0)
1.137 bouyer 1414: /*
1415: * It's OK to pool here, it's fast enouth
1416: * to not bother waiting for interrupt
1417: */
1.31 bouyer 1418: if (ata_set_mode(drvp, 0x08 | (i + 3),
1.125 mycroft 1419: AT_WAIT) != CMD_OK)
1.2 bouyer 1420: continue;
1.31 bouyer 1421: if (!printed) {
1.123 thorpej 1422: aprint_normal("%s: drive supports PIO mode %d",
1.39 bouyer 1423: drv_dev->dv_xname, i + 3);
1.31 bouyer 1424: sep = ",";
1425: printed = 1;
1426: }
1427: /*
1428: * If controller's driver can't set its PIO mode,
1429: * get the highter one for the drive.
1430: */
1431: if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 ||
1.52 bouyer 1432: wdc->PIO_cap >= i + 3) {
1.31 bouyer 1433: drvp->PIO_mode = i + 3;
1.48 bouyer 1434: drvp->PIO_cap = i + 3;
1.2 bouyer 1435: break;
1436: }
1437: }
1.31 bouyer 1438: if (!printed) {
1439: /*
1440: * We didn't find a valid PIO mode.
1441: * Assume the values returned for DMA are buggy too
1442: */
1443: return;
1.2 bouyer 1444: }
1.35 bouyer 1445: drvp->drive_flags |= DRIVE_MODE;
1.31 bouyer 1446: printed = 0;
1447: for (i = 7; i >= 0; i--) {
1448: if ((params.atap_dmamode_supp & (1 << i)) == 0)
1449: continue;
1450: if ((wdc->cap & WDC_CAPABILITY_DMA) &&
1451: (wdc->cap & WDC_CAPABILITY_MODE))
1.125 mycroft 1452: if (ata_set_mode(drvp, 0x20 | i, AT_WAIT)
1.31 bouyer 1453: != CMD_OK)
1454: continue;
1455: if (!printed) {
1.123 thorpej 1456: aprint_normal("%s DMA mode %d", sep, i);
1.31 bouyer 1457: sep = ",";
1458: printed = 1;
1459: }
1460: if (wdc->cap & WDC_CAPABILITY_DMA) {
1461: if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1.52 bouyer 1462: wdc->DMA_cap < i)
1.31 bouyer 1463: continue;
1464: drvp->DMA_mode = i;
1.48 bouyer 1465: drvp->DMA_cap = i;
1.31 bouyer 1466: drvp->drive_flags |= DRIVE_DMA;
1467: }
1.2 bouyer 1468: break;
1469: }
1.31 bouyer 1470: if (params.atap_extensions & WDC_EXT_UDMA_MODES) {
1.71 bouyer 1471: printed = 0;
1.31 bouyer 1472: for (i = 7; i >= 0; i--) {
1473: if ((params.atap_udmamode_supp & (1 << i))
1474: == 0)
1475: continue;
1476: if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1477: (wdc->cap & WDC_CAPABILITY_UDMA))
1478: if (ata_set_mode(drvp, 0x40 | i,
1.125 mycroft 1479: AT_WAIT) != CMD_OK)
1.31 bouyer 1480: continue;
1.71 bouyer 1481: if (!printed) {
1.123 thorpej 1482: aprint_normal("%s Ultra-DMA mode %d",
1483: sep, i);
1.93 wrstuden 1484: if (i == 2)
1.123 thorpej 1485: aprint_normal(" (Ultra/33)");
1.93 wrstuden 1486: else if (i == 4)
1.123 thorpej 1487: aprint_normal(" (Ultra/66)");
1.93 wrstuden 1488: else if (i == 5)
1.123 thorpej 1489: aprint_normal(" (Ultra/100)");
1.117 bouyer 1490: else if (i == 6)
1.123 thorpej 1491: aprint_normal(" (Ultra/133)");
1.71 bouyer 1492: sep = ",";
1493: printed = 1;
1494: }
1.31 bouyer 1495: if (wdc->cap & WDC_CAPABILITY_UDMA) {
1.50 bouyer 1496: if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1.52 bouyer 1497: wdc->UDMA_cap < i)
1.50 bouyer 1498: continue;
1.31 bouyer 1499: drvp->UDMA_mode = i;
1.48 bouyer 1500: drvp->UDMA_cap = i;
1.31 bouyer 1501: drvp->drive_flags |= DRIVE_UDMA;
1502: }
1503: break;
1504: }
1505: }
1.123 thorpej 1506: aprint_normal("\n");
1.55 bouyer 1507: }
1508:
1509: /* Try to guess ATA version here, if it didn't get reported */
1510: if (drvp->ata_vers == 0) {
1511: if (drvp->drive_flags & DRIVE_UDMA)
1512: drvp->ata_vers = 4; /* should be at last ATA-4 */
1513: else if (drvp->PIO_cap > 2)
1514: drvp->ata_vers = 2; /* should be at last ATA-2 */
1.48 bouyer 1515: }
1516: cf_flags = drv_dev->dv_cfdata->cf_flags;
1517: if (cf_flags & ATA_CONFIG_PIO_SET) {
1518: drvp->PIO_mode =
1519: (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF;
1520: drvp->drive_flags |= DRIVE_MODE;
1521: }
1522: if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) {
1523: /* don't care about DMA modes */
1524: return;
1525: }
1526: if (cf_flags & ATA_CONFIG_DMA_SET) {
1527: if ((cf_flags & ATA_CONFIG_DMA_MODES) ==
1528: ATA_CONFIG_DMA_DISABLE) {
1529: drvp->drive_flags &= ~DRIVE_DMA;
1530: } else {
1531: drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >>
1532: ATA_CONFIG_DMA_OFF;
1533: drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE;
1534: }
1.101 bouyer 1535: }
1536: if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) {
1537: /* don't care about UDMA modes */
1538: return;
1.48 bouyer 1539: }
1540: if (cf_flags & ATA_CONFIG_UDMA_SET) {
1541: if ((cf_flags & ATA_CONFIG_UDMA_MODES) ==
1542: ATA_CONFIG_UDMA_DISABLE) {
1543: drvp->drive_flags &= ~DRIVE_UDMA;
1544: } else {
1545: drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >>
1546: ATA_CONFIG_UDMA_OFF;
1547: drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE;
1548: }
1.2 bouyer 1549: }
1.54 bouyer 1550: }
1551:
1552: /*
1.56 bouyer 1553: * downgrade the transfer mode of a drive after an error. return 1 if
1.54 bouyer 1554: * downgrade was possible, 0 otherwise.
1555: */
1556: int
1.163 thorpej 1557: wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags)
1.54 bouyer 1558: {
1.168 thorpej 1559: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 1560: struct wdc_softc *wdc = chp->ch_wdc;
1.54 bouyer 1561: struct device *drv_dev = drvp->drv_softc;
1562: int cf_flags = drv_dev->dv_cfdata->cf_flags;
1563:
1564: /* if drive or controller don't know its mode, we can't do much */
1565: if ((drvp->drive_flags & DRIVE_MODE) == 0 ||
1566: (wdc->cap & WDC_CAPABILITY_MODE) == 0)
1567: return 0;
1568: /* current drive mode was set by a config flag, let it this way */
1569: if ((cf_flags & ATA_CONFIG_PIO_SET) ||
1570: (cf_flags & ATA_CONFIG_DMA_SET) ||
1571: (cf_flags & ATA_CONFIG_UDMA_SET))
1572: return 0;
1573:
1.61 bouyer 1574: /*
1.73 bouyer 1575: * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first.
1576: * Maybe we didn't properly notice the cable type
1.78 bouyer 1577: * If we were using Ultra-DMA mode 2, downgrade to mode 1 first.
1578: * It helps in some cases.
1.73 bouyer 1579: */
1.78 bouyer 1580: if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) {
1581: drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2;
1582: printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n",
1.73 bouyer 1583: drv_dev->dv_xname, drvp->UDMA_mode);
1584: }
1585:
1586: /*
1.61 bouyer 1587: * If we were using ultra-DMA, don't downgrade to multiword DMA
1588: * if we noticed a CRC error. It has been noticed that CRC errors
1589: * in ultra-DMA lead to silent data corruption in multiword DMA.
1590: * Data corruption is less likely to occur in PIO mode.
1591: */
1.73 bouyer 1592: else if ((drvp->drive_flags & DRIVE_UDMA) &&
1.61 bouyer 1593: (drvp->drive_flags & DRIVE_DMAERR) == 0) {
1.54 bouyer 1594: drvp->drive_flags &= ~DRIVE_UDMA;
1595: drvp->drive_flags |= DRIVE_DMA;
1596: drvp->DMA_mode = drvp->DMA_cap;
1.56 bouyer 1597: printf("%s: transfer error, downgrading to DMA mode %d\n",
1.54 bouyer 1598: drv_dev->dv_xname, drvp->DMA_mode);
1.61 bouyer 1599: } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
1600: drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
1.54 bouyer 1601: drvp->PIO_mode = drvp->PIO_cap;
1.56 bouyer 1602: printf("%s: transfer error, downgrading to PIO mode %d\n",
1.54 bouyer 1603: drv_dev->dv_xname, drvp->PIO_mode);
1604: } else /* already using PIO, can't downgrade */
1605: return 0;
1606:
1607: wdc->set_modes(chp);
1.137 bouyer 1608: wdc_print_modes(chp);
1609: /* reset the channel, which will shedule all drives for setup */
1.172.2.5 jmc 1610: wdc_reset_channel(drvp, flags | AT_RST_NOCMD);
1.54 bouyer 1611: return 1;
1.2 bouyer 1612: }
1613:
1614: int
1.163 thorpej 1615: wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c)
1.31 bouyer 1616: {
1.168 thorpej 1617: struct wdc_channel *chp = drvp->chnl_softc;
1.169 thorpej 1618: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1619: struct ata_xfer *xfer;
1.31 bouyer 1620: int s, ret;
1.2 bouyer 1621:
1.34 bouyer 1622: WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n",
1.169 thorpej 1623: wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive),
1.34 bouyer 1624: DEBUG_FUNCS);
1.2 bouyer 1625:
1.31 bouyer 1626: /* set up an xfer and queue. Wait for completion */
1627: xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP :
1628: WDC_NOSLEEP);
1629: if (xfer == NULL) {
1630: return WDC_TRY_AGAIN;
1631: }
1.2 bouyer 1632:
1.169 thorpej 1633: if (wdc->cap & WDC_CAPABILITY_NOIRQ)
1.98 bjh21 1634: wdc_c->flags |= AT_POLL;
1.31 bouyer 1635: if (wdc_c->flags & AT_POLL)
1636: xfer->c_flags |= C_POLL;
1.165 thorpej 1637: xfer->c_drive = drvp->drive;
1638: xfer->c_databuf = wdc_c->data;
1.31 bouyer 1639: xfer->c_bcount = wdc_c->bcount;
1.165 thorpej 1640: xfer->c_cmd = wdc_c;
1.31 bouyer 1641: xfer->c_start = __wdccommand_start;
1642: xfer->c_intr = __wdccommand_intr;
1.172.2.5 jmc 1643: xfer->c_kill_xfer = __wdccommand_kill_xfer;
1.2 bouyer 1644:
1.31 bouyer 1645: s = splbio();
1646: wdc_exec_xfer(chp, xfer);
1647: #ifdef DIAGNOSTIC
1648: if ((wdc_c->flags & AT_POLL) != 0 &&
1649: (wdc_c->flags & AT_DONE) == 0)
1.118 provos 1650: panic("wdc_exec_command: polled command not done");
1.2 bouyer 1651: #endif
1.31 bouyer 1652: if (wdc_c->flags & AT_DONE) {
1653: ret = WDC_COMPLETE;
1654: } else {
1655: if (wdc_c->flags & AT_WAIT) {
1.69 bouyer 1656: while ((wdc_c->flags & AT_DONE) == 0) {
1657: tsleep(wdc_c, PRIBIO, "wdccmd", 0);
1658: }
1.31 bouyer 1659: ret = WDC_COMPLETE;
1660: } else {
1661: ret = WDC_QUEUED;
1.2 bouyer 1662: }
1663: }
1.31 bouyer 1664: splx(s);
1665: return ret;
1.2 bouyer 1666: }
1667:
1.167 thorpej 1668: static void
1.168 thorpej 1669: __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer)
1.31 bouyer 1670: {
1.169 thorpej 1671: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1672: int drive = xfer->c_drive;
1673: struct wdc_command *wdc_c = xfer->c_cmd;
1.31 bouyer 1674:
1.34 bouyer 1675: WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n",
1.169 thorpej 1676: wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive),
1.34 bouyer 1677: DEBUG_FUNCS);
1.31 bouyer 1678:
1.169 thorpej 1679: if (wdc->cap & WDC_CAPABILITY_SELECT)
1680: wdc->select(chp,drive);
1.157 fvdl 1681: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.31 bouyer 1682: WDSD_IBM | (drive << 4));
1.137 bouyer 1683: switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ,
1684: wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) {
1685: case WDCWAIT_OK:
1686: break;
1687: case WDCWAIT_TOUT:
1.31 bouyer 1688: wdc_c->flags |= AT_TIMEOU;
1689: __wdccommand_done(chp, xfer);
1.53 bouyer 1690: return;
1.137 bouyer 1691: case WDCWAIT_THR:
1692: return;
1.31 bouyer 1693: }
1.135 bouyer 1694: if (wdc_c->flags & AT_POLL) {
1695: /* polled command, disable interrupts */
1696: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
1697: WDCTL_4BIT | WDCTL_IDS);
1698: }
1.31 bouyer 1699: wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head,
1700: wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp);
1.139 bouyer 1701:
1.31 bouyer 1702: if ((wdc_c->flags & AT_POLL) == 0) {
1703: chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */
1.81 thorpej 1704: callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz,
1705: wdctimeout, chp);
1.31 bouyer 1706: return;
1.2 bouyer 1707: }
1708: /*
1.31 bouyer 1709: * Polled command. Wait for drive ready or drq. Done in intr().
1710: * Wait for at last 400ns for status bit to be valid.
1.2 bouyer 1711: */
1.134 mycroft 1712: delay(10); /* 400ns delay */
1.66 bouyer 1713: __wdccommand_intr(chp, xfer, 0);
1.2 bouyer 1714: }
1715:
1.167 thorpej 1716: static int
1.168 thorpej 1717: __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq)
1.2 bouyer 1718: {
1.169 thorpej 1719: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1720: struct wdc_command *wdc_c = xfer->c_cmd;
1.31 bouyer 1721: int bcount = wdc_c->bcount;
1722: char *data = wdc_c->data;
1.137 bouyer 1723: int wflags;
1724:
1725: if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) {
1726: /* both wait and poll, we can tsleep here */
1.147 bouyer 1727: wflags = AT_WAIT | AT_POLL;
1.137 bouyer 1728: } else {
1729: wflags = AT_POLL;
1730: }
1.31 bouyer 1731:
1.163 thorpej 1732: again:
1.34 bouyer 1733: WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n",
1.169 thorpej 1734: wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive),
1.165 thorpej 1735: DEBUG_INTR);
1.137 bouyer 1736: /*
1737: * after a ATAPI_SOFT_RESET, the device will have released the bus.
1738: * Reselect again, it doesn't hurt for others commands, and the time
1739: * penalty for the extra regiter write is acceptable,
1740: * wdc_exec_command() isn't called often (mosly for autoconfig)
1741: */
1.157 fvdl 1742: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.165 thorpej 1743: WDSD_IBM | (xfer->c_drive << 4));
1.114 bouyer 1744: if ((wdc_c->flags & AT_XFDONE) != 0) {
1745: /*
1746: * We have completed a data xfer. The drive should now be
1747: * in its initial state
1748: */
1749: if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ,
1.137 bouyer 1750: wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0,
1751: wflags) == WDCWAIT_TOUT) {
1.114 bouyer 1752: if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1753: return 0; /* IRQ was not for us */
1754: wdc_c->flags |= AT_TIMEOU;
1755: }
1.131 mycroft 1756: goto out;
1.114 bouyer 1757: }
1.31 bouyer 1758: if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask,
1.137 bouyer 1759: (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) {
1.66 bouyer 1760: if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1.63 bouyer 1761: return 0; /* IRQ was not for us */
1762: wdc_c->flags |= AT_TIMEOU;
1.131 mycroft 1763: goto out;
1.2 bouyer 1764: }
1.169 thorpej 1765: if (wdc->cap & WDC_CAPABILITY_IRQACK)
1766: wdc->irqack(chp);
1.31 bouyer 1767: if (wdc_c->flags & AT_READ) {
1.131 mycroft 1768: if ((chp->ch_status & WDCS_DRQ) == 0) {
1769: wdc_c->flags |= AT_TIMEOU;
1770: goto out;
1771: }
1.165 thorpej 1772: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) {
1.31 bouyer 1773: bus_space_read_multi_4(chp->data32iot, chp->data32ioh,
1774: 0, (u_int32_t*)data, bcount >> 2);
1775: data += bcount & 0xfffffffc;
1776: bcount = bcount & 0x03;
1777: }
1778: if (bcount > 0)
1.157 fvdl 1779: bus_space_read_multi_2(chp->cmd_iot,
1780: chp->cmd_iohs[wd_data], 0,
1781: (u_int16_t *)data, bcount >> 1);
1.114 bouyer 1782: /* at this point the drive should be in its initial state */
1783: wdc_c->flags |= AT_XFDONE;
1.137 bouyer 1784: /* XXX should read status register here ? */
1.131 mycroft 1785: } else if (wdc_c->flags & AT_WRITE) {
1786: if ((chp->ch_status & WDCS_DRQ) == 0) {
1.114 bouyer 1787: wdc_c->flags |= AT_TIMEOU;
1.131 mycroft 1788: goto out;
1789: }
1.165 thorpej 1790: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) {
1.31 bouyer 1791: bus_space_write_multi_4(chp->data32iot, chp->data32ioh,
1792: 0, (u_int32_t*)data, bcount >> 2);
1793: data += bcount & 0xfffffffc;
1794: bcount = bcount & 0x03;
1795: }
1796: if (bcount > 0)
1.157 fvdl 1797: bus_space_write_multi_2(chp->cmd_iot,
1798: chp->cmd_iohs[wd_data], 0,
1799: (u_int16_t *)data, bcount >> 1);
1.114 bouyer 1800: wdc_c->flags |= AT_XFDONE;
1801: if ((wdc_c->flags & AT_POLL) == 0) {
1802: chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */
1803: callout_reset(&chp->ch_callout,
1804: wdc_c->timeout / 1000 * hz, wdctimeout, chp);
1805: return 1;
1806: } else {
1807: goto again;
1808: }
1.2 bouyer 1809: }
1.163 thorpej 1810: out:
1.31 bouyer 1811: __wdccommand_done(chp, xfer);
1812: return 1;
1.2 bouyer 1813: }
1814:
1.167 thorpej 1815: static void
1.168 thorpej 1816: __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer)
1.2 bouyer 1817: {
1.169 thorpej 1818: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 1819: struct wdc_command *wdc_c = xfer->c_cmd;
1.2 bouyer 1820:
1.34 bouyer 1821: WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n",
1.169 thorpej 1822: wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive),
1.165 thorpej 1823: DEBUG_FUNCS);
1.70 bouyer 1824:
1825:
1.31 bouyer 1826: if (chp->ch_status & WDCS_DWF)
1827: wdc_c->flags |= AT_DF;
1828: if (chp->ch_status & WDCS_ERR) {
1829: wdc_c->flags |= AT_ERROR;
1830: wdc_c->r_error = chp->ch_error;
1831: }
1.80 enami 1832: if ((wdc_c->flags & AT_READREG) != 0 &&
1.169 thorpej 1833: (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 &&
1.75 enami 1834: (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) {
1.157 fvdl 1835: wdc_c->r_head = bus_space_read_1(chp->cmd_iot,
1836: chp->cmd_iohs[wd_sdh], 0);
1837: wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot,
1838: chp->cmd_iohs[wd_cyl_hi], 0) << 8;
1839: wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot,
1840: chp->cmd_iohs[wd_cyl_lo], 0);
1841: wdc_c->r_sector = bus_space_read_1(chp->cmd_iot,
1842: chp->cmd_iohs[wd_sector], 0);
1843: wdc_c->r_count = bus_space_read_1(chp->cmd_iot,
1844: chp->cmd_iohs[wd_seccnt], 0);
1845: wdc_c->r_error = bus_space_read_1(chp->cmd_iot,
1846: chp->cmd_iohs[wd_error], 0);
1847: wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot,
1848: chp->cmd_iohs[wd_precomp], 0);
1.135 bouyer 1849: }
1.172.2.5 jmc 1850: __wdccommand_done_end(chp, xfer);
1851: }
1.137 bouyer 1852:
1.172.2.5 jmc 1853: static void
1854: __wdccommand_done_end(struct wdc_channel *chp, struct ata_xfer *xfer)
1855: {
1856: struct wdc_command *wdc_c = xfer->c_cmd;
1857:
1858: callout_stop(&chp->ch_callout);
1859: wdc_c->flags |= AT_DONE;
1.135 bouyer 1860: if (wdc_c->flags & AT_POLL) {
1861: /* enable interrupts */
1862: bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
1863: WDCTL_4BIT);
1.172.2.1 tron 1864: delay(10); /* some drives need a little delay here */
1.46 kenh 1865: }
1.31 bouyer 1866: wdc_free_xfer(chp, xfer);
1.71 bouyer 1867: if (wdc_c->flags & AT_WAIT)
1868: wakeup(wdc_c);
1869: else if (wdc_c->callback)
1870: wdc_c->callback(wdc_c->callback_arg);
1.45 drochner 1871: wdcstart(chp);
1.31 bouyer 1872: return;
1.2 bouyer 1873: }
1874:
1.172.2.5 jmc 1875: static void
1876: __wdccommand_kill_xfer(struct wdc_channel *chp, struct ata_xfer *xfer,
1877: int reason)
1878: {
1879: struct wdc_command *wdc_c = xfer->c_cmd;
1880:
1881: switch (reason) {
1882: case KILL_GONE:
1883: wdc_c->flags |= AT_GONE;
1884: break;
1885: case KILL_RESET:
1886: wdc_c->flags |= AT_RESET;
1887: break;
1888: default:
1889: printf("__wdccommand_kill_xfer: unknown reason %d\n",
1890: reason);
1891: panic("__wdccommand_kill_xfer");
1892: }
1893: __wdccommand_done_end(chp, xfer);
1894:
1895: }
1896:
1.2 bouyer 1897: /*
1.31 bouyer 1898: * Send a command. The drive should be ready.
1.2 bouyer 1899: * Assumes interrupts are blocked.
1900: */
1.31 bouyer 1901: void
1.168 thorpej 1902: wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command,
1.163 thorpej 1903: u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count,
1904: u_int8_t precomp)
1.31 bouyer 1905: {
1.169 thorpej 1906: struct wdc_softc *wdc = chp->ch_wdc;
1.163 thorpej 1907:
1.31 bouyer 1908: WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d "
1.169 thorpej 1909: "sector=%d count=%d precomp=%d\n", wdc->sc_dev.dv_xname,
1910: chp->ch_channel, drive, command, cylin, head, sector, count,
1911: precomp), DEBUG_FUNCS);
1.31 bouyer 1912:
1.169 thorpej 1913: if (wdc->cap & WDC_CAPABILITY_SELECT)
1914: wdc->select(chp,drive);
1.107 dbj 1915:
1.31 bouyer 1916: /* Select drive, head, and addressing mode. */
1.157 fvdl 1917: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.31 bouyer 1918: WDSD_IBM | (drive << 4) | head);
1919: /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */
1.157 fvdl 1920: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0,
1.31 bouyer 1921: precomp);
1.157 fvdl 1922: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin);
1923: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi],
1924: 0, cylin >> 8);
1925: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector);
1926: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count);
1.108 christos 1927:
1928: /* Send command. */
1.157 fvdl 1929: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command);
1.108 christos 1930: return;
1931: }
1932:
1933: /*
1934: * Send a 48-bit addressing command. The drive should be ready.
1935: * Assumes interrupts are blocked.
1936: */
1937: void
1.168 thorpej 1938: wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command,
1.163 thorpej 1939: u_int64_t blkno, u_int16_t count)
1.108 christos 1940: {
1.169 thorpej 1941: struct wdc_softc *wdc = chp->ch_wdc;
1.163 thorpej 1942:
1.108 christos 1943: WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d "
1.169 thorpej 1944: "count=%d\n", wdc->sc_dev.dv_xname,
1945: chp->ch_channel, drive, command, (u_int32_t) blkno, count),
1.108 christos 1946: DEBUG_FUNCS);
1947:
1.169 thorpej 1948: if (wdc->cap & WDC_CAPABILITY_SELECT)
1949: wdc->select(chp,drive);
1.108 christos 1950:
1951: /* Select drive, head, and addressing mode. */
1.157 fvdl 1952: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.108 christos 1953: (drive << 4) | WDSD_LBA);
1954:
1955: /* previous */
1.157 fvdl 1956: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0);
1957: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt],
1958: 0, count >> 8);
1959: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi],
1960: 0, blkno >> 40);
1961: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi],
1962: 0, blkno >> 32);
1963: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo],
1964: 0, blkno >> 24);
1.108 christos 1965:
1966: /* current */
1.157 fvdl 1967: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0);
1968: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count);
1969: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi],
1970: 0, blkno >> 16);
1971: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi],
1972: 0, blkno >> 8);
1973: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno);
1.2 bouyer 1974:
1.31 bouyer 1975: /* Send command. */
1.157 fvdl 1976: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command);
1.31 bouyer 1977: return;
1.2 bouyer 1978: }
1979:
1980: /*
1.31 bouyer 1981: * Simplified version of wdccommand(). Unbusy/ready/drq must be
1982: * tested by the caller.
1.2 bouyer 1983: */
1.31 bouyer 1984: void
1.168 thorpej 1985: wdccommandshort(struct wdc_channel *chp, int drive, int command)
1.2 bouyer 1986: {
1.169 thorpej 1987: struct wdc_softc *wdc = chp->ch_wdc;
1.2 bouyer 1988:
1.31 bouyer 1989: WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n",
1.169 thorpej 1990: wdc->sc_dev.dv_xname, chp->ch_channel, drive, command),
1.31 bouyer 1991: DEBUG_FUNCS);
1.107 dbj 1992:
1.169 thorpej 1993: if (wdc->cap & WDC_CAPABILITY_SELECT)
1994: wdc->select(chp,drive);
1.2 bouyer 1995:
1.31 bouyer 1996: /* Select drive. */
1.157 fvdl 1997: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
1.31 bouyer 1998: WDSD_IBM | (drive << 4));
1.2 bouyer 1999:
1.157 fvdl 2000: bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command);
1.31 bouyer 2001: }
1.2 bouyer 2002:
1.31 bouyer 2003: /* Add a command to the queue and start controller. Must be called at splbio */
1.2 bouyer 2004: void
1.168 thorpej 2005: wdc_exec_xfer(struct wdc_channel *chp, struct ata_xfer *xfer)
1.2 bouyer 2006: {
1.163 thorpej 2007:
1.33 bouyer 2008: WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer,
1.169 thorpej 2009: chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
1.2 bouyer 2010:
1.31 bouyer 2011: /* complete xfer setup */
1.165 thorpej 2012: xfer->c_chp = chp;
1.2 bouyer 2013:
2014: /* insert at the end of command list */
1.165 thorpej 2015: TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
1.31 bouyer 2016: WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n",
1.33 bouyer 2017: chp->ch_flags), DEBUG_XFERS);
1.45 drochner 2018: wdcstart(chp);
1.31 bouyer 2019: }
1.2 bouyer 2020:
1.165 thorpej 2021: struct ata_xfer *
1.163 thorpej 2022: wdc_get_xfer(int flags)
1.2 bouyer 2023: {
1.165 thorpej 2024: struct ata_xfer *xfer;
1.72 bouyer 2025: int s;
1.2 bouyer 2026:
1.72 bouyer 2027: s = splbio();
1.71 bouyer 2028: xfer = pool_get(&wdc_xfer_pool,
2029: ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK));
1.72 bouyer 2030: splx(s);
1.99 chs 2031: if (xfer != NULL) {
1.165 thorpej 2032: memset(xfer, 0, sizeof(struct ata_xfer));
1.99 chs 2033: }
1.2 bouyer 2034: return xfer;
2035: }
2036:
2037: void
1.168 thorpej 2038: wdc_free_xfer(struct wdc_channel *chp, struct ata_xfer *xfer)
1.2 bouyer 2039: {
1.169 thorpej 2040: struct wdc_softc *wdc = chp->ch_wdc;
1.2 bouyer 2041: int s;
2042:
1.31 bouyer 2043: if (wdc->cap & WDC_CAPABILITY_HWLOCK)
2044: (*wdc->free_hw)(chp);
1.2 bouyer 2045: s = splbio();
1.31 bouyer 2046: chp->ch_flags &= ~WDCF_ACTIVE;
1.165 thorpej 2047: TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
1.72 bouyer 2048: pool_put(&wdc_xfer_pool, xfer);
1.2 bouyer 2049: splx(s);
1.75 enami 2050: }
2051:
2052: /*
1.168 thorpej 2053: * Kill off all pending xfers for a wdc_channel.
1.75 enami 2054: *
2055: * Must be called at splbio().
2056: */
2057: void
1.168 thorpej 2058: wdc_kill_pending(struct wdc_channel *chp)
1.75 enami 2059: {
1.165 thorpej 2060: struct ata_xfer *xfer;
1.75 enami 2061:
1.165 thorpej 2062: while ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) != NULL) {
2063: chp = xfer->c_chp;
1.172.2.5 jmc 2064: (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE);
1.75 enami 2065: }
1.2 bouyer 2066: }
2067:
1.31 bouyer 2068: static void
1.168 thorpej 2069: __wdcerror(struct wdc_channel *chp, char *msg)
1.2 bouyer 2070: {
1.169 thorpej 2071: struct wdc_softc *wdc = chp->ch_wdc;
1.165 thorpej 2072: struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
1.88 mrg 2073:
1.2 bouyer 2074: if (xfer == NULL)
1.169 thorpej 2075: printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel,
1.31 bouyer 2076: msg);
1.2 bouyer 2077: else
1.169 thorpej 2078: printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname,
2079: chp->ch_channel, xfer->c_drive, msg);
1.2 bouyer 2080: }
2081:
2082: /*
2083: * the bit bucket
2084: */
2085: void
1.168 thorpej 2086: wdcbit_bucket(struct wdc_channel *chp, int size)
1.2 bouyer 2087: {
2088:
1.12 cgd 2089: for (; size >= 2; size -= 2)
1.157 fvdl 2090: (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0);
1.12 cgd 2091: if (size)
1.157 fvdl 2092: (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0);
1.44 thorpej 2093: }
2094:
2095: int
1.168 thorpej 2096: wdc_addref(struct wdc_channel *chp)
1.44 thorpej 2097: {
1.169 thorpej 2098: struct wdc_softc *wdc = chp->ch_wdc;
1.96 bouyer 2099: struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic;
1.44 thorpej 2100: int s, error = 0;
2101:
2102: s = splbio();
1.96 bouyer 2103: if (adapt->adapt_refcnt++ == 0 &&
2104: adapt->adapt_enable != NULL) {
2105: error = (*adapt->adapt_enable)(&wdc->sc_dev, 1);
1.44 thorpej 2106: if (error)
1.96 bouyer 2107: adapt->adapt_refcnt--;
1.44 thorpej 2108: }
2109: splx(s);
2110: return (error);
2111: }
2112:
2113: void
1.168 thorpej 2114: wdc_delref(struct wdc_channel *chp)
1.44 thorpej 2115: {
1.169 thorpej 2116: struct wdc_softc *wdc = chp->ch_wdc;
1.96 bouyer 2117: struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic;
1.44 thorpej 2118: int s;
2119:
2120: s = splbio();
1.96 bouyer 2121: if (adapt->adapt_refcnt-- == 1 &&
2122: adapt->adapt_enable != NULL)
2123: (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0);
1.44 thorpej 2124: splx(s);
1.93 wrstuden 2125: }
2126:
2127: void
1.168 thorpej 2128: wdc_print_modes(struct wdc_channel *chp)
1.93 wrstuden 2129: {
1.169 thorpej 2130: struct wdc_softc *wdc = chp->ch_wdc;
1.93 wrstuden 2131: int drive;
2132: struct ata_drive_datas *drvp;
2133:
2134: for (drive = 0; drive < 2; drive++) {
2135: drvp = &chp->ch_drive[drive];
2136: if ((drvp->drive_flags & DRIVE) == 0)
2137: continue;
1.123 thorpej 2138: aprint_normal("%s(%s:%d:%d): using PIO mode %d",
1.93 wrstuden 2139: drvp->drv_softc->dv_xname,
1.169 thorpej 2140: wdc->sc_dev.dv_xname,
2141: chp->ch_channel, drive, drvp->PIO_mode);
1.93 wrstuden 2142: if (drvp->drive_flags & DRIVE_DMA)
1.123 thorpej 2143: aprint_normal(", DMA mode %d", drvp->DMA_mode);
1.93 wrstuden 2144: if (drvp->drive_flags & DRIVE_UDMA) {
1.123 thorpej 2145: aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode);
1.93 wrstuden 2146: if (drvp->UDMA_mode == 2)
1.123 thorpej 2147: aprint_normal(" (Ultra/33)");
1.93 wrstuden 2148: else if (drvp->UDMA_mode == 4)
1.123 thorpej 2149: aprint_normal(" (Ultra/66)");
1.93 wrstuden 2150: else if (drvp->UDMA_mode == 5)
1.123 thorpej 2151: aprint_normal(" (Ultra/100)");
2152: else if (drvp->UDMA_mode == 6)
2153: aprint_normal(" (Ultra/133)");
1.93 wrstuden 2154: }
2155: if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA))
1.123 thorpej 2156: aprint_normal(" (using DMA data transfers)");
2157: aprint_normal("\n");
1.93 wrstuden 2158: }
1.2 bouyer 2159: }
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