Annotation of src/sys/dev/ic/nvmereg.h, Revision 1.1.2.3
1.1.2.3 ! skrll 1: /* $NetBSD: nvmereg.h,v 1.1.2.2 2016/05/29 08:44:21 skrll Exp $ */
1.1.2.2 skrll 2: /* $OpenBSD: nvmereg.h,v 1.10 2016/04/14 11:18:32 dlg Exp $ */
3:
4: /*
5: * Copyright (c) 2014 David Gwynne <dlg@openbsd.org>
6: *
7: * Permission to use, copy, modify, and distribute this software for any
8: * purpose with or without fee is hereby granted, provided that the above
9: * copyright notice and this permission notice appear in all copies.
10: *
11: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18: */
19:
1.1.2.3 ! skrll 20: #ifndef __NVMEREG_H__
! 21: #define __NVMEREG_H__
! 22:
1.1.2.2 skrll 23: #define NVME_CAP 0x0000 /* Controller Capabilities */
24: #define NVME_CAP_MPSMAX(_r) (12 + (((_r) >> 52) & 0xf)) /* shift */
25: #define NVME_CAP_MPSMIN(_r) (12 + (((_r) >> 48) & 0xf)) /* shift */
26: #define NVME_CAP_CSS(_r) (((_r) >> 37) & 0x7f)
27: #define NVME_CAP_CSS_NVM __BIT(0)
28: #define NVME_CAP_NSSRS(_r) ISSET((_r), __BIT(36))
29: #define NVME_CAP_DSTRD(_r) __BIT(2 + (((_r) >> 32) & 0xf)) /* bytes */
30: #define NVME_CAP_TO(_r) (500 * (((_r) >> 24) & 0xff)) /* ms */
31: #define NVME_CAP_AMS(_r) (((_r) >> 17) & 0x3)
32: #define NVME_CAP_AMS_WRR __BIT(0)
33: #define NVME_CAP_AMS_VENDOR __BIT(1)
34: #define NVME_CAP_CQR(_r) ISSET((_r), __BIT(16))
35: #define NVME_CAP_MQES(_r) (((_r) & 0xffff) + 1)
36: #define NVME_CAP_LO 0x0000
37: #define NVME_CAP_HI 0x0004
38: #define NVME_VS 0x0008 /* Version */
39: #define NVME_VS_MJR(_r) (((_r) >> 16) & 0xffff)
40: #define NVME_VS_MNR(_r) ((_r) & 0xffff)
41: #define NVME_VS_1_0 0x00010000
42: #define NVME_VS_1_1 0x00010100
43: #define NVME_VS_1_2 0x00010200
44: #define NVME_INTMS 0x000c /* Interrupt Mask Set */
45: #define NVME_INTMC 0x0010 /* Interrupt Mask Clear */
46: #define NVME_CC 0x0014 /* Controller Configuration */
47: #define NVME_CC_IOCQES(_v) (((_v) & 0xf) << 20)
48: #define NVME_CC_IOCQES_MASK NVME_CC_IOCQES(0xf)
49: #define NVME_CC_IOCQES_R(_v) (((_v) >> 20) & 0xf)
50: #define NVME_CC_IOSQES(_v) (((_v) & 0xf) << 16)
51: #define NVME_CC_IOSQES_MASK NVME_CC_IOSQES(0xf)
52: #define NVME_CC_IOSQES_R(_v) (((_v) >> 16) & 0xf)
53: #define NVME_CC_SHN(_v) (((_v) & 0x3) << 14)
54: #define NVME_CC_SHN_MASK NVME_CC_SHN(0x3)
55: #define NVME_CC_SHN_R(_v) (((_v) >> 15) & 0x3)
56: #define NVME_CC_SHN_NONE 0
57: #define NVME_CC_SHN_NORMAL 1
58: #define NVME_CC_SHN_ABRUPT 2
59: #define NVME_CC_AMS(_v) (((_v) & 0x7) << 11)
60: #define NVME_CC_AMS_MASK NVME_CC_AMS(0x7)
61: #define NVME_CC_AMS_R(_v) (((_v) >> 11) & 0xf)
62: #define NVME_CC_AMS_RR 0 /* round-robin */
63: #define NVME_CC_AMS_WRR_U 1 /* weighted round-robin w/ urgent */
64: #define NVME_CC_AMS_VENDOR 7 /* vendor */
65: #define NVME_CC_MPS(_v) ((((_v) - 12) & 0xf) << 7)
66: #define NVME_CC_MPS_MASK (0xf << 7)
67: #define NVME_CC_MPS_R(_v) (12 + (((_v) >> 7) & 0xf))
68: #define NVME_CC_CSS(_v) (((_v) & 0x7) << 4)
69: #define NVME_CC_CSS_MASK NVME_CC_CSS(0x7)
70: #define NVME_CC_CSS_R(_v) (((_v) >> 4) & 0x7)
71: #define NVME_CC_CSS_NVM 0
72: #define NVME_CC_EN __BIT(0)
73: #define NVME_CSTS 0x001c /* Controller Status */
74: #define NVME_CSTS_SHST_MASK (0x3 << 2)
75: #define NVME_CSTS_SHST_NONE (0x0 << 2) /* normal operation */
76: #define NVME_CSTS_SHST_WAIT (0x1 << 2) /* shutdown processing occurring */
77: #define NVME_CSTS_SHST_DONE (0x2 << 2) /* shutdown processing complete */
78: #define NVME_CSTS_CFS (1 << 1)
79: #define NVME_CSTS_RDY (1 << 0)
80: #define NVME_NSSR 0x0020 /* NVM Subsystem Reset (Optional) */
81: #define NVME_AQA 0x0024 /* Admin Queue Attributes */
82: /* Admin Completion Queue Size */
83: #define NVME_AQA_ACQS(_v) (((_v) - 1) << 16)
84: /* Admin Submission Queue Size */
85: #define NVME_AQA_ASQS(_v) (((_v) - 1) << 0)
86: #define NVME_ASQ 0x0028 /* Admin Submission Queue Base Address */
87: #define NVME_ACQ 0x0030 /* Admin Completion Queue Base Address */
88:
89: #define NVME_ADMIN_Q 0
90: /* Submission Queue Tail Doorbell */
91: #define NVME_SQTDBL(_q, _s) (0x1000 + (2 * (_q) + 0) * (_s))
92: /* Completion Queue Head Doorbell */
93: #define NVME_CQHDBL(_q, _s) (0x1000 + (2 * (_q) + 1) * (_s))
94:
95: struct nvme_sge {
96: uint8_t id;
97: uint8_t _reserved[15];
98: } __packed __aligned(8);
99:
100: struct nvme_sge_data {
101: uint8_t id;
102: uint8_t _reserved[3];
103:
104: uint32_t length;
105:
106: uint64_t address;
107: } __packed __aligned(8);
108:
109: struct nvme_sge_bit_bucket {
110: uint8_t id;
111: uint8_t _reserved[3];
112:
113: uint32_t length;
114:
115: uint64_t address;
116: } __packed __aligned(8);
117:
118: struct nvme_sqe {
119: uint8_t opcode;
120: uint8_t flags;
121: uint16_t cid;
122:
123: uint32_t nsid;
124:
125: uint8_t _reserved[8];
126:
127: uint64_t mptr;
128:
129: union {
130: uint64_t prp[2];
131: struct nvme_sge sge;
132: } __packed entry;
133:
134: uint32_t cdw10;
135: uint32_t cdw11;
136: uint32_t cdw12;
137: uint32_t cdw13;
138: uint32_t cdw14;
139: uint32_t cdw15;
140: } __packed __aligned(8);
141:
142: struct nvme_sqe_q {
143: uint8_t opcode;
144: uint8_t flags;
145: uint16_t cid;
146:
147: uint8_t _reserved1[20];
148:
149: uint64_t prp1;
150:
151: uint8_t _reserved2[8];
152:
153: uint16_t qid;
154: uint16_t qsize;
155:
156: uint8_t qflags;
157: #define NVM_SQE_SQ_QPRIO_URG (0x0 << 1)
158: #define NVM_SQE_SQ_QPRIO_HI (0x1 << 1)
159: #define NVM_SQE_SQ_QPRIO_MED (0x2 << 1)
160: #define NVM_SQE_SQ_QPRIO_LOW (0x3 << 1)
161: #define NVM_SQE_CQ_IEN (1 << 1)
162: #define NVM_SQE_Q_PC (1 << 0)
163: uint8_t _reserved3;
164: uint16_t cqid; /* XXX interrupt vector for cq */
165:
166: uint8_t _reserved4[16];
167: } __packed __aligned(8);
168:
169: struct nvme_sqe_io {
170: uint8_t opcode;
171: uint8_t flags;
172: uint16_t cid;
173:
174: uint32_t nsid;
175:
176: uint8_t _reserved[8];
177:
178: uint64_t mptr;
179:
180: union {
181: uint64_t prp[2];
182: struct nvme_sge sge;
183: } __packed entry;
184:
185: uint64_t slba; /* Starting LBA */
186:
187: uint16_t nlb; /* Number of Logical Blocks */
188: uint16_t ioflags;
189:
190: uint8_t dsm; /* Dataset Management */
191: uint8_t _reserved2[3];
192:
193: uint32_t eilbrt; /* Expected Initial Logical Block
194: Reference Tag */
195:
196: uint16_t elbat; /* Expected Logical Block
197: Application Tag */
198: uint16_t elbatm; /* Expected Logical Block
199: Application Tag Mask */
200: } __packed __aligned(8);
201:
202: struct nvme_cqe {
203: uint32_t cdw0;
204:
205: uint32_t _reserved;
206:
207: uint16_t sqhd; /* SQ Head Pointer */
208: uint16_t sqid; /* SQ Identifier */
209:
210: uint16_t cid; /* Command Identifier */
211: uint16_t flags;
212: #define NVME_CQE_DNR __BIT(15)
213: #define NVME_CQE_M __BIT(14)
1.1.2.3 ! skrll 214: #define NVME_CQE_SCT_MASK __BITS(8, 10)
1.1.2.2 skrll 215: #define NVME_CQE_SCT(_f) ((_f) & (0x07 << 8))
216: #define NVME_CQE_SCT_GENERIC (0x00 << 8)
217: #define NVME_CQE_SCT_COMMAND (0x01 << 8)
218: #define NVME_CQE_SCT_MEDIAERR (0x02 << 8)
219: #define NVME_CQE_SCT_VENDOR (0x07 << 8)
1.1.2.3 ! skrll 220: #define NVME_CQE_SC_MASK __BITS(1, 7)
1.1.2.2 skrll 221: #define NVME_CQE_SC(_f) ((_f) & (0x7f << 1))
1.1.2.3 ! skrll 222: /* generic command status codes */
1.1.2.2 skrll 223: #define NVME_CQE_SC_SUCCESS (0x00 << 1)
224: #define NVME_CQE_SC_INVALID_OPCODE (0x01 << 1)
225: #define NVME_CQE_SC_INVALID_FIELD (0x02 << 1)
226: #define NVME_CQE_SC_CID_CONFLICT (0x03 << 1)
227: #define NVME_CQE_SC_DATA_XFER_ERR (0x04 << 1)
228: #define NVME_CQE_SC_ABRT_BY_NO_PWR (0x05 << 1)
229: #define NVME_CQE_SC_INTERNAL_DEV_ERR (0x06 << 1)
230: #define NVME_CQE_SC_CMD_ABRT_REQD (0x07 << 1)
231: #define NVME_CQE_SC_CMD_ABDR_SQ_DEL (0x08 << 1)
232: #define NVME_CQE_SC_CMD_ABDR_FUSE_ERR (0x09 << 1)
233: #define NVME_CQE_SC_CMD_ABDR_FUSE_MISS (0x0a << 1)
234: #define NVME_CQE_SC_INVALID_NS (0x0b << 1)
235: #define NVME_CQE_SC_CMD_SEQ_ERR (0x0c << 1)
236: #define NVME_CQE_SC_INVALID_LAST_SGL (0x0d << 1)
237: #define NVME_CQE_SC_INVALID_NUM_SGL (0x0e << 1)
238: #define NVME_CQE_SC_DATA_SGL_LEN (0x0f << 1)
239: #define NVME_CQE_SC_MDATA_SGL_LEN (0x10 << 1)
240: #define NVME_CQE_SC_SGL_TYPE_INVALID (0x11 << 1)
241: #define NVME_CQE_SC_LBA_RANGE (0x80 << 1)
242: #define NVME_CQE_SC_CAP_EXCEEDED (0x81 << 1)
1.1.2.3 ! skrll 243: #define NVME_CQE_SC_NS_NOT_RDY (0x82 << 1)
! 244: #define NVME_CQE_SC_RSV_CONFLICT (0x83 << 1)
! 245: /* command specific status codes */
! 246: #define NVME_CQE_SC_CQE_INVALID (0x00 << 1)
! 247: #define NVME_CQE_SC_INVALID_QID (0x01 << 1)
! 248: #define NVME_CQE_SC_MAX_Q_SIZE (0x02 << 1)
! 249: #define NVME_CQE_SC_ABORT_LIMIT (0x03 << 1)
! 250: #define NVME_CQE_SC_ASYNC_EV_REQ_LIMIT (0x05 << 1)
! 251: #define NVME_CQE_SC_INVALID_FW_SLOT (0x06 << 1)
! 252: #define NVME_CQE_SC_INVALID_FW_IMAGE (0x07 << 1)
! 253: #define NVME_CQE_SC_INVALID_INT_VEC (0x08 << 1)
! 254: #define NVME_CQE_SC_INVALID_LOG_PAGE (0x09 << 1)
! 255: #define NVME_CQE_SC_INVALID_FORMAT (0x0a << 1)
! 256: #define NVME_CQE_SC_FW_REQ_CNV_RESET (0x0b << 1)
! 257: #define NVME_CQE_SC_FW_REQ_NVM_RESET (0x10 << 1)
! 258: #define NVME_CQE_SC_FW_REQ_RESET (0x11 << 1)
! 259: #define NVME_CQE_SC_FW_MAX_TIME_VIO (0x12 << 1)
! 260: #define NVME_CQE_SC_FW_PROHIBIT (0x13 << 1)
! 261: #define NVME_CQE_SC_OVERLAP_RANGE (0x14 << 1)
! 262: #define NVME_CQE_SC_CONFLICT_ATTRS (0x80 << 1)
! 263: #define NVME_CQE_SC_INVALID_PROT_INFO (0x81 << 1)
! 264: #define NVME_CQE_SC_ATT_WR_TO_RO_PAGE (0x82 << 1)
! 265: /* media error status codes */
! 266: #define NVME_CQE_SC_WRITE_FAULTS (0x80 << 1)
! 267: #define NVME_CQE_SC_UNRECV_READ_ERR (0x81 << 1)
! 268: #define NVME_CQE_SC_GUARD_CHECK_ERR (0x82 << 1)
! 269: #define NVME_CQE_SC_APPL_TAG_CHECK_ERR (0x83 << 1)
! 270: #define NVME_CQE_SC_REF_TAG_CHECK_ERR (0x84 << 1)
! 271: #define NVME_CQE_SC_CMP_FAIL (0x85 << 1)
! 272: #define NVME_CQE_SC_ACCESS_DENIED (0x86 << 1)
1.1.2.2 skrll 273: #define NVME_CQE_PHASE __BIT(0)
274: } __packed __aligned(8);
275:
276: #define NVM_ADMIN_DEL_IOSQ 0x00 /* Delete I/O Submission Queue */
277: #define NVM_ADMIN_ADD_IOSQ 0x01 /* Create I/O Submission Queue */
278: #define NVM_ADMIN_GET_LOG_PG 0x02 /* Get Log Page */
279: #define NVM_ADMIN_DEL_IOCQ 0x04 /* Delete I/O Completion Queue */
280: #define NVM_ADMIN_ADD_IOCQ 0x05 /* Create I/O Completion Queue */
281: #define NVM_ADMIN_IDENTIFY 0x06 /* Identify */
282: #define NVM_ADMIN_ABORT 0x08 /* Abort */
283: #define NVM_ADMIN_SET_FEATURES 0x09 /* Set Features */
284: #define NVM_ADMIN_GET_FEATURES 0x0a /* Get Features */
285: #define NVM_ADMIN_ASYNC_EV_REQ 0x0c /* Asynchronous Event Request */
1.1.2.3 ! skrll 286: #define NVM_ADMIN_FW_COMMIT 0x10 /* Firmware Commit */
1.1.2.2 skrll 287: #define NVM_ADMIN_FW_DOWNLOAD 0x11 /* Firmware Image Download */
288:
289: #define NVM_CMD_FLUSH 0x00 /* Flush */
290: #define NVM_CMD_WRITE 0x01 /* Write */
291: #define NVM_CMD_READ 0x02 /* Read */
292: #define NVM_CMD_WR_UNCOR 0x04 /* Write Uncorrectable */
293: #define NVM_CMD_COMPARE 0x05 /* Compare */
294: #define NVM_CMD_DSM 0x09 /* Dataset Management */
295:
296: /* Power State Descriptor Data */
297: struct nvm_identify_psd {
298: uint16_t mp; /* Max Power */
1.1.2.3 ! skrll 299: uint8_t _reserved1;
! 300: uint8_t flags;
! 301: #define NVME_PSD_NOPS __BIT(1)
! 302: #define NVME_PSD_MPS __BIT(0)
1.1.2.2 skrll 303:
304: uint32_t enlat; /* Entry Latency */
305:
306: uint32_t exlat; /* Exit Latency */
307:
308: uint8_t rrt; /* Relative Read Throughput */
1.1.2.3 ! skrll 309: #define NVME_PSD_RRT_MASK __BITS(0, 4)
1.1.2.2 skrll 310: uint8_t rrl; /* Relative Read Latency */
1.1.2.3 ! skrll 311: #define NVME_PSD_RRL_MASK __BITS(0, 4)
1.1.2.2 skrll 312: uint8_t rwt; /* Relative Write Throughput */
1.1.2.3 ! skrll 313: #define NVME_PSD_RWT_MASK __BITS(0, 4)
1.1.2.2 skrll 314: uint8_t rwl; /* Relative Write Latency */
1.1.2.3 ! skrll 315: #define NVME_PSD_RWL_MASK __BITS(0, 4)
1.1.2.2 skrll 316:
1.1.2.3 ! skrll 317: uint16_t idlp; /* Idle Power */
! 318: uint8_t ips; /* Idle Power Scale */
! 319: #define NVME_PSD_IPS_MASK __BITS(0, 1)
! 320: uint8_t _reserved2;
! 321: uint16_t actp; /* Active Power */
! 322: uint16_t ap; /* Active Power Workload/Scale */
! 323: #define NVME_PSD_APW_MASK __BITS(0, 2)
! 324: #define NVME_PSD_APS_MASK __BITS(6, 7)
! 325:
! 326: uint8_t _reserved[8];
1.1.2.2 skrll 327: } __packed __aligned(8);
328:
329: struct nvm_identify_controller {
330: /* Controller Capabilities and Features */
331:
332: uint16_t vid; /* PCI Vendor ID */
333: uint16_t ssvid; /* PCI Subsystem Vendor ID */
334:
335: uint8_t sn[20]; /* Serial Number */
336: uint8_t mn[40]; /* Model Number */
337: uint8_t fr[8]; /* Firmware Revision */
338:
339: uint8_t rab; /* Recommended Arbitration Burst */
340: uint8_t ieee[3]; /* IEEE OUI Identifier */
341:
342: uint8_t cmic; /* Controller Multi-Path I/O and
343: Namespace Sharing Capabilities */
344: uint8_t mdts; /* Maximum Data Transfer Size */
345: uint16_t cntlid; /* Controller ID */
346:
347: uint8_t _reserved1[176];
348:
349: /* Admin Command Set Attributes & Optional Controller Capabilities */
350:
351: uint16_t oacs; /* Optional Admin Command Support */
1.1.2.3 ! skrll 352: #define NVME_ID_CTRLR_OACS_NS __BIT(3)
! 353: #define NVME_ID_CTRLR_OACS_FW __BIT(2)
! 354: #define NVME_ID_CTRLR_OACS_FORMAT __BIT(1)
! 355: #define NVME_ID_CTRLR_OACS_SECURITY __BIT(0)
1.1.2.2 skrll 356: uint8_t acl; /* Abort Command Limit */
357: uint8_t aerl; /* Asynchronous Event Request Limit */
358:
359: uint8_t frmw; /* Firmware Updates */
1.1.2.3 ! skrll 360: #define NVME_ID_CTRLR_FRMW_NOREQ_RESET __BIT(4)
! 361: #define NVME_ID_CTRLR_FRMW_NSLOT __BITS(1, 3)
! 362: #define NVME_ID_CTRLR_FRMW_SLOT1_RO __BIT(0)
1.1.2.2 skrll 363: uint8_t lpa; /* Log Page Attributes */
1.1.2.3 ! skrll 364: #define NVME_ID_CTRLR_LPA_CMD_EFFECT __BIT(1)
! 365: #define NVME_ID_CTRLR_LPA_NS_SMART __BIT(0)
1.1.2.2 skrll 366: uint8_t elpe; /* Error Log Page Entries */
367: uint8_t npss; /* Number of Power States Support */
368:
369: uint8_t avscc; /* Admin Vendor Specific Command
370: Configuration */
371: uint8_t apsta; /* Autonomous Power State Transition
372: Attributes */
373:
374: uint8_t _reserved2[246];
375:
376: /* NVM Command Set Attributes */
377:
378: uint8_t sqes; /* Submission Queue Entry Size */
1.1.2.3 ! skrll 379: #define NVME_ID_CTRLR_SQES_MAX __BITS(4, 7)
! 380: #define NVME_ID_CTRLR_SQES_MIN __BITS(0, 3)
1.1.2.2 skrll 381: uint8_t cqes; /* Completion Queue Entry Size */
1.1.2.3 ! skrll 382: #define NVME_ID_CTRLR_CQES_MAX __BITS(4, 7)
! 383: #define NVME_ID_CTRLR_CQES_MIN __BITS(0, 3)
1.1.2.2 skrll 384: uint8_t _reserved3[2];
385:
386: uint32_t nn; /* Number of Namespaces */
387:
388: uint16_t oncs; /* Optional NVM Command Support */
1.1.2.3 ! skrll 389: #define NVME_ID_CTRLR_ONCS_RESERVATION __BIT(5)
! 390: #define NVME_ID_CTRLR_ONCS_SET_FEATURES __BIT(4)
! 391: #define NVME_ID_CTRLR_ONCS_WRITE_ZERO __BIT(3)
! 392: #define NVME_ID_CTRLR_ONCS_DSM __BIT(2)
! 393: #define NVME_ID_CTRLR_ONCS_WRITE_UNC __BIT(1)
! 394: #define NVME_ID_CTRLR_ONCS_COMPARE __BIT(0)
1.1.2.2 skrll 395: uint16_t fuses; /* Fused Operation Support */
396:
397: uint8_t fna; /* Format NVM Attributes */
398: uint8_t vwc; /* Volatile Write Cache */
1.1.2.3 ! skrll 399: #define NVME_ID_CTRLR_VWC_PRESENT __BIT(0)
1.1.2.2 skrll 400: uint16_t awun; /* Atomic Write Unit Normal */
401:
402: uint16_t awupf; /* Atomic Write Unit Power Fail */
403: uint8_t nvscc; /* NVM Vendor Specific Command */
404: uint8_t _reserved4[1];
405:
406: uint16_t acwu; /* Atomic Compare & Write Unit */
407: uint8_t _reserved5[2];
408:
409: uint32_t sgls; /* SGL Support */
410:
411: uint8_t _reserved6[164];
412:
413: /* I/O Command Set Attributes */
414:
415: uint8_t _reserved7[1344];
416:
417: /* Power State Descriptors */
418:
419: struct nvm_identify_psd psd[32]; /* Power State Descriptors */
420:
421: /* Vendor Specific */
422:
423: uint8_t _reserved8[1024];
424: } __packed __aligned(8);
425:
426: struct nvm_namespace_format {
427: uint16_t ms; /* Metadata Size */
428: uint8_t lbads; /* LBA Data Size */
429: uint8_t rp; /* Relative Performance */
430: } __packed __aligned(4);
431:
432: struct nvm_identify_namespace {
433: uint64_t nsze; /* Namespace Size */
434:
435: uint64_t ncap; /* Namespace Capacity */
436:
437: uint64_t nuse; /* Namespace Utilization */
438:
439: uint8_t nsfeat; /* Namespace Features */
1.1.2.3 ! skrll 440: #define NVME_ID_NS_NSFEAT_LOGICAL_BLK_ERR __BIT(2)
! 441: #define NVME_ID_NS_NSFEAT_NS __BIT(1)
! 442: #define NVME_ID_NS_NSFEAT_THIN_PROV __BIT(0)
1.1.2.2 skrll 443: uint8_t nlbaf; /* Number of LBA Formats */
444: uint8_t flbas; /* Formatted LBA Size */
445: #define NVME_ID_NS_FLBAS(_f) ((_f) & 0x0f)
446: #define NVME_ID_NS_FLBAS_MD 0x10
447: uint8_t mc; /* Metadata Capabilities */
448: uint8_t dpc; /* End-to-end Data Protection
449: Capabilities */
450: uint8_t dps; /* End-to-end Data Protection Type Settings */
451:
452: uint8_t _reserved1[98];
453:
454: struct nvm_namespace_format
455: lbaf[16]; /* LBA Format Support */
456:
457: uint8_t _reserved2[192];
458:
459: uint8_t vs[3712];
460: } __packed __aligned(8);
1.1.2.3 ! skrll 461:
! 462: #endif /* __NVMEREG_H__ */
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