Annotation of src/sys/dev/ic/mvsata.c, Revision 1.34
1.34 ! christos 1: /* $NetBSD: mvsata.c,v 1.33 2014/02/17 13:41:20 kiyohara Exp $ */
1.1 kiyohara 2: /*
3: * Copyright (c) 2008 KIYOHARA Takashi
4: * All rights reserved.
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: *
15: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25: * POSSIBILITY OF SUCH DAMAGE.
26: */
27:
28: #include <sys/cdefs.h>
1.34 ! christos 29: __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.33 2014/02/17 13:41:20 kiyohara Exp $");
1.1 kiyohara 30:
31: #include "opt_mvsata.h"
32:
1.24 bouyer 33: /* ATAPI implementation not finished. */
1.1 kiyohara 34: //#include "atapibus.h"
35:
36: #include <sys/param.h>
37: #if NATAPIBUS > 0
38: #include <sys/buf.h>
39: #endif
40: #include <sys/bus.h>
41: #include <sys/cpu.h>
42: #include <sys/device.h>
43: #include <sys/disklabel.h>
44: #include <sys/errno.h>
45: #include <sys/kernel.h>
46: #include <sys/malloc.h>
47: #include <sys/proc.h>
48:
49: #include <machine/vmparam.h>
50:
51: #include <dev/ata/atareg.h>
52: #include <dev/ata/atavar.h>
53: #include <dev/ic/wdcvar.h>
1.29 jakllsch 54: #include <dev/ata/satapmpreg.h>
1.1 kiyohara 55: #include <dev/ata/satareg.h>
56: #include <dev/ata/satavar.h>
57:
58: #if NATAPIBUS > 0
59: #include <dev/scsipi/scsi_all.h> /* for SCSI status */
60: #endif
61:
62: #include <dev/pci/pcidevs.h>
63:
64: #include <dev/ic/mvsatareg.h>
65: #include <dev/ic/mvsatavar.h>
66:
67:
68: #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev)
69: #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev)
70:
71: #define MVSATA_HC_READ_4(hc, reg) \
72: bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg))
73: #define MVSATA_HC_WRITE_4(hc, reg, val) \
74: bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val))
75: #define MVSATA_EDMA_READ_4(mvport, reg) \
76: bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg))
77: #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \
78: bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val))
79: #define MVSATA_WDC_READ_2(mvport, reg) \
1.24 bouyer 80: bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, \
81: SHADOW_REG_BLOCK_OFFSET + (reg))
1.1 kiyohara 82: #define MVSATA_WDC_READ_1(mvport, reg) \
1.24 bouyer 83: bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, \
84: SHADOW_REG_BLOCK_OFFSET + (reg))
1.1 kiyohara 85: #define MVSATA_WDC_WRITE_2(mvport, reg, val) \
1.24 bouyer 86: bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, \
87: SHADOW_REG_BLOCK_OFFSET + (reg), (val))
1.1 kiyohara 88: #define MVSATA_WDC_WRITE_1(mvport, reg, val) \
1.24 bouyer 89: bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, \
90: SHADOW_REG_BLOCK_OFFSET + (reg), (val))
1.1 kiyohara 91:
92: #ifdef MVSATA_DEBUG
93: #define DPRINTF(x) if (mvsata_debug) printf x
94: #define DPRINTFN(n,x) if (mvsata_debug >= (n)) printf x
1.10 jakllsch 95: int mvsata_debug = 2;
1.1 kiyohara 96: #else
97: #define DPRINTF(x)
98: #define DPRINTFN(n,x)
99: #endif
100:
101: #define ATA_DELAY 10000 /* 10s for a drive I/O */
102: #define ATAPI_DELAY 10 /* 10 ms, this is used only before
103: sending a cmd */
1.2 snj 104: #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */
1.1 kiyohara 105:
106: #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * (MAXPHYS / PAGE_SIZE))
107:
108:
1.32 kiyohara 109: static void mvsata_probe_drive(struct ata_channel *);
1.1 kiyohara 110: #ifndef MVSATA_WITHOUTDMA
111: static int mvsata_bio(struct ata_drive_datas *, struct ata_bio *);
1.24 bouyer 112: static void mvsata_reset_drive(struct ata_drive_datas *, int, uint32_t *);
1.1 kiyohara 113: static void mvsata_reset_channel(struct ata_channel *, int);
114: static int mvsata_exec_command(struct ata_drive_datas *, struct ata_command *);
115: static int mvsata_addref(struct ata_drive_datas *);
116: static void mvsata_delref(struct ata_drive_datas *);
117: static void mvsata_killpending(struct ata_drive_datas *);
118:
119: #if NATAPIBUS > 0
120: static void mvsata_atapibus_attach(struct atabus_softc *);
121: static void mvsata_atapi_scsipi_request(struct scsipi_channel *,
122: scsipi_adapter_req_t, void *);
123: static void mvsata_atapi_minphys(struct buf *);
124: static void mvsata_atapi_probe_device(struct atapibus_softc *, int);
125: static void mvsata_atapi_kill_pending(struct scsipi_periph *);
126: #endif
127: #endif
128:
129: static void mvsata_setup_channel(struct ata_channel *);
130:
131: #ifndef MVSATA_WITHOUTDMA
132: static void mvsata_bio_start(struct ata_channel *, struct ata_xfer *);
133: static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int);
134: static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int);
135: static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *);
136: static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int,
137: int);
138: static void mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *);
139: static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int);
140: static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *,
141: int);
142: static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *);
143: static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *);
144: #if NATAPIBUS > 0
145: static void mvsata_atapi_start(struct ata_channel *, struct ata_xfer *);
146: static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int);
147: static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *,
148: int);
149: static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *);
150: static void mvsata_atapi_phase_complete(struct ata_xfer *);
151: static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *);
152: static void mvsata_atapi_polldsc(void *);
153: #endif
154:
1.9 jakllsch 155: static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_bio *, void *);
1.1 kiyohara 156: static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *);
157: static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int);
158: static void mvsata_edma_timeout(void *);
159: static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *);
160: #if NATAPIBUS > 0
161: static int mvsata_bdma_init(struct mvsata_port *, struct scsipi_xfer *, void *);
162: static void mvsata_bdma_start(struct mvsata_port *);
163: #endif
164: #endif
165:
166: static int mvsata_port_init(struct mvsata_hc *, int);
167: static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *);
168: #ifndef MVSATA_WITHOUTDMA
169: static inline void mvsata_quetag_init(struct mvsata_port *);
170: static inline int mvsata_quetag_get(struct mvsata_port *);
171: static inline void mvsata_quetag_put(struct mvsata_port *, int);
172: static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t,
173: bus_dmamap_t *, size_t, int);
174: static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t,
175: bus_dmamap_t, void *);
176: static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int);
177: static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int);
178: #endif
179:
180: static void mvsata_hreset_port(struct mvsata_port *);
181: static void mvsata_reset_port(struct mvsata_port *);
182: static void mvsata_reset_hc(struct mvsata_hc *);
1.29 jakllsch 183: static uint32_t mvsata_softreset(struct mvsata_port *, int);
1.1 kiyohara 184: #ifndef MVSATA_WITHOUTDMA
185: static void mvsata_edma_reset_qptr(struct mvsata_port *);
186: static inline void mvsata_edma_enable(struct mvsata_port *);
187: static int mvsata_edma_disable(struct mvsata_port *, int, int);
188: static void mvsata_edma_config(struct mvsata_port *, int);
189:
190: static void mvsata_edma_setup_crqb(struct mvsata_port *, int, int,
191: struct ata_bio *);
192: #endif
193: static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *);
194: static void mvsata_fix_phy_gen1(struct mvsata_port *);
195: static void mvsata_devconn_gen1(struct mvsata_port *);
196:
197: static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *);
198: static void mvsata_fix_phy_gen2(struct mvsata_port *);
199: #ifndef MVSATA_WITHOUTDMA
200: static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, int,
201: struct ata_bio *);
202:
203: #ifdef MVSATA_DEBUG
204: static void mvsata_print_crqb(struct mvsata_port *, int);
205: static void mvsata_print_crpb(struct mvsata_port *, int);
206: static void mvsata_print_eprd(struct mvsata_port *, int);
207: #endif
208:
209: struct ata_bustype mvsata_ata_bustype = {
210: SCSIPI_BUSTYPE_ATA,
211: mvsata_bio,
212: mvsata_reset_drive,
213: mvsata_reset_channel,
214: mvsata_exec_command,
215: ata_get_params,
216: mvsata_addref,
217: mvsata_delref,
218: mvsata_killpending
219: };
220:
221: #if NATAPIBUS > 0
222: static const struct scsipi_bustype mvsata_atapi_bustype = {
223: SCSIPI_BUSTYPE_ATAPI,
224: atapi_scsipi_cmd,
225: atapi_interpret_sense,
226: atapi_print_addr,
227: mvsata_atapi_kill_pending,
1.16 bouyer 228: NULL,
1.1 kiyohara 229: };
230: #endif /* NATAPIBUS */
231: #endif
232:
1.29 jakllsch 233: static void
234: mvsata_pmp_select(struct mvsata_port *mvport, int pmpport)
235: {
236: uint32_t ifctl;
237:
238: KASSERT(pmpport < PMP_MAX_DRIVES);
239: #if defined(DIAGNOSTIC) || defined(MVSATA_DEBUG)
240: if ((MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) != 0) {
241: panic("EDMA enabled");
242: }
243: #endif
244:
245: ifctl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL);
246: ifctl &= ~0xf;
247: ifctl |= pmpport;
248: MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICTL, ifctl);
249: }
1.1 kiyohara 250:
251: int
1.5 kiyohara 252: mvsata_attach(struct mvsata_softc *sc, struct mvsata_product *product,
1.1 kiyohara 253: int (*mvsata_sreset)(struct mvsata_softc *),
254: int (*mvsata_misc_reset)(struct mvsata_softc *),
255: int read_pre_amps)
256: {
257: struct mvsata_hc *mvhc;
258: struct mvsata_port *mvport;
259: uint32_t (*read_preamps)(struct mvsata_port *) = NULL;
260: void (*_fix_phy)(struct mvsata_port *) = NULL;
261: #ifndef MVSATA_WITHOUTDMA
262: void (*edma_setup_crqb)
263: (struct mvsata_port *, int, int, struct ata_bio *) = NULL;
264: #endif
1.5 kiyohara 265: int hc, port, channel;
1.1 kiyohara 266:
267: aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n",
268: (product->generation == gen1) ? "I" :
269: ((product->generation == gen2) ? "II" : "IIe"),
270: product->hc, product->port);
271:
272:
273: switch (product->generation) {
274: case gen1:
275: mvsata_sreset = NULL;
276: read_pre_amps = 1; /* MUST */
277: read_preamps = mvsata_read_preamps_gen1;
278: _fix_phy = mvsata_fix_phy_gen1;
279: #ifndef MVSATA_WITHOUTDMA
280: edma_setup_crqb = mvsata_edma_setup_crqb;
281: #endif
282: break;
283:
284: case gen2:
285: read_preamps = mvsata_read_preamps_gen2;
286: _fix_phy = mvsata_fix_phy_gen2;
287: #ifndef MVSATA_WITHOUTDMA
288: edma_setup_crqb = mvsata_edma_setup_crqb;
289: #endif
290: break;
291:
292: case gen2e:
293: read_preamps = mvsata_read_preamps_gen2;
294: _fix_phy = mvsata_fix_phy_gen2;
295: #ifndef MVSATA_WITHOUTDMA
296: edma_setup_crqb = mvsata_edma_setup_crqb_gen2e;
297: #endif
298: break;
299: }
300:
1.5 kiyohara 301: sc->sc_gen = product->generation;
302: sc->sc_hc = product->hc;
303: sc->sc_port = product->port;
304: sc->sc_flags = product->flags;
1.1 kiyohara 305:
306: #ifdef MVSATA_WITHOUTDMA
307: sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
308: #else
1.3 mbalmer 309: sc->sc_edma_setup_crqb = edma_setup_crqb;
1.1 kiyohara 310: sc->sc_wdcdev.sc_atac.atac_cap |=
311: (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA);
312: #endif
313: sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
1.6 kiyohara 314: #ifdef MVSATA_WITHOUTDMA
1.1 kiyohara 315: sc->sc_wdcdev.sc_atac.atac_dma_cap = 0;
316: sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
317: #else
318: sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
319: sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
320: #endif
321: sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels;
322: sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port;
323: #ifndef MVSATA_WITHOUTDMA
324: sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype;
325: #if NATAPIBUS > 0
326: sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach;
327: #endif
328: #endif
1.24 bouyer 329: sc->sc_wdcdev.wdc_maxdrives = 1; /* SATA is always 1 drive */
1.29 jakllsch 330: sc->sc_wdcdev.sc_atac.atac_probe = mvsata_probe_drive;
1.1 kiyohara 331: sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel;
332:
333: sc->sc_wdc_regs =
334: malloc(sizeof(struct wdc_regs) * product->hc * product->port,
335: M_DEVBUF, M_NOWAIT);
336: if (sc->sc_wdc_regs == NULL) {
337: aprint_error_dev(MVSATA_DEV(sc),
338: "can't allocate wdc regs memory\n");
339: return ENOMEM;
340: }
341: sc->sc_wdcdev.regs = sc->sc_wdc_regs;
342:
343: for (hc = 0; hc < sc->sc_hc; hc++) {
344: mvhc = &sc->sc_hcs[hc];
345: mvhc->hc = hc;
346: mvhc->hc_sc = sc;
347: mvhc->hc_iot = sc->sc_iot;
348: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
349: hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE,
350: &mvhc->hc_ioh)) {
351: aprint_error_dev(MVSATA_DEV(sc),
352: "can't subregion SATAHC %d registers\n", hc);
353: continue;
354: }
355:
356: for (port = 0; port < sc->sc_port; port++)
357: if (mvsata_port_init(mvhc, port) == 0) {
358: int pre_amps;
359:
360: mvport = mvhc->hc_ports[port];
361: pre_amps = read_pre_amps ?
362: read_preamps(mvport) : 0x00000720;
363: mvport->_fix_phy_param.pre_amps = pre_amps;
364: mvport->_fix_phy_param._fix_phy = _fix_phy;
365:
366: if (!mvsata_sreset)
367: mvsata_reset_port(mvport);
368: }
369:
370: if (!mvsata_sreset)
371: mvsata_reset_hc(mvhc);
372: }
373: if (mvsata_sreset)
374: mvsata_sreset(sc);
375:
376: if (mvsata_misc_reset)
377: mvsata_misc_reset(sc);
378:
379: for (hc = 0; hc < sc->sc_hc; hc++)
380: for (port = 0; port < sc->sc_port; port++) {
381: mvport = sc->sc_hcs[hc].hc_ports[port];
382: if (mvport == NULL)
383: continue;
384: if (mvsata_sreset)
385: mvport->_fix_phy_param._fix_phy(mvport);
386: }
387: for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++)
388: wdcattach(sc->sc_ata_channels[channel]);
389:
390: return 0;
391: }
392:
393: int
394: mvsata_intr(struct mvsata_hc *mvhc)
395: {
396: struct mvsata_softc *sc = mvhc->hc_sc;
397: struct mvsata_port *mvport;
398: uint32_t cause;
399: int port, handled = 0;
400:
401: cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC);
402:
403: DPRINTFN(3, ("%s:%d: mvsata_intr: cause=0x%08x\n",
404: device_xname(MVSATA_DEV(sc)), mvhc->hc, cause));
405:
406: if (cause & SATAHC_IC_SAINTCOAL)
407: MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL);
408: cause &= ~SATAHC_IC_SAINTCOAL;
409: for (port = 0; port < sc->sc_port; port++) {
410: mvport = mvhc->hc_ports[port];
411:
412: if (cause & SATAHC_IC_DONE(port)) {
413: #ifndef MVSATA_WITHOUTDMA
414: handled = mvsata_edma_handle(mvport, NULL);
415: #endif
416: MVSATA_HC_WRITE_4(mvhc, SATAHC_IC,
417: ~SATAHC_IC_DONE(port));
418: }
419:
420: if (cause & SATAHC_IC_SADEVINTERRUPT(port)) {
421: wdcintr(&mvport->port_ata_channel);
422: MVSATA_HC_WRITE_4(mvhc, SATAHC_IC,
423: ~SATAHC_IC_SADEVINTERRUPT(port));
424: handled = 1;
425: }
426: }
427:
428: return handled;
429: }
430:
431: int
432: mvsata_error(struct mvsata_port *mvport)
433: {
434: struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
435: uint32_t cause;
436:
437: cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC);
1.29 jakllsch 438: /*
439: * We must ack SATA_SE and SATA_FISIC before acking coresponding bits
440: * in EDMA_IEC.
441: */
442: if (cause & EDMA_IE_SERRINT) {
443: MVSATA_EDMA_WRITE_4(mvport, SATA_SE,
444: MVSATA_EDMA_READ_4(mvport, SATA_SEIM));
445: }
446: if (cause & EDMA_IE_ETRANSINT) {
447: MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC,
448: ~MVSATA_EDMA_READ_4(mvport, SATA_FISIM));
449: }
1.1 kiyohara 450: MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause);
451:
452: DPRINTFN(3, ("%s:%d:%d:"
453: " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n",
454: device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc,
455: mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM),
456: MVSATA_EDMA_READ_4(mvport, EDMA_S)));
457:
458: cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM);
459: if (!cause)
460: return 0;
461:
1.29 jakllsch 462: if (cause & EDMA_IE_EDEVDIS) {
1.1 kiyohara 463: aprint_normal("%s:%d:%d: device disconnect\n",
464: device_xname(MVSATA_DEV2(mvport)),
465: mvport->port_hc->hc, mvport->port);
1.29 jakllsch 466: }
1.1 kiyohara 467: if (cause & EDMA_IE_EDEVCON) {
468: if (sc->sc_gen == gen1)
469: mvsata_devconn_gen1(mvport);
470:
471: DPRINTFN(3, (" device connected\n"));
472: }
473: #ifndef MVSATA_WITHOUTDMA
474: if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) ||
475: (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) {
476: switch (mvport->port_edmamode) {
477: case dma:
478: case queued:
479: case ncq:
480: mvsata_edma_reset_qptr(mvport);
481: mvsata_edma_enable(mvport);
482: if (cause & EDMA_IE_EDEVERR)
483: break;
484:
485: /* FALLTHROUGH */
486:
487: case nodma:
488: default:
489: aprint_error(
490: "%s:%d:%d: EDMA self disable happen 0x%x\n",
491: device_xname(MVSATA_DEV2(mvport)),
492: mvport->port_hc->hc, mvport->port, cause);
493: break;
494: }
495: }
496: #endif
497: if (cause & EDMA_IE_ETRANSINT) {
498: /* hot plug the Port Multiplier */
499: aprint_normal("%s:%d:%d: detect Port Multiplier?\n",
500: device_xname(MVSATA_DEV2(mvport)),
501: mvport->port_hc->hc, mvport->port);
502: }
503:
1.29 jakllsch 504: return 1;
1.1 kiyohara 505: }
506:
507:
508: /*
509: * ATA callback entry points
510: */
511:
1.29 jakllsch 512: static void
513: mvsata_probe_drive(struct ata_channel *chp)
514: {
515: struct mvsata_port * const mvport = (struct mvsata_port *)chp;
516: uint32_t sstat, sig;
517:
518: sstat = sata_reset_interface(chp, mvport->port_iot,
1.30 bouyer 519: mvport->port_sata_scontrol, mvport->port_sata_sstatus, AT_WAIT);
1.29 jakllsch 520: switch (sstat) {
521: case SStatus_DET_DEV:
522: mvsata_pmp_select(mvport, PMP_PORT_CTL);
523: sig = mvsata_softreset(mvport, AT_WAIT);
524: sata_interpret_sig(chp, 0, sig);
525: break;
526: default:
527: break;
528: }
529: }
530:
1.1 kiyohara 531: #ifndef MVSATA_WITHOUTDMA
532: static int
533: mvsata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio)
534: {
535: struct ata_channel *chp = drvp->chnl_softc;
536: struct atac_softc *atac = chp->ch_atac;
537: struct ata_xfer *xfer;
538:
1.7 riz 539: DPRINTFN(1, ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64
540: ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel,
541: drvp->drive, ata_bio->blkno, ata_bio->bcount));
1.1 kiyohara 542:
543: xfer = ata_get_xfer(ATAXF_NOSLEEP);
544: if (xfer == NULL)
545: return ATACMD_TRY_AGAIN;
546: if (atac->atac_cap & ATAC_CAP_NOIRQ)
547: ata_bio->flags |= ATA_POLL;
548: if (ata_bio->flags & ATA_POLL)
549: xfer->c_flags |= C_POLL;
1.24 bouyer 550: if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) &&
1.1 kiyohara 551: (ata_bio->flags & ATA_SINGLE) == 0)
552: xfer->c_flags |= C_DMA;
553: xfer->c_drive = drvp->drive;
554: xfer->c_cmd = ata_bio;
555: xfer->c_databuf = ata_bio->databuf;
556: xfer->c_bcount = ata_bio->bcount;
557: xfer->c_start = mvsata_bio_start;
558: xfer->c_intr = mvsata_bio_intr;
559: xfer->c_kill_xfer = mvsata_bio_kill_xfer;
560: ata_exec_xfer(chp, xfer);
561: return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED;
562: }
563:
564: static void
1.24 bouyer 565: mvsata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp)
1.1 kiyohara 566: {
567: struct ata_channel *chp = drvp->chnl_softc;
568: struct mvsata_port *mvport = (struct mvsata_port *)chp;
569: uint32_t edma_c;
1.29 jakllsch 570: uint32_t sig;
1.24 bouyer 571:
1.1 kiyohara 572: edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD);
573:
574: DPRINTF(("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n",
575: device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive,
576: (edma_c & EDMA_CMD_EENEDMA) ? "" : "not "));
577:
578: if (edma_c & EDMA_CMD_EENEDMA)
579: mvsata_edma_disable(mvport, 10000, flags & AT_WAIT);
580:
1.29 jakllsch 581: mvsata_pmp_select(mvport, drvp->drive);
582:
583: sig = mvsata_softreset(mvport, flags & AT_WAIT);
584:
585: if (sigp)
586: *sigp = sig;
1.1 kiyohara 587:
588: if (edma_c & EDMA_CMD_EENEDMA) {
589: mvsata_edma_reset_qptr(mvport);
590: mvsata_edma_enable(mvport);
591: }
592: return;
593: }
594:
595: static void
596: mvsata_reset_channel(struct ata_channel *chp, int flags)
597: {
598: struct mvsata_port *mvport = (struct mvsata_port *)chp;
599: struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
600: struct ata_xfer *xfer;
601: uint32_t sstat, ctrl;
602: int i;
603:
604: DPRINTF(("%s: mvsata_reset_channel: channel=%d\n",
605: device_xname(MVSATA_DEV2(mvport)), chp->ch_channel));
606:
607: mvsata_hreset_port(mvport);
608: sstat = sata_reset_interface(chp, mvport->port_iot,
1.30 bouyer 609: mvport->port_sata_scontrol, mvport->port_sata_sstatus, flags);
1.1 kiyohara 610:
611: if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE &&
612: sc->sc_gen != gen1) {
613: /* Downgrade to GenI */
614: const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY |
615: SControl_DET_DISABLE;
616:
617: MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val);
618:
619: ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG);
620: ctrl &= ~(1 << 17); /* Disable GenII */
621: MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl);
622:
623: mvsata_hreset_port(mvport);
624: sata_reset_interface(chp, mvport->port_iot,
1.30 bouyer 625: mvport->port_sata_scontrol, mvport->port_sata_sstatus,
626: flags);
1.1 kiyohara 627: }
628:
1.8 jakllsch 629: for (i = 0; i < MVSATA_EDMAQ_LEN; i++) {
1.1 kiyohara 630: xfer = mvport->port_reqtbl[i].xfer;
631: if (xfer == NULL)
632: continue;
633: chp->ch_queue->active_xfer = xfer;
634: xfer->c_kill_xfer(chp, xfer, KILL_RESET);
635: }
636:
637: mvsata_edma_config(mvport, mvport->port_edmamode);
638: mvsata_edma_reset_qptr(mvport);
639: mvsata_edma_enable(mvport);
640: return;
641: }
642:
643:
644: static int
645: mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c)
646: {
647: struct ata_channel *chp = drvp->chnl_softc;
648: #ifdef MVSATA_DEBUG
649: struct mvsata_port *mvport = (struct mvsata_port *)chp;
650: #endif
651: struct ata_xfer *xfer;
652: int rv, s;
653:
654: DPRINTFN(1, ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d,"
1.29 jakllsch 655: " r_lba=0x%012"PRIx64", r_count=0x%04x, r_features=0x%04x,"
656: " r_device=0x%02x, r_command=0x%02x\n",
1.1 kiyohara 657: device_xname(MVSATA_DEV2(mvport)), chp->ch_channel,
1.29 jakllsch 658: drvp->drive, ata_c->bcount, ata_c->r_lba, ata_c->r_count,
659: ata_c->r_features, ata_c->r_device, ata_c->r_command));
1.1 kiyohara 660:
661: xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP :
662: ATAXF_NOSLEEP);
663: if (xfer == NULL)
664: return ATACMD_TRY_AGAIN;
665: if (ata_c->flags & AT_POLL)
666: xfer->c_flags |= C_POLL;
667: if (ata_c->flags & AT_WAIT)
668: xfer->c_flags |= C_WAIT;
669: xfer->c_drive = drvp->drive;
670: xfer->c_databuf = ata_c->data;
671: xfer->c_bcount = ata_c->bcount;
672: xfer->c_cmd = ata_c;
673: xfer->c_start = mvsata_wdc_cmd_start;
674: xfer->c_intr = mvsata_wdc_cmd_intr;
675: xfer->c_kill_xfer = mvsata_wdc_cmd_kill_xfer;
676: s = splbio();
677: ata_exec_xfer(chp, xfer);
678: #ifdef DIAGNOSTIC
679: if ((ata_c->flags & AT_POLL) != 0 &&
680: (ata_c->flags & AT_DONE) == 0)
681: panic("mvsata_exec_command: polled command not done");
682: #endif
683: if (ata_c->flags & AT_DONE)
684: rv = ATACMD_COMPLETE;
685: else {
686: if (ata_c->flags & AT_WAIT) {
687: while ((ata_c->flags & AT_DONE) == 0)
688: tsleep(ata_c, PRIBIO, "mvsatacmd", 0);
689: rv = ATACMD_COMPLETE;
690: } else
691: rv = ATACMD_QUEUED;
692: }
693: splx(s);
694: return rv;
695: }
696:
697: static int
698: mvsata_addref(struct ata_drive_datas *drvp)
699: {
700:
701: return 0;
702: }
703:
704: static void
705: mvsata_delref(struct ata_drive_datas *drvp)
706: {
707:
708: return;
709: }
710:
711: static void
712: mvsata_killpending(struct ata_drive_datas *drvp)
713: {
714:
715: return;
716: }
717:
718: #if NATAPIBUS > 0
719: static void
720: mvsata_atapibus_attach(struct atabus_softc *ata_sc)
721: {
722: struct ata_channel *chp = ata_sc->sc_chan;
723: struct atac_softc *atac = chp->ch_atac;
724: struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
725: struct scsipi_channel *chan = &chp->ch_atapi_channel;
726:
727: /*
728: * Fill in the scsipi_adapter.
729: */
730: adapt->adapt_dev = atac->atac_dev;
731: adapt->adapt_nchannels = atac->atac_nchannels;
732: adapt->adapt_request = mvsata_atapi_scsipi_request;
733: adapt->adapt_minphys = mvsata_atapi_minphys;
734: atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device;
735:
736: /*
737: * Fill in the scsipi_channel.
738: */
739: memset(chan, 0, sizeof(*chan));
740: chan->chan_adapter = adapt;
741: chan->chan_bustype = &mvsata_atapi_bustype;
742: chan->chan_channel = chp->ch_channel;
743: chan->chan_flags = SCSIPI_CHAN_OPENINGS;
744: chan->chan_openings = 1;
745: chan->chan_max_periph = 1;
746: chan->chan_ntargets = 1;
747: chan->chan_nluns = 1;
748:
749: chp->atapibus =
750: config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint);
751: }
752:
753: static void
754: mvsata_atapi_scsipi_request(struct scsipi_channel *chan,
755: scsipi_adapter_req_t req, void *arg)
756: {
757: struct scsipi_adapter *adapt = chan->chan_adapter;
758: struct scsipi_periph *periph;
759: struct scsipi_xfer *sc_xfer;
760: struct mvsata_softc *sc = device_private(adapt->adapt_dev);
761: struct atac_softc *atac = &sc->sc_wdcdev.sc_atac;
762: struct ata_xfer *xfer;
763: int channel = chan->chan_channel;
764: int drive, s;
765:
766: switch (req) {
767: case ADAPTER_REQ_RUN_XFER:
768: sc_xfer = arg;
769: periph = sc_xfer->xs_periph;
770: drive = periph->periph_target;
771:
772: if (!device_is_active(atac->atac_dev)) {
773: sc_xfer->error = XS_DRIVER_STUFFUP;
774: scsipi_done(sc_xfer);
775: return;
776: }
777: xfer = ata_get_xfer(ATAXF_NOSLEEP);
778: if (xfer == NULL) {
779: sc_xfer->error = XS_RESOURCE_SHORTAGE;
780: scsipi_done(sc_xfer);
781: return;
782: }
783:
784: if (sc_xfer->xs_control & XS_CTL_POLL)
785: xfer->c_flags |= C_POLL;
786: xfer->c_drive = drive;
787: xfer->c_flags |= C_ATAPI;
788: xfer->c_cmd = sc_xfer;
789: xfer->c_databuf = sc_xfer->data;
790: xfer->c_bcount = sc_xfer->datalen;
791: xfer->c_start = mvsata_atapi_start;
792: xfer->c_intr = mvsata_atapi_intr;
793: xfer->c_kill_xfer = mvsata_atapi_kill_xfer;
794: xfer->c_dscpoll = 0;
795: s = splbio();
796: ata_exec_xfer(atac->atac_channels[channel], xfer);
797: #ifdef DIAGNOSTIC
798: if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 &&
799: (sc_xfer->xs_status & XS_STS_DONE) == 0)
800: panic("mvsata_atapi_scsipi_request:"
801: " polled command not done");
802: #endif
803: splx(s);
804: return;
805:
806: default:
807: /* Not supported, nothing to do. */
808: ;
809: }
810: }
811:
812: static void
813: mvsata_atapi_minphys(struct buf *bp)
814: {
815:
816: if (bp->b_bcount > MAXPHYS)
817: bp->b_bcount = MAXPHYS;
818: minphys(bp);
819: }
820:
821: static void
822: mvsata_atapi_probe_device(struct atapibus_softc *sc, int target)
823: {
824: struct scsipi_channel *chan = sc->sc_channel;
825: struct scsipi_periph *periph;
826: struct ataparams ids;
827: struct ataparams *id = &ids;
828: struct mvsata_softc *mvc =
829: device_private(chan->chan_adapter->adapt_dev);
830: struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac;
831: struct ata_channel *chp = atac->atac_channels[chan->chan_channel];
832: struct ata_drive_datas *drvp = &chp->ch_drive[target];
833: struct scsipibus_attach_args sa;
834: char serial_number[21], model[41], firmware_revision[9];
835: int s;
836:
837: /* skip if already attached */
838: if (scsipi_lookup_periph(chan, target, 0) != NULL)
839: return;
840:
841: /* if no ATAPI device detected at attach time, skip */
1.24 bouyer 842: if (drvp->drive_type != ATA_DRIVET_ATAPI) {
1.1 kiyohara 843: DPRINTF(("%s:%d: mvsata_atapi_probe_device:"
844: " drive %d not present\n",
845: device_xname(atac->atac_dev), chp->ch_channel, target));
846: return;
847: }
848:
849: /* Some ATAPI devices need a bit more time after software reset. */
850: delay(5000);
851: if (ata_get_params(drvp, AT_WAIT, id) == 0) {
852: #ifdef ATAPI_DEBUG_PROBE
853: log(LOG_DEBUG, "%s:%d: drive %d: cmdsz 0x%x drqtype 0x%x\n",
854: device_xname(atac->atac_dev), chp->ch_channel, target,
855: id->atap_config & ATAPI_CFG_CMD_MASK,
856: id->atap_config & ATAPI_CFG_DRQ_MASK);
857: #endif
858: periph = scsipi_alloc_periph(M_NOWAIT);
859: if (periph == NULL) {
860: aprint_error_dev(atac->atac_dev,
861: "unable to allocate periph"
862: " for channel %d drive %d\n",
863: chp->ch_channel, target);
864: return;
865: }
866: periph->periph_dev = NULL;
867: periph->periph_channel = chan;
868: periph->periph_switch = &atapi_probe_periphsw;
869: periph->periph_target = target;
870: periph->periph_lun = 0;
871: periph->periph_quirks = PQUIRK_ONLYBIG;
872:
873: #ifdef SCSIPI_DEBUG
874: if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI &&
875: SCSIPI_DEBUG_TARGET == target)
876: periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS;
877: #endif
878: periph->periph_type = ATAPI_CFG_TYPE(id->atap_config);
879: if (id->atap_config & ATAPI_CFG_REMOV)
880: periph->periph_flags |= PERIPH_REMOVABLE;
881: if (periph->periph_type == T_SEQUENTIAL) {
882: s = splbio();
1.24 bouyer 883: drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW;
1.1 kiyohara 884: splx(s);
885: }
886:
887: sa.sa_periph = periph;
888: sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config);
889: sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ?
890: T_REMOV : T_FIXED;
891: scsipi_strvis((u_char *)model, 40, id->atap_model, 40);
892: scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 20);
893: scsipi_strvis((u_char *)firmware_revision, 8, id->atap_revision,
894: 8);
895: sa.sa_inqbuf.vendor = model;
896: sa.sa_inqbuf.product = serial_number;
897: sa.sa_inqbuf.revision = firmware_revision;
898:
899: /*
900: * Determine the operating mode capabilities of the device.
901: */
902: if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16)
903: periph->periph_cap |= PERIPH_CAP_CMD16;
904: /* XXX This is gross. */
905: periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK);
906:
907: drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa);
908:
909: if (drvp->drv_softc)
910: ata_probe_caps(drvp);
911: else {
912: s = splbio();
1.24 bouyer 913: drvp->drive_type = ATA_DRIVET_NONE;
1.1 kiyohara 914: splx(s);
915: }
916: } else {
917: DPRINTF(("%s:%d: mvsata_atapi_probe_device:"
918: " ATAPI_IDENTIFY_DEVICE failed for drive %d: error 0x%x\n",
919: device_xname(atac->atac_dev), chp->ch_channel, target,
920: chp->ch_error));
921: s = splbio();
1.24 bouyer 922: drvp->drive_type = ATA_DRIVET_NONE;
1.1 kiyohara 923: splx(s);
924: }
925: }
926:
927: /*
928: * Kill off all pending xfers for a periph.
929: *
930: * Must be called at splbio().
931: */
932: static void
933: mvsata_atapi_kill_pending(struct scsipi_periph *periph)
934: {
935: struct atac_softc *atac =
936: device_private(periph->periph_channel->chan_adapter->adapt_dev);
937: struct ata_channel *chp =
938: atac->atac_channels[periph->periph_channel->chan_channel];
939:
940: ata_kill_pending(&chp->ch_drive[periph->periph_target]);
941: }
942: #endif /* NATAPIBUS > 0 */
943: #endif /* MVSATA_WITHOUTDMA */
944:
945:
946: /*
947: * mvsata_setup_channel()
948: * Setup EDMA registers and prepare/purge DMA resources.
949: * We assuming already stopped the EDMA.
950: */
951: static void
952: mvsata_setup_channel(struct ata_channel *chp)
953: {
954: #if !defined(MVSATA_WITHOUTDMA) || defined(MVSATA_DEBUG)
955: struct mvsata_port *mvport = (struct mvsata_port *)chp;
956: #endif
957: struct ata_drive_datas *drvp;
958: uint32_t edma_mode;
959: int drive, s;
960: #ifndef MVSATA_WITHOUTDMA
961: int i;
962: const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN;
963: const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN;
964: const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN;
965: #endif
966:
967: DPRINTF(("%s:%d: mvsata_setup_channel: ",
968: device_xname(MVSATA_DEV2(mvport)), chp->ch_channel));
969:
970: edma_mode = nodma;
1.24 bouyer 971: for (drive = 0; drive < chp->ch_ndrives; drive++) {
1.1 kiyohara 972: drvp = &chp->ch_drive[drive];
973:
974: /* If no drive, skip */
1.24 bouyer 975: if (drvp->drive_type == ATA_DRIVET_NONE)
1.1 kiyohara 976: continue;
977:
1.24 bouyer 978: if (drvp->drive_flags & ATA_DRIVE_UDMA) {
1.1 kiyohara 979: /* use Ultra/DMA */
980: s = splbio();
1.24 bouyer 981: drvp->drive_flags &= ~ATA_DRIVE_DMA;
1.1 kiyohara 982: splx(s);
983: }
984:
1.24 bouyer 985: if (drvp->drive_flags & (ATA_DRIVE_UDMA | ATA_DRIVE_DMA))
986: if (drvp->drive_type == ATA_DRIVET_ATA)
1.1 kiyohara 987: edma_mode = dma;
988: }
989:
990: DPRINTF(("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : ""));
991:
992: #ifndef MVSATA_WITHOUTDMA
993: if (edma_mode == nodma) {
994: no_edma:
995: if (mvport->port_crqb != NULL)
996: mvsata_edma_resource_purge(mvport, mvport->port_dmat,
997: mvport->port_crqb_dmamap, mvport->port_crqb);
998: if (mvport->port_crpb != NULL)
999: mvsata_edma_resource_purge(mvport, mvport->port_dmat,
1000: mvport->port_crpb_dmamap, mvport->port_crpb);
1001: if (mvport->port_eprd != NULL)
1002: mvsata_edma_resource_purge(mvport, mvport->port_dmat,
1003: mvport->port_eprd_dmamap, mvport->port_eprd);
1004:
1005: return;
1006: }
1007:
1008: if (mvport->port_crqb == NULL)
1009: mvport->port_crqb = mvsata_edma_resource_prepare(mvport,
1010: mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1);
1011: if (mvport->port_crpb == NULL)
1012: mvport->port_crpb = mvsata_edma_resource_prepare(mvport,
1013: mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0);
1014: if (mvport->port_eprd == NULL) {
1015: mvport->port_eprd = mvsata_edma_resource_prepare(mvport,
1016: mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size,
1017: 1);
1018: for (i = 0; i < MVSATA_EDMAQ_LEN; i++) {
1019: mvport->port_reqtbl[i].eprd_offset =
1020: i * MVSATA_EPRD_MAX_SIZE;
1021: mvport->port_reqtbl[i].eprd = mvport->port_eprd +
1022: i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd);
1023: }
1024: }
1025:
1026: if (mvport->port_crqb == NULL || mvport->port_crpb == NULL ||
1027: mvport->port_eprd == NULL) {
1028: aprint_error_dev(MVSATA_DEV2(mvport),
1029: "channel %d: can't use EDMA\n", chp->ch_channel);
1030: s = splbio();
1.24 bouyer 1031: for (drive = 0; drive < chp->ch_ndrives; drive++) {
1.1 kiyohara 1032: drvp = &chp->ch_drive[drive];
1033:
1034: /* If no drive, skip */
1.24 bouyer 1035: if (drvp->drive_type == ATA_DRIVET_NONE)
1.1 kiyohara 1036: continue;
1037:
1.24 bouyer 1038: drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA);
1.1 kiyohara 1039: }
1040: splx(s);
1041: goto no_edma;
1042: }
1043:
1044: mvsata_edma_config(mvport, edma_mode);
1045: mvsata_edma_reset_qptr(mvport);
1046: mvsata_edma_enable(mvport);
1047: #endif
1048: }
1049:
1050: #ifndef MVSATA_WITHOUTDMA
1051: static void
1052: mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer)
1053: {
1054: struct mvsata_port *mvport = (struct mvsata_port *)chp;
1055: struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
1056: struct atac_softc *atac = chp->ch_atac;
1057: struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1058: struct ata_bio *ata_bio = xfer->c_cmd;
1059: struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
1060: int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0;
1061: u_int16_t cyl;
1062: u_int8_t head, sect, cmd = 0;
1063: int nblks, error;
1064:
1065: DPRINTFN(2, ("%s:%d: mvsata_bio_start: drive=%d\n",
1066: device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive));
1067:
1068: if (xfer->c_flags & C_DMA)
1069: if (drvp->n_xfers <= NXFER)
1070: drvp->n_xfers++;
1071:
1072: again:
1073: /*
1074: *
1075: * When starting a multi-sector transfer, or doing single-sector
1076: * transfers...
1077: */
1078: if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) {
1079: if (ata_bio->flags & ATA_SINGLE)
1080: nblks = 1;
1081: else
1082: nblks = xfer->c_bcount / ata_bio->lp->d_secsize;
1083: /* Check for bad sectors and adjust transfer, if necessary. */
1084: if ((ata_bio->lp->d_flags & D_BADSECT) != 0) {
1085: long blkdiff;
1086: int i;
1087:
1088: for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1;
1089: i++) {
1090: blkdiff -= ata_bio->blkno;
1091: if (blkdiff < 0)
1092: continue;
1093: if (blkdiff == 0)
1094: /* Replace current block of transfer. */
1095: ata_bio->blkno =
1096: ata_bio->lp->d_secperunit -
1097: ata_bio->lp->d_nsectors - i - 1;
1098: if (blkdiff < nblks) {
1099: /* Bad block inside transfer. */
1100: ata_bio->flags |= ATA_SINGLE;
1101: nblks = 1;
1102: }
1103: break;
1104: }
1105: /* Transfer is okay now. */
1106: }
1107: if (xfer->c_flags & C_DMA) {
1108: ata_bio->nblks = nblks;
1109: ata_bio->nbytes = xfer->c_bcount;
1110:
1111: if (xfer->c_flags & C_POLL)
1112: sc->sc_enable_intr(mvport, 0 /*off*/);
1.9 jakllsch 1113: error = mvsata_edma_enqueue(mvport, ata_bio,
1.1 kiyohara 1114: (char *)xfer->c_databuf + xfer->c_skip);
1115: if (error) {
1116: if (error == EINVAL) {
1117: /*
1118: * We can't do DMA on this transfer
1119: * for some reason. Fall back to
1120: * PIO.
1121: */
1122: xfer->c_flags &= ~C_DMA;
1123: error = 0;
1124: goto do_pio;
1125: }
1126: if (error == EBUSY) {
1127: aprint_error_dev(atac->atac_dev,
1128: "channel %d: EDMA Queue full\n",
1129: chp->ch_channel);
1130: /*
1131: * XXXX: Perhaps, after it waits for
1132: * a while, it is necessary to call
1133: * bio_start again.
1134: */
1135: }
1136: ata_bio->error = ERR_DMA;
1137: ata_bio->r_error = 0;
1138: mvsata_bio_done(chp, xfer);
1139: return;
1140: }
1141: chp->ch_flags |= ATACH_DMA_WAIT;
1142: /* start timeout machinery */
1143: if ((xfer->c_flags & C_POLL) == 0)
1144: callout_reset(&chp->ch_callout,
1145: ATA_DELAY / 1000 * hz,
1146: mvsata_edma_timeout, xfer);
1147: /* wait for irq */
1148: goto intr;
1149: } /* else not DMA */
1150: do_pio:
1151: if (ata_bio->flags & ATA_LBA48) {
1152: sect = 0;
1153: cyl = 0;
1154: head = 0;
1155: } else if (ata_bio->flags & ATA_LBA) {
1156: sect = (ata_bio->blkno >> 0) & 0xff;
1157: cyl = (ata_bio->blkno >> 8) & 0xffff;
1158: head = (ata_bio->blkno >> 24) & 0x0f;
1159: head |= WDSD_LBA;
1160: } else {
1161: int blkno = ata_bio->blkno;
1162: sect = blkno % ata_bio->lp->d_nsectors;
1163: sect++; /* Sectors begin with 1, not 0. */
1164: blkno /= ata_bio->lp->d_nsectors;
1165: head = blkno % ata_bio->lp->d_ntracks;
1166: blkno /= ata_bio->lp->d_ntracks;
1167: cyl = blkno;
1168: head |= WDSD_CHS;
1169: }
1170: ata_bio->nblks = min(nblks, ata_bio->multi);
1171: ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize;
1172: KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0);
1173: if (ata_bio->nblks > 1)
1174: cmd = (ata_bio->flags & ATA_READ) ?
1175: WDCC_READMULTI : WDCC_WRITEMULTI;
1176: else
1177: cmd = (ata_bio->flags & ATA_READ) ?
1178: WDCC_READ : WDCC_WRITE;
1179:
1180: /* EDMA disable, if enabled this channel. */
1181: if (mvport->port_edmamode != nodma)
1182: mvsata_edma_disable(mvport, 10 /* ms */, wait_flags);
1183:
1.29 jakllsch 1184: mvsata_pmp_select(mvport, xfer->c_drive);
1185:
1.1 kiyohara 1186: /* Do control operations specially. */
1187: if (__predict_false(drvp->state < READY)) {
1188: /*
1189: * Actually, we want to be careful not to mess with
1190: * the control state if the device is currently busy,
1191: * but we can assume that we never get to this point
1192: * if that's the case.
1193: */
1194: /*
1195: * If it's not a polled command, we need the kernel
1196: * thread
1197: */
1198: if ((xfer->c_flags & C_POLL) == 0 && cpu_intr_p()) {
1199: chp->ch_queue->queue_freeze++;
1200: wakeup(&chp->ch_thread);
1201: return;
1202: }
1203: if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive,
1204: (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) {
1205: mvsata_bio_done(chp, xfer);
1206: return;
1207: }
1208: }
1209:
1210: /* Initiate command! */
1211: MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1212: switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) {
1213: case WDCWAIT_OK:
1214: break;
1215: case WDCWAIT_TOUT:
1216: goto timeout;
1217: case WDCWAIT_THR:
1218: return;
1219: }
1220: if (ata_bio->flags & ATA_LBA48)
1.29 jakllsch 1221: wdccommandext(chp, 0, atacmd_to48(cmd),
1.25 jakllsch 1222: ata_bio->blkno, nblks, 0, WDSD_LBA);
1.1 kiyohara 1223: else
1.29 jakllsch 1224: wdccommand(chp, 0, cmd, cyl,
1.1 kiyohara 1225: head, sect, nblks,
1.34 ! christos 1226: (ata_bio->lp->d_type == DKTYPE_ST506) ?
1.1 kiyohara 1227: ata_bio->lp->d_precompcyl / 4 : 0);
1228:
1229: /* start timeout machinery */
1230: if ((xfer->c_flags & C_POLL) == 0)
1231: callout_reset(&chp->ch_callout,
1232: ATA_DELAY / 1000 * hz, wdctimeout, chp);
1233: } else if (ata_bio->nblks > 1) {
1234: /* The number of blocks in the last stretch may be smaller. */
1235: nblks = xfer->c_bcount / ata_bio->lp->d_secsize;
1236: if (ata_bio->nblks > nblks) {
1237: ata_bio->nblks = nblks;
1238: ata_bio->nbytes = xfer->c_bcount;
1239: }
1240: }
1241: /* If this was a write and not using DMA, push the data. */
1242: if ((ata_bio->flags & ATA_READ) == 0) {
1243: /*
1244: * we have to busy-wait here, we can't rely on running in
1245: * thread context.
1246: */
1247: if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) {
1248: aprint_error_dev(atac->atac_dev,
1249: "channel %d: drive %d timeout waiting for DRQ,"
1250: " st=0x%02x, err=0x%02x\n",
1251: chp->ch_channel, xfer->c_drive, chp->ch_status,
1252: chp->ch_error);
1253: ata_bio->error = TIMEOUT;
1254: mvsata_bio_done(chp, xfer);
1255: return;
1256: }
1257: if (chp->ch_status & WDCS_ERR) {
1258: ata_bio->error = ERROR;
1259: ata_bio->r_error = chp->ch_error;
1260: mvsata_bio_done(chp, xfer);
1261: return;
1262: }
1263:
1264: wdc->dataout_pio(chp, drvp->drive_flags,
1265: (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes);
1266: }
1267:
1268: intr:
1269: /* Wait for IRQ (either real or polled) */
1270: if ((ata_bio->flags & ATA_POLL) == 0) {
1271: chp->ch_flags |= ATACH_IRQ_WAIT;
1272: } else {
1273: /* Wait for at last 400ns for status bit to be valid */
1274: delay(1);
1275: if (chp->ch_flags & ATACH_DMA_WAIT) {
1276: mvsata_edma_wait(mvport, xfer, ATA_DELAY);
1277: sc->sc_enable_intr(mvport, 1 /*on*/);
1278: chp->ch_flags &= ~ATACH_DMA_WAIT;
1279: }
1280: mvsata_bio_intr(chp, xfer, 0);
1281: if ((ata_bio->flags & ATA_ITSDONE) == 0)
1282: goto again;
1283: }
1284: return;
1285:
1286: timeout:
1287: aprint_error_dev(atac->atac_dev,
1288: "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n",
1289: chp->ch_channel, xfer->c_drive, chp->ch_status, chp->ch_error);
1290: ata_bio->error = TIMEOUT;
1291: mvsata_bio_done(chp, xfer);
1292: return;
1293: }
1294:
1295: static int
1296: mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
1297: {
1298: struct atac_softc *atac = chp->ch_atac;
1299: struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1300: struct ata_bio *ata_bio = xfer->c_cmd;
1301: struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
1302:
1303: DPRINTFN(2, ("%s:%d: mvsata_bio_intr: drive=%d\n",
1304: device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive));
1305:
1.10 jakllsch 1306: chp->ch_flags &= ~(ATACH_IRQ_WAIT|ATACH_DMA_WAIT);
1307:
1.1 kiyohara 1308: /*
1.10 jakllsch 1309: * If we missed an interrupt transfer, reset and restart.
1.1 kiyohara 1310: * Don't try to continue transfer, we may have missed cycles.
1311: */
1312: if (xfer->c_flags & C_TIMEOU) {
1313: ata_bio->error = TIMEOUT;
1314: mvsata_bio_done(chp, xfer);
1315: return 1;
1316: }
1317:
1.28 jakllsch 1318: /* Is it not a transfer, but a control operation? */
1319: if (!(xfer->c_flags & C_DMA) && drvp->state < READY) {
1320: aprint_error_dev(atac->atac_dev,
1321: "channel %d: drive %d bad state %d in mvsata_bio_intr\n",
1322: chp->ch_channel, xfer->c_drive, drvp->state);
1323: panic("mvsata_bio_intr: bad state");
1324: }
1325:
1.1 kiyohara 1326: /* Ack interrupt done by wdc_wait_for_unbusy */
1327: if (!(xfer->c_flags & C_DMA) &&
1328: (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL)
1329: == WDCWAIT_TOUT)) {
1330: if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1331: return 0; /* IRQ was not for us */
1332: aprint_error_dev(atac->atac_dev,
1333: "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n",
1334: chp->ch_channel, xfer->c_drive, xfer->c_bcount,
1335: xfer->c_skip);
1336: ata_bio->error = TIMEOUT;
1337: mvsata_bio_done(chp, xfer);
1338: return 1;
1339: }
1340:
1341: if (xfer->c_flags & C_DMA) {
1342: if (ata_bio->error == NOERROR)
1343: goto end;
1344: if (ata_bio->error == ERR_DMA)
1345: ata_dmaerr(drvp,
1346: (xfer->c_flags & C_POLL) ? AT_POLL : 0);
1347: }
1348:
1349: /* if we had an error, end */
1350: if (ata_bio->error != NOERROR) {
1351: mvsata_bio_done(chp, xfer);
1352: return 1;
1353: }
1354:
1355: /* If this was a read and not using DMA, fetch the data. */
1356: if ((ata_bio->flags & ATA_READ) != 0) {
1357: if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) {
1358: aprint_error_dev(atac->atac_dev,
1359: "channel %d: drive %d read intr before drq\n",
1360: chp->ch_channel, xfer->c_drive);
1361: ata_bio->error = TIMEOUT;
1362: mvsata_bio_done(chp, xfer);
1363: return 1;
1364: }
1365: wdc->datain_pio(chp, drvp->drive_flags,
1366: (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes);
1367: }
1368:
1369: end:
1370: ata_bio->blkno += ata_bio->nblks;
1371: ata_bio->blkdone += ata_bio->nblks;
1372: xfer->c_skip += ata_bio->nbytes;
1373: xfer->c_bcount -= ata_bio->nbytes;
1374: /* See if this transfer is complete. */
1375: if (xfer->c_bcount > 0) {
1376: if ((ata_bio->flags & ATA_POLL) == 0)
1377: /* Start the next operation */
1378: mvsata_bio_start(chp, xfer);
1379: else
1380: /* Let mvsata_bio_start do the loop */
1381: return 1;
1382: } else { /* Done with this transfer */
1383: ata_bio->error = NOERROR;
1384: mvsata_bio_done(chp, xfer);
1385: }
1386: return 1;
1387: }
1388:
1389: static void
1390: mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
1391: {
1392: struct mvsata_port *mvport = (struct mvsata_port *)chp;
1393: struct atac_softc *atac = chp->ch_atac;
1394: struct ata_bio *ata_bio = xfer->c_cmd;
1395: int drive = xfer->c_drive;
1396:
1397: DPRINTFN(2, ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n",
1398: device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive));
1399:
1400: /* EDMA restart, if enabled */
1401: if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) {
1402: mvsata_edma_reset_qptr(mvport);
1403: mvsata_edma_enable(mvport);
1404: }
1405:
1406: ata_free_xfer(chp, xfer);
1407:
1408: ata_bio->flags |= ATA_ITSDONE;
1409: switch (reason) {
1410: case KILL_GONE:
1411: ata_bio->error = ERR_NODEV;
1412: break;
1413: case KILL_RESET:
1414: ata_bio->error = ERR_RESET;
1415: break;
1416: default:
1417: aprint_error_dev(atac->atac_dev,
1418: "mvsata_bio_kill_xfer: unknown reason %d\n", reason);
1419: panic("mvsata_bio_kill_xfer");
1420: }
1421: ata_bio->r_error = WDCE_ABRT;
1422: (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
1423: }
1424:
1425: static void
1426: mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer)
1427: {
1428: struct mvsata_port *mvport = (struct mvsata_port *)chp;
1429: struct ata_bio *ata_bio = xfer->c_cmd;
1430: int drive = xfer->c_drive;
1431:
1432: DPRINTFN(2, ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n",
1433: device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive,
1434: (u_int)xfer->c_flags));
1435:
1436: callout_stop(&chp->ch_callout);
1437:
1438: /* EDMA restart, if enabled */
1439: if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) {
1440: mvsata_edma_reset_qptr(mvport);
1441: mvsata_edma_enable(mvport);
1442: }
1443:
1444: /* feed back residual bcount to our caller */
1445: ata_bio->bcount = xfer->c_bcount;
1446:
1447: /* mark controller inactive and free xfer */
1.10 jakllsch 1448: KASSERT(chp->ch_queue->active_xfer != NULL);
1.1 kiyohara 1449: chp->ch_queue->active_xfer = NULL;
1450: ata_free_xfer(chp, xfer);
1451:
1.24 bouyer 1452: if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) {
1.1 kiyohara 1453: ata_bio->error = ERR_NODEV;
1.24 bouyer 1454: chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN;
1.1 kiyohara 1455: wakeup(&chp->ch_queue->active_xfer);
1456: }
1457: ata_bio->flags |= ATA_ITSDONE;
1458: (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
1459: atastart(chp);
1460: }
1461:
1462: static int
1463: mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive,
1464: int flags)
1465: {
1466: struct ata_channel *chp = &mvport->port_ata_channel;
1467: struct atac_softc *atac = chp->ch_atac;
1468: struct ata_drive_datas *drvp = &chp->ch_drive[drive];
1469: const char *errstring;
1470:
1.31 jakllsch 1471: flags |= AT_POLL; /* XXX */
1472:
1.1 kiyohara 1473: /*
1474: * disable interrupts, all commands here should be quick
1.4 snj 1475: * enough to be able to poll, and we don't go here that often
1.1 kiyohara 1476: */
1477: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS);
1478: MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1479: DELAY(10);
1480: errstring = "wait";
1481: if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1482: goto ctrltimeout;
1.29 jakllsch 1483: wdccommandshort(chp, 0, WDCC_RECAL);
1484: /* Wait for at least 400ns for status bit to be valid */
1.1 kiyohara 1485: DELAY(1);
1486: errstring = "recal";
1487: if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1488: goto ctrltimeout;
1489: if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
1490: goto ctrlerror;
1491: /* Don't try to set modes if controller can't be adjusted */
1492: if (atac->atac_set_modes == NULL)
1493: goto geometry;
1494: /* Also don't try if the drive didn't report its mode */
1.24 bouyer 1495: if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0)
1.1 kiyohara 1496: goto geometry;
1.29 jakllsch 1497: wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1.1 kiyohara 1498: 0x08 | drvp->PIO_mode, WDSF_SET_MODE);
1499: errstring = "piomode";
1500: if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1501: goto ctrltimeout;
1502: if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
1503: goto ctrlerror;
1.24 bouyer 1504: if (drvp->drive_flags & ATA_DRIVE_UDMA)
1.29 jakllsch 1505: wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1.1 kiyohara 1506: 0x40 | drvp->UDMA_mode, WDSF_SET_MODE);
1.24 bouyer 1507: else if (drvp->drive_flags & ATA_DRIVE_DMA)
1.29 jakllsch 1508: wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1.1 kiyohara 1509: 0x20 | drvp->DMA_mode, WDSF_SET_MODE);
1510: else
1511: goto geometry;
1512: errstring = "dmamode";
1513: if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1514: goto ctrltimeout;
1515: if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
1516: goto ctrlerror;
1517: geometry:
1518: if (ata_bio->flags & ATA_LBA)
1519: goto multimode;
1.29 jakllsch 1520: wdccommand(chp, 0, WDCC_IDP, ata_bio->lp->d_ncylinders,
1.1 kiyohara 1521: ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors,
1.34 ! christos 1522: (ata_bio->lp->d_type == DKTYPE_ST506) ?
1.1 kiyohara 1523: ata_bio->lp->d_precompcyl / 4 : 0);
1524: errstring = "geometry";
1525: if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1526: goto ctrltimeout;
1527: if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
1528: goto ctrlerror;
1529: multimode:
1530: if (ata_bio->multi == 1)
1531: goto ready;
1.29 jakllsch 1532: wdccommand(chp, 0, WDCC_SETMULTI, 0, 0, 0, ata_bio->multi, 0);
1.1 kiyohara 1533: errstring = "setmulti";
1534: if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1535: goto ctrltimeout;
1536: if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
1537: goto ctrlerror;
1538: ready:
1539: drvp->state = READY;
1540: /*
1541: * The drive is usable now
1542: */
1543: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
1544: delay(10); /* some drives need a little delay here */
1545: return 0;
1546:
1547: ctrltimeout:
1548: aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n",
1549: chp->ch_channel, drive, errstring);
1550: ata_bio->error = TIMEOUT;
1551: goto ctrldone;
1552: ctrlerror:
1553: aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ",
1554: chp->ch_channel, drive, errstring);
1555: if (chp->ch_status & WDCS_DWF) {
1556: aprint_error("drive fault\n");
1557: ata_bio->error = ERR_DF;
1558: } else {
1559: aprint_error("error (%x)\n", chp->ch_error);
1560: ata_bio->r_error = chp->ch_error;
1561: ata_bio->error = ERROR;
1562: }
1563: ctrldone:
1564: drvp->state = 0;
1565: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
1566: return -1;
1567: }
1568:
1569: static void
1570: mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer)
1571: {
1572: struct mvsata_port *mvport = (struct mvsata_port *)chp;
1573: int drive = xfer->c_drive;
1574: int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0;
1575: struct ata_command *ata_c = xfer->c_cmd;
1576:
1577: DPRINTFN(1, ("%s:%d: mvsata_cmd_start: drive=%d\n",
1578: device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive));
1579:
1580: /* First, EDMA disable, if enabled this channel. */
1581: if (mvport->port_edmamode != nodma)
1582: mvsata_edma_disable(mvport, 10 /* ms */, wait_flags);
1583:
1.29 jakllsch 1584: mvsata_pmp_select(mvport, drive);
1585:
1.1 kiyohara 1586: MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1587: switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ,
1588: ata_c->r_st_bmask, ata_c->timeout, wait_flags)) {
1589: case WDCWAIT_OK:
1590: break;
1591: case WDCWAIT_TOUT:
1592: ata_c->flags |= AT_TIMEOU;
1593: mvsata_wdc_cmd_done(chp, xfer);
1594: return;
1595: case WDCWAIT_THR:
1596: return;
1597: }
1598: if (ata_c->flags & AT_POLL)
1599: /* polled command, disable interrupts */
1600: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS);
1.15 jakllsch 1601: if ((ata_c->flags & AT_LBA48) != 0) {
1.29 jakllsch 1602: wdccommandext(chp, 0, ata_c->r_command,
1.25 jakllsch 1603: ata_c->r_lba, ata_c->r_count, ata_c->r_features,
1604: ata_c->r_device & ~0x10);
1.15 jakllsch 1605: } else {
1.29 jakllsch 1606: wdccommand(chp, 0, ata_c->r_command,
1.15 jakllsch 1607: (ata_c->r_lba >> 8) & 0xffff,
1608: (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) |
1609: ((ata_c->r_lba >> 24) & 0x0f),
1610: ata_c->r_lba & 0xff,
1611: ata_c->r_count & 0xff,
1612: ata_c->r_features & 0xff);
1613: }
1.1 kiyohara 1614:
1615: if ((ata_c->flags & AT_POLL) == 0) {
1616: chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
1617: callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz,
1618: wdctimeout, chp);
1619: return;
1620: }
1621: /*
1622: * Polled command. Wait for drive ready or drq. Done in intr().
1623: * Wait for at last 400ns for status bit to be valid.
1624: */
1625: delay(10); /* 400ns delay */
1626: mvsata_wdc_cmd_intr(chp, xfer, 0);
1627: }
1628:
1629: static int
1630: mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
1631: {
1632: struct mvsata_port *mvport = (struct mvsata_port *)chp;
1633: struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1634: struct ata_command *ata_c = xfer->c_cmd;
1635: int bcount = ata_c->bcount;
1636: char *data = ata_c->data;
1637: int wflags;
1638: int drive_flags;
1639:
1640: if (ata_c->r_command == WDCC_IDENTIFY ||
1641: ata_c->r_command == ATAPI_IDENTIFY_DEVICE)
1642: /*
1643: * The IDENTIFY data has been designed as an array of
1644: * u_int16_t, so we can byteswap it on the fly.
1645: * Historically it's what we have always done so keeping it
1646: * here ensure binary backward compatibility.
1647: */
1.24 bouyer 1648: drive_flags = ATA_DRIVE_NOSTREAM |
1.1 kiyohara 1649: chp->ch_drive[xfer->c_drive].drive_flags;
1650: else
1651: /*
1652: * Other data structure are opaque and should be transfered
1653: * as is.
1654: */
1655: drive_flags = chp->ch_drive[xfer->c_drive].drive_flags;
1656:
1657: if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL))
1658: /* both wait and poll, we can tsleep here */
1659: wflags = AT_WAIT | AT_POLL;
1660: else
1661: wflags = AT_POLL;
1662:
1663: again:
1664: DPRINTFN(1, ("%s:%d: mvsata_cmd_intr: drive=%d\n",
1665: device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive));
1666:
1667: /*
1668: * after a ATAPI_SOFT_RESET, the device will have released the bus.
1669: * Reselect again, it doesn't hurt for others commands, and the time
1.13 jakllsch 1670: * penalty for the extra register write is acceptable,
1671: * wdc_exec_command() isn't called often (mostly for autoconfig)
1.1 kiyohara 1672: */
1.15 jakllsch 1673: if ((xfer->c_flags & C_ATAPI) != 0) {
1674: MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1675: }
1.1 kiyohara 1676: if ((ata_c->flags & AT_XFDONE) != 0) {
1677: /*
1678: * We have completed a data xfer. The drive should now be
1679: * in its initial state
1680: */
1681: if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ,
1682: ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0,
1683: wflags) == WDCWAIT_TOUT) {
1684: if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1685: return 0; /* IRQ was not for us */
1686: ata_c->flags |= AT_TIMEOU;
1687: }
1688: goto out;
1689: }
1690: if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask,
1691: (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) {
1692: if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1693: return 0; /* IRQ was not for us */
1694: ata_c->flags |= AT_TIMEOU;
1695: goto out;
1696: }
1.33 kiyohara 1697: delay(20); /* XXXXX: Delay more times. */
1.1 kiyohara 1698: if (ata_c->flags & AT_READ) {
1699: if ((chp->ch_status & WDCS_DRQ) == 0) {
1700: ata_c->flags |= AT_TIMEOU;
1701: goto out;
1702: }
1703: wdc->datain_pio(chp, drive_flags, data, bcount);
1704: /* at this point the drive should be in its initial state */
1705: ata_c->flags |= AT_XFDONE;
1706: /*
1707: * XXX checking the status register again here cause some
1708: * hardware to timeout.
1709: */
1710: } else if (ata_c->flags & AT_WRITE) {
1711: if ((chp->ch_status & WDCS_DRQ) == 0) {
1712: ata_c->flags |= AT_TIMEOU;
1713: goto out;
1714: }
1715: wdc->dataout_pio(chp, drive_flags, data, bcount);
1716: ata_c->flags |= AT_XFDONE;
1717: if ((ata_c->flags & AT_POLL) == 0) {
1718: chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for intr */
1719: callout_reset(&chp->ch_callout,
1720: mstohz(ata_c->timeout), wdctimeout, chp);
1721: return 1;
1722: } else
1723: goto again;
1724: }
1725: out:
1726: mvsata_wdc_cmd_done(chp, xfer);
1727: return 1;
1728: }
1729:
1730: static void
1731: mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer,
1732: int reason)
1733: {
1734: struct mvsata_port *mvport = (struct mvsata_port *)chp;
1735: struct ata_command *ata_c = xfer->c_cmd;
1736:
1737: DPRINTFN(1, ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n",
1738: device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive));
1739:
1740: switch (reason) {
1741: case KILL_GONE:
1742: ata_c->flags |= AT_GONE;
1743: break;
1744: case KILL_RESET:
1745: ata_c->flags |= AT_RESET;
1746: break;
1747: default:
1748: aprint_error_dev(MVSATA_DEV2(mvport),
1749: "mvsata_cmd_kill_xfer: unknown reason %d\n", reason);
1750: panic("mvsata_cmd_kill_xfer");
1751: }
1752: mvsata_wdc_cmd_done_end(chp, xfer);
1753: }
1754:
1755: static void
1756: mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer)
1757: {
1758: struct mvsata_port *mvport = (struct mvsata_port *)chp;
1759: struct atac_softc *atac = chp->ch_atac;
1760: struct ata_command *ata_c = xfer->c_cmd;
1761:
1762: DPRINTFN(1, ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n",
1763: device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
1764: ata_c->flags));
1765:
1766: if (chp->ch_status & WDCS_DWF)
1767: ata_c->flags |= AT_DF;
1768: if (chp->ch_status & WDCS_ERR) {
1769: ata_c->flags |= AT_ERROR;
1770: ata_c->r_error = chp->ch_error;
1771: }
1772: if ((ata_c->flags & AT_READREG) != 0 &&
1773: device_is_active(atac->atac_dev) &&
1774: (ata_c->flags & (AT_ERROR | AT_DF)) == 0) {
1.15 jakllsch 1775: ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS);
1776: ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE);
1.1 kiyohara 1777: ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC);
1.15 jakllsch 1778: ata_c->r_lba =
1779: (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0;
1780: ata_c->r_lba |=
1781: (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8;
1782: ata_c->r_lba |=
1783: (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16;
1784: ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H);
1785: if ((ata_c->flags & AT_LBA48) != 0) {
1786: if ((ata_c->flags & AT_POLL) != 0) {
1787: MVSATA_WDC_WRITE_1(mvport, SRB_CAS,
1788: WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS);
1789: } else {
1790: MVSATA_WDC_WRITE_1(mvport, SRB_CAS,
1791: WDCTL_HOB|WDCTL_4BIT);
1792: }
1793: ata_c->r_count |=
1794: MVSATA_WDC_READ_1(mvport, SRB_SC) << 8;
1.24 bouyer 1795: ata_c->r_lba |=
1.15 jakllsch 1796: (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24;
1797: ata_c->r_lba |=
1798: (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32;
1799: ata_c->r_lba |=
1800: (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40;
1801: if ((ata_c->flags & AT_POLL) != 0) {
1802: MVSATA_WDC_WRITE_1(mvport, SRB_CAS,
1803: WDCTL_4BIT|WDCTL_IDS);
1804: } else {
1805: MVSATA_WDC_WRITE_1(mvport, SRB_CAS,
1806: WDCTL_4BIT);
1807: }
1808: } else {
1809: ata_c->r_lba |=
1810: (uint64_t)(ata_c->r_device & 0x0f) << 24;
1811: }
1.1 kiyohara 1812: }
1813: callout_stop(&chp->ch_callout);
1814: chp->ch_queue->active_xfer = NULL;
1815: if (ata_c->flags & AT_POLL) {
1816: /* enable interrupts */
1817: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
1818: delay(10); /* some drives need a little delay here */
1819: }
1.24 bouyer 1820: if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) {
1.1 kiyohara 1821: mvsata_wdc_cmd_kill_xfer(chp, xfer, KILL_GONE);
1.24 bouyer 1822: chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN;
1.1 kiyohara 1823: wakeup(&chp->ch_queue->active_xfer);
1824: } else
1825: mvsata_wdc_cmd_done_end(chp, xfer);
1826: }
1827:
1828: static void
1829: mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer)
1830: {
1831: struct mvsata_port *mvport = (struct mvsata_port *)chp;
1832: struct ata_command *ata_c = xfer->c_cmd;
1833:
1834: /* EDMA restart, if enabled */
1835: if (mvport->port_edmamode != nodma) {
1836: mvsata_edma_reset_qptr(mvport);
1837: mvsata_edma_enable(mvport);
1838: }
1839:
1840: ata_c->flags |= AT_DONE;
1841: ata_free_xfer(chp, xfer);
1842: if (ata_c->flags & AT_WAIT)
1843: wakeup(ata_c);
1844: else if (ata_c->callback)
1845: ata_c->callback(ata_c->callback_arg);
1846: atastart(chp);
1847:
1848: return;
1849: }
1850:
1851: #if NATAPIBUS > 0
1852: static void
1853: mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer)
1854: {
1855: struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac;
1856: struct mvsata_port *mvport = (struct mvsata_port *)chp;
1857: struct atac_softc *atac = &sc->sc_wdcdev.sc_atac;
1858: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1859: struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
1860: const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0;
1861: const char *errstring;
1862:
1863: DPRINTFN(2, ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n",
1864: device_xname(chp->ch_atac->atac_dev), chp->ch_channel,
1865: xfer->c_drive, sc_xfer->xs_control));
1866:
1867: if (mvport->port_edmamode != nodma)
1868: mvsata_edma_disable(mvport, 10 /* ms */, wait_flags);
1869:
1.29 jakllsch 1870: mvsata_pmp_select(mvport, xfer->c_drive);
1871:
1.1 kiyohara 1872: if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER))
1873: drvp->n_xfers++;
1874:
1875: /* Do control operations specially. */
1876: if (__predict_false(drvp->state < READY)) {
1877: /* If it's not a polled command, we need the kernel thread */
1878: if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && cpu_intr_p()) {
1879: chp->ch_queue->queue_freeze++;
1880: wakeup(&chp->ch_thread);
1881: return;
1882: }
1883: /*
1884: * disable interrupts, all commands here should be quick
1.4 snj 1885: * enough to be able to poll, and we don't go here that often
1.1 kiyohara 1886: */
1887: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS);
1888:
1889: MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1890: /* Don't try to set mode if controller can't be adjusted */
1891: if (atac->atac_set_modes == NULL)
1892: goto ready;
1893: /* Also don't try if the drive didn't report its mode */
1.24 bouyer 1894: if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0)
1.1 kiyohara 1895: goto ready;
1896: errstring = "unbusy";
1897: if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags))
1898: goto timeout;
1.29 jakllsch 1899: wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1.1 kiyohara 1900: 0x08 | drvp->PIO_mode, WDSF_SET_MODE);
1901: errstring = "piomode";
1902: if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags))
1903: goto timeout;
1904: if (chp->ch_status & WDCS_ERR) {
1905: if (chp->ch_error == WDCE_ABRT) {
1906: /*
1907: * Some ATAPI drives reject PIO settings.
1908: * Fall back to PIO mode 3 since that's the
1909: * minimum for ATAPI.
1910: */
1911: aprint_error_dev(atac->atac_dev,
1912: "channel %d drive %d: PIO mode %d rejected,"
1913: " falling back to PIO mode 3\n",
1914: chp->ch_channel, xfer->c_drive,
1915: drvp->PIO_mode);
1916: if (drvp->PIO_mode > 3)
1917: drvp->PIO_mode = 3;
1918: } else
1919: goto error;
1920: }
1.24 bouyer 1921: if (drvp->drive_flags & ATA_DRIVE_UDMA)
1.29 jakllsch 1922: wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1.1 kiyohara 1923: 0x40 | drvp->UDMA_mode, WDSF_SET_MODE);
1924: else
1.24 bouyer 1925: if (drvp->drive_flags & ATA_DRIVE_DMA)
1.29 jakllsch 1926: wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1.1 kiyohara 1927: 0x20 | drvp->DMA_mode, WDSF_SET_MODE);
1928: else
1929: goto ready;
1930: errstring = "dmamode";
1931: if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags))
1932: goto timeout;
1933: if (chp->ch_status & WDCS_ERR) {
1934: if (chp->ch_error == WDCE_ABRT) {
1.24 bouyer 1935: if (drvp->drive_flags & ATA_DRIVE_UDMA)
1.1 kiyohara 1936: goto error;
1937: else {
1938: /*
1939: * The drive rejected our DMA setting.
1940: * Fall back to mode 1.
1941: */
1942: aprint_error_dev(atac->atac_dev,
1943: "channel %d drive %d:"
1944: " DMA mode %d rejected,"
1945: " falling back to DMA mode 0\n",
1946: chp->ch_channel, xfer->c_drive,
1947: drvp->DMA_mode);
1948: if (drvp->DMA_mode > 0)
1949: drvp->DMA_mode = 0;
1950: }
1951: } else
1952: goto error;
1953: }
1954: ready:
1955: drvp->state = READY;
1956: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
1957: delay(10); /* some drives need a little delay here */
1958: }
1959: /* start timeout machinery */
1960: if ((sc_xfer->xs_control & XS_CTL_POLL) == 0)
1961: callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout),
1962: wdctimeout, chp);
1963:
1964: MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1965: switch (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags) < 0) {
1966: case WDCWAIT_OK:
1967: break;
1968: case WDCWAIT_TOUT:
1969: aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n",
1970: chp->ch_status);
1971: sc_xfer->error = XS_TIMEOUT;
1972: mvsata_atapi_reset(chp, xfer);
1973: return;
1974: case WDCWAIT_THR:
1975: return;
1976: }
1977:
1978: /*
1979: * Even with WDCS_ERR, the device should accept a command packet
1980: * Limit length to what can be stuffed into the cylinder register
1981: * (16 bits). Some CD-ROMs seem to interpret '0' as 65536,
1982: * but not all devices do that and it's not obvious from the
1983: * ATAPI spec that that behaviour should be expected. If more
1984: * data is necessary, multiple data transfer phases will be done.
1985: */
1986:
1.29 jakllsch 1987: wdccommand(chp, 0, ATAPI_PKT_CMD,
1.1 kiyohara 1988: xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0,
1989: (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0);
1990:
1991: /*
1992: * If there is no interrupt for CMD input, busy-wait for it (done in
1993: * the interrupt routine. If it is a polled command, call the interrupt
1994: * routine until command is done.
1995: */
1996: if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) !=
1997: ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) {
1998: /* Wait for at last 400ns for status bit to be valid */
1999: DELAY(1);
2000: mvsata_atapi_intr(chp, xfer, 0);
2001: } else
2002: chp->ch_flags |= ATACH_IRQ_WAIT;
2003: if (sc_xfer->xs_control & XS_CTL_POLL) {
2004: if (chp->ch_flags & ATACH_DMA_WAIT) {
2005: wdc_dmawait(chp, xfer, sc_xfer->timeout);
2006: chp->ch_flags &= ~ATACH_DMA_WAIT;
2007: }
2008: while ((sc_xfer->xs_status & XS_STS_DONE) == 0) {
2009: /* Wait for at last 400ns for status bit to be valid */
2010: DELAY(1);
2011: mvsata_atapi_intr(chp, xfer, 0);
2012: }
2013: }
2014: return;
2015:
2016: timeout:
2017: aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n",
2018: chp->ch_channel, xfer->c_drive, errstring);
2019: sc_xfer->error = XS_TIMEOUT;
2020: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
2021: delay(10); /* some drives need a little delay here */
2022: mvsata_atapi_reset(chp, xfer);
2023: return;
2024:
2025: error:
2026: aprint_error_dev(atac->atac_dev,
2027: "channel %d drive %d: %s error (0x%x)\n",
2028: chp->ch_channel, xfer->c_drive, errstring, chp->ch_error);
2029: sc_xfer->error = XS_SHORTSENSE;
2030: sc_xfer->sense.atapi_sense = chp->ch_error;
2031: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
2032: delay(10); /* some drives need a little delay here */
2033: mvsata_atapi_reset(chp, xfer);
2034: return;
2035: }
2036:
2037: static int
2038: mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
2039: {
2040: struct mvsata_port *mvport = (struct mvsata_port *)chp;
2041: struct atac_softc *atac = chp->ch_atac;
2042: struct wdc_softc *wdc = CHAN_TO_WDC(chp);
2043: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
2044: struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
2045: int len, phase, ire, error, retries=0, i;
2046: void *cmd;
2047:
2048: DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr\n",
2049: device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive));
2050:
2051: /* Is it not a transfer, but a control operation? */
2052: if (drvp->state < READY) {
2053: aprint_error_dev(atac->atac_dev,
2054: "channel %d drive %d: bad state %d\n",
2055: chp->ch_channel, xfer->c_drive, drvp->state);
2056: panic("mvsata_atapi_intr: bad state");
2057: }
2058: /*
2059: * If we missed an interrupt in a PIO transfer, reset and restart.
2060: * Don't try to continue transfer, we may have missed cycles.
2061: */
2062: if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) {
2063: sc_xfer->error = XS_TIMEOUT;
2064: mvsata_atapi_reset(chp, xfer);
2065: return 1;
2066: }
2067:
2068: /* Ack interrupt done in wdc_wait_for_unbusy */
2069: MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
2070: if (wdc_wait_for_unbusy(chp,
2071: (irq == 0) ? sc_xfer->timeout : 0, AT_POLL) == WDCWAIT_TOUT) {
2072: if (irq && (xfer->c_flags & C_TIMEOU) == 0)
2073: return 0; /* IRQ was not for us */
2074: aprint_error_dev(atac->atac_dev,
2075: "channel %d: device timeout, c_bcount=%d, c_skip=%d\n",
2076: chp->ch_channel, xfer->c_bcount, xfer->c_skip);
2077: if (xfer->c_flags & C_DMA)
2078: ata_dmaerr(drvp,
2079: (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2080: sc_xfer->error = XS_TIMEOUT;
2081: mvsata_atapi_reset(chp, xfer);
2082: return 1;
2083: }
2084:
2085: /*
2086: * If we missed an IRQ and were using DMA, flag it as a DMA error
2087: * and reset device.
2088: */
2089: if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) {
2090: ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2091: sc_xfer->error = XS_RESET;
2092: mvsata_atapi_reset(chp, xfer);
2093: return (1);
2094: }
2095: /*
2096: * if the request sense command was aborted, report the short sense
2097: * previously recorded, else continue normal processing
2098: */
2099:
2100: again:
2101: len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) +
2102: 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH);
2103: ire = MVSATA_WDC_READ_1(mvport, SRB_SC);
2104: phase = (ire & (WDCI_CMD | WDCI_IN)) | (chp->ch_status & WDCS_DRQ);
2105: DPRINTF((
2106: "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :",
2107: xfer->c_bcount, len, chp->ch_status, chp->ch_error, ire));
2108:
2109: switch (phase) {
2110: case PHASE_CMDOUT:
2111: cmd = sc_xfer->cmd;
2112: DPRINTF(("PHASE_CMDOUT\n"));
2113: /* Init the DMA channel if necessary */
2114: if (xfer->c_flags & C_DMA) {
2115: error = mvsata_bdma_init(mvport, sc_xfer,
2116: (char *)xfer->c_databuf + xfer->c_skip);
2117: if (error) {
2118: if (error == EINVAL) {
2119: /*
2120: * We can't do DMA on this transfer
2121: * for some reason. Fall back to PIO.
2122: */
2123: xfer->c_flags &= ~C_DMA;
2124: error = 0;
2125: } else {
2126: sc_xfer->error = XS_DRIVER_STUFFUP;
2127: break;
2128: }
2129: }
2130: }
2131:
2132: /* send packet command */
2133: /* Commands are 12 or 16 bytes long. It's 32-bit aligned */
2134: wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen);
2135:
2136: /* Start the DMA channel if necessary */
2137: if (xfer->c_flags & C_DMA) {
2138: mvsata_bdma_start(mvport);
2139: chp->ch_flags |= ATACH_DMA_WAIT;
2140: }
2141:
2142: if ((sc_xfer->xs_control & XS_CTL_POLL) == 0)
2143: chp->ch_flags |= ATACH_IRQ_WAIT;
2144: return 1;
2145:
2146: case PHASE_DATAOUT:
2147: /* write data */
2148: DPRINTF(("PHASE_DATAOUT\n"));
2149: if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 ||
2150: (xfer->c_flags & C_DMA) != 0) {
2151: aprint_error_dev(atac->atac_dev,
2152: "channel %d drive %d: bad data phase DATAOUT\n",
2153: chp->ch_channel, xfer->c_drive);
2154: if (xfer->c_flags & C_DMA)
2155: ata_dmaerr(drvp,
2156: (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2157: sc_xfer->error = XS_TIMEOUT;
2158: mvsata_atapi_reset(chp, xfer);
2159: return 1;
2160: }
2161: xfer->c_lenoff = len - xfer->c_bcount;
2162: if (xfer->c_bcount < len) {
2163: aprint_error_dev(atac->atac_dev, "channel %d drive %d:"
2164: " warning: write only %d of %d requested bytes\n",
2165: chp->ch_channel, xfer->c_drive, xfer->c_bcount,
2166: len);
2167: len = xfer->c_bcount;
2168: }
2169:
2170: wdc->dataout_pio(chp, drvp->drive_flags,
2171: (char *)xfer->c_databuf + xfer->c_skip, len);
2172:
2173: for (i = xfer->c_lenoff; i > 0; i -= 2)
2174: MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0);
2175:
2176: xfer->c_skip += len;
2177: xfer->c_bcount -= len;
2178: if ((sc_xfer->xs_control & XS_CTL_POLL) == 0)
2179: chp->ch_flags |= ATACH_IRQ_WAIT;
2180: return 1;
2181:
2182: case PHASE_DATAIN:
2183: /* Read data */
2184: DPRINTF(("PHASE_DATAIN\n"));
2185: if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 ||
2186: (xfer->c_flags & C_DMA) != 0) {
2187: aprint_error_dev(atac->atac_dev,
2188: "channel %d drive %d: bad data phase DATAIN\n",
2189: chp->ch_channel, xfer->c_drive);
2190: if (xfer->c_flags & C_DMA)
2191: ata_dmaerr(drvp,
2192: (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2193: sc_xfer->error = XS_TIMEOUT;
2194: mvsata_atapi_reset(chp, xfer);
2195: return 1;
2196: }
2197: xfer->c_lenoff = len - xfer->c_bcount;
2198: if (xfer->c_bcount < len) {
2199: aprint_error_dev(atac->atac_dev, "channel %d drive %d:"
2200: " warning: reading only %d of %d bytes\n",
2201: chp->ch_channel, xfer->c_drive, xfer->c_bcount,
2202: len);
2203: len = xfer->c_bcount;
2204: }
2205:
2206: wdc->datain_pio(chp, drvp->drive_flags,
2207: (char *)xfer->c_databuf + xfer->c_skip, len);
2208:
2209: if (xfer->c_lenoff > 0)
2210: wdcbit_bucket(chp, len - xfer->c_bcount);
2211:
2212: xfer->c_skip += len;
2213: xfer->c_bcount -= len;
2214: if ((sc_xfer->xs_control & XS_CTL_POLL) == 0)
2215: chp->ch_flags |= ATACH_IRQ_WAIT;
2216: return 1;
2217:
2218: case PHASE_ABORTED:
2219: case PHASE_COMPLETED:
2220: DPRINTF(("PHASE_COMPLETED\n"));
2221: if (xfer->c_flags & C_DMA)
2222: xfer->c_bcount -= sc_xfer->datalen;
2223: sc_xfer->resid = xfer->c_bcount;
2224: mvsata_atapi_phase_complete(xfer);
2225: return 1;
2226:
2227: default:
2228: if (++retries<500) {
2229: DELAY(100);
2230: chp->ch_status = MVSATA_WDC_READ_1(mvport, SRB_CS);
2231: chp->ch_error = MVSATA_WDC_READ_1(mvport, SRB_FE);
2232: goto again;
2233: }
2234: aprint_error_dev(atac->atac_dev,
2235: "channel %d drive %d: unknown phase 0x%x\n",
2236: chp->ch_channel, xfer->c_drive, phase);
2237: if (chp->ch_status & WDCS_ERR) {
2238: sc_xfer->error = XS_SHORTSENSE;
2239: sc_xfer->sense.atapi_sense = chp->ch_error;
2240: } else {
2241: if (xfer->c_flags & C_DMA)
2242: ata_dmaerr(drvp,
2243: (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2244: sc_xfer->error = XS_RESET;
2245: mvsata_atapi_reset(chp, xfer);
2246: return (1);
2247: }
2248: }
2249: DPRINTF(("mvsata_atapi_intr: mvsata_atapi_done() (end), error 0x%x "
2250: "sense 0x%x\n", sc_xfer->error, sc_xfer->sense.atapi_sense));
2251: mvsata_atapi_done(chp, xfer);
2252: return 1;
2253: }
2254:
2255: static void
2256: mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer,
2257: int reason)
2258: {
2259: struct mvsata_port *mvport = (struct mvsata_port *)chp;
2260: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
2261:
2262: /* remove this command from xfer queue */
2263: switch (reason) {
2264: case KILL_GONE:
2265: sc_xfer->error = XS_DRIVER_STUFFUP;
2266: break;
2267:
2268: case KILL_RESET:
2269: sc_xfer->error = XS_RESET;
2270: break;
2271:
2272: default:
2273: aprint_error_dev(MVSATA_DEV2(mvport),
2274: "mvsata_atapi_kill_xfer: unknown reason %d\n", reason);
2275: panic("mvsata_atapi_kill_xfer");
2276: }
2277: ata_free_xfer(chp, xfer);
2278: scsipi_done(sc_xfer);
2279: }
2280:
2281: static void
2282: mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer)
2283: {
2284: struct atac_softc *atac = chp->ch_atac;
2285: struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
2286: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
2287:
1.29 jakllsch 2288: mvsata_pmp_select(mvport, xfer->c_drive);
2289:
2290: wdccommandshort(chp, 0, ATAPI_SOFT_RESET);
1.1 kiyohara 2291: drvp->state = 0;
2292: if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL) != 0) {
2293: printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev),
2294: chp->ch_channel, xfer->c_drive);
2295: sc_xfer->error = XS_SELTIMEOUT;
2296: }
2297: mvsata_atapi_done(chp, xfer);
2298: return;
2299: }
2300:
2301: static void
2302: mvsata_atapi_phase_complete(struct ata_xfer *xfer)
2303: {
2304: struct ata_channel *chp = xfer->c_chp;
2305: struct atac_softc *atac = chp->ch_atac;
2306: struct wdc_softc *wdc = CHAN_TO_WDC(chp);
2307: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
2308: struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
2309:
2310: /* wait for DSC if needed */
1.24 bouyer 2311: if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) {
1.1 kiyohara 2312: DPRINTFN(1,
2313: ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n",
2314: device_xname(atac->atac_dev), chp->ch_channel,
2315: xfer->c_drive, xfer->c_dscpoll));
2316: if (cold)
2317: panic("mvsata_atapi_phase_complete: cold");
2318:
2319: if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL) ==
2320: WDCWAIT_TOUT) {
2321: /* 10ms not enough, try again in 1 tick */
2322: if (xfer->c_dscpoll++ > mstohz(sc_xfer->timeout)) {
2323: aprint_error_dev(atac->atac_dev,
2324: "channel %d: wait_for_dsc failed\n",
2325: chp->ch_channel);
2326: sc_xfer->error = XS_TIMEOUT;
2327: mvsata_atapi_reset(chp, xfer);
2328: return;
2329: } else
2330: callout_reset(&chp->ch_callout, 1,
2331: mvsata_atapi_polldsc, xfer);
2332: return;
2333: }
2334: }
2335:
2336: /*
2337: * Some drive occasionally set WDCS_ERR with
2338: * "ATA illegal length indication" in the error
2339: * register. If we read some data the sense is valid
2340: * anyway, so don't report the error.
2341: */
2342: if (chp->ch_status & WDCS_ERR &&
2343: ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 ||
2344: sc_xfer->resid == sc_xfer->datalen)) {
2345: /* save the short sense */
2346: sc_xfer->error = XS_SHORTSENSE;
2347: sc_xfer->sense.atapi_sense = chp->ch_error;
2348: if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) {
2349: /* ask scsipi to send a REQUEST_SENSE */
2350: sc_xfer->error = XS_BUSY;
2351: sc_xfer->status = SCSI_CHECK;
2352: } else
2353: if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) {
2354: ata_dmaerr(drvp,
2355: (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2356: sc_xfer->error = XS_RESET;
2357: mvsata_atapi_reset(chp, xfer);
2358: return;
2359: }
2360: }
2361: if (xfer->c_bcount != 0)
2362: DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr:"
2363: " bcount value is %d after io\n",
2364: device_xname(atac->atac_dev), chp->ch_channel,
2365: xfer->c_drive, xfer->c_bcount));
2366: #ifdef DIAGNOSTIC
2367: if (xfer->c_bcount < 0)
2368: aprint_error_dev(atac->atac_dev,
2369: "channel %d drive %d: mvsata_atapi_intr:"
2370: " warning: bcount value is %d after io\n",
2371: chp->ch_channel, xfer->c_drive, xfer->c_bcount);
2372: #endif
2373:
2374: DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_phase_complete:"
2375: " mvsata_atapi_done(), error 0x%x sense 0x%x\n",
2376: device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
2377: sc_xfer->error, sc_xfer->sense.atapi_sense));
2378: mvsata_atapi_done(chp, xfer);
2379: }
2380:
2381: static void
2382: mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer)
1.14 jakllsch 2383: {
1.1 kiyohara 2384: struct atac_softc *atac = chp->ch_atac;
2385: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
2386: int drive = xfer->c_drive;
2387:
2388: DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n",
2389: device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
2390: (u_int)xfer->c_flags));
2391: callout_stop(&chp->ch_callout);
2392: /* mark controller inactive and free the command */
2393: chp->ch_queue->active_xfer = NULL;
2394: ata_free_xfer(chp, xfer);
2395:
1.24 bouyer 2396: if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) {
1.1 kiyohara 2397: sc_xfer->error = XS_DRIVER_STUFFUP;
1.24 bouyer 2398: chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN;
1.1 kiyohara 2399: wakeup(&chp->ch_queue->active_xfer);
2400: }
2401:
2402: DPRINTFN(1, ("%s:%d: mvsata_atapi_done: scsipi_done\n",
2403: device_xname(atac->atac_dev), chp->ch_channel));
2404: scsipi_done(sc_xfer);
2405: DPRINTFN(1, ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n",
2406: device_xname(atac->atac_dev), chp->ch_channel, chp->ch_flags));
2407: atastart(chp);
2408: }
2409:
2410: static void
2411: mvsata_atapi_polldsc(void *arg)
2412: {
2413:
2414: mvsata_atapi_phase_complete(arg);
2415: }
2416: #endif /* NATAPIBUS > 0 */
2417:
2418:
2419: /*
1.9 jakllsch 2420: * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(),
1.1 kiyohara 2421: * if supported queuing command by atabus? The race condition will not happen
2422: * if this is called only to the thread of atabus.
2423: */
2424: static int
1.9 jakllsch 2425: mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_bio *ata_bio,
1.1 kiyohara 2426: void *databuf)
2427: {
2428: struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
2429: struct ata_channel *chp = &mvport->port_ata_channel;
2430: struct eprd *eprd;
2431: bus_addr_t crqb_base_addr;
2432: bus_dmamap_t data_dmamap;
2433: uint32_t reg;
2434: int quetag, erqqip, erqqop, next, rv, i;
2435:
1.9 jakllsch 2436: DPRINTFN(2, ("%s:%d:%d: mvsata_edma_enqueue:"
1.7 riz 2437: " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n",
1.1 kiyohara 2438: device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc,
2439: mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags));
2440:
2441: reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP);
2442: erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;
2443: reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP);
2444: erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;
2445: next = erqqip;
2446: MVSATA_EDMAQ_INC(next);
2447: if (next == erqqop)
2448: /* queue full */
2449: return EBUSY;
2450: if ((quetag = mvsata_quetag_get(mvport)) == -1)
2451: /* tag nothing */
2452: return EBUSY;
2453: DPRINTFN(2, (" erqqip=%d, quetag=%d\n", erqqip, quetag));
2454:
2455: rv = mvsata_dma_bufload(mvport, quetag, databuf, ata_bio->nbytes,
2456: ata_bio->flags);
2457: if (rv != 0)
2458: return rv;
2459:
1.10 jakllsch 2460: KASSERT(mvport->port_reqtbl[quetag].xfer == NULL);
2461: KASSERT(chp->ch_queue->active_xfer != NULL);
1.1 kiyohara 2462: mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer;
2463:
2464: /* setup EDMA Physical Region Descriptors (ePRD) Table Data */
2465: data_dmamap = mvport->port_reqtbl[quetag].data_dmamap;
2466: eprd = mvport->port_reqtbl[quetag].eprd;
2467: for (i = 0; i < data_dmamap->dm_nsegs; i++) {
2468: bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr;
2469: bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len;
2470:
2471: eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK);
2472: eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len));
2473: eprd->eot = htole16(0);
2474: eprd->prdbah = htole32((ds_addr >> 16) >> 16);
2475: eprd++;
2476: }
2477: (eprd - 1)->eot |= htole16(EPRD_EOT);
2478: #ifdef MVSATA_DEBUG
2479: if (mvsata_debug >= 3)
2480: mvsata_print_eprd(mvport, quetag);
2481: #endif
2482: bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap,
2483: mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE,
2484: BUS_DMASYNC_PREWRITE);
2485:
2486: /* setup EDMA Command Request Block (CRQB) Data */
2487: sc->sc_edma_setup_crqb(mvport, erqqip, quetag, ata_bio);
2488: #ifdef MVSATA_DEBUG
2489: if (mvsata_debug >= 3)
2490: mvsata_print_crqb(mvport, erqqip);
2491: #endif
2492: bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap,
2493: erqqip * sizeof(union mvsata_crqb),
2494: sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE);
2495:
2496: MVSATA_EDMAQ_INC(erqqip);
2497:
2498: crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr &
2499: (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK);
2500: MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16);
2501: MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP,
2502: crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT));
2503:
2504: return 0;
2505: }
2506:
2507: static int
2508: mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1)
2509: {
2510: struct ata_channel *chp = &mvport->port_ata_channel;
2511: struct crpb *crpb;
2512: struct ata_bio *ata_bio;
2513: struct ata_xfer *xfer;
2514: uint32_t reg;
2515: int erqqip, erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n;
2516:
2517: /* First, Sync for Request Queue buffer */
2518: reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP);
2519: erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;
2520: if (mvport->port_prev_erqqop != erqqop) {
2521: const int s = sizeof(union mvsata_crqb);
2522:
2523: if (mvport->port_prev_erqqop < erqqop)
2524: n = erqqop - mvport->port_prev_erqqop;
2525: else {
2526: if (erqqop > 0)
2527: bus_dmamap_sync(mvport->port_dmat,
2528: mvport->port_crqb_dmamap, 0, erqqop * s,
2529: BUS_DMASYNC_POSTWRITE);
2530: n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop;
2531: }
2532: if (n > 0)
2533: bus_dmamap_sync(mvport->port_dmat,
2534: mvport->port_crqb_dmamap,
2535: mvport->port_prev_erqqop * s, n * s,
2536: BUS_DMASYNC_POSTWRITE);
2537: mvport->port_prev_erqqop = erqqop;
2538: }
2539:
2540: reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP);
2541: erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT;
2542: reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP);
2543: erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT;
2544:
2545: DPRINTFN(3, ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n",
2546: device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc,
2547: mvport->port, erpqip, erpqop));
2548:
2549: if (erpqop == erpqip)
2550: return 0;
2551:
2552: if (erpqop < erpqip)
2553: n = erpqip - erpqop;
2554: else {
2555: if (erpqip > 0)
2556: bus_dmamap_sync(mvport->port_dmat,
2557: mvport->port_crpb_dmamap,
2558: 0, erpqip * sizeof(struct crpb),
2559: BUS_DMASYNC_POSTREAD);
2560: n = MVSATA_EDMAQ_LEN - erpqop;
2561: }
2562: if (n > 0)
2563: bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap,
2564: erpqop * sizeof(struct crpb),
2565: n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD);
2566:
2567: prev_erpqop = erpqop;
2568: while (erpqop != erpqip) {
2569: #ifdef MVSATA_DEBUG
2570: if (mvsata_debug >= 3)
2571: mvsata_print_crpb(mvport, erpqop);
2572: #endif
2573: crpb = mvport->port_crpb + erpqop;
2574: quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id));
1.10 jakllsch 2575: KASSERT(chp->ch_queue->active_xfer != NULL);
2576: xfer = chp->ch_queue->active_xfer;
2577: KASSERT(xfer == mvport->port_reqtbl[quetag].xfer);
1.1 kiyohara 2578: #ifdef DIAGNOSTIC
2579: if (xfer == NULL)
1.10 jakllsch 2580: panic("unknown response received: %s:%d:%d: tag 0x%x\n",
1.1 kiyohara 2581: device_xname(MVSATA_DEV2(mvport)),
2582: mvport->port_hc->hc, mvport->port, quetag);
2583: #endif
2584:
2585: bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap,
2586: mvport->port_reqtbl[quetag].eprd_offset,
2587: MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE);
2588:
2589: chp->ch_status = CRPB_CDEVSTS(le16toh(crpb->rspflg));
2590: chp->ch_error = CRPB_CEDMASTS(le16toh(crpb->rspflg));
2591: ata_bio = xfer->c_cmd;
2592: ata_bio->error = NOERROR;
2593: ata_bio->r_error = 0;
2594: if (chp->ch_status & WDCS_ERR)
2595: ata_bio->error = ERROR;
2596: if (chp->ch_status & WDCS_BSY)
2597: ata_bio->error = TIMEOUT;
2598: if (chp->ch_error)
2599: ata_bio->error = ERR_DMA;
2600:
2601: mvsata_dma_bufunload(mvport, quetag, ata_bio->flags);
2602: mvport->port_reqtbl[quetag].xfer = NULL;
2603: mvsata_quetag_put(mvport, quetag);
2604: MVSATA_EDMAQ_INC(erpqop);
2605:
2606: #if 1 /* XXXX: flags clears here, because necessary the atabus layer. */
2607: erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) &
2608: EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;
2609: if (erpqop == erqqip)
2610: chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT);
2611: #endif
2612: mvsata_bio_intr(chp, xfer, 1);
2613: if (xfer1 == NULL)
2614: handled++;
2615: else if (xfer == xfer1) {
2616: handled = 1;
2617: break;
2618: }
2619: }
2620: if (prev_erpqop < erpqop)
2621: n = erpqop - prev_erpqop;
2622: else {
2623: if (erpqop > 0)
2624: bus_dmamap_sync(mvport->port_dmat,
2625: mvport->port_crpb_dmamap, 0,
2626: erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD);
2627: n = MVSATA_EDMAQ_LEN - prev_erpqop;
2628: }
2629: if (n > 0)
2630: bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap,
2631: prev_erpqop * sizeof(struct crpb),
2632: n * sizeof(struct crpb), BUS_DMASYNC_PREREAD);
2633:
2634: reg &= ~EDMA_RESQP_ERPQP_MASK;
2635: reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT);
2636: MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg);
2637:
2638: #if 0 /* already cleared ago? */
2639: erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) &
2640: EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;
2641: if (erpqop == erqqip)
2642: chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT);
2643: #endif
2644:
2645: return handled;
2646: }
2647:
2648: static int
2649: mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout)
2650: {
2651: struct ata_bio *ata_bio = xfer->c_cmd;
2652: int xtime;
2653:
2654: for (xtime = 0; xtime < timeout / 10; xtime++) {
2655: if (mvsata_edma_handle(mvport, xfer))
2656: return 0;
1.30 bouyer 2657: if (ata_bio->flags & ATA_POLL)
1.1 kiyohara 2658: delay(10000);
2659: else
2660: tsleep(&xfer, PRIBIO, "mvsataipl", mstohz(10));
2661: }
2662:
2663: DPRINTF(("mvsata_edma_wait: timeout: %p\n", xfer));
2664: mvsata_edma_rqq_remove(mvport, xfer);
2665: xfer->c_flags |= C_TIMEOU;
2666: return 1;
2667: }
2668:
2669: static void
2670: mvsata_edma_timeout(void *arg)
2671: {
2672: struct ata_xfer *xfer = (struct ata_xfer *)arg;
2673: struct ata_channel *chp = xfer->c_chp;
2674: struct mvsata_port *mvport = (struct mvsata_port *)chp;
2675: int s;
2676:
2677: s = splbio();
2678: DPRINTF(("mvsata_edma_timeout: %p\n", xfer));
2679: if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) {
2680: mvsata_edma_rqq_remove(mvport, xfer);
2681: xfer->c_flags |= C_TIMEOU;
2682: mvsata_bio_intr(chp, xfer, 1);
2683: }
2684: splx(s);
2685: }
2686:
2687: static void
2688: mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer)
2689: {
2690: struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
2691: struct ata_bio *ata_bio;
2692: bus_addr_t crqb_base_addr;
2693: int erqqip, i;
2694:
2695: /* First, hardware reset, stop EDMA */
2696: mvsata_hreset_port(mvport);
2697:
2698: /* cleanup completed EDMA safely */
2699: mvsata_edma_handle(mvport, NULL);
2700:
2701: bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0,
2702: sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE);
2703: for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) {
2704: if (mvport->port_reqtbl[i].xfer == NULL)
2705: continue;
2706:
2707: ata_bio = mvport->port_reqtbl[i].xfer->c_cmd;
2708: if (mvport->port_reqtbl[i].xfer == xfer) {
2709: /* remove xfer from EDMA request queue */
2710: bus_dmamap_sync(mvport->port_dmat,
2711: mvport->port_eprd_dmamap,
2712: mvport->port_reqtbl[i].eprd_offset,
2713: MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE);
2714: mvsata_dma_bufunload(mvport, i, ata_bio->flags);
2715: mvport->port_reqtbl[i].xfer = NULL;
2716: mvsata_quetag_put(mvport, i);
2717: continue;
2718: }
2719:
2720: sc->sc_edma_setup_crqb(mvport, erqqip, i, ata_bio);
2721: erqqip++;
2722: }
2723: bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0,
2724: sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN,
2725: BUS_DMASYNC_POSTWRITE);
2726:
2727: mvsata_edma_config(mvport, mvport->port_edmamode);
2728: mvsata_edma_reset_qptr(mvport);
2729: mvsata_edma_enable(mvport);
2730:
2731: crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr &
2732: (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK);
2733: MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16);
2734: MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP,
2735: crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT));
2736: }
2737:
2738: #if NATAPIBUS > 0
2739: static int
2740: mvsata_bdma_init(struct mvsata_port *mvport, struct scsipi_xfer *sc_xfer,
2741: void *databuf)
2742: {
2743: struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
2744: struct eprd *eprd;
2745: bus_dmamap_t data_dmamap;
2746: bus_addr_t eprd_addr;
2747: int quetag, rv;
2748:
2749: DPRINTFN(2,
2750: ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n",
2751: device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc,
2752: mvport->port, sc_xfer->datalen, sc_xfer->xs_control));
2753:
2754: if ((quetag = mvsata_quetag_get(mvport)) == -1)
2755: /* tag nothing */
2756: return EBUSY;
2757: DPRINTFN(2, (" quetag=%d\n", quetag));
2758:
2759: rv = mvsata_dma_bufload(mvport, quetag, databuf, sc_xfer->datalen,
2760: sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0);
2761: if (rv != 0)
2762: return rv;
2763:
1.10 jakllsch 2764: KASSERT(chp->ch_queue->active_xfer != NULL);
2765: KASSERT(mvport->port_reqtbl[quetag].xfer == NULL);
1.1 kiyohara 2766: mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer;
2767:
2768: /* setup EDMA Physical Region Descriptors (ePRD) Table Data */
2769: data_dmamap = mvport->port_reqtbl[quetag].data_dmamap;
2770: eprd = mvport->port_reqtbl[quetag].eprd;
2771: for (i = 0; i < data_dmamap->dm_nsegs; i++) {
2772: bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr;
2773: bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len;
2774:
2775: eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK);
2776: eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len));
2777: eprd->eot = htole16(0);
2778: eprd->prdbah = htole32((ds_addr >> 16) >> 16);
2779: eprd++;
2780: }
2781: (eprd - 1)->eot |= htole16(EPRD_EOT);
2782: #ifdef MVSATA_DEBUG
2783: if (mvsata_debug >= 3)
2784: mvsata_print_eprd(mvport, quetag);
2785: #endif
2786: bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap,
2787: mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE,
2788: BUS_DMASYNC_PREWRITE);
2789: eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr +
2790: mvport->port_reqtbl[quetag].eprd_offset;
2791:
2792: MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK);
2793: MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16);
2794:
2795: if (sc_xfer->xs_control & XS_CTL_DATA_IN)
2796: MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ);
2797: else
2798: MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0);
2799:
2800: return 0;
2801: }
2802:
2803: static void
2804: mvsata_bdma_start(struct mvsata_port *mvport)
2805: {
2806:
2807: #ifdef MVSATA_DEBUG
2808: if (mvsata_debug >= 3)
2809: mvsata_print_eprd(mvport, 0);
2810: #endif
2811:
2812: MVSATA_EDMA_WRITE_4(mvport, DMA_C,
2813: MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START);
2814: }
2815: #endif
2816: #endif
2817:
2818:
2819: static int
2820: mvsata_port_init(struct mvsata_hc *mvhc, int port)
2821: {
2822: struct mvsata_softc *sc = mvhc->hc_sc;
2823: struct mvsata_port *mvport;
2824: struct ata_channel *chp;
2825: int channel, rv, i;
2826: const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN;
2827: const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN;
2828: const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN;
2829:
2830: mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF,
2831: M_ZERO | M_NOWAIT);
2832: if (mvport == NULL) {
2833: aprint_error("%s:%d: can't allocate memory for port %d\n",
2834: device_xname(MVSATA_DEV(sc)), mvhc->hc, port);
2835: return ENOMEM;
2836: }
2837:
2838: mvport->port = port;
2839: mvport->port_hc = mvhc;
2840: mvport->port_edmamode = nodma;
2841:
2842: rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh,
2843: EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE,
2844: EDMA_REGISTERS_SIZE, &mvport->port_ioh);
2845: if (rv != 0) {
2846: aprint_error("%s:%d: can't subregion EDMA %d registers\n",
2847: device_xname(MVSATA_DEV(sc)), mvhc->hc, port);
2848: goto fail0;
2849: }
2850: mvport->port_iot = mvhc->hc_iot;
2851: rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4,
2852: &mvport->port_sata_sstatus);
2853: if (rv != 0) {
2854: aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n",
2855: device_xname(MVSATA_DEV(sc)), mvhc->hc, port);
2856: goto fail0;
2857: }
2858: rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4,
2859: &mvport->port_sata_serror);
2860: if (rv != 0) {
2861: aprint_error("%s:%d:%d: couldn't subregion serror regs\n",
2862: device_xname(MVSATA_DEV(sc)), mvhc->hc, port);
2863: goto fail0;
2864: }
2865: if (sc->sc_rev == gen1)
2866: rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh,
2867: SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol);
2868: else
2869: rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
2870: SATA_SC, 4, &mvport->port_sata_scontrol);
2871: if (rv != 0) {
2872: aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n",
2873: device_xname(MVSATA_DEV(sc)), mvhc->hc, port);
2874: goto fail0;
2875: }
2876: mvport->port_dmat = sc->sc_dmat;
2877: #ifndef MVSATA_WITHOUTDMA
2878: mvsata_quetag_init(mvport);
2879: #endif
2880: mvhc->hc_ports[port] = mvport;
2881:
2882: channel = mvhc->hc * sc->sc_port + port;
2883: chp = &mvport->port_ata_channel;
2884: chp->ch_channel = channel;
2885: chp->ch_atac = &sc->sc_wdcdev.sc_atac;
2886: chp->ch_queue = &mvport->port_ata_queue;
2887: sc->sc_ata_channels[channel] = chp;
2888:
2889: rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel);
2890: if (rv != 0)
2891: goto fail0;
2892:
2893: rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0,
2894: BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap);
2895: if (rv != 0) {
2896: aprint_error(
2897: "%s:%d:%d: EDMA CRQB map create failed: error=%d\n",
2898: device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv);
2899: goto fail0;
2900: }
2901: rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0,
2902: BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap);
2903: if (rv != 0) {
2904: aprint_error(
2905: "%s:%d:%d: EDMA CRPB map create failed: error=%d\n",
2906: device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv);
2907: goto fail1;
2908: }
2909: rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1,
2910: eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap);
2911: if (rv != 0) {
2912: aprint_error(
2913: "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n",
2914: device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv);
2915: goto fail2;
2916: }
2917: for (i = 0; i < MVSATA_EDMAQ_LEN; i++) {
2918: rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS,
2919: MAXPHYS / PAGE_SIZE, MAXPHYS, 0, BUS_DMA_NOWAIT,
2920: &mvport->port_reqtbl[i].data_dmamap);
2921: if (rv != 0) {
2922: aprint_error("%s:%d:%d:"
2923: " EDMA data map(%d) create failed: error=%d\n",
2924: device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i,
2925: rv);
2926: goto fail3;
2927: }
2928: }
2929:
2930: return 0;
2931:
2932: fail3:
2933: for (i--; i >= 0; i--)
2934: bus_dmamap_destroy(mvport->port_dmat,
2935: mvport->port_reqtbl[i].data_dmamap);
2936: bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap);
2937: fail2:
2938: bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap);
2939: fail1:
2940: bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap);
2941: fail0:
2942: return rv;
2943: }
2944:
2945: static int
2946: mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr)
2947: {
2948: int hc, port, rv, i;
2949:
2950: hc = mvport->port_hc->hc;
2951: port = mvport->port;
2952:
2953: /* Create subregion for Shadow Registers Map */
2954: rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
2955: SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh);
2956: if (rv != 0) {
2957: aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n",
2958: device_xname(MVSATA_DEV2(mvport)), hc, port);
2959: return rv;
2960: }
2961: wdr->cmd_iot = mvport->port_iot;
2962:
2963: /* Once create subregion for each command registers */
2964: for (i = 0; i < WDC_NREG; i++) {
2965: rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
2966: i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]);
2967: if (rv != 0) {
2968: aprint_error("%s:%d:%d: couldn't subregion cmd regs\n",
2969: device_xname(MVSATA_DEV2(mvport)), hc, port);
2970: return rv;
2971: }
2972: }
2973: /* Create subregion for Alternate Status register */
2974: rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
2975: i * 4, sizeof(uint32_t), &wdr->ctl_ioh);
2976: if (rv != 0) {
2977: aprint_error("%s:%d:%d: couldn't subregion cmd regs\n",
2978: device_xname(MVSATA_DEV2(mvport)), hc, port);
2979: return rv;
2980: }
2981: wdr->ctl_iot = mvport->port_iot;
2982:
2983: wdc_init_shadow_regs(&mvport->port_ata_channel);
2984:
2985: rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
2986: SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh);
2987: if (rv != 0) {
2988: aprint_error("%s:%d:%d: couldn't subregion SATA regs\n",
2989: device_xname(MVSATA_DEV2(mvport)), hc, port);
2990: return rv;
2991: }
2992: wdr->sata_iot = mvport->port_iot;
2993: rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
2994: SATA_SC, sizeof(uint32_t), &wdr->sata_control);
2995: if (rv != 0) {
2996: aprint_error("%s:%d:%d: couldn't subregion SControl\n",
2997: device_xname(MVSATA_DEV2(mvport)), hc, port);
2998: return rv;
2999: }
3000: rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
3001: SATA_SS, sizeof(uint32_t), &wdr->sata_status);
3002: if (rv != 0) {
3003: aprint_error("%s:%d:%d: couldn't subregion SStatus\n",
3004: device_xname(MVSATA_DEV2(mvport)), hc, port);
3005: return rv;
3006: }
3007: rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
3008: SATA_SE, sizeof(uint32_t), &wdr->sata_error);
3009: if (rv != 0) {
3010: aprint_error("%s:%d:%d: couldn't subregion SError\n",
3011: device_xname(MVSATA_DEV2(mvport)), hc, port);
3012: return rv;
3013: }
3014:
3015: return 0;
3016: }
3017:
3018:
3019: #ifndef MVSATA_WITHOUTDMA
3020: /*
3021: * There are functions to determine Host Queue Tag.
3022: * XXXX: We hope to rotate Tag to facilitate debugging.
3023: */
3024:
3025: static inline void
3026: mvsata_quetag_init(struct mvsata_port *mvport)
3027: {
3028:
3029: mvport->port_quetagidx = 0;
3030: }
3031:
3032: static inline int
3033: mvsata_quetag_get(struct mvsata_port *mvport)
3034: {
3035: int begin = mvport->port_quetagidx;
3036:
3037: do {
3038: if (mvport->port_reqtbl[mvport->port_quetagidx].xfer == NULL) {
3039: MVSATA_EDMAQ_INC(mvport->port_quetagidx);
3040: return mvport->port_quetagidx;
3041: }
3042: MVSATA_EDMAQ_INC(mvport->port_quetagidx);
3043: } while (mvport->port_quetagidx != begin);
3044:
3045: return -1;
3046: }
3047:
3048: static inline void
3049: mvsata_quetag_put(struct mvsata_port *mvport, int quetag)
3050: {
3051:
3052: /* nothing */
3053: }
3054:
3055: static void *
3056: mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat,
3057: bus_dmamap_t *dmamap, size_t size, int write)
3058: {
3059: bus_dma_segment_t seg;
3060: int nseg, rv;
3061: void *kva;
3062:
3063: rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg,
3064: BUS_DMA_NOWAIT);
3065: if (rv != 0) {
3066: aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n",
3067: device_xname(MVSATA_DEV2(mvport)),
3068: mvport->port_hc->hc, mvport->port, rv);
3069: goto fail;
3070: }
3071:
3072: rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT);
3073: if (rv != 0) {
3074: aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n",
3075: device_xname(MVSATA_DEV2(mvport)),
3076: mvport->port_hc->hc, mvport->port, rv);
3077: goto free;
3078: }
3079:
3080: rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL,
3081: BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ));
3082: if (rv != 0) {
3083: aprint_error("%s:%d:%d: DMA map load failed: error=%d\n",
3084: device_xname(MVSATA_DEV2(mvport)),
3085: mvport->port_hc->hc, mvport->port, rv);
3086: goto unmap;
3087: }
3088:
3089: if (!write)
3090: bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD);
3091:
3092: return kva;
3093:
3094: unmap:
3095: bus_dmamem_unmap(dmat, kva, size);
3096: free:
3097: bus_dmamem_free(dmat, &seg, nseg);
3098: fail:
3099: return NULL;
3100: }
3101:
3102: /* ARGSUSED */
3103: static void
3104: mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat,
3105: bus_dmamap_t dmamap, void *kva)
3106: {
3107:
3108: bus_dmamap_unload(dmat, dmamap);
3109: bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize);
3110: bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs);
3111: }
3112:
3113: static int
3114: mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf,
3115: size_t datalen, int flags)
3116: {
3117: int rv, lop, sop;
3118: bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap;
3119:
3120: lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE;
3121: sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE;
3122:
3123: rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen,
3124: NULL, BUS_DMA_NOWAIT | lop);
3125: if (rv) {
3126: aprint_error("%s:%d:%d: buffer load failed: error=%d",
3127: device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc,
3128: mvport->port, rv);
3129: return rv;
3130: }
3131: bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0,
3132: data_dmamap->dm_mapsize, sop);
3133:
3134: return 0;
3135: }
3136:
3137: static inline void
3138: mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags)
3139: {
3140: bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap;
3141:
3142: bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0,
3143: data_dmamap->dm_mapsize,
3144: (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3145: bus_dmamap_unload(mvport->port_dmat, data_dmamap);
3146: }
3147: #endif
3148:
3149: static void
3150: mvsata_hreset_port(struct mvsata_port *mvport)
3151: {
3152: struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
3153:
3154: MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST);
3155:
3156: delay(25); /* allow reset propagation */
3157:
3158: MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0);
3159:
3160: mvport->_fix_phy_param._fix_phy(mvport);
3161:
3162: if (sc->sc_gen == gen1)
3163: delay(1000);
3164: }
3165:
3166: static void
3167: mvsata_reset_port(struct mvsata_port *mvport)
3168: {
3169: device_t parent = device_parent(MVSATA_DEV2(mvport));
3170:
3171: MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA);
3172:
3173: mvsata_hreset_port(mvport);
3174:
3175: if (device_is_a(parent, "pci"))
3176: MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG,
3177: EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ);
3178: else /* SoC */
3179: MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG,
3180: EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2);
3181: MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0);
1.29 jakllsch 3182: MVSATA_EDMA_WRITE_4(mvport, SATA_SEIM, 0x019c0000);
3183: MVSATA_EDMA_WRITE_4(mvport, SATA_SE, ~0);
3184: MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0);
1.1 kiyohara 3185: MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0);
3186: MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0);
3187: MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0);
3188: MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0);
3189: MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0);
3190: MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0);
3191: MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0);
3192: MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0);
3193: MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0);
3194: MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0);
3195: MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc);
3196: }
3197:
3198: static void
3199: mvsata_reset_hc(struct mvsata_hc *mvhc)
3200: {
3201: #if 0
3202: uint32_t val;
3203: #endif
3204:
3205: MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0);
3206: MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0);
3207: MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0);
3208:
3209: #if 0 /* XXXX needs? */
3210: MVSATA_HC_WRITE_4(mvhc, 0x01c, 0);
3211:
3212: /*
3213: * Keep the SS during power on and the reference clock bits (reset
3214: * sample)
3215: */
3216: val = MVSATA_HC_READ_4(mvhc, 0x020);
3217: val &= 0x1c1c1c1c;
3218: val |= 0x03030303;
3219: MVSATA_HC_READ_4(mvhc, 0x020, 0);
3220: #endif
3221: }
3222:
1.29 jakllsch 3223: #define WDCDELAY 100 /* 100 microseconds */
3224: #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY)
3225:
3226: static uint32_t
1.1 kiyohara 3227: mvsata_softreset(struct mvsata_port *mvport, int waitok)
3228: {
1.29 jakllsch 3229: uint32_t sig0 = ~0;
3230: int timeout, nloop;
3231: uint8_t st0;
1.1 kiyohara 3232:
1.29 jakllsch 3233: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
3234: delay(10);
3235: (void) MVSATA_WDC_READ_1(mvport, SRB_FE);
3236: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS | WDCTL_4BIT);
1.1 kiyohara 3237: delay(10);
3238:
1.29 jakllsch 3239: if (!waitok)
3240: nloop = WDCNDELAY_RST;
3241: else
3242: nloop = WDC_RESET_WAIT * hz / 1000;
3243:
3244: /* wait for BSY to deassert */
3245: for (timeout = 0; timeout < nloop; timeout++) {
3246: st0 = MVSATA_WDC_READ_1(mvport, SRB_CS);
3247:
3248: if ((st0 & WDCS_BSY) == 0) {
3249: sig0 = MVSATA_WDC_READ_1(mvport, SRB_SC) << 0;
3250: sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 8;
3251: sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 16;
3252: sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 24;
3253: goto out;
1.1 kiyohara 3254: }
1.29 jakllsch 3255: if (!waitok)
3256: delay(WDCDELAY);
3257: else
3258: tsleep(&nloop, PRIBIO, "atarst", 1);
1.1 kiyohara 3259: }
1.29 jakllsch 3260:
3261: out:
3262: MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
3263: return sig0;
1.1 kiyohara 3264: }
3265:
1.29 jakllsch 3266: #ifndef MVSATA_WITHOUTDMA
1.1 kiyohara 3267: static void
3268: mvsata_edma_reset_qptr(struct mvsata_port *mvport)
3269: {
3270: const bus_addr_t crpb_addr =
3271: mvport->port_crpb_dmamap->dm_segs[0].ds_addr;
3272: const uint32_t crpb_addr_mask =
3273: EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK;
3274:
3275: MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0);
3276: MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0);
3277: MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0);
3278: MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16);
3279: MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0);
3280: MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask));
3281: }
3282:
3283: static inline void
3284: mvsata_edma_enable(struct mvsata_port *mvport)
3285: {
3286:
3287: MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA);
3288: }
3289:
3290: static int
3291: mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int waitok)
3292: {
3293: uint32_t status, command;
3294: int ms;
3295:
3296: if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) {
3297: for (ms = 0; ms < timeout; ms++) {
3298: status = MVSATA_EDMA_READ_4(mvport, EDMA_S);
3299: if (status & EDMA_S_EDMAIDLE)
3300: break;
3301: if (waitok)
3302: tsleep(&waitok, PRIBIO, "mvsata_edma1",
3303: mstohz(1));
3304: else
3305: delay(1000);
3306: }
1.29 jakllsch 3307: if (ms == timeout) {
3308: aprint_error("%s:%d:%d: unable to stop EDMA\n",
3309: device_xname(MVSATA_DEV2(mvport)),
3310: mvport->port_hc->hc, mvport->port);
1.1 kiyohara 3311: return EBUSY;
1.29 jakllsch 3312: }
1.1 kiyohara 3313:
3314: /* The diable bit (eDsEDMA) is self negated. */
3315: MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA);
3316:
3317: for ( ; ms < timeout; ms++) {
3318: command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD);
3319: if (!(command & EDMA_CMD_EENEDMA))
3320: break;
3321: if (waitok)
3322: tsleep(&waitok, PRIBIO, "mvsata_edma2",
3323: mstohz(1));
3324: else
3325: delay(1000);
3326: }
3327: if (ms == timeout) {
3328: aprint_error("%s:%d:%d: unable to stop EDMA\n",
3329: device_xname(MVSATA_DEV2(mvport)),
3330: mvport->port_hc->hc, mvport->port);
3331: return EBUSY;
3332: }
3333: }
3334: return 0;
3335: }
3336:
3337: /*
3338: * Set EDMA registers according to mode.
3339: * ex. NCQ/TCQ(queued)/non queued.
3340: */
3341: static void
3342: mvsata_edma_config(struct mvsata_port *mvport, int mode)
3343: {
3344: struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
3345: uint32_t reg;
3346:
3347: reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG);
3348: reg |= EDMA_CFG_RESERVED;
3349:
3350: if (mode == ncq) {
3351: if (sc->sc_gen == gen1) {
3352: aprint_error_dev(MVSATA_DEV2(mvport),
3353: "GenI not support NCQ\n");
3354: return;
3355: } else if (sc->sc_gen == gen2)
3356: reg |= EDMA_CFG_EDEVERR;
3357: reg |= EDMA_CFG_ESATANATVCMDQUE;
3358: } else if (mode == queued) {
3359: reg &= ~EDMA_CFG_ESATANATVCMDQUE;
3360: reg |= EDMA_CFG_EQUE;
3361: } else
3362: reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE);
3363:
3364: if (sc->sc_gen == gen1)
3365: reg |= EDMA_CFG_ERDBSZ;
3366: else if (sc->sc_gen == gen2)
3367: reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN);
3368: else if (sc->sc_gen == gen2e) {
3369: device_t parent = device_parent(MVSATA_DEV(sc));
3370:
3371: reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN);
3372: reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN);
3373:
3374: if (device_is_a(parent, "pci"))
3375: reg |= (
3376: #if NATAPIBUS > 0
3377: EDMA_CFG_EEARLYCOMPLETIONEN |
3378: #endif
3379: EDMA_CFG_ECUTTHROUGHEN |
3380: EDMA_CFG_EWRBUFFERLEN |
3381: EDMA_CFG_ERDBSZEXT);
3382: }
3383: MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg);
3384:
3385: reg = (
3386: EDMA_IE_EIORDYERR |
3387: EDMA_IE_ETRANSINT |
3388: EDMA_IE_EDEVCON |
3389: EDMA_IE_EDEVDIS);
3390: if (sc->sc_gen != gen1)
3391: reg |= (
3392: EDMA_IE_TRANSPROTERR |
3393: EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) |
3394: EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) |
3395: EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) |
3396: EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) |
3397: EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) |
3398: EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) |
3399: EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) |
3400: EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) |
3401: EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) |
3402: EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) |
3403: EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) |
3404: EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) |
3405: EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) |
3406: EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) |
3407: EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) |
3408: EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) |
3409: EDMA_IE_ESELFDIS);
3410:
3411: if (mode == ncq)
3412: reg |= EDMA_IE_EDEVERR;
3413: MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg);
3414: reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC);
3415: reg &= ~EDMA_IE_EDEVERR;
3416: if (mode != ncq)
3417: reg |= EDMA_IE_EDEVERR;
3418: MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg);
3419: if (sc->sc_gen == gen2e) {
3420: /*
3421: * Clear FISWait4HostRdyEn[0] and [2].
3422: * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1.
3423: * [2]: SDB FIS is received with <ERR> bit set to 1.
3424: */
3425: reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC);
3426: reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 |
3427: SATA_FISC_FISWAIT4HOSTRDYEN_B2);
3428: MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg);
3429: }
3430:
3431: mvport->port_edmamode = mode;
3432: }
3433:
3434:
3435: /*
3436: * Generation dependent functions
3437: */
3438:
3439: static void
3440: mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, int quetag,
3441: struct ata_bio *ata_bio)
3442: {
3443: struct crqb *crqb;
3444: bus_addr_t eprd_addr;
3445: daddr_t blkno;
3446: uint32_t rw;
3447: uint8_t cmd, head;
3448: int i;
3449: const int drive =
3450: mvport->port_ata_channel.ch_queue->active_xfer->c_drive;
3451:
3452: eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr +
3453: mvport->port_reqtbl[quetag].eprd_offset;
3454: rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE;
3455: cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA;
1.26 jakllsch 3456: if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) {
3457: head = WDSD_LBA;
3458: } else {
3459: head = 0;
3460: }
1.1 kiyohara 3461: blkno = ata_bio->blkno;
3462: if (ata_bio->flags & ATA_LBA48)
3463: cmd = atacmd_to48(cmd);
3464: else {
3465: head |= ((ata_bio->blkno >> 24) & 0xf);
3466: blkno &= 0xffffff;
3467: }
3468: crqb = &mvport->port_crqb->crqb + erqqip;
3469: crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK);
3470: crqb->cprdbh = htole32((eprd_addr >> 16) >> 16);
3471: crqb->ctrlflg =
3472: htole16(rw | CRQB_CHOSTQUETAG(quetag) | CRQB_CPMPORT(drive));
3473: i = 0;
3474: if (mvport->port_edmamode == dma) {
3475: if (ata_bio->flags & ATA_LBA48)
3476: crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3477: CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8));
3478: crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3479: CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks));
3480: } else { /* ncq/queued */
3481:
3482: /*
3483: * XXXX: Oops, ata command is not correct. And, atabus layer
3484: * has not been supported yet now.
3485: * Queued DMA read/write.
3486: * read/write FPDMAQueued.
3487: */
3488:
3489: if (ata_bio->flags & ATA_LBA48)
3490: crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3491: CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8));
3492: crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3493: CRQB_ATACOMMAND_FEATURES, ata_bio->nblks));
3494: crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3495: CRQB_ATACOMMAND_SECTORCOUNT, quetag << 3));
3496: }
3497: if (ata_bio->flags & ATA_LBA48) {
3498: crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3499: CRQB_ATACOMMAND_LBALOW, blkno >> 24));
3500: crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3501: CRQB_ATACOMMAND_LBAMID, blkno >> 32));
3502: crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3503: CRQB_ATACOMMAND_LBAHIGH, blkno >> 40));
3504: }
3505: crqb->atacommand[i++] =
3506: htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno));
3507: crqb->atacommand[i++] =
3508: htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8));
3509: crqb->atacommand[i++] =
3510: htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16));
3511: crqb->atacommand[i++] =
3512: htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head));
3513: crqb->atacommand[i++] = htole16(
3514: CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) |
3515: CRQB_ATACOMMAND_LAST);
3516: }
3517: #endif
3518:
3519: static uint32_t
3520: mvsata_read_preamps_gen1(struct mvsata_port *mvport)
3521: {
3522: struct mvsata_hc *hc = mvport->port_hc;
3523: uint32_t reg;
3524:
3525: reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port));
3526: /*
3527: * [12:11] : pre
3528: * [7:5] : amps
3529: */
3530: return reg & 0x000018e0;
3531: }
3532:
3533: static void
3534: mvsata_fix_phy_gen1(struct mvsata_port *mvport)
3535: {
3536: struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
3537: struct mvsata_hc *mvhc = mvport->port_hc;
3538: uint32_t reg;
3539: int port = mvport->port, fix_apm_sq = 0;
3540:
3541: if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) {
3542: if (sc->sc_rev == 0x01)
3543: fix_apm_sq = 1;
3544: } else {
3545: if (sc->sc_rev == 0x00)
3546: fix_apm_sq = 1;
3547: }
3548:
3549: if (fix_apm_sq) {
3550: /*
3551: * Disable auto-power management
3552: * 88SX50xx FEr SATA#12
3553: */
3554: reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port));
3555: reg |= (1 << 19);
3556: MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg);
3557:
3558: /*
3559: * Fix squelch threshold
3560: * 88SX50xx FEr SATA#9
3561: */
3562: reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port));
3563: reg &= ~0x3;
3564: reg |= 0x1;
3565: MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg);
3566: }
3567:
3568: /* Revert values of pre-emphasis and signal amps to the saved ones */
3569: reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port));
3570: reg &= ~0x000018e0; /* pre and amps mask */
3571: reg |= mvport->_fix_phy_param.pre_amps;
3572: MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg);
3573: }
3574:
3575: static void
3576: mvsata_devconn_gen1(struct mvsata_port *mvport)
3577: {
3578: struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
3579:
3580: /* Fix for 88SX50xx FEr SATA#2 */
3581: mvport->_fix_phy_param._fix_phy(mvport);
3582:
3583: /* If disk is connected, then enable the activity LED */
3584: if (sc->sc_rev == 0x03) {
3585: /* XXXXX */
3586: }
3587: }
3588:
3589: static uint32_t
3590: mvsata_read_preamps_gen2(struct mvsata_port *mvport)
3591: {
3592: uint32_t reg;
3593:
3594: reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);
3595: /*
3596: * [10:8] : amps
3597: * [7:5] : pre
3598: */
3599: return reg & 0x000007e0;
3600: }
3601:
3602: static void
3603: mvsata_fix_phy_gen2(struct mvsata_port *mvport)
3604: {
3605: struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
3606: uint32_t reg;
3607:
3608: if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) ||
3609: sc->sc_gen == gen2e) {
3610: /*
3611: * Fix for
3612: * 88SX60X1 FEr SATA #23
3613: * 88SX6042/88SX7042 FEr SATA #23
3614: * 88F5182 FEr #SATA-S13
3615: * 88F5082 FEr #SATA-S13
3616: */
3617: reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);
3618: reg &= ~(1 << 16);
3619: reg |= (1 << 31);
3620: MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg);
3621:
3622: delay(200);
3623:
3624: reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);
3625: reg &= ~((1 << 16) | (1 << 31));
3626: MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg);
3627:
3628: delay(200);
3629: }
3630:
3631: /* Fix values in PHY Mode 3 Register.*/
3632: reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3);
3633: reg &= ~0x7F900000;
3634: reg |= 0x2A800000;
3635: /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */
3636: if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 ||
3637: sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 ||
3638: sc->sc_model == PCI_PRODUCT_MARVELL_88F6082)
3639: reg &= ~0x0000001c;
3640: MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg);
3641:
3642: /*
3643: * Fix values in PHY Mode 4 Register.
3644: * 88SX60x1 FEr SATA#10
3645: * 88F5182 GL #SATA-S10
3646: * 88F5082 GL #SATA-S10
3647: */
3648: if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) ||
3649: sc->sc_gen == gen2e) {
3650: uint32_t tmp = 0;
3651:
3652: /* 88SX60x1 FEr SATA #13 */
3653: if (sc->sc_gen == 2 && sc->sc_rev == 0x07)
3654: tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3);
3655:
3656: reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4);
3657: reg |= (1 << 0);
3658: reg &= ~(1 << 1);
3659: /* PHY Mode 4 Register of Gen IIE has some restriction */
3660: if (sc->sc_gen == gen2e) {
3661: reg &= ~0x5de3fffc;
3662: reg |= (1 << 2);
3663: }
3664: MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg);
3665:
3666: /* 88SX60x1 FEr SATA #13 */
3667: if (sc->sc_gen == 2 && sc->sc_rev == 0x07)
3668: MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp);
3669: }
3670:
3671: /* Revert values of pre-emphasis and signal amps to the saved ones */
3672: reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);
3673: reg &= ~0x000007e0; /* pre and amps mask */
3674: reg |= mvport->_fix_phy_param.pre_amps;
3675: reg &= ~(1 << 16);
3676: if (sc->sc_gen == gen2e) {
3677: /*
3678: * according to mvSata 3.6.1, some IIE values are fixed.
3679: * some reserved fields must be written with fixed values.
3680: */
3681: reg &= ~0xC30FF01F;
3682: reg |= 0x0000900F;
3683: }
3684: MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg);
3685: }
3686:
3687: #ifndef MVSATA_WITHOUTDMA
3688: static void
3689: mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, int quetag,
3690: struct ata_bio *ata_bio)
3691: {
3692: struct crqb_gen2e *crqb;
3693: bus_addr_t eprd_addr;
3694: daddr_t blkno;
3695: uint32_t ctrlflg, rw;
3696: uint8_t cmd, head;
3697: const int drive =
3698: mvport->port_ata_channel.ch_queue->active_xfer->c_drive;
3699:
3700: eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr +
3701: mvport->port_reqtbl[quetag].eprd_offset;
3702: rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE;
1.27 jakllsch 3703: ctrlflg = (rw | CRQB_CDEVICEQUETAG(0) | CRQB_CPMPORT(drive) |
1.1 kiyohara 3704: CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(quetag));
3705: cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA;
1.26 jakllsch 3706: if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) {
3707: head = WDSD_LBA;
3708: } else {
3709: head = 0;
3710: }
1.1 kiyohara 3711: blkno = ata_bio->blkno;
3712: if (ata_bio->flags & ATA_LBA48)
3713: cmd = atacmd_to48(cmd);
3714: else {
3715: head |= ((ata_bio->blkno >> 24) & 0xf);
3716: blkno &= 0xffffff;
3717: }
3718: crqb = &mvport->port_crqb->crqb_gen2e + erqqip;
3719: crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK);
3720: crqb->cprdbh = htole32((eprd_addr >> 16) >> 16);
3721: crqb->ctrlflg = htole32(ctrlflg);
3722: if (mvport->port_edmamode == dma) {
3723: crqb->atacommand[0] = htole32(cmd << 16);
3724: crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24);
3725: crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff));
3726: crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff);
3727: } else { /* ncq/queued */
3728:
3729: /*
3730: * XXXX: Oops, ata command is not correct. And, atabus layer
3731: * has not been supported yet now.
3732: * Queued DMA read/write.
3733: * read/write FPDMAQueued.
3734: */
3735:
3736: crqb->atacommand[0] = htole32(
3737: (cmd << 16) | ((ata_bio->nblks & 0xff) << 24));
3738: crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24);
3739: crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff) |
3740: ((ata_bio->nblks >> 8) & 0xff));
3741: crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff);
3742: crqb->atacommand[3] = htole32(quetag << 3);
3743: }
3744: }
3745:
3746:
3747: #ifdef MVSATA_DEBUG
3748: #define MVSATA_DEBUG_PRINT(type, size, n, p) \
3749: do { \
3750: int _i; \
3751: u_char *_p = (p); \
3752: \
3753: printf(#type "(%d)", (n)); \
3754: for (_i = 0; _i < (size); _i++, _p++) { \
3755: if (_i % 16 == 0) \
3756: printf("\n "); \
3757: printf(" %02x", *_p); \
3758: } \
3759: printf("\n"); \
3760: } while (0 /* CONSTCOND */)
3761:
3762: static void
3763: mvsata_print_crqb(struct mvsata_port *mvport, int n)
3764: {
3765:
3766: MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb),
3767: n, (u_char *)(mvport->port_crqb + n));
3768: }
3769:
3770: static void
3771: mvsata_print_crpb(struct mvsata_port *mvport, int n)
3772: {
3773:
3774: MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb),
3775: n, (u_char *)(mvport->port_crpb + n));
3776: }
3777:
3778: static void
3779: mvsata_print_eprd(struct mvsata_port *mvport, int n)
3780: {
3781: struct eprd *eprd;
3782: int i = 0;
3783:
3784: eprd = mvport->port_reqtbl[n].eprd;
3785: while (1 /*CONSTCOND*/) {
3786: MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd),
3787: i, (u_char *)eprd);
3788: if (eprd->eot & EPRD_EOT)
3789: break;
3790: eprd++;
3791: i++;
3792: }
3793: }
3794: #endif
3795: #endif
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