CVS log for src/sys/dev/ic/i82801lpcreg.h

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Pull up following revision(s) (requested by riastradh in ticket #282):

	sys/dev/pci/ichsmb.c: revision 1.82
	sys/arch/amd64/conf/GENERIC: revision 1.602
	sys/arch/x86/pci/tco.c: revision 1.10
	sys/arch/x86/pci/tco.h: revision 1.5
	sys/arch/x86/pci/ichlpcib.c: revision 1.59
	sys/dev/ic/i82801lpcreg.h: revision 1.17
	sys/arch/x86/pci/files.pci: revision 1.27
	sys/dev/pci/files.pci: revision 1.446

ichsmb(4), tco(4): Add support for TCO on newer Intel chipsets.

TCO (`Total Cost of Ownership', Intel's bizarre name for a watchdog
timer) used to hang off the Intel I/O platform controller hub's (ICH)
low-pin-count interface bridge (LPC IB), or ichlpcib(4).  On newer
devices, it hangs off the ICH SMBus instead.
Tested on INTEL 100SERIES_SMB (works) and INTEL 100SERIES_LP_SMB
(doesn't work, still not sure why).

XXX kernel revbump: This breaks the module ABI -- tco(4) modules
older than the change to make ta_has_rcba into ta_version will
incorrectly attach at buses they do not understand.  (However, the
tco(4) driver is statically built into GENERIC, so maybe it's safe
for pullup since the module wouldn't have worked anyway.)

ichsmb(4), tco(4): Add support for TCO on newer Intel chipsets.

TCO (`Total Cost of Ownership', Intel's bizarre name for a watchdog
timer) used to hang off the Intel I/O platform controller hub's (ICH)
low-pin-count interface bridge (LPC IB), or ichlpcib(4).  On newer
devices, it hangs off the ICH SMBus instead.

Tested on INTEL 100SERIES_SMB (works) and INTEL 100SERIES_LP_SMB
(doesn't work, still not sure why).

XXX kernel revbump: This breaks the module ABI -- tco(4) modules
older than the change to make ta_has_rcba into ta_version will
incorrectly attach at buses they do not understand.  (However, the
tco(4) driver is statically built into GENERIC, so maybe it's safe
for pullup since the module wouldn't have worked anyway.)

ichsmb(4): Remove confusing `lpcib_' prefix on register names.

tco(4): Nix PMC_TCO_BASE offset in TCO register definitions.

This just uses a subregion with PMC_TCO_BASE automatically applied.

No functional change intended.

tco(4): Use a subregion of the PMC registers for TCO registers.

This is an intermediate step that will let us decouple it from access
via PMBASE.

ichlpcib(4), tco(4): Take `lpcib_' off various names.

For PMC-specific ones, change `lpcib_' to `pmc_'.  These are in a
separate PCI device in newer chipsets.

For TCO-specific ones, which may live in different places, whether at
their own base address or as an offset from PMBASE, just leave it as
`tco_' or `tcotimer'.

No functional change intended.

update from HEAD

Sync with HEAD

Pull up the following changes, requested by msaitoh in ticket #1942:

sys/arch/x86/pci/ichlpcib.c		1.40, 1.45 via patch
sys/dev/ic/i82801lpcreg.h		1.12
sys/dev/pci/pci_map.c			1.32 via patch

	- Fix a bug that ichlpcib(4) maps I/O area incorrectly. It might also
	  fixes ACPI related problem described in PR#48960:
	  - The LPCIB_PCI_PMBASE and LPCIB_PCI_GPIO register are alike PCI BAR
	    but not completely compatible with it. It's ok because the
	    registers' addresses are out of BAR0-BAR5(0x10-0x24) and are
	    located in the device-dependent header. The PMBASE and GPIO
	    registers define the base address and the type but not describe
	    the size. The size is fixed to 128bytes. So use
	    pci_mapreg_submap().
	  - Fix the calculation of the map size in pci_mapreg_submap().
	- Use '\n' at the end of aprint_error_dev() format strings.

Pull up following revision(s) (requested by msaitoh in ticket #1229):
	sys/arch/x86/pci/ichlpcib.c: revision 1.40, 1.45
	sys/dev/pci/pcivar.h: revision 1.101
	sys/dev/pci/pci_map.c: revision 1.32
	sys/dev/ic/i82801lpcreg.h: revision 1.12
Use '\n' at the end of all aprint_error_dev() format strings.
--
Fix a bug that ichlpcib(4) maps I/O area incorrectly and then fails to attach
gpio. It might also fixes ACPI related problem described in PR#48960:
 - The LPCIB_PCI_PMBASE and LPCIB_PCI_GPIO register are alike PCI BAR but not
   completely compatible with it. It's ok because the registers' addresses are
   out of BAR0-BAR5(0x10-0x24) and are located in the device-dependent header.
   The PMBASE and GPIO registers define the base address and the type but not
   describe the size. The size is fixed to 128bytes. So use
   pci_mapreg_submap().
 - Make pci_mapreg_submap() extern again.
 - Fix the calculation of the map size in pci_mapreg_submap().

Pull up following revision(s) (requested by msaitoh in ticket #394):
	sys/dev/pci/pcivar.h: revision 1.101
	sys/dev/pci/pci_map.c: revision 1.32
	sys/dev/ic/i82801lpcreg.h: revision 1.12
	sys/arch/x86/pci/ichlpcib.c: revision 1.45
Fix a bug that ichlpcib(4) maps I/O area incorrectly and then fails to attach
gpio. It might also fix ACPI related problem described in PR#48960:
  - The LPCIB_PCI_PMBASE and LPCIB_PCI_GPIO register are alike PCI BAR but not
    completely compatible with it. It's ok because the registers' addresses are
    out of BAR0-BAR5(0x10-0x24) and are located in the device-dependent header.
    The PMBASE and GPIO registers define the base address and the type but not
    describe the size. The size is fixed to 128bytes. So use
    pci_mapreg_submap().
  - Make pci_mapreg_submap() extern again.
  - Fix the calculation of the map size in pci_mapreg_submap().

Fix a bug that ichlpcib(4) maps I/O area incorrectly and then fails to attach
gpio. It might also fix ACPI related problem described in PR#48960:
 - The LPCIB_PCI_PMBASE and LPCIB_PCI_GPIO register are alike PCI BAR but not
   completely compatible with it. It's ok because the registers' addresses are
   out of BAR0-BAR5(0x10-0x24) and are located in the device-dependent header.
   The PMBASE and GPIO registers define the base address and the type but not
   describe the size. The size is fixed to 128bytes. So use
   pci_mapreg_submap().
 - Make pci_mapreg_submap() extern again.
 - Fix the calculation of the map size in pci_mapreg_submap().

sync with head

Sync with HEAD.

sync with head.

Finish cleaning up pchb from recent change.
Use fewer magic numbers in ichlpcib.
Slightly improve style conformance.
Update paths in cpp re-inclusion guards.

sync with head

gpio(4) support for Intel ICH southbridges.

Tested on Intel SS4200-E (ICH7), and Acorp 6A815EPD (ICH2) motherboards,
on amd64 and i386 ports respectively.

It should be noted that the majority of boards with ICH chips do not
expose the GPIO pins for off-board use.  For instance, aside from the
three exposed-on-a-header pins on the 6A815EPD, another pin is also
used to control write protect on the FWH.  The SS4200 exposes the GPIO
on a header that connects to the 10 LEDs on the front panel, as well
as a tact switch on the back panel.

Add more-complete definitions of ICH GPIO-related registers.
While here, fix a typo in a register number.

Sync with HEAD.

sync with head.

sync with head.

Remove clause 3 and 4 from TNF licenses

sync with head

sync with HEAD

Sync with head.

sync with head.

Merge jmcneill-pm branch.

Sync with head.

Don't use a global variable to decide whether this is a ICH6+,
use a variable in the softc to determine whether the RCBA is supported.
Add generic HPET support for ICH5 and ICH6+.

This is not (yet) enabled by default, until someone adds the code to
not use the direct attachment if hpet was configured via ACPI.

Sync with HEAD.

sync with head.

Sync with HEAD.

Move the ICH SMB defs to dev/ic/i82801lpcreg.h, it's where it belongs.
This is to avoid code duplication.

Some changes for the ichlpcib driver:

- Moved to x86/pci, so that EM64T systems running NetBSD/amd64 can use it.
- Added support for the TCO on ICH6 or newer chipsets, adapted from
  FreeBSD.
- Added timecounter support for the power management timer, adapted from
  OpenBSD.
- Plus some misc/cosmetic changes.

Thanks to yukonbob on irc@freenode for testing the TCO part on ICH4-M.
Tested by me with ICH7 too.

sync with head

sync with head.

Sync with head.

sync with head.

Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

merge ktrace-lwp.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

file i82801lpcreg.h was added on branch ktrace-lwp on 2004-08-03 10:46:15 +0000

add several definitions useful for ICH-based speedstep.
(from linux and freebsd.)

Add Intel ICHn PCI-LPC bridge driver.
It is a pcib, but with sysmon watchdog support.