CVS log for src/sys/dev/ic/dwc_gmac_reg.h

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#define<tab> consistency

Handle GMAC_MAC_Version's that include USERVER.

Remove unused "SHIFT" defines. The "MASK" versions exist.

fix various typos in comments.

Pull up following revision(s) (requested by mrg in ticket #1045):

	sys/kern/uipc_mbuf.c: revision 1.235
	sys/dev/ic/dwc_gmac.c: revision 1.70
	sys/dev/ic/dwc_gmac_reg.h: revision 1.20
	sys/dev/ic/dwc_gmac.c: revision 1.66
	sys/dev/ic/dwc_gmac.c: revision 1.67
	sys/dev/ic/dwc_gmac.c: revision 1.68

awge: fix issue that caused rx packets to be corrupt with DIAGNOSTIC kernel

It seems the hardware can only reliably do rx DMA to addresses that are
dcache size aligned. This is hinted at by some GMAC data sheets but hard to
find an authoritative source.

on non-DIAGNOSTIC kernels we always implicitly get MCLBYTES-aligned mbuf
data pointers, but with the reintroduction of POOL_REDZONE for DIAGNOSTIC
we can get 8-byte alignment due to redzone padding. So align rx pointers to
64 bytes which should be good for both arm32 and aarch64.
While here change some bus_dmamap_load() to bus_dmamap_load_mbuf() and add
one missing bus_dmamap_sync(). Also fixes the code to not assume that
MCLBYTES == AWGE_MAX_PACKET. User may override MCLSHIFT in kernel config.
correct pointer arithmetics

mcl_cache: align items to COHERENCY_UNIT

Because we do cache incoherent DMA to/from mbufs we cannot safely share
share cache lines with adjacent items that may be concurrently accessed.

awge: drop redundant m_adj(). Handled via uipc_mbuf.c r1.235 instead.

Mask all the MMC counter interrupts if the MMC module is present.

Mask all the MMC counter interrupts if the MMC module is present.

Sync with HEAD

Sync with head

Bring back support for enhanced descriptor format in newer core versions.
Fix a few endian bugs and check the main core version before trying to
read the hardware feature mask. Only read the hardware feature register
if core version reported is >= 3.5 (all my older hardware reports 0).
With some hints and patches from jared, and ok from aymeric

Ssync with HEAD

Revert the recent support for enhanced descriptors until a viable solution is
found.

It broke at least Cubietruck, Orange Pi One, and maybe Rock64 ethernets in
different ways. Unfortunately it works on my Olinuxino Micro and Lime 2 so I
can't reproduce the bugs for now.

Should fix PR#53637

Add support for the enhanced descriptors feature.

This makes "recent" dwc gmac controllers, as found e.g. on the Cyclone V, work.
The change was also tested working on an Allwinner A20 which doesn't have the
feature.

No negative reaction on port-arm.

Sync with HEAD

Add flag for disabling store-and-forward mode, and a callback for notifying
bus glue that the link speed has changed.

update from HEAD

Sync with HEAD (as of 26th Dec)

Pull up following revision(s) (requested by jmcneill in ticket #1053):
	sys/dev/ic/dwc_gmac_reg.h: revision 1.15
Fix an off by one in the bit definition for RX store and forward mode.
Pointed out by ganbold.
While there add a few other bits of the same register.

Pull up following revision(s) (requested by jmcneill in ticket #1053):
	sys/dev/ic/dwc_gmac_reg.h: revision 1.15
Fix an off by one in the bit definition for RX store and forward mode.
Pointed out by ganbold.
While there add a few other bits of the same register.

file dwc_gmac_reg.h was added on branch tls-maxphys on 2017-12-03 11:37:03 +0000

Fix an off by one in the bit definition for RX store and forward mode.
Pointed out by ganbold.
While there add a few other bits of the same register.

Pull up following revision(s) (requested by snj in ticket #481):
	sys/dev/ic/dwc_gmac_var.h: revision 1.6
	sys/dev/ic/dwc_gmac_reg.h: revision 1.13
	sys/dev/ic/dwc_gmac.c: revision 1.25
	sys/dev/ic/dwc_gmac.c: revision 1.26
	sys/dev/ic/dwc_gmac.c: revision 1.28
	sys/dev/ic/dwc_gmac.c: revision 1.31
- Add MII flow control support
- Set "disable jabber" and "auto padding/CRC stripping" bits in MAC conf
- Write intr mask to intr mask register, not status
- Setup both TX and RX burst modes
- Setup both TX and RX store & forward modes
- Correct an issue with the "end" descriptor passed to dwc_gmac_txdesc_sync
  in dwc_gmac_tx_intr
ok martin@
Revert previous change to dwc_gmac_txintr() - while it looks strange at
first sight (and sorry I didn't spot it when reviewing), it is a small
optimization and actually correct.
Add a comment explaining it.
After handling an interrupt, try to handle more packets as we may have
space in the descriptor ring now.
Pointed out by Jared.
fix a couple txq fencepost issues, from FUKAUMI Naoki <fun@naobsd.org>

Bits and values for checksum insertion controll

- Add MII flow control support
- Set "disable jabber" and "auto padding/CRC stripping" bits in MAC conf
- Write intr mask to intr mask register, not status
- Setup both TX and RX burst modes
- Setup both TX and RX store & forward modes
- Correct an issue with the "end" descriptor passed to dwc_gmac_txdesc_sync
  in dwc_gmac_tx_intr

ok martin@

Pull up following revision(s) (requested by martin in ticket #189):
	sys/dev/ic/dwc_gmac.c: revision 1.1-1.24
	sys/dev/ic/dwc_gmac_reg.h: revision 1.1-1.12
	sys/dev/ic/dwc_gmac_var.h: revision 1.1-1.5
Add support for Synopsis Designware GMAC ethernet core, as found on
various Allwiner boards and used by the awge(4) driver.

file dwc_gmac_reg.h was added on branch netbsd-7 on 2014-11-09 19:06:57 +0000

Fix grammar

multicast hash filter support

add $NetBSD$ to top of files

The RXINT bit is a RX interrupt DISABLE bit.

Add more comments

Add more bits and comments, parts from jmcneill.

Fix GMAC_MII_CLKMASK and add a few clk setup bits for it.

Add MAC config register bit definitions

Fix a few bits, add more status bit definitions and some comments.
Remove driver specific preference definitions.

Cleanup and __BIT()ify

Make the MII clock variable and passed in from the frontend.

Add work-in-progress driver for the Designware GMAC core, found on some
allwinner chips.