Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

===================================================================
RCS file: /ftp/cvs/cvsroot/src/sys/dev/ic/dwc_gmac.c,v
rcsdiff: /ftp/cvs/cvsroot/src/sys/dev/ic/dwc_gmac.c,v: warning: Unknown phrases like `commitid ...;' are present.
retrieving revision 1.24
retrieving revision 1.25
diff -u -p -r1.24 -r1.25
--- src/sys/dev/ic/dwc_gmac.c	2014/10/27 09:40:00	1.24
+++ src/sys/dev/ic/dwc_gmac.c	2014/11/22 18:31:03	1.25
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_gmac.c,v 1.24 2014/10/27 09:40:00 skrll Exp $ */
+/* $NetBSD: dwc_gmac.c,v 1.25 2014/11/22 18:31:03 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
@@ -41,7 +41,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.24 2014/10/27 09:40:00 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.25 2014/11/22 18:31:03 jmcneill Exp $");
 
 /* #define	DWC_GMAC_DEBUG	1 */
 
@@ -225,7 +225,8 @@ dwc_gmac_attach(struct dwc_gmac_softc *s
         mii->mii_readreg = dwc_gmac_miibus_read_reg;
         mii->mii_writereg = dwc_gmac_miibus_write_reg;
         mii->mii_statchg = dwc_gmac_miibus_statchg;
-        mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
+        mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY,
+	    MIIF_DOPAUSE);
 
         if (LIST_EMPTY(&mii->mii_phys)) { 
                 aprint_error_dev(sc->sc_dev, "no PHY found!\n");
@@ -246,7 +247,7 @@ dwc_gmac_attach(struct dwc_gmac_softc *s
 	 * Enable interrupts
 	 */
 	s = splnet();
-	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_INTR,
+	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_INTMASK,
 	    AWIN_DEF_MAC_INTRMASK);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_INTENABLE,
 	    GMAC_DEF_DMA_INT_MASK);
@@ -668,7 +669,7 @@ dwc_gmac_miibus_statchg(struct ifnet *if
 {
 	struct dwc_gmac_softc * const sc = ifp->if_softc;
 	struct mii_data * const mii = &sc->sc_mii;
-	uint32_t conf;
+	uint32_t conf, flow;
 
 	/*
 	 * Set MII or GMII interface based on the speed
@@ -679,6 +680,8 @@ dwc_gmac_miibus_statchg(struct ifnet *if
 	    |AWIN_GMAC_MAC_CONF_FULLDPLX);
 	conf |= AWIN_GMAC_MAC_CONF_FRAMEBURST
 	    | AWIN_GMAC_MAC_CONF_DISABLERXOWN
+	    | AWIN_GMAC_MAC_CONF_DISABLEJABBER
+	    | AWIN_GMAC_MAC_CONF_ACS
 	    | AWIN_GMAC_MAC_CONF_RXENABLE
 	    | AWIN_GMAC_MAC_CONF_TXENABLE;
 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
@@ -692,8 +695,20 @@ dwc_gmac_miibus_statchg(struct ifnet *if
 	case IFM_1000_T:
 		break;
 	}
-	if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX)
+
+	flow = 0;
+	if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
 		conf |= AWIN_GMAC_MAC_CONF_FULLDPLX;
+		flow |= __SHIFTIN(0x200, AWIN_GMAC_MAC_FLOWCTRL_PAUSE);
+	}
+	if (mii->mii_media_active & IFM_ETH_TXPAUSE) {
+		flow |= AWIN_GMAC_MAC_FLOWCTRL_TFE;
+	}
+	if (mii->mii_media_active & IFM_ETH_RXPAUSE) {
+		flow |= AWIN_GMAC_MAC_FLOWCTRL_RFE;
+	}
+	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+	    AWIN_GMAC_MAC_FLOWCTRL, flow);
 
 #ifdef DWC_GMAC_DEBUG
 	aprint_normal_dev(sc->sc_dev,
@@ -720,9 +735,9 @@ dwc_gmac_init(struct ifnet *ifp)
 	 * XXX - the GMAC_BUSMODE_PRIORXTX bits are undocumented.
 	 */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE,
-	    GMAC_BUSMODE_FIXEDBURST |
-	    __SHIFTIN(GMAC_BUSMODE_PRIORXTX_41, GMAC_BUSMODE_PRIORXTX) |
-	    __SHIFTIN(8, GMCA_BUSMODE_PBL));
+	    GMAC_BUSMODE_FIXEDBURST | GMAC_BUSMODE_4PBL |
+	    __SHIFTIN(2, GMAC_BUSMODE_RPBL) |
+	    __SHIFTIN(2, GMAC_BUSMODE_PBL));
 
 	/*
 	 * Set up address filter
@@ -758,7 +773,7 @@ dwc_gmac_init(struct ifnet *ifp)
 	 */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 	    AWIN_GMAC_DMA_OPMODE, GMAC_DMA_OP_RXSTART | GMAC_DMA_OP_TXSTART |
-	    GMAC_DMA_OP_STOREFORWARD);
+	    GMAC_DMA_OP_RXSTOREFORWARD | GMAC_DMA_OP_TXSTOREFORWARD);
 
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
@@ -967,7 +982,7 @@ dwc_gmac_tx_intr(struct dwc_gmac_softc *
 #endif
 
 		desc = &sc->sc_txq.t_desc[i];
-		dwc_gmac_txdesc_sync(sc, i, i+1,
+		dwc_gmac_txdesc_sync(sc, i, TX_NEXT(i),
 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 		flags = le32toh(desc->ddesc_status);