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eqos(4): Extend bitwidth of SYSBUS_MODE_{RD,WR}_OSR_LMT to 4bits.
eqos(4): Set bit 31 when writing MAC_ADDRESS0_HIGH register.
Pull up following revision(s) (requested by msaitoh in ticket #446):
sys/dev/pci/if_eqos_pci.c: revision 1.3
sys/arch/i386/conf/GENERIC: revision 1.1251
sys/arch/i386/conf/GENERIC: revision 1.1252
sys/arch/amd64/conf/GENERIC: revision 1.607
sys/arch/amd64/conf/GENERIC: revision 1.608
sys/dev/ic/dwc_eqos.c: revision 1.20
sys/dev/ic/dwc_eqos.c: revision 1.21
share/man/man4/eqos.4: revision 1.2
sys/dev/ic/dwc_eqos.c: revision 1.22
sys/dev/ic/dwc_eqos_reg.h: revision 1.7
sys/dev/ic/dwc_eqos.c: revision 1.23
sys/dev/ic/dwc_eqos_reg.h: revision 1.8
sys/dev/ic/dwc_eqos.c: revision 1.24
sys/dev/ic/dwc_eqos.c: revision 1.25
sys/dev/ic/dwc_eqos.c: revision 1.26
sys/dev/ic/dwc_eqos.c: revision 1.27
sys/dev/ic/dwc_eqos_var.h: revision 1.5
sys/dev/ic/dwc_eqos.c: revision 1.28
sys/dev/ic/dwc_eqos_var.h: revision 1.6
sys/dev/ic/dwc_eqos.c: revision 1.29
sys/dev/ic/dwc_eqos.c: revision 1.18
sys/dev/ic/dwc_eqos.c: revision 1.19
sys/dev/pci/files.pci: revision 1.448
sys/dev/pci/if_eqos_pci.c: revision 1.1
sys/dev/pci/if_eqos_pci.c: revision 1.2
eqos(4): Fix definition of GMAC_MAC_HW_FEATURE1_RXFIFOSIZE.
eqos(4): Fix a bug that the MAC address is swapped.
Don't swap the MAC address in eqos_get_eaddr(). Other OSes except FreeBSD
(which was based on NetBSD's) don't swap it. With this change, my own
OnLogic Helix 330's MAC address becomes correct. The OUI is 84:8b:cd:4d.
It's owned by Logic Supply and they were acquired by OnLogic.
On Quartz64 with UEFI, the MAC address is wrongly set and the multicast
bit might be set. To do workaround, clear the bit if it's set.
eqos(4): Add missing clock range.
eqos(4): Accept if snpsver == 0x52. Tested with Intel Elkhart Lake.
TODO:
Multiqueue support.
Add watchdog timer.
Add detach function.
eqos(4): Add initial support for Intel Elkhart Lake internal Ethernet devices.
- Only tested on PSE SGMII 1G Ethernet MAC with MaxLinear GPY115.
- I don't know why dmat64 doesn't work. eqos_attach() have a special
code if EQOS_HW_FEATURE_ADDR64_32BIT(sc) is true, but it seems it doesn't
work.
- TODO:
Multiqueue support.
Detach support.
eqos(4): Fix compile error for arch that sizeof(bus_size_t) == 4 (i386).
Trailing whitespace
eqos(4): Disable eqos(4) by default because it's not stable on x86.
eqos(4): KNF. No functional change.
eqos(4): Add and modify some DPRINTF()s.
eqos(4): Add sysctls for debugging.
eqos(4): Use EQOS_TXLOCK() more to be stable.
Fix a bug that sc_tx.{cur,next,queued} become inconsitent.
Use txlock when accessing TX data.
eqos(4): Set TX/RX DMA burst length to improve performance.
eqos(4): Set flow control correctly.
eqos_pci: Limit to 32bit DMA only for PSE devices.
eqos(4): Fix typo in comment.
eqos(4): Set TX/RX DMA burst length to improve performance.
eqos(4): Fix definition of GMAC_MAC_HW_FEATURE1_RXFIFOSIZE.
rename EQOS_TDES3_* macro to EQOS_TDES3_{TX,RX}_*, and add more defs.
Avoid confusion because some definitions are different bits with the same name for TX and RX.
no functional changes.
Fix eqos(4) to work on RK3588 as well. - Several registers needed to be initialized - Add some register definitions
add some register bits for interrupt control/error status. (not yet used.)
eqos: handle the GMAC_MTL_INTERRUPT_STATUS register having something drain a couple of registers that want either a read or a write-1-to- clear bit, and keep track of how many happen via evcnt. i had this trigger one time, but not since adding instrumentation to see exactly it was saying (the GMAC_MTL_INTERRUPT_STATUS_Q0IS bit was set, and it requires some handling now implemented.) ok jmcneill
eqos: interrupt evcnt and minor fix there's basic interrupt evcnt, which is the parent for the rx and tx interrupts, and 3 status interrupts, one of which has 7 more subtypes (watchdog timeout, carrier missing/lost, etc.) as these cases are evcnt counted now, make some debugging default off. avoid removing bits from dma_status when rx/tx is handled, so that later check of dma_status for non-zero does not trip. the two bits in dma_status removed are never checked again besides the test that may have failed (but probably doesn't as at least one other bit in two other variables will be set.) ok jmcneill
Add driver for DesignWare Ethernet Quality-of-Service controller.