CVS log for src/sys/dev/ic/ahcisatavar.h

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Pull up following revision(s) (requested by abs in ticket #366):

	sys/dev/pci/ahcisata_pci.c: revision 1.70
	sys/dev/ic/ahcisata_core.c: revision 1.108
	sys/dev/ic/ahcisatavar.h: revision 1.28
	sys/conf/files: revision 1.1309

Rework AHCISATA_EXTRA_DELAY for kern/56737
- Remove AHCI_QUIRK_EXTRA_DELAY as issue appears to be drive and
  not controller related
- Replace AHCISATA_EXTRA_DELAY with AHCISATA_REMOVE_EXTRA_DELAY,
  so defaulting to enabling the extra delay, as the downside of
  slower probing on systems which do not need it is less than having
  other systems intermittently fail to probe and attach drives
- Also allow disabling extra delay with AHCISATA_EXTRA_DELAY_MS = 0

We should return to this code to work out which of the extra delays
are needed, and how long they need to be. It may be that faster
systems are more likely to trigger the issue (I've only seen it on
a 13th gen i7-13700, though only tested on a limited set)

Rework AHCISATA_EXTRA_DELAY for kern/56737

- Remove AHCI_QUIRK_EXTRA_DELAY as issue appears to be drive and
  not controller related
- Replace AHCISATA_EXTRA_DELAY with AHCISATA_REMOVE_EXTRA_DELAY,
  so defaulting to enabling the extra delay, as the downside of
  slower probing on systems which do not need it is less than having
  other systems intermittently fail to probe and attach drives
- Also allow disabling extra delay with AHCISATA_EXTRA_DELAY_MS = 0

We should return to this code to work out which of the extra delays
are needed, and how long they need to be. It may be that faster
systems are more likely to trigger the issue (I've only seen it on
a 13th gen i7-13700, though only tested on a limited set)

XXX pullup -10

ahcisata(4): Introduce AHCI_QUIRK_EXTRA_DELAY quirk for devices that
need extra delays as done by AHCISATA_EXTRA_DELAY option.

Enable this quirk for "C600/X79 AHCI". Also add commented out quirk
entries for "Bay Trail SATA (AHCI)" and "Mobile AHCI SATA Controller",
for which non-reproducible failures worked around by extra delays have
been reported.

500 ms of delays inserted by these option/quirk may be too much. Add
AHCISATA_EXTRA_DELAY_MS option to adjust number of delays in ms, like:

----
options 	AHCISATA_EXTRA_DELAY_MS=200
----

Thanks prlw1@ and jun@ for testing!

Sync w/ HEAD.

Pull up following revision(s) (requested by jmcneill in ticket #1167):

	sys/dev/ic/ahcisata_core.c: revision 1.84
	sys/dev/ic/ahcisata_core.c: revision 1.85
	sys/dev/ic/ahcisata_core.c: revision 1.88
	sys/dev/ic/ahcisata_core.c: revision 1.89
	sys/arch/arm/nvidia/tegra_ahcisata.c: revision 1.13
	sys/dev/ic/ahcisatavar.h: revision 1.26
	sys/dev/ic/ahcisata_core.c: revision 1.90
	sys/dev/ic/ahcisata_core.c: revision 1.91
	sys/dev/ic/ahcisata_core.c: revision 1.92
	sys/dev/ata/satareg.h: revision 1.6

ahci_exec_fis: wait for the correct amount of time when AT_WAIT is set

Retry clearing WDCTL_RST a few times before giving up. Makes SATA work in
Solidrun Honeycomb LX2K.

AHCI 1.3.1 specification says that it is good practice for system software
to 'zero-out' the memory allocated and referenced by PxCLB and PxFB.

ahci_intr: use ffs in the port bitmask instead of looping over all 32 bits

AHCI 1.3.1 section 5.5.3 "Processing Completed Commands" says that we
should clear PxIS before IS.IPS.

Add G3 and DevSleep definitions. This changes the mask used by
SControl_IPM_NONE from 0x3 to 0x7.

Make sure to ack IS after PxIS when polling and when using multiple MSI-X
messages.

Remove the AHCI_QUIRK_SKIP_RESET quirk now that the underlying issue is
fixed.

Remove the AHCI_QUIRK_SKIP_RESET quirk now that the underlying issue is
fixed.

Trailing whitespace

Mostly merge changes from HEAD upto 20200411

Merge changes from current as of 20200406

Sync with head.

Pull up following revision(s) (requested by simonb in ticket #630):

	sys/dev/ic/ahcisatavar.h: revision 1.24
	sys/dev/pci/ahcisata_pci.c: revision 1.57
	sys/dev/ic/ahcisata_core.c: revision 1.81

Add new AHCI_QUIRK_BADNCQ quick for controllers that have issues with
NCQ on (some) drives.  Enable this quirk for ATI (AMD) SB600/SB700
controllers.  Alternate fix for kern/54790 and kern/54855.
ok jdolecek@, tested on my SB700 chipset and tsutsui's SB600 chipset.

Add new AHCI_QUIRK_BADNCQ quick for controllers that have issues with
NCQ on (some) drives.  Enable this quirk for ATI (AMD) SB600/SB700
controllers.  Alternate fix for kern/54790 and kern/54855.

ok jdolecek@, tested on my SB700 chipset and tsutsui's SB600 chipset.

Make AHCI_RFIS_SYNC macro (currently unused) compile.

Sync with HEAD

Synch with HEAD

nothing handles AHCI_QUIRK_BADPMPRESET quirk, remove and change all entries
using it (ATI SB600/SB700) to instead use AHCI_QUIRK_BADPMP

Sync with HEAD, resolve a few conflicts

add optional hook for intr establish when active port is attached, export
ahci_intr_port() in form suitable for interrupt hanlder, and probe for GHC
MRSM flag as courtesy for use by the intr hook

towards multi-vector MSI/MSI-X support

Sync with HEAD, resolve a couple of conflicts

detach the controller itself on shutdown; adjust to not detach already
detached atabus/channel

Merge jdolecek-ncqfixes branch

- ata_xfer's are dynamicall allocated as needed using a pool, no longer
  limited to number of possible openings supported by controller; dump
  and recovery paths use dedicated pre-allocated storage
- moved callouts and condvars from ata_xfer to queue or channel, so that
  ata_xfer does not need special initialization
- slot allocation now done when xfer is being activated, uncoupled
  from memory allocation; active slots are no longer tracked by controller
  code
- channel and drive reset is done always via the atabus thread, and
  now executes with channel locked the whole time
- NCQ recovery moved to shared function, and run via the thread also
- added some workarounds for buggy error recovery AHCI emulation in QEMU
  and Parallels

designed to primarily fix kern/52614, but might also help with kern/47041
and kern/53183

refactor shared parts of the SATA error recovery into new function
ata_recovery_resume() and use for ahcisata/siisata/mvsata, also replace
per-controller hold/unhold with generic version

move the shared recovery code into separate file ata_recovery.c

update from HEAD

Merge support for SATA NCQ (Native Command Queueing) from jdolecek-ncq branch

ATA subsystem was changed to support several outstanding commands, and use
NCQ xfers if supported by both the controller and the disk, including NCQ
error recovery. Set NCQ high priority for BPRIO_TIMECRITICAL xfers
if supported. Added FUA support.

Done some work towards MP-safe, all ATA code tsleep()/wakeup() replaced
by condvars, and switched most code from spl* to mutexes (separate
wd(4) and ata channel lock).

Introduced new option WD_CHAOS_MONKEY to facilitate testing of error
handling, fixed several uncovered issues. Also fixed several problems
with kernel dump to wd(4) disk.

Tested with ahcisata(4), mvsata(4), siisata(4), piixide(4) on amd64,
with and without port multiplier, both disk and ATAPI devices; other
drivers and archs mechanically adjusted and compile-tested. NCQ is
supported for ahcisata(4) and siisata(4) for any controller, for
mvsata(4) only Gen IIe ones for now. Also enabled ATAPI support in
mvsata(4).

Thanks to Matt Thomas for initial ATA infrastructure patch, and
Jonathan A.Kollasch for siisata(4) NCQ changes and general testing.

Also fixes PR kern/43169 (wd(4)); and PR kern/11811, PR kern/47041,
PR kern/51979 (kernel dump)

fix logic bug in processing of finished commands - mask of active
commands can change during the loop as c_intr() callback can queue
new commands, so the interrupt routine should only mark as finished
those which were actually active before the loop started; otherwise
the code marked as finished commands which were just started, and
being executed by HBA, leading to all sorts of data corruption

while here mark the active mask volatile, as it is modified from
interrupt context

this fixes for good the random crashes, short reads, and fatal command
errors which I've been tracing down for past couple weeks

thanks to Jonathan (jakllsch@) for testing, and a script to easily
triggered the condition, and led to this bug being finally found and squashed

make compile without AHCI_DEBUG

update error handling:
- switch to ata_timeout()
- stop using ch_status/ch_error for passing state/error, stop setting
  ATACH_IRQ_WAIT in ch_flags; pass the state via the last parameter
  to c_intr() routine
- add NCQ recovery and KILL_REQUEUE
- only call atastart() in c_intr() if there was no error

ahcisata-specific tweaks:
- add some handling for PM in the error recovery using FBS register,
  according to spec it should be independant of actual FBSS feature; untested
  as my hw doesn't support PM

Sync with HEAD

Add AHCI_QUIRK_SKIP_RESET quirk to allow for skipping the drive reset
sequence in ahci_do_reset_drive.

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Merge needed changes from HEAD for cubie

- Only enable AHCI mode if it is not already enabled.
- Add support for capturing initial CAP/CAP2/PI regs before reset (and
  restoring them afterwords)
- Add optional callbacks for channel_start / channel_stop.

Allow the attachment to override ahci_ports.
Keep ACHI_PI cached in the softc.

Resync to 2012-11-19 00:00:00 UTC

sync with head

sc_ahci_cap should be uint32_t

Fix typo, pointed out by Markus W Kilbinger

Give AHCI_QUIRK_BADPMPRESET its own bit. Pointed out by Chuck Silvers, thanks !

Work around some SATA PMP issues in some AHCI controllers by either
disabling PMP entirely, or special handling in the reset function.
Controller list from linux and FreeBSD.

Apply back changes that were reverted on Jul 24 and Jul 26 (general ata/wdc
cleanup and SATA PMP support), now that I'm back to fix the fallouts.

Revert, with intention of restoring in a less invasive way, the SATA Port
Multiplier code.

ok christos@

Add sata Port MultiPlier (PMP) support to the ata bus layer,
as described in
http://mail-index.netbsd.org/tech-kern/2012/06/23/msg013442.html
PMP support in integrated to the atabus layer.
struct ata_channel's ch_drive[] is not dynamically allocated, and ch_ndrive
(renamed to ch_ndrives) closely reflects the size of the ch_drive[] array.
Add helper functions atabus_alloc_drives() and atabus_free_drives()
to manage ch_drive[]/ch_ndrives.
Add wdc_maxdrives to struct wdc_softc so that bus front-end can specify
how much drive they really support (master/slave or single).
ata_reset_drive() callback gains a uint32_t *sigp argument which,
when not NULL, will contain the signature of the device being reset.
While there, some cosmetic changes:
- added a drive_type enum to ata_drive_datas, and stop encoding the
  probed drive type in drive_flags (we were out of drive flags anyway).
- rename DRIVE_ATAPIST to DRIVE_ATAPIDSCW to better reflect what this
  really is
- remove ata_channel->ata_drives, it's redundant with the pointer in
  ata_drive_datas
- factor out the interpretation of SATA signatures in sata_interpet_sig()

propagate these changes to the ATA HBA drivers, and add support for PMP
to ahcisata(4) and siisata(4).

Thanks to:
- Protocase (http://www.protocase.com/) which provided a system
  with lots of controllers, SATA PMP and drive slots
- Conservation Genomics Laboratory, Department of Biology, New Mexico State
  University for hosting the above system
- Brook Milligan, who set up remote access and has been very responsive
  when SATA cable move was needed

sync with head

Sync with HEAD.

sync with head.

Support detachment of ahcisata(4).
Use use 64-bit DMA tag (where available) for ahcisata(4) at jmide(4).
Beginnings of detach/resume support for jmide(4).
Sprinkle static.  Misc. little changes.

Convert ahcisata(4) to C99 exact-width integer types.

sync with head

Remove closes 3 & 4 from my licence. Lots of thanks to Soren Jacobsen
for the booring work !

Sync with HEAD.

sync with head.

sync with head.

sync with HEAD

Split device_t and softc for ATA devices, as well as wd(4).  Other
cosmetic changes where appropriate.

Sync with HEAD.

sync with head.

Attach ahcisata(4) to any RAID controller that supports AHCI, and make it
pass the ATAC_CAP_RAID capability for them. ok'ed by bouyer@.

sync with HEAD

Sync with HEAD.

sync with head.

Sync with HEAD

Merge refactoring from jmcneill-pm.

sync with head.

Sync w/ NetBSD-4-RC_1

Pull up following revision(s) (requested by bouyer in ticket #678):
	distrib/sets/lists/man/mi: revision 1.1001
	doc/CHANGES: revision 1.853 via patch
	share/man/man4/Makefile: revision 1.428
	share/man/man4/jmide.4: revision 1.1
	sys/arch/amd64/conf/GENERIC: revision 1.143
	sys/arch/amd64/conf/INSTALL: revision 1.69
	sys/arch/i386/conf/GENERIC: revision 1.827
	sys/arch/i386/conf/INSTALL_LARGE: revision 1.2 via patch
	sys/arch/i386/conf/XEN2_DOM0: revision 1.26
	sys/conf/files: revision 1.844 via patch
	sys/dev/ic/ahcisata_core.c: revision 1.1 via patch
	sys/dev/ic/ahcisata_core.c: revision 1.3
	sys/dev/ic/ahcisatareg.h: revision 1.1
	sys/dev/ic/ahcisatavar.h: revision 1.1
	sys/dev/pci/ahcisata.c: delete
	sys/dev/pci/ahcisatareg.h: delete
	sys/dev/pci/ahcisata_pci.c: revision 1.1
	sys/dev/pci/files.pci: revision 1.287-1.288
	sys/dev/pci/jmide.c: revision 1.1-1.2
	sys/dev/pci/jmide_reg.h: revision 1.1
	sys/dev/pci/pcidevs: revision 1.878
Add JMicron Technology vendor ID, and their current PCIe SATA/PATA
controllers.

Split the ahcisata driver in pci front-end and bus-independant back-end.
add jmide(4), a driver for the JMicron Technology JMB36x PCIe to SATA II/PATA
controllers. These controllers can be found on add-on PCIe cards, or
on some motherboards to provide the PATA connectivity (e.g. some intel
ICH8-based motherboards).
Thanks to JMicron Technology for providing me documentation and
different sample boards for this work.

Move mapping of AHCI register so that jmide knows if it fails, and avoids
calling ahci_intr() (which would cause a panic).
Try to use the pciide function for SATA drives if attaching ahci fails (this
doesn't seems to work though, it may be BIOS dependant).
Thanks to Gary Duzan for testing multiple pacthes.

We're not ready to handle ATAPI yet so just claim there's no drive to the
upper layer. This should work around a NULL pointer dereference when
an ATAPI device is detected on a AHCI device.

Factor out the hardware initialization code in ahcisata_core.c,
and provide them to the pci frontend, which has now grown its own
softc and a power management handler.

There may be one too many re-initializations done on resume (witness
the multiple kernel messages from ahcisata), but at least this is
sufficient to get the Lenovo T60 to come out of resume with a
working disk controller and disk.

Sync with head.

Sync with head.

sync with head.

file ahcisatavar.h was added on branch yamt-lazymbuf on 2007-09-03 14:34:14 +0000

file ahcisatavar.h was added on branch wrstuden-fixsa on 2007-09-03 07:04:23 +0000

file ahcisatavar.h was added on branch netbsd-4 on 2007-08-31 20:09:24 +0000

file ahcisatavar.h was added on branch mjf-ufs-trans on 2007-07-11 20:05:39 +0000

file ahcisatavar.h was added on branch vmlocking on 2007-06-09 21:37:13 +0000

file ahcisatavar.h was added on branch yamt-idlelwp on 2007-05-17 13:41:25 +0000

Split the ahcisata driver in pci front-end and bus-independant back-end.