Annotation of src/sys/dev/ic/ahcisata_core.c, Revision 1.62.2.2
1.62.2.2! jdolecek 1: /* $NetBSD: ahcisata_core.c,v 1.62.2.1 2018/08/31 19:08:03 jdolecek Exp $ */
1.1 bouyer 2:
3: /*
4: * Copyright (c) 2006 Manuel Bouyer.
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: *
15: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25: *
26: */
27:
28: #include <sys/cdefs.h>
1.62.2.2! jdolecek 29: __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.62.2.1 2018/08/31 19:08:03 jdolecek Exp $");
1.1 bouyer 30:
31: #include <sys/types.h>
32: #include <sys/malloc.h>
33: #include <sys/param.h>
34: #include <sys/kernel.h>
35: #include <sys/systm.h>
36: #include <sys/disklabel.h>
1.4 ad 37: #include <sys/proc.h>
1.8 bouyer 38: #include <sys/buf.h>
1.1 bouyer 39:
40: #include <dev/ata/atareg.h>
41: #include <dev/ata/satavar.h>
42: #include <dev/ata/satareg.h>
1.26 jakllsch 43: #include <dev/ata/satafisvar.h>
1.20 jakllsch 44: #include <dev/ata/satafisreg.h>
1.40 bouyer 45: #include <dev/ata/satapmpreg.h>
1.1 bouyer 46: #include <dev/ic/ahcisatavar.h>
1.40 bouyer 47: #include <dev/ic/wdcreg.h>
1.1 bouyer 48:
1.16 bouyer 49: #include <dev/scsipi/scsi_all.h> /* for SCSI status */
50:
1.8 bouyer 51: #include "atapibus.h"
52:
1.1 bouyer 53: #ifdef AHCI_DEBUG
1.40 bouyer 54: int ahcidebug_mask = 0;
1.1 bouyer 55: #endif
56:
1.29 jakllsch 57: static void ahci_probe_drive(struct ata_channel *);
58: static void ahci_setup_channel(struct ata_channel *);
1.1 bouyer 59:
1.58 jdolecek 60: static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *);
61: static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *,
62: struct ata_xfer *xfer);
1.40 bouyer 63: static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *);
1.29 jakllsch 64: static void ahci_reset_channel(struct ata_channel *, int);
1.58 jdolecek 65: static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *);
1.29 jakllsch 66: static int ahci_ata_addref(struct ata_drive_datas *);
67: static void ahci_ata_delref(struct ata_drive_datas *);
68: static void ahci_killpending(struct ata_drive_datas *);
69:
1.58 jdolecek 70: static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *);
1.29 jakllsch 71: static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int);
1.58 jdolecek 72: static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *);
73: static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *);
74: static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *);
75: static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *);
76: static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int);
77: static int ahci_bio_start(struct ata_channel *, struct ata_xfer *);
78: static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *);
79: static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *);
1.29 jakllsch 80: static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int);
81: static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ;
82: static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int);
1.40 bouyer 83: static void ahci_channel_start(struct ahci_softc *, struct ata_channel *,
84: int, int);
1.58 jdolecek 85: void ahci_channel_recover(struct ahci_softc *, struct ata_channel *, int);
1.29 jakllsch 86: static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int);
1.1 bouyer 87:
1.8 bouyer 88: #if NATAPIBUS > 0
1.29 jakllsch 89: static void ahci_atapibus_attach(struct atabus_softc *);
90: static void ahci_atapi_kill_pending(struct scsipi_periph *);
91: static void ahci_atapi_minphys(struct buf *);
92: static void ahci_atapi_scsipi_request(struct scsipi_channel *,
1.8 bouyer 93: scsipi_adapter_req_t, void *);
1.58 jdolecek 94: static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *);
95: static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *);
96: static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *);
1.29 jakllsch 97: static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int);
98: static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int);
99: static void ahci_atapi_probe_device(struct atapibus_softc *, int);
1.8 bouyer 100:
101: static const struct scsipi_bustype ahci_atapi_bustype = {
102: SCSIPI_BUSTYPE_ATAPI,
103: atapi_scsipi_cmd,
104: atapi_interpret_sense,
105: atapi_print_addr,
106: ahci_atapi_kill_pending,
1.34 bouyer 107: NULL,
1.8 bouyer 108: };
109: #endif /* NATAPIBUS */
110:
1.1 bouyer 111: #define ATA_DELAY 10000 /* 10s for a drive I/O */
1.24 bouyer 112: #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */
113: #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10)
1.1 bouyer 114:
115: const struct ata_bustype ahci_ata_bustype = {
116: SCSIPI_BUSTYPE_ATA,
117: ahci_ata_bio,
118: ahci_reset_drive,
119: ahci_reset_channel,
120: ahci_exec_command,
121: ata_get_params,
122: ahci_ata_addref,
123: ahci_ata_delref,
124: ahci_killpending
125: };
126:
1.29 jakllsch 127: static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *);
1.7 joerg 128: static void ahci_setup_port(struct ahci_softc *sc, int i);
129:
1.51 jmcneill 130: static void
131: ahci_enable(struct ahci_softc *sc)
132: {
133: uint32_t ghc;
134:
135: ghc = AHCI_READ(sc, AHCI_GHC);
136: if (!(ghc & AHCI_GHC_AE)) {
137: ghc |= AHCI_GHC_AE;
138: AHCI_WRITE(sc, AHCI_GHC, ghc);
139: }
140: }
141:
1.29 jakllsch 142: static int
1.7 joerg 143: ahci_reset(struct ahci_softc *sc)
1.1 bouyer 144: {
1.7 joerg 145: int i;
1.1 bouyer 146:
147: /* reset controller */
148: AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR);
149: /* wait up to 1s for reset to complete */
150: for (i = 0; i < 1000; i++) {
1.6 bouyer 151: delay(1000);
1.1 bouyer 152: if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0)
153: break;
154: }
155: if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) {
156: aprint_error("%s: reset failed\n", AHCINAME(sc));
1.7 joerg 157: return -1;
1.1 bouyer 158: }
159: /* enable ahci mode */
1.51 jmcneill 160: ahci_enable(sc);
161:
162: if (sc->sc_save_init_data) {
163: AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap);
164: if (sc->sc_init_data.cap2)
165: AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2);
166: AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports);
167: }
168:
1.7 joerg 169: return 0;
170: }
1.1 bouyer 171:
1.29 jakllsch 172: static void
1.7 joerg 173: ahci_setup_ports(struct ahci_softc *sc)
174: {
175: int i, port;
176:
177: for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
1.62 kamil 178: if ((sc->sc_ahci_ports & (1U << i)) == 0)
1.7 joerg 179: continue;
180: if (port >= sc->sc_atac.atac_nchannels) {
181: aprint_error("%s: more ports than announced\n",
182: AHCINAME(sc));
183: break;
184: }
185: ahci_setup_port(sc, i);
186: }
187: }
188:
1.29 jakllsch 189: static void
1.7 joerg 190: ahci_reprobe_drives(struct ahci_softc *sc)
191: {
192: int i, port;
193: struct ahci_channel *achp;
194: struct ata_channel *chp;
195:
196: for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
1.62 kamil 197: if ((sc->sc_ahci_ports & (1U << i)) == 0)
1.7 joerg 198: continue;
199: if (port >= sc->sc_atac.atac_nchannels) {
200: aprint_error("%s: more ports than announced\n",
201: AHCINAME(sc));
202: break;
203: }
204: achp = &sc->sc_channels[i];
205: chp = &achp->ata_channel;
206:
207: ahci_probe_drive(chp);
208: }
209: }
210:
211: static void
212: ahci_setup_port(struct ahci_softc *sc, int i)
213: {
214: struct ahci_channel *achp;
215:
216: achp = &sc->sc_channels[i];
217:
218: AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh);
1.28 jakllsch 219: AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32);
1.7 joerg 220: AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis);
1.28 jakllsch 221: AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32);
1.7 joerg 222: }
223:
1.29 jakllsch 224: static void
1.7 joerg 225: ahci_enable_intrs(struct ahci_softc *sc)
226: {
227:
228: /* clear interrupts */
229: AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS));
230: /* enable interrupts */
231: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
232: }
233:
234: void
235: ahci_attach(struct ahci_softc *sc)
236: {
1.50 matt 237: uint32_t ahci_rev;
1.7 joerg 238: int i, j, port;
239: struct ahci_channel *achp;
240: struct ata_channel *chp;
241: int error;
242: int dmasize;
1.32 jakllsch 243: char buf[128];
1.7 joerg 244: void *cmdhp;
245: void *cmdtblp;
246:
1.51 jmcneill 247: if (sc->sc_save_init_data) {
248: ahci_enable(sc);
249:
250: sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP);
251: sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI);
252:
253: ahci_rev = AHCI_READ(sc, AHCI_VS);
254: if (AHCI_VS_MJR(ahci_rev) > 1 ||
255: (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) {
256: sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2);
257: } else {
258: sc->sc_init_data.cap2 = 0;
259: }
260: if (sc->sc_init_data.ports == 0) {
261: sc->sc_init_data.ports = sc->sc_ahci_ports;
262: }
263: }
264:
1.7 joerg 265: if (ahci_reset(sc) != 0)
266: return;
1.1 bouyer 267:
1.40 bouyer 268: sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP);
1.43 bouyer 269: if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) {
1.41 bouyer 270: aprint_verbose_dev(sc->sc_atac.atac_dev,
271: "ignoring broken port multiplier support\n");
272: sc->sc_ahci_cap &= ~AHCI_CAP_SPM;
273: }
1.40 bouyer 274: sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1;
275: sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1;
1.1 bouyer 276: ahci_rev = AHCI_READ(sc, AHCI_VS);
1.32 jakllsch 277: snprintb(buf, sizeof(buf), "\177\020"
278: /* "f\000\005NP\0" */
279: "b\005SXS\0"
280: "b\006EMS\0"
281: "b\007CCCS\0"
282: /* "f\010\005NCS\0" */
283: "b\015PSC\0"
284: "b\016SSC\0"
285: "b\017PMD\0"
286: "b\020FBSS\0"
287: "b\021SPM\0"
288: "b\022SAM\0"
289: "b\023SNZO\0"
290: "f\024\003ISS\0"
291: "=\001Gen1\0"
292: "=\002Gen2\0"
293: "=\003Gen3\0"
294: "b\030SCLO\0"
295: "b\031SAL\0"
296: "b\032SALP\0"
297: "b\033SSS\0"
298: "b\034SMPS\0"
299: "b\035SSNTF\0"
300: "b\036SNCQ\0"
301: "b\037S64A\0"
1.40 bouyer 302: "\0", sc->sc_ahci_cap);
1.32 jakllsch 303: aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u"
1.49 matt 304: ", %d port%s, %d slot%s, CAP %s\n",
1.32 jakllsch 305: AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev),
1.49 matt 306: sc->sc_atac.atac_nchannels,
307: (sc->sc_atac.atac_nchannels == 1 ? "" : "s"),
308: sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf);
1.1 bouyer 309:
1.58 jdolecek 310: sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA
311: | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0);
1.12 xtraeme 312: sc->sc_atac.atac_cap |= sc->sc_atac_capflags;
1.1 bouyer 313: sc->sc_atac.atac_pio_cap = 4;
314: sc->sc_atac.atac_dma_cap = 2;
315: sc->sc_atac.atac_udma_cap = 6;
316: sc->sc_atac.atac_channels = sc->sc_chanarray;
317: sc->sc_atac.atac_probe = ahci_probe_drive;
318: sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype;
319: sc->sc_atac.atac_set_modes = ahci_setup_channel;
1.8 bouyer 320: #if NATAPIBUS > 0
321: sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach;
322: #endif
1.1 bouyer 323:
324: dmasize =
325: (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels;
326: error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
1.29 jakllsch 327: &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT);
1.1 bouyer 328: if (error) {
329: aprint_error("%s: unable to allocate command header memory"
330: ", error=%d\n", AHCINAME(sc), error);
331: return;
332: }
1.29 jakllsch 333: error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg,
334: sc->sc_cmd_hdr_nseg, dmasize,
1.1 bouyer 335: &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
336: if (error) {
337: aprint_error("%s: unable to map command header memory"
338: ", error=%d\n", AHCINAME(sc), error);
339: return;
340: }
341: error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
342: BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd);
343: if (error) {
344: aprint_error("%s: unable to create command header map"
345: ", error=%d\n", AHCINAME(sc), error);
346: return;
347: }
348: error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd,
349: cmdhp, dmasize, NULL, BUS_DMA_NOWAIT);
350: if (error) {
351: aprint_error("%s: unable to load command header map"
352: ", error=%d\n", AHCINAME(sc), error);
353: return;
354: }
355: sc->sc_cmd_hdr = cmdhp;
356:
1.7 joerg 357: ahci_enable_intrs(sc);
1.1 bouyer 358:
1.50 matt 359: if (sc->sc_ahci_ports == 0) {
360: sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI);
361: AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports),
362: DEBUG_PROBE);
363: }
1.1 bouyer 364: for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
1.62 kamil 365: if ((sc->sc_ahci_ports & (1U << i)) == 0)
1.1 bouyer 366: continue;
367: if (port >= sc->sc_atac.atac_nchannels) {
368: aprint_error("%s: more ports than announced\n",
369: AHCINAME(sc));
370: break;
371: }
372: achp = &sc->sc_channels[i];
1.29 jakllsch 373: chp = &achp->ata_channel;
1.1 bouyer 374: sc->sc_chanarray[i] = chp;
375: chp->ch_channel = i;
376: chp->ch_atac = &sc->sc_atac;
1.58 jdolecek 377: chp->ch_queue = ata_queue_alloc(sc->sc_ncmds);
1.1 bouyer 378: if (chp->ch_queue == NULL) {
379: aprint_error("%s port %d: can't allocate memory for "
380: "command queue", AHCINAME(sc), i);
381: break;
382: }
383: dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds;
384: error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
1.29 jakllsch 385: &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg,
386: BUS_DMA_NOWAIT);
1.1 bouyer 387: if (error) {
388: aprint_error("%s: unable to allocate command table "
389: "memory, error=%d\n", AHCINAME(sc), error);
390: break;
391: }
1.29 jakllsch 392: error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg,
393: achp->ahcic_cmd_tbl_nseg, dmasize,
1.1 bouyer 394: &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
395: if (error) {
396: aprint_error("%s: unable to map command table memory"
397: ", error=%d\n", AHCINAME(sc), error);
398: break;
399: }
400: error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
401: BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld);
402: if (error) {
403: aprint_error("%s: unable to create command table map"
404: ", error=%d\n", AHCINAME(sc), error);
405: break;
406: }
407: error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld,
408: cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT);
409: if (error) {
410: aprint_error("%s: unable to load command table map"
411: ", error=%d\n", AHCINAME(sc), error);
412: break;
413: }
414: achp->ahcic_cmdh = (struct ahci_cmd_header *)
415: ((char *)cmdhp + AHCI_CMDH_SIZE * port);
416: achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
417: AHCI_CMDH_SIZE * port;
418: achp->ahcic_rfis = (struct ahci_r_fis *)
419: ((char *)cmdhp +
420: AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
421: AHCI_RFIS_SIZE * port);
422: achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
423: AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
424: AHCI_RFIS_SIZE * port;
1.28 jakllsch 425: AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") "
426: "rfis %p (0x%" PRIx64 ")\n", i,
427: achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh,
428: achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis),
1.1 bouyer 429: DEBUG_PROBE);
430:
431: for (j = 0; j < sc->sc_ncmds; j++) {
432: achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *)
433: ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j);
434: achp->ahcic_bus_cmd_tbl[j] =
435: achp->ahcic_cmd_tbld->dm_segs[0].ds_addr +
436: AHCI_CMDTBL_SIZE * j;
437: achp->ahcic_cmdh[j].cmdh_cmdtba =
1.28 jakllsch 438: htole64(achp->ahcic_bus_cmd_tbl[j]);
439: AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j,
1.1 bouyer 440: achp->ahcic_cmd_tbl[j],
1.28 jakllsch 441: (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE);
1.1 bouyer 442: /* The xfer DMA map */
443: error = bus_dmamap_create(sc->sc_dmat, MAXPHYS,
444: AHCI_NPRD, 0x400000 /* 4MB */, 0,
445: BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
446: &achp->ahcic_datad[j]);
447: if (error) {
448: aprint_error("%s: couldn't alloc xfer DMA map, "
449: "error=%d\n", AHCINAME(sc), error);
450: goto end;
451: }
452: }
1.7 joerg 453: ahci_setup_port(sc, i);
1.1 bouyer 454: if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
1.22 jakllsch 455: AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) {
1.1 bouyer 456: aprint_error("%s: couldn't map channel %d "
457: "sata_status regs\n", AHCINAME(sc), i);
458: break;
459: }
460: if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
1.22 jakllsch 461: AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) {
1.1 bouyer 462: aprint_error("%s: couldn't map channel %d "
463: "sata_control regs\n", AHCINAME(sc), i);
464: break;
465: }
466: if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
1.22 jakllsch 467: AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) {
1.1 bouyer 468: aprint_error("%s: couldn't map channel %d "
469: "sata_error regs\n", AHCINAME(sc), i);
470: break;
471: }
472: ata_channel_attach(chp);
473: port++;
474: end:
475: continue;
476: }
477: }
478:
479: int
1.29 jakllsch 480: ahci_detach(struct ahci_softc *sc, int flags)
481: {
482: struct atac_softc *atac;
483: struct ahci_channel *achp;
484: struct ata_channel *chp;
485: struct scsipi_adapter *adapt;
486: int i, j;
487: int error;
488:
489: atac = &sc->sc_atac;
490: adapt = &atac->atac_atapi_adapter._generic;
491:
492: for (i = 0; i < AHCI_MAX_PORTS; i++) {
493: achp = &sc->sc_channels[i];
494: chp = &achp->ata_channel;
495:
1.62 kamil 496: if ((sc->sc_ahci_ports & (1U << i)) == 0)
1.29 jakllsch 497: continue;
498: if (i >= sc->sc_atac.atac_nchannels) {
499: aprint_error("%s: more ports than announced\n",
500: AHCINAME(sc));
501: break;
502: }
503:
504: if (chp->atabus == NULL)
505: continue;
506: if ((error = config_detach(chp->atabus, flags)) != 0)
507: return error;
508:
509: for (j = 0; j < sc->sc_ncmds; j++)
510: bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]);
511:
512: bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld);
513: bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld);
514: bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0],
515: AHCI_CMDTBL_SIZE * sc->sc_ncmds);
516: bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg,
517: achp->ahcic_cmd_tbl_nseg);
518:
519: chp->atabus = NULL;
1.58 jdolecek 520:
521: ata_channel_detach(chp);
1.29 jakllsch 522: }
523:
524: bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd);
525: bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd);
526: bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr,
527: (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels);
528: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg);
529:
530: if (adapt->adapt_refcnt != 0)
531: return EBUSY;
532:
533: return 0;
534: }
535:
536: void
537: ahci_resume(struct ahci_softc *sc)
538: {
539: ahci_reset(sc);
540: ahci_setup_ports(sc);
541: ahci_reprobe_drives(sc);
542: ahci_enable_intrs(sc);
543: }
544:
545: int
1.1 bouyer 546: ahci_intr(void *v)
547: {
548: struct ahci_softc *sc = v;
1.27 jakllsch 549: uint32_t is;
1.1 bouyer 550: int i, r = 0;
551:
552: while ((is = AHCI_READ(sc, AHCI_IS))) {
553: AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is),
554: DEBUG_INTR);
555: r = 1;
556: AHCI_WRITE(sc, AHCI_IS, is);
557: for (i = 0; i < AHCI_MAX_PORTS; i++)
1.62 kamil 558: if (is & (1U << i))
1.1 bouyer 559: ahci_intr_port(sc, &sc->sc_channels[i]);
560: }
561: return r;
562: }
563:
1.29 jakllsch 564: static void
1.1 bouyer 565: ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp)
566: {
1.58 jdolecek 567: uint32_t is, tfd, sact;
1.1 bouyer 568: struct ata_channel *chp = &achp->ata_channel;
1.58 jdolecek 569: struct ata_xfer *xfer;
570: int slot = -1;
571: bool recover = false;
1.1 bouyer 572:
573: is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
574: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is);
1.60 jdolecek 575:
1.58 jdolecek 576: AHCIDEBUG_PRINT((
577: "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n",
578: AHCINAME(sc),
579: chp->ch_channel, is,
580: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)),
581: AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)),
582: AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))),
1.1 bouyer 583: DEBUG_INTR);
584:
1.58 jdolecek 585: if ((chp->ch_flags & ATACH_NCQ) == 0) {
586: /* Non-NCQ operation */
587: sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel));
588: } else {
589: /* NCQ operation */
590: sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel));
591: }
592:
593: /* Handle errors */
594: if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS |
595: AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) {
596: /* Fatal errors */
1.1 bouyer 597: if (is & AHCI_P_IX_TFES) {
598: tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
1.58 jdolecek 599:
600: if ((chp->ch_flags & ATACH_NCQ) == 0) {
601: /* Slot valid only for Non-NCQ operation */
602: slot = (AHCI_READ(sc,
603: AHCI_P_CMD(chp->ch_channel))
604: & AHCI_P_CMD_CCS_MASK)
605: >> AHCI_P_CMD_CCS_SHIFT;
606: }
607:
1.60 jdolecek 608: AHCIDEBUG_PRINT((
609: "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n",
610: AHCINAME(sc), chp->ch_channel, sact, is, tfd),
611: DEBUG_INTR);
1.1 bouyer 612: } else {
1.58 jdolecek 613: /* mark an error, and set BSY */
614: tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) |
615: WDCS_ERR | WDCS_BSY;
1.1 bouyer 616: }
1.58 jdolecek 617:
1.40 bouyer 618: if (is & AHCI_P_IX_IFS) {
1.60 jdolecek 619: AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n",
1.40 bouyer 620: AHCINAME(sc), chp->ch_channel,
1.60 jdolecek 621: AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))),
622: DEBUG_INTR);
1.40 bouyer 623: }
1.58 jdolecek 624:
625: if (!achp->ahcic_recovering)
626: recover = true;
627: } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) {
628: tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
629:
630: /* D2H Register FIS or Set Device Bits */
631: if ((tfd & WDCS_ERR) != 0) {
632: if (!achp->ahcic_recovering)
633: recover = true;
634:
1.60 jdolecek 635: AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n",
636: AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR);
1.58 jdolecek 637:
638: }
639: } else {
640: tfd = 0;
641: }
642:
643: if (__predict_false(recover))
644: ata_channel_freeze(chp);
645:
646: if (slot >= 0) {
647: if ((achp->ahcic_cmds_active & __BIT(slot)) != 0 &&
648: (sact & __BIT(slot)) == 0) {
649: xfer = ata_queue_hwslot_to_xfer(chp, slot);
650: xfer->c_intr(chp, xfer, tfd);
651: }
1.1 bouyer 652: } else {
1.58 jdolecek 653: /*
654: * For NCQ, HBA halts processing when error is notified,
655: * and any further D2H FISes are ignored until the error
656: * condition is cleared. Hence if a command is inactive,
657: * it means it actually already finished successfully.
658: * Note: active slots can change as c_intr() callback
659: * can activate another command(s), so must only process
660: * commands active before we start processing.
661: */
662: uint32_t aslots = achp->ahcic_cmds_active;
663:
664: for (slot=0; slot < sc->sc_ncmds; slot++) {
665: if ((aslots & __BIT(slot)) != 0 &&
666: (sact & __BIT(slot)) == 0) {
667: xfer = ata_queue_hwslot_to_xfer(chp, slot);
668: xfer->c_intr(chp, xfer, tfd);
669: }
1.1 bouyer 670: }
671: }
1.58 jdolecek 672:
673: if (__predict_false(recover)) {
674: ata_channel_thaw(chp);
675: ahci_channel_recover(sc, chp, tfd);
676: }
1.1 bouyer 677: }
678:
1.29 jakllsch 679: static void
1.40 bouyer 680: ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp)
1.1 bouyer 681: {
682: struct ata_channel *chp = drvp->chnl_softc;
1.40 bouyer 683: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1.58 jdolecek 684: struct ata_xfer *xfer;
685:
686: xfer = ata_get_xfer_ext(chp, C_RECOVERY, 0);
687:
688: ata_channel_lock(chp);
689:
1.40 bouyer 690: AHCI_WRITE(sc, AHCI_GHC,
691: AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
692: ahci_channel_stop(sc, chp, flags);
1.58 jdolecek 693: if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp, xfer) != 0)
1.40 bouyer 694: ata_reset_channel(chp, flags);
695: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
1.58 jdolecek 696:
697: ata_channel_unlock(chp);
698:
699: ata_free_xfer(chp, xfer);
700:
1.1 bouyer 701: return;
702: }
703:
1.40 bouyer 704: /* return error code from ata_bio */
705: static int
1.58 jdolecek 706: ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot)
1.40 bouyer 707: {
708: struct ahci_channel *achp = (struct ahci_channel *)chp;
709: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
710: int i;
711: uint32_t is;
712:
1.52 joerg 713: /*
714: * Base timeout is specified in ms.
715: * If we are allowed to sleep, wait a tick each round.
1.53 joerg 716: * Otherwise delay for 10ms on each round.
1.52 joerg 717: */
718: if (flags & AT_WAIT)
719: timeout = MAX(1, mstohz(timeout));
1.53 joerg 720: else
721: timeout = timeout / 10;
1.52 joerg 722:
1.58 jdolecek 723: AHCI_CMDH_SYNC(sc, achp, slot,
724: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1.40 bouyer 725: /* start command */
1.62 kamil 726: AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot);
1.40 bouyer 727: for (i = 0; i < timeout; i++) {
1.62 kamil 728: if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) ==
1.58 jdolecek 729: 0)
1.40 bouyer 730: return 0;
731: is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
1.58 jdolecek 732: if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS |
733: AHCI_P_IX_IFS |
1.40 bouyer 734: AHCI_P_IX_OFS | AHCI_P_IX_UFS)) {
735: if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) ==
736: (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) {
737: /*
738: * we got the D2H FIS anyway,
739: * assume sig is valid.
740: * channel is restarted later
741: */
742: return ERROR;
743: }
744: aprint_debug("%s channel %d: error 0x%x sending FIS\n",
745: AHCINAME(sc), chp->ch_channel, is);
746: return ERR_DF;
747: }
1.58 jdolecek 748: ata_delay(chp, 10, "ahcifis", flags);
1.40 bouyer 749: }
1.52 joerg 750:
1.40 bouyer 751: aprint_debug("%s channel %d: timeout sending FIS\n",
752: AHCINAME(sc), chp->ch_channel);
753: return TIMEOUT;
754: }
755:
756: static int
757: ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags,
1.58 jdolecek 758: uint32_t *sigp, struct ata_xfer *xfer)
1.40 bouyer 759: {
760: struct ahci_channel *achp = (struct ahci_channel *)chp;
761: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
762: struct ahci_cmd_tbl *cmd_tbl;
763: struct ahci_cmd_header *cmd_h;
764: int i;
765: uint32_t sig;
766:
767: KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0);
1.58 jdolecek 768: ata_channel_lock_owned(chp);
769:
1.42 bouyer 770: again:
1.40 bouyer 771: /* clear port interrupt register */
772: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
773: /* clear SErrors and start operations */
774: if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) {
775: /*
776: * issue a command list override to clear BSY.
777: * This is needed if there's a PMP with no drive
778: * on port 0
779: */
780: ahci_channel_start(sc, chp, flags, 1);
781: } else {
782: ahci_channel_start(sc, chp, flags, 0);
783: }
784: if (drive > 0) {
785: KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM);
786: }
1.54 jmcneill 787:
788: if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET)
789: goto skip_reset;
790:
1.40 bouyer 791: /* polled command, assume interrupts are disabled */
1.58 jdolecek 792:
793: cmd_h = &achp->ahcic_cmdh[xfer->c_slot];
794: cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot];
1.40 bouyer 795: cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY |
796: RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT));
797: cmd_h->cmdh_prdbc = 0;
798: memset(cmd_tbl->cmdt_cfis, 0, 64);
799: cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE;
800: cmd_tbl->cmdt_cfis[rhd_c] = drive;
801: cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST;
1.58 jdolecek 802: switch(ahci_exec_fis(chp, 100, flags, xfer->c_slot)) {
1.40 bouyer 803: case ERR_DF:
804: case TIMEOUT:
805: aprint_error("%s channel %d: setting WDCTL_RST failed "
806: "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive);
807: if (sigp)
808: *sigp = 0xffffffff;
809: goto end;
810: default:
811: break;
812: }
813: cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 |
814: (drive << AHCI_CMDH_F_PMP_SHIFT));
815: cmd_h->cmdh_prdbc = 0;
816: memset(cmd_tbl->cmdt_cfis, 0, 64);
817: cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE;
818: cmd_tbl->cmdt_cfis[rhd_c] = drive;
819: cmd_tbl->cmdt_cfis[rhd_control] = 0;
1.58 jdolecek 820: switch(ahci_exec_fis(chp, 310, flags, xfer->c_slot)) {
1.40 bouyer 821: case ERR_DF:
822: case TIMEOUT:
1.43 bouyer 823: if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 &&
1.41 bouyer 824: drive == PMP_PORT_CTL) {
825: /*
826: * some controllers fails to reset when
827: * targeting a PMP but a single drive is attached.
828: * try again with port 0
829: */
830: drive = 0;
1.42 bouyer 831: ahci_channel_stop(sc, chp, flags);
1.41 bouyer 832: goto again;
833: }
1.40 bouyer 834: aprint_error("%s channel %d: clearing WDCTL_RST failed "
835: "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive);
836: if (sigp)
837: *sigp = 0xffffffff;
838: goto end;
839: default:
840: break;
841: }
1.54 jmcneill 842:
843: skip_reset:
1.40 bouyer 844: /*
845: * wait 31s for BSY to clear
846: * This should not be needed, but some controllers clear the
847: * command slot before receiving the D2H FIS ...
848: */
1.46 matt 849: for (i = 0; i < AHCI_RST_WAIT; i++) {
1.40 bouyer 850: sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
1.46 matt 851: if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0)
1.40 bouyer 852: break;
1.58 jdolecek 853: ata_delay(chp, 10, "ahcid2h", flags);
1.40 bouyer 854: }
855: if (i == AHCI_RST_WAIT) {
856: aprint_error("%s: BSY never cleared, TD 0x%x\n",
857: AHCINAME(sc), sig);
858: if (sigp)
859: *sigp = 0xffffffff;
860: goto end;
861: }
862: AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
863: DEBUG_PROBE);
864: sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel));
865: if (sigp)
866: *sigp = sig;
867: AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n",
868: AHCINAME(sc), chp->ch_channel, sig,
869: AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE);
870: end:
871: ahci_channel_stop(sc, chp, flags);
1.58 jdolecek 872: ata_delay(chp, 500, "ahcirst", flags);
1.40 bouyer 873: /* clear port interrupt register */
874: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
1.47 bouyer 875: ahci_channel_start(sc, chp, flags,
1.40 bouyer 876: (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0);
877: return 0;
878: }
879:
1.29 jakllsch 880: static void
1.1 bouyer 881: ahci_reset_channel(struct ata_channel *chp, int flags)
882: {
883: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
884: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.18 bouyer 885: int i, tfd;
1.1 bouyer 886:
1.58 jdolecek 887: ata_channel_lock(chp);
888:
1.5 bouyer 889: ahci_channel_stop(sc, chp, flags);
1.1 bouyer 890: if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
1.47 bouyer 891: achp->ahcic_sstatus, flags) != SStatus_DET_DEV) {
1.33 jakllsch 892: printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel);
1.1 bouyer 893: /* XXX and then ? */
894: }
1.58 jdolecek 895: ata_kill_active(chp, KILL_RESET, flags);
896: ata_delay(chp, 500, "ahcirst", flags);
1.24 bouyer 897: /* clear port interrupt register */
898: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
899: /* clear SErrors and start operations */
1.57 jmcneill 900: ahci_channel_start(sc, chp, flags,
901: (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0);
1.18 bouyer 902: /* wait 31s for BSY to clear */
1.24 bouyer 903: for (i = 0; i <AHCI_RST_WAIT; i++) {
1.18 bouyer 904: tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
1.58 jdolecek 905: if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0)
1.8 bouyer 906: break;
1.58 jdolecek 907: ata_delay(chp, 10, "ahcid2h", flags);
1.8 bouyer 908: }
1.58 jdolecek 909: if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0)
1.18 bouyer 910: aprint_error("%s: BSY never cleared, TD 0x%x\n",
911: AHCINAME(sc), tfd);
912: AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
913: DEBUG_PROBE);
1.8 bouyer 914: /* clear port interrupt register */
915: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
916:
1.58 jdolecek 917: ata_channel_unlock(chp);
918:
1.1 bouyer 919: return;
920: }
921:
1.29 jakllsch 922: static int
1.1 bouyer 923: ahci_ata_addref(struct ata_drive_datas *drvp)
924: {
925: return 0;
926: }
927:
1.29 jakllsch 928: static void
1.1 bouyer 929: ahci_ata_delref(struct ata_drive_datas *drvp)
930: {
931: return;
932: }
933:
1.29 jakllsch 934: static void
1.1 bouyer 935: ahci_killpending(struct ata_drive_datas *drvp)
936: {
937: return;
938: }
939:
1.29 jakllsch 940: static void
1.1 bouyer 941: ahci_probe_drive(struct ata_channel *chp)
942: {
943: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
944: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.27 jakllsch 945: uint32_t sig;
1.58 jdolecek 946: struct ata_xfer *xfer;
947:
948: xfer = ata_get_xfer_ext(chp, 0, 0);
949: if (xfer == NULL) {
950: aprint_error_dev(sc->sc_atac.atac_dev,
951: "%s: failed to get xfer port %d\n",
952: __func__, chp->ch_channel);
953: return;
954: }
955:
956: ata_channel_lock(chp);
1.1 bouyer 957:
1.18 bouyer 958: /* bring interface up, accept FISs, power up and spin up device */
1.1 bouyer 959: AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1.18 bouyer 960: AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE |
961: AHCI_P_CMD_POD | AHCI_P_CMD_SUD);
1.1 bouyer 962: /* reset the PHY and bring online */
963: switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
1.47 bouyer 964: achp->ahcic_sstatus, AT_WAIT)) {
1.1 bouyer 965: case SStatus_DET_DEV:
1.58 jdolecek 966: ata_delay(chp, 500, "ahcidv", AT_WAIT);
1.40 bouyer 967: if (sc->sc_ahci_cap & AHCI_CAP_SPM) {
1.58 jdolecek 968: ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig,
969: xfer);
1.40 bouyer 970: } else {
1.58 jdolecek 971: ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, xfer);
1.8 bouyer 972: }
1.40 bouyer 973: sata_interpret_sig(chp, 0, sig);
974: /* if we have a PMP attached, inform the controller */
975: if (chp->ch_ndrives > PMP_PORT_CTL &&
976: chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) {
977: AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
978: AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) |
979: AHCI_P_CMD_PMA);
1.23 bouyer 980: }
981: /* clear port interrupt register */
982: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
1.44 matt 983:
1.23 bouyer 984: /* and enable interrupts */
1.1 bouyer 985: AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel),
1.58 jdolecek 986: AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS |
987: AHCI_P_IX_IFS |
1.1 bouyer 988: AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS |
1.58 jdolecek 989: AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS);
1.17 dillo 990: /* wait 500ms before actually starting operations */
1.58 jdolecek 991: ata_delay(chp, 500, "ahciprb", AT_WAIT);
1.1 bouyer 992: break;
993:
994: default:
995: break;
996: }
1.58 jdolecek 997: ata_channel_unlock(chp);
1.1 bouyer 998: }
999:
1.29 jakllsch 1000: static void
1.1 bouyer 1001: ahci_setup_channel(struct ata_channel *chp)
1002: {
1003: return;
1004: }
1005:
1.29 jakllsch 1006: static int
1.58 jdolecek 1007: ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer)
1.1 bouyer 1008: {
1009: struct ata_channel *chp = drvp->chnl_softc;
1.58 jdolecek 1010: struct ata_command *ata_c = &xfer->c_ata_c;
1.1 bouyer 1011: int ret;
1012: int s;
1013:
1014: AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n",
1.58 jdolecek 1015: chp->ch_channel,
1016: AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))),
1.1 bouyer 1017: DEBUG_XFERS);
1018: if (ata_c->flags & AT_POLL)
1019: xfer->c_flags |= C_POLL;
1020: if (ata_c->flags & AT_WAIT)
1021: xfer->c_flags |= C_WAIT;
1022: xfer->c_drive = drvp->drive;
1023: xfer->c_databuf = ata_c->data;
1024: xfer->c_bcount = ata_c->bcount;
1025: xfer->c_start = ahci_cmd_start;
1.58 jdolecek 1026: xfer->c_poll = ahci_cmd_poll;
1027: xfer->c_abort = ahci_cmd_abort;
1.1 bouyer 1028: xfer->c_intr = ahci_cmd_complete;
1029: xfer->c_kill_xfer = ahci_cmd_kill_xfer;
1030: s = splbio();
1031: ata_exec_xfer(chp, xfer);
1032: #ifdef DIAGNOSTIC
1033: if ((ata_c->flags & AT_POLL) != 0 &&
1034: (ata_c->flags & AT_DONE) == 0)
1035: panic("ahci_exec_command: polled command not done");
1036: #endif
1037: if (ata_c->flags & AT_DONE) {
1038: ret = ATACMD_COMPLETE;
1039: } else {
1040: if (ata_c->flags & AT_WAIT) {
1.62.2.1 jdolecek 1041: ata_wait_cmd(chp, xfer);
1.1 bouyer 1042: ret = ATACMD_COMPLETE;
1043: } else {
1044: ret = ATACMD_QUEUED;
1045: }
1046: }
1047: splx(s);
1048: return ret;
1049: }
1050:
1.58 jdolecek 1051: static int
1.1 bouyer 1052: ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer)
1053: {
1.58 jdolecek 1054: struct ahci_softc *sc = AHCI_CH2SC(chp);
1.1 bouyer 1055: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.58 jdolecek 1056: struct ata_command *ata_c = &xfer->c_ata_c;
1057: int slot = xfer->c_slot;
1.1 bouyer 1058: struct ahci_cmd_tbl *cmd_tbl;
1059: struct ahci_cmd_header *cmd_h;
1060:
1.58 jdolecek 1061: AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d",
1062: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)),
1063: ata_c->timeout, slot),
1.44 matt 1064: DEBUG_XFERS);
1.1 bouyer 1065:
1.58 jdolecek 1066: ata_channel_lock_owned(chp);
1.62 kamil 1067: KASSERT((achp->ahcic_cmds_active & (1U << slot)) == 0);
1.58 jdolecek 1068:
1.1 bouyer 1069: cmd_tbl = achp->ahcic_cmd_tbl[slot];
1070: AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
1071: cmd_tbl), DEBUG_XFERS);
1072:
1.20 jakllsch 1073: satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis);
1.40 bouyer 1074: cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive;
1.1 bouyer 1075:
1076: cmd_h = &achp->ahcic_cmdh[slot];
1077: AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
1078: chp->ch_channel, cmd_h), DEBUG_XFERS);
1079: if (ahci_dma_setup(chp, slot,
1.31 tsutsui 1080: (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ?
1081: ata_c->data : NULL,
1.1 bouyer 1082: ata_c->bcount,
1083: (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
1084: ata_c->flags |= AT_DF;
1.58 jdolecek 1085: return ATASTART_ABORT;
1.1 bouyer 1086: }
1087: cmd_h->cmdh_flags = htole16(
1088: ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) |
1.40 bouyer 1089: RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT));
1.1 bouyer 1090: cmd_h->cmdh_prdbc = 0;
1091: AHCI_CMDH_SYNC(sc, achp, slot,
1092: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1093:
1094: if (ata_c->flags & AT_POLL) {
1095: /* polled command, disable interrupts */
1096: AHCI_WRITE(sc, AHCI_GHC,
1097: AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
1098: }
1099: /* start command */
1.62 kamil 1100: AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot);
1.1 bouyer 1101: /* and says we started this command */
1.62 kamil 1102: achp->ahcic_cmds_active |= 1U << slot;
1.1 bouyer 1103:
1104: if ((ata_c->flags & AT_POLL) == 0) {
1.62.2.1 jdolecek 1105: callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout),
1106: ata_timeout, chp);
1.58 jdolecek 1107: return ATASTART_STARTED;
1108: } else
1109: return ATASTART_POLL;
1110: }
1111:
1112: static void
1113: ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer)
1114: {
1115: struct ahci_softc *sc = AHCI_CH2SC(chp);
1116: struct ahci_channel *achp = (struct ahci_channel *)chp;
1117:
1118: ata_channel_lock(chp);
1119:
1.1 bouyer 1120: /*
1121: * Polled command.
1122: */
1.58 jdolecek 1123: for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) {
1124: if (xfer->c_ata_c.flags & AT_DONE)
1.1 bouyer 1125: break;
1.58 jdolecek 1126: ata_channel_unlock(chp);
1.1 bouyer 1127: ahci_intr_port(sc, achp);
1.58 jdolecek 1128: ata_channel_lock(chp);
1129: ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags);
1.1 bouyer 1130: }
1.58 jdolecek 1131: AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel,
1.1 bouyer 1132: AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
1.58 jdolecek 1133: AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)),
1134: AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)),
1135: AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)),
1136: AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)),
1137: AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)),
1138: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
1.1 bouyer 1139: DEBUG_XFERS);
1.58 jdolecek 1140:
1141: ata_channel_unlock(chp);
1142:
1143: if ((xfer->c_ata_c.flags & AT_DONE) == 0) {
1144: xfer->c_ata_c.flags |= AT_TIMEOU;
1145: xfer->c_intr(chp, xfer, 0);
1.1 bouyer 1146: }
1147: /* reenable interrupts */
1148: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
1149: }
1150:
1.29 jakllsch 1151: static void
1.58 jdolecek 1152: ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer)
1153: {
1154: ahci_cmd_complete(chp, xfer, 0);
1155: }
1156:
1157: static void
1.1 bouyer 1158: ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
1159: {
1.58 jdolecek 1160: struct ahci_channel *achp = (struct ahci_channel *)chp;
1161: struct ata_command *ata_c = &xfer->c_ata_c;
1162: bool deactivate = true;
1163:
1.1 bouyer 1164: AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel),
1165: DEBUG_FUNCS);
1166:
1167: switch (reason) {
1.58 jdolecek 1168: case KILL_GONE_INACTIVE:
1169: deactivate = false;
1170: /* FALLTHROUGH */
1.1 bouyer 1171: case KILL_GONE:
1172: ata_c->flags |= AT_GONE;
1173: break;
1174: case KILL_RESET:
1175: ata_c->flags |= AT_RESET;
1176: break;
1.58 jdolecek 1177: case KILL_REQUEUE:
1178: panic("%s: not supposed to be requeued\n", __func__);
1179: break;
1.1 bouyer 1180: default:
1181: printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason);
1182: panic("ahci_cmd_kill_xfer");
1183: }
1.58 jdolecek 1184:
1.62.2.1 jdolecek 1185: ahci_cmd_done_end(chp, xfer);
1186:
1.58 jdolecek 1187: if (deactivate) {
1.62 kamil 1188: KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0);
1189: achp->ahcic_cmds_active &= ~(1U << xfer->c_slot);
1.58 jdolecek 1190: ata_deactivate_xfer(chp, xfer);
1191: }
1.1 bouyer 1192: }
1193:
1.29 jakllsch 1194: static int
1.58 jdolecek 1195: ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd)
1.1 bouyer 1196: {
1.58 jdolecek 1197: struct ata_command *ata_c = &xfer->c_ata_c;
1.26 jakllsch 1198: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.1 bouyer 1199:
1200: AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n",
1.58 jdolecek 1201: chp->ch_channel,
1202: AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)),
1203: AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))),
1.1 bouyer 1204: DEBUG_FUNCS);
1.58 jdolecek 1205:
1206: if (ata_waitdrain_xfer_check(chp, xfer))
1207: return 0;
1208:
1.1 bouyer 1209: if (xfer->c_flags & C_TIMEOU) {
1210: ata_c->flags |= AT_TIMEOU;
1211: }
1.26 jakllsch 1212:
1.58 jdolecek 1213: if (AHCI_TFD_ST(tfd) & WDCS_BSY) {
1.26 jakllsch 1214: ata_c->flags |= AT_TIMEOU;
1.58 jdolecek 1215: } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) {
1216: ata_c->r_error = AHCI_TFD_ERR(tfd);
1.26 jakllsch 1217: ata_c->flags |= AT_ERROR;
1.1 bouyer 1218: }
1.26 jakllsch 1219:
1220: if (ata_c->flags & AT_READREG)
1221: satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis);
1222:
1.58 jdolecek 1223: ahci_cmd_done(chp, xfer);
1.62.2.1 jdolecek 1224:
1.62.2.2! jdolecek 1225: KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0);
! 1226: achp->ahcic_cmds_active &= ~(1U << xfer->c_slot);
1.62.2.1 jdolecek 1227: ata_deactivate_xfer(chp, xfer);
1228:
1.1 bouyer 1229: return 0;
1230: }
1231:
1.29 jakllsch 1232: static void
1.58 jdolecek 1233: ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer)
1.1 bouyer 1234: {
1235: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1236: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.58 jdolecek 1237: struct ata_command *ata_c = &xfer->c_ata_c;
1.25 jakllsch 1238: uint16_t *idwordbuf;
1.58 jdolecek 1239: int flags = ata_c->flags;
1.25 jakllsch 1240: int i;
1.1 bouyer 1241:
1.58 jdolecek 1242: AHCIDEBUG_PRINT(("ahci_cmd_done channel %d flags %#x/%#x\n",
1243: chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS);
1.1 bouyer 1244:
1.31 tsutsui 1245: if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) {
1.58 jdolecek 1246: bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot];
1.44 matt 1247: bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1.1 bouyer 1248: (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD :
1249: BUS_DMASYNC_POSTWRITE);
1.44 matt 1250: bus_dmamap_unload(sc->sc_dmat, map);
1.1 bouyer 1251: }
1252:
1.58 jdolecek 1253: AHCI_CMDH_SYNC(sc, achp, xfer->c_slot,
1.2 fvdl 1254: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1255:
1.25 jakllsch 1256: /* ata(4) expects IDENTIFY data to be in host endianess */
1257: if (ata_c->r_command == WDCC_IDENTIFY ||
1258: ata_c->r_command == ATAPI_IDENTIFY_DEVICE) {
1259: idwordbuf = xfer->c_databuf;
1260: for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) {
1261: idwordbuf[i] = le16toh(idwordbuf[i]);
1262: }
1263: }
1264:
1.58 jdolecek 1265: if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc)
1266: ata_c->flags |= AT_XFDONE;
1.62.2.1 jdolecek 1267:
1.58 jdolecek 1268: ahci_cmd_done_end(chp, xfer);
1.62.2.1 jdolecek 1269:
1.58 jdolecek 1270: if ((flags & (AT_TIMEOU|AT_ERROR)) == 0)
1271: atastart(chp);
1272: }
1273:
1274: static void
1275: ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer)
1276: {
1277: struct ata_command *ata_c = &xfer->c_ata_c;
1278:
1.1 bouyer 1279: ata_c->flags |= AT_DONE;
1280: }
1281:
1.29 jakllsch 1282: static int
1.58 jdolecek 1283: ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer)
1.1 bouyer 1284: {
1285: struct ata_channel *chp = drvp->chnl_softc;
1.58 jdolecek 1286: struct ata_bio *ata_bio = &xfer->c_bio;
1.1 bouyer 1287:
1288: AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n",
1.58 jdolecek 1289: chp->ch_channel,
1290: AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))),
1.1 bouyer 1291: DEBUG_XFERS);
1292: if (ata_bio->flags & ATA_POLL)
1293: xfer->c_flags |= C_POLL;
1294: xfer->c_drive = drvp->drive;
1295: xfer->c_databuf = ata_bio->databuf;
1296: xfer->c_bcount = ata_bio->bcount;
1297: xfer->c_start = ahci_bio_start;
1.58 jdolecek 1298: xfer->c_poll = ahci_bio_poll;
1299: xfer->c_abort = ahci_bio_abort;
1.1 bouyer 1300: xfer->c_intr = ahci_bio_complete;
1301: xfer->c_kill_xfer = ahci_bio_kill_xfer;
1302: ata_exec_xfer(chp, xfer);
1303: return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED;
1304: }
1305:
1.58 jdolecek 1306: static int
1.1 bouyer 1307: ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer)
1308: {
1309: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1310: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.58 jdolecek 1311: struct ata_bio *ata_bio = &xfer->c_bio;
1.1 bouyer 1312: struct ahci_cmd_tbl *cmd_tbl;
1313: struct ahci_cmd_header *cmd_h;
1314:
1315: AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n",
1316: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
1317:
1.58 jdolecek 1318: ata_channel_lock_owned(chp);
1319:
1320: cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot];
1.1 bouyer 1321: AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
1322: cmd_tbl), DEBUG_XFERS);
1323:
1.20 jakllsch 1324: satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis);
1.40 bouyer 1325: cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive;
1.1 bouyer 1326:
1.58 jdolecek 1327: cmd_h = &achp->ahcic_cmdh[xfer->c_slot];
1.1 bouyer 1328: AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
1329: chp->ch_channel, cmd_h), DEBUG_XFERS);
1.58 jdolecek 1330: if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount,
1.1 bouyer 1331: (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
1332: ata_bio->error = ERR_DMA;
1333: ata_bio->r_error = 0;
1.58 jdolecek 1334: return ATASTART_ABORT;
1.1 bouyer 1335: }
1336: cmd_h->cmdh_flags = htole16(
1337: ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) |
1.40 bouyer 1338: RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT));
1.1 bouyer 1339: cmd_h->cmdh_prdbc = 0;
1.58 jdolecek 1340: AHCI_CMDH_SYNC(sc, achp, xfer->c_slot,
1.2 fvdl 1341: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1.1 bouyer 1342:
1343: if (xfer->c_flags & C_POLL) {
1344: /* polled command, disable interrupts */
1345: AHCI_WRITE(sc, AHCI_GHC,
1346: AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
1347: }
1.58 jdolecek 1348: if (xfer->c_flags & C_NCQ)
1.62 kamil 1349: AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot);
1.1 bouyer 1350: /* start command */
1.62 kamil 1351: AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot);
1.1 bouyer 1352: /* and says we started this command */
1.62 kamil 1353: achp->ahcic_cmds_active |= 1U << xfer->c_slot;
1.1 bouyer 1354:
1355: if ((xfer->c_flags & C_POLL) == 0) {
1.62.2.1 jdolecek 1356: callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY),
1357: ata_timeout, chp);
1.58 jdolecek 1358: return ATASTART_STARTED;
1359: } else
1360: return ATASTART_POLL;
1361: }
1362:
1363: static void
1364: ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer)
1365: {
1366: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1367: struct ahci_channel *achp = (struct ahci_channel *)chp;
1368:
1.1 bouyer 1369: /*
1370: * Polled command.
1371: */
1.58 jdolecek 1372: for (int i = 0; i < ATA_DELAY * 10; i++) {
1373: if (xfer->c_bio.flags & ATA_ITSDONE)
1.1 bouyer 1374: break;
1375: ahci_intr_port(sc, achp);
1.47 bouyer 1376: delay(100);
1.1 bouyer 1377: }
1.58 jdolecek 1378: AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel,
1.1 bouyer 1379: AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
1.58 jdolecek 1380: AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)),
1381: AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)),
1382: AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)),
1383: AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)),
1384: AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)),
1385: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
1.1 bouyer 1386: DEBUG_XFERS);
1.58 jdolecek 1387: if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) {
1388: xfer->c_bio.error = TIMEOUT;
1389: xfer->c_intr(chp, xfer, 0);
1.1 bouyer 1390: }
1391: /* reenable interrupts */
1392: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
1393: }
1394:
1.29 jakllsch 1395: static void
1.58 jdolecek 1396: ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer)
1397: {
1398: ahci_bio_complete(chp, xfer, 0);
1399: }
1400:
1401: static void
1.1 bouyer 1402: ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
1403: {
1404: int drive = xfer->c_drive;
1.58 jdolecek 1405: struct ata_bio *ata_bio = &xfer->c_bio;
1.1 bouyer 1406: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.58 jdolecek 1407: bool deactivate = true;
1408:
1.1 bouyer 1409: AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel),
1410: DEBUG_FUNCS);
1411:
1412: ata_bio->flags |= ATA_ITSDONE;
1413: switch (reason) {
1.58 jdolecek 1414: case KILL_GONE_INACTIVE:
1415: deactivate = false;
1416: /* FALLTHROUGH */
1.1 bouyer 1417: case KILL_GONE:
1418: ata_bio->error = ERR_NODEV;
1419: break;
1420: case KILL_RESET:
1421: ata_bio->error = ERR_RESET;
1422: break;
1.58 jdolecek 1423: case KILL_REQUEUE:
1424: ata_bio->error = REQUEUE;
1425: break;
1.1 bouyer 1426: default:
1427: printf("ahci_bio_kill_xfer: unknown reason %d\n", reason);
1428: panic("ahci_bio_kill_xfer");
1429: }
1430: ata_bio->r_error = WDCE_ABRT;
1.58 jdolecek 1431:
1432: if (deactivate) {
1.62 kamil 1433: KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0);
1434: achp->ahcic_cmds_active &= ~(1U << xfer->c_slot);
1.58 jdolecek 1435: ata_deactivate_xfer(chp, xfer);
1436: }
1437:
1438: (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer);
1.1 bouyer 1439: }
1440:
1.29 jakllsch 1441: static int
1.58 jdolecek 1442: ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd)
1.1 bouyer 1443: {
1.58 jdolecek 1444: struct ata_bio *ata_bio = &xfer->c_bio;
1.1 bouyer 1445: int drive = xfer->c_drive;
1446: struct ahci_channel *achp = (struct ahci_channel *)chp;
1447: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1448:
1449: AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel),
1450: DEBUG_FUNCS);
1451:
1.58 jdolecek 1452: if (ata_waitdrain_xfer_check(chp, xfer))
1453: return 0;
1454:
1.5 bouyer 1455: if (xfer->c_flags & C_TIMEOU) {
1456: ata_bio->error = TIMEOUT;
1457: }
1.1 bouyer 1458:
1.58 jdolecek 1459: bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0,
1460: achp->ahcic_datad[xfer->c_slot]->dm_mapsize,
1.1 bouyer 1461: (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD :
1462: BUS_DMASYNC_POSTWRITE);
1.58 jdolecek 1463: bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]);
1.1 bouyer 1464:
1465: ata_bio->flags |= ATA_ITSDONE;
1.58 jdolecek 1466: if (AHCI_TFD_ERR(tfd) & WDCS_DWF) {
1.1 bouyer 1467: ata_bio->error = ERR_DF;
1.58 jdolecek 1468: } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) {
1.1 bouyer 1469: ata_bio->error = ERROR;
1.58 jdolecek 1470: ata_bio->r_error = AHCI_TFD_ERR(tfd);
1471: } else if (AHCI_TFD_ST(tfd) & WDCS_CORR)
1.1 bouyer 1472: ata_bio->flags |= ATA_CORR;
1473:
1.58 jdolecek 1474: AHCI_CMDH_SYNC(sc, achp, xfer->c_slot,
1.1 bouyer 1475: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1476: AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld",
1477: ata_bio->bcount), DEBUG_XFERS);
1.19 bouyer 1478: /*
1.58 jdolecek 1479: * If it was a write, complete data buffer may have been transfered
1.19 bouyer 1480: * before error detection; in this case don't use cmdh_prdbc
1481: * as it won't reflect what was written to media. Assume nothing
1482: * was transfered and leave bcount as-is.
1.58 jdolecek 1483: * For queued commands, PRD Byte Count should not be used, and is
1484: * not required to be valid; in that case underflow is always illegal.
1.19 bouyer 1485: */
1.58 jdolecek 1486: if ((xfer->c_flags & C_NCQ) != 0) {
1487: if (ata_bio->error == NOERROR)
1488: ata_bio->bcount = 0;
1489: } else {
1.61 jdolecek 1490: if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR)
1491: ata_bio->bcount -=
1492: le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc);
1.58 jdolecek 1493: }
1.1 bouyer 1494: AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS);
1.62.2.2! jdolecek 1495:
! 1496: KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0);
! 1497: achp->ahcic_cmds_active &= ~(1U << xfer->c_slot);
! 1498: ata_deactivate_xfer(chp, xfer);
! 1499:
1.58 jdolecek 1500: (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer);
1501: if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0)
1502: atastart(chp);
1.1 bouyer 1503: return 0;
1504: }
1505:
1.29 jakllsch 1506: static void
1.5 bouyer 1507: ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags)
1508: {
1509: int i;
1510: /* stop channel */
1511: AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1512: AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST);
1513: /* wait 1s for channel to stop */
1514: for (i = 0; i <100; i++) {
1515: if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR)
1516: == 0)
1517: break;
1.58 jdolecek 1518: ata_delay(chp, 10, "ahcistop", flags);
1.5 bouyer 1519: }
1520: if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) {
1521: printf("%s: channel wouldn't stop\n", AHCINAME(sc));
1522: /* XXX controller reset ? */
1523: return;
1524: }
1.51 jmcneill 1525:
1526: if (sc->sc_channel_stop)
1527: sc->sc_channel_stop(sc, chp);
1.5 bouyer 1528: }
1529:
1.29 jakllsch 1530: static void
1.40 bouyer 1531: ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp,
1532: int flags, int clo)
1.1 bouyer 1533: {
1.40 bouyer 1534: int i;
1535: uint32_t p_cmd;
1.1 bouyer 1536: /* clear error */
1.18 bouyer 1537: AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel),
1538: AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel)));
1.1 bouyer 1539:
1.40 bouyer 1540: if (clo) {
1541: /* issue command list override */
1542: KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO);
1543: AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1544: AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO);
1545: /* wait 1s for AHCI_CAP_CLO to clear */
1546: for (i = 0; i <100; i++) {
1547: if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) &
1548: AHCI_P_CMD_CLO) == 0)
1549: break;
1.58 jdolecek 1550: ata_delay(chp, 10, "ahciclo", flags);
1.40 bouyer 1551: }
1552: if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) {
1553: printf("%s: channel wouldn't CLO\n", AHCINAME(sc));
1554: /* XXX controller reset ? */
1555: return;
1556: }
1557: }
1.51 jmcneill 1558:
1559: if (sc->sc_channel_start)
1560: sc->sc_channel_start(sc, chp);
1561:
1.1 bouyer 1562: /* and start controller */
1.40 bouyer 1563: p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1564: AHCI_P_CMD_FRE | AHCI_P_CMD_ST;
1565: if (chp->ch_ndrives > PMP_PORT_CTL &&
1566: chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) {
1567: p_cmd |= AHCI_P_CMD_PMA;
1568: }
1569: AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd);
1.1 bouyer 1570: }
1571:
1.29 jakllsch 1572: static void
1.58 jdolecek 1573: ahci_hold(struct ahci_channel *achp)
1574: {
1575: achp->ahcic_cmds_hold |= achp->ahcic_cmds_active;
1576: achp->ahcic_cmds_active = 0;
1577: }
1578:
1579: static void
1580: ahci_unhold(struct ahci_channel *achp)
1581: {
1582: achp->ahcic_cmds_active = achp->ahcic_cmds_hold;
1583: achp->ahcic_cmds_hold = 0;
1584: }
1585:
1586: /* Recover channel after command failure */
1587: void
1588: ahci_channel_recover(struct ahci_softc *sc, struct ata_channel *chp, int tfd)
1.1 bouyer 1589: {
1.58 jdolecek 1590: struct ahci_channel *achp = (struct ahci_channel *)chp;
1591: struct ata_drive_datas *drvp;
1592: uint8_t slot, eslot, st, err;
1593: int drive = -1, error;
1594: struct ata_xfer *xfer;
1595: bool reset = false;
1596:
1597: KASSERT(!achp->ahcic_recovering);
1598:
1599: achp->ahcic_recovering = true;
1600:
1601: /*
1602: * Read FBS to get the drive which caused the error, if PM is in use.
1603: * According to AHCI 1.3 spec, this register is available regardless
1604: * if FIS-based switching (FBSS) feature is supported, or disabled.
1605: * If FIS-based switching is not in use, it merely maintains single
1606: * pair of DRQ/BSY state, but it is enough since in that case we
1607: * never issue commands for more than one device at the time anyway.
1608: * XXX untested
1609: */
1610: if (chp->ch_ndrives > PMP_PORT_CTL) {
1611: uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel));
1612: if (fbs & AHCI_P_FBS_SDE) {
1613: drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT;
1614:
1615: /*
1616: * Tell HBA to reset PM port X (value in DWE) state,
1617: * and resume processing commands for other ports.
1618: */
1619: fbs |= AHCI_P_FBS_DEC;
1620: AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs);
1621: for (int i = 0; i < 1000; i++) {
1622: fbs = AHCI_READ(sc,
1623: AHCI_P_FBS(chp->ch_channel));
1624: if ((fbs & AHCI_P_FBS_DEC) == 0)
1625: break;
1626: DELAY(1000);
1627: }
1628: if ((fbs & AHCI_P_FBS_DEC) != 0) {
1629: /* follow non-device specific recovery */
1630: drive = -1;
1631: reset = true;
1632: }
1633: } else {
1634: /* not device specific, reset channel */
1635: drive = -1;
1636: reset = true;
1637: }
1638: } else
1639: drive = 0;
1640:
1641: drvp = &chp->ch_drive[drive];
1642:
1643: /*
1644: * If BSY or DRQ bits are set, must execute COMRESET to return
1645: * device to idle state. If drive is idle, it's enough to just
1646: * reset CMD.ST, it's not necessary to do software reset.
1647: * After resetting CMD.ST, need to execute READ LOG EXT for NCQ
1648: * to unblock device processing if COMRESET was not done.
1649: */
1650: if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0)
1651: goto reset;
1652:
1653: KASSERT(drive >= 0);
1654: ahci_channel_stop(sc, chp, AT_POLL);
1655: ahci_channel_start(sc, chp, AT_POLL,
1656: (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0);
1657:
1658: ahci_hold(achp);
1659:
1660: /*
1661: * When running NCQ commands, READ LOG EXT is necessary to clear the
1662: * error condition and unblock the device.
1663: */
1664: error = ata_read_log_ext_ncq(drvp, AT_POLL, &eslot, &st, &err);
1665:
1666: ahci_unhold(achp);
1667:
1668: switch (error) {
1669: case 0:
1670: /* Error out the particular NCQ xfer, then requeue the others */
1.62 kamil 1671: if ((achp->ahcic_cmds_active & (1U << eslot)) != 0) {
1.58 jdolecek 1672: xfer = ata_queue_hwslot_to_xfer(chp, eslot);
1673: xfer->c_flags |= C_RECOVERED;
1674: xfer->c_intr(chp, xfer,
1675: (err << AHCI_P_TFD_ERR_SHIFT) | st);
1676: }
1677: break;
1678:
1679: case EOPNOTSUPP:
1680: /*
1681: * Non-NCQ command error, just find the slot and end with
1682: * the error.
1683: */
1684: for (slot = 0; slot < sc->sc_ncmds; slot++) {
1.62 kamil 1685: if ((achp->ahcic_cmds_active & (1U << slot)) != 0) {
1.58 jdolecek 1686: xfer = ata_queue_hwslot_to_xfer(chp, slot);
1687: xfer->c_intr(chp, xfer, tfd);
1688: }
1689: }
1690: break;
1691:
1692: case EAGAIN:
1693: /*
1694: * Failed to get resources to run the recovery command, must
1695: * reset the drive. This will also kill all still outstanding
1696: * transfers.
1697: */
1698: reset:
1699: ahci_reset_channel(chp, AT_POLL);
1700: goto out;
1701: /* NOTREACHED */
1702:
1703: default:
1704: /*
1705: * The command to get the slot failed. Kill outstanding
1706: * commands for the same drive only. No need to reset
1707: * the drive, it's unblocked nevertheless.
1708: */
1709: break;
1710: }
1711:
1712: /* Requeue all unfinished commands for same drive as failed command */
1713: for (slot = 0; slot < sc->sc_ncmds; slot++) {
1.62 kamil 1714: if ((achp->ahcic_cmds_active & (1U << slot)) == 0)
1.58 jdolecek 1715: continue;
1716:
1717: xfer = ata_queue_hwslot_to_xfer(chp, slot);
1718: if (drive != xfer->c_drive)
1719: continue;
1720:
1721: xfer->c_kill_xfer(chp, xfer,
1722: (error == 0) ? KILL_REQUEUE : KILL_RESET);
1.1 bouyer 1723: }
1.58 jdolecek 1724:
1725: out:
1726: /* Drive unblocked, back to normal operation */
1727: achp->ahcic_recovering = false;
1728: atastart(chp);
1.1 bouyer 1729: }
1730:
1.29 jakllsch 1731: static int
1.1 bouyer 1732: ahci_dma_setup(struct ata_channel *chp, int slot, void *data,
1733: size_t count, int op)
1734: {
1735: int error, seg;
1736: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1737: struct ahci_channel *achp = (struct ahci_channel *)chp;
1738: struct ahci_cmd_tbl *cmd_tbl;
1739: struct ahci_cmd_header *cmd_h;
1740:
1741: cmd_h = &achp->ahcic_cmdh[slot];
1742: cmd_tbl = achp->ahcic_cmd_tbl[slot];
1743:
1744: if (data == NULL) {
1745: cmd_h->cmdh_prdtl = 0;
1746: goto end;
1747: }
1748:
1749: error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot],
1750: data, count, NULL,
1751: BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op);
1752: if (error) {
1753: printf("%s port %d: failed to load xfer: %d\n",
1754: AHCINAME(sc), chp->ch_channel, error);
1755: return error;
1756: }
1757: bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1758: achp->ahcic_datad[slot]->dm_mapsize,
1759: (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1760: for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) {
1.28 jakllsch 1761: cmd_tbl->cmdt_prd[seg].prd_dba = htole64(
1.1 bouyer 1762: achp->ahcic_datad[slot]->dm_segs[seg].ds_addr);
1763: cmd_tbl->cmdt_prd[seg].prd_dbc = htole32(
1764: achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1);
1765: }
1766: cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC);
1767: cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs);
1768: end:
1769: AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE);
1770: return 0;
1771: }
1.8 bouyer 1772:
1773: #if NATAPIBUS > 0
1.29 jakllsch 1774: static void
1.8 bouyer 1775: ahci_atapibus_attach(struct atabus_softc * ata_sc)
1776: {
1777: struct ata_channel *chp = ata_sc->sc_chan;
1778: struct atac_softc *atac = chp->ch_atac;
1779: struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
1780: struct scsipi_channel *chan = &chp->ch_atapi_channel;
1781: /*
1782: * Fill in the scsipi_adapter.
1783: */
1.13 cube 1784: adapt->adapt_dev = atac->atac_dev;
1.8 bouyer 1785: adapt->adapt_nchannels = atac->atac_nchannels;
1786: adapt->adapt_request = ahci_atapi_scsipi_request;
1787: adapt->adapt_minphys = ahci_atapi_minphys;
1788: atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device;
1789:
1790: /*
1791: * Fill in the scsipi_channel.
1792: */
1793: memset(chan, 0, sizeof(*chan));
1794: chan->chan_adapter = adapt;
1795: chan->chan_bustype = &ahci_atapi_bustype;
1796: chan->chan_channel = chp->ch_channel;
1797: chan->chan_flags = SCSIPI_CHAN_OPENINGS;
1798: chan->chan_openings = 1;
1799: chan->chan_max_periph = 1;
1800: chan->chan_ntargets = 1;
1801: chan->chan_nluns = 1;
1.13 cube 1802: chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan,
1.8 bouyer 1803: atapiprint);
1804: }
1805:
1.29 jakllsch 1806: static void
1.8 bouyer 1807: ahci_atapi_minphys(struct buf *bp)
1808: {
1809: if (bp->b_bcount > MAXPHYS)
1810: bp->b_bcount = MAXPHYS;
1811: minphys(bp);
1812: }
1813:
1814: /*
1815: * Kill off all pending xfers for a periph.
1816: *
1817: * Must be called at splbio().
1818: */
1.29 jakllsch 1819: static void
1.8 bouyer 1820: ahci_atapi_kill_pending(struct scsipi_periph *periph)
1821: {
1822: struct atac_softc *atac =
1.13 cube 1823: device_private(periph->periph_channel->chan_adapter->adapt_dev);
1.8 bouyer 1824: struct ata_channel *chp =
1825: atac->atac_channels[periph->periph_channel->chan_channel];
1826:
1827: ata_kill_pending(&chp->ch_drive[periph->periph_target]);
1828: }
1829:
1.29 jakllsch 1830: static void
1.8 bouyer 1831: ahci_atapi_scsipi_request(struct scsipi_channel *chan,
1832: scsipi_adapter_req_t req, void *arg)
1833: {
1834: struct scsipi_adapter *adapt = chan->chan_adapter;
1835: struct scsipi_periph *periph;
1836: struct scsipi_xfer *sc_xfer;
1.13 cube 1837: struct ahci_softc *sc = device_private(adapt->adapt_dev);
1.8 bouyer 1838: struct atac_softc *atac = &sc->sc_atac;
1839: struct ata_xfer *xfer;
1840: int channel = chan->chan_channel;
1841: int drive, s;
1842:
1843: switch (req) {
1844: case ADAPTER_REQ_RUN_XFER:
1845: sc_xfer = arg;
1846: periph = sc_xfer->xs_periph;
1847: drive = periph->periph_target;
1.13 cube 1848: if (!device_is_active(atac->atac_dev)) {
1.8 bouyer 1849: sc_xfer->error = XS_DRIVER_STUFFUP;
1850: scsipi_done(sc_xfer);
1851: return;
1852: }
1.58 jdolecek 1853: xfer = ata_get_xfer_ext(atac->atac_channels[channel], 0, 0);
1.8 bouyer 1854: if (xfer == NULL) {
1855: sc_xfer->error = XS_RESOURCE_SHORTAGE;
1856: scsipi_done(sc_xfer);
1857: return;
1858: }
1859:
1860: if (sc_xfer->xs_control & XS_CTL_POLL)
1861: xfer->c_flags |= C_POLL;
1862: xfer->c_drive = drive;
1863: xfer->c_flags |= C_ATAPI;
1.58 jdolecek 1864: xfer->c_scsipi = sc_xfer;
1.8 bouyer 1865: xfer->c_databuf = sc_xfer->data;
1866: xfer->c_bcount = sc_xfer->datalen;
1867: xfer->c_start = ahci_atapi_start;
1.58 jdolecek 1868: xfer->c_poll = ahci_atapi_poll;
1869: xfer->c_abort = ahci_atapi_abort;
1.8 bouyer 1870: xfer->c_intr = ahci_atapi_complete;
1871: xfer->c_kill_xfer = ahci_atapi_kill_xfer;
1872: xfer->c_dscpoll = 0;
1873: s = splbio();
1874: ata_exec_xfer(atac->atac_channels[channel], xfer);
1875: #ifdef DIAGNOSTIC
1876: if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 &&
1877: (sc_xfer->xs_status & XS_STS_DONE) == 0)
1878: panic("ahci_atapi_scsipi_request: polled command "
1879: "not done");
1880: #endif
1881: splx(s);
1882: return;
1883: default:
1884: /* Not supported, nothing to do. */
1885: ;
1886: }
1887: }
1888:
1.58 jdolecek 1889: static int
1.8 bouyer 1890: ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer)
1891: {
1892: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1893: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.58 jdolecek 1894: struct scsipi_xfer *sc_xfer = xfer->c_scsipi;
1.8 bouyer 1895: struct ahci_cmd_tbl *cmd_tbl;
1896: struct ahci_cmd_header *cmd_h;
1897:
1898: AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n",
1899: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
1900:
1.58 jdolecek 1901: ata_channel_lock_owned(chp);
1902:
1903: cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot];
1.8 bouyer 1904: AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
1905: cmd_tbl), DEBUG_XFERS);
1906:
1.20 jakllsch 1907: satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis);
1.40 bouyer 1908: cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive;
1.8 bouyer 1909: memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd));
1910: memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen);
1911:
1.58 jdolecek 1912: cmd_h = &achp->ahcic_cmdh[xfer->c_slot];
1.8 bouyer 1913: AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
1914: chp->ch_channel, cmd_h), DEBUG_XFERS);
1.58 jdolecek 1915: if (ahci_dma_setup(chp, xfer->c_slot,
1916: sc_xfer->datalen ? sc_xfer->data : NULL,
1.8 bouyer 1917: sc_xfer->datalen,
1918: (sc_xfer->xs_control & XS_CTL_DATA_IN) ?
1919: BUS_DMA_READ : BUS_DMA_WRITE)) {
1920: sc_xfer->error = XS_DRIVER_STUFFUP;
1.58 jdolecek 1921: return ATASTART_ABORT;
1.8 bouyer 1922: }
1923: cmd_h->cmdh_flags = htole16(
1924: ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) |
1.40 bouyer 1925: RHD_FISLEN / 4 | AHCI_CMDH_F_A |
1926: (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT));
1.8 bouyer 1927: cmd_h->cmdh_prdbc = 0;
1.58 jdolecek 1928: AHCI_CMDH_SYNC(sc, achp, xfer->c_slot,
1.8 bouyer 1929: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1930:
1931: if (xfer->c_flags & C_POLL) {
1932: /* polled command, disable interrupts */
1933: AHCI_WRITE(sc, AHCI_GHC,
1934: AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
1935: }
1936: /* start command */
1.62 kamil 1937: AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot);
1.8 bouyer 1938: /* and says we started this command */
1.62 kamil 1939: achp->ahcic_cmds_active |= 1U << xfer->c_slot;
1.8 bouyer 1940:
1941: if ((xfer->c_flags & C_POLL) == 0) {
1.62.2.1 jdolecek 1942: callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout),
1943: ata_timeout, chp);
1.58 jdolecek 1944: return ATASTART_STARTED;
1945: } else
1946: return ATASTART_POLL;
1947: }
1948:
1949: static void
1950: ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer)
1951: {
1952: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1953: struct ahci_channel *achp = (struct ahci_channel *)chp;
1954:
1.8 bouyer 1955: /*
1956: * Polled command.
1957: */
1.58 jdolecek 1958: for (int i = 0; i < ATA_DELAY / 10; i++) {
1959: if (xfer->c_scsipi->xs_status & XS_STS_DONE)
1.8 bouyer 1960: break;
1961: ahci_intr_port(sc, achp);
1962: delay(10000);
1963: }
1.58 jdolecek 1964: AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel,
1.8 bouyer 1965: AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
1.58 jdolecek 1966: AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)),
1967: AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)),
1968: AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)),
1969: AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)),
1970: AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)),
1971: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
1.8 bouyer 1972: DEBUG_XFERS);
1.58 jdolecek 1973: if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) {
1974: xfer->c_scsipi->error = XS_TIMEOUT;
1975: xfer->c_intr(chp, xfer, 0);
1.8 bouyer 1976: }
1977: /* reenable interrupts */
1978: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
1979: }
1980:
1.58 jdolecek 1981: static void
1982: ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer)
1983: {
1984: ahci_atapi_complete(chp, xfer, 0);
1985: }
1986:
1.29 jakllsch 1987: static int
1.58 jdolecek 1988: ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd)
1.8 bouyer 1989: {
1.58 jdolecek 1990: struct scsipi_xfer *sc_xfer = xfer->c_scsipi;
1.8 bouyer 1991: struct ahci_channel *achp = (struct ahci_channel *)chp;
1992: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1993:
1994: AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel),
1995: DEBUG_FUNCS);
1996:
1.58 jdolecek 1997: if (ata_waitdrain_xfer_check(chp, xfer))
1998: return 0;
1999:
1.8 bouyer 2000: if (xfer->c_flags & C_TIMEOU) {
2001: sc_xfer->error = XS_TIMEOUT;
2002: }
2003:
1.55 jakllsch 2004: if (xfer->c_bcount > 0) {
1.58 jdolecek 2005: bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0,
2006: achp->ahcic_datad[xfer->c_slot]->dm_mapsize,
1.55 jakllsch 2007: (sc_xfer->xs_control & XS_CTL_DATA_IN) ?
2008: BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1.58 jdolecek 2009: bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]);
1.55 jakllsch 2010: }
1.8 bouyer 2011:
1.58 jdolecek 2012: AHCI_CMDH_SYNC(sc, achp, xfer->c_slot,
1.8 bouyer 2013: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2014: sc_xfer->resid = sc_xfer->datalen;
1.58 jdolecek 2015: sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc);
1.8 bouyer 2016: AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n",
2017: sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS);
1.58 jdolecek 2018: if (AHCI_TFD_ST(tfd) & WDCS_ERR &&
1.16 bouyer 2019: ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 ||
2020: sc_xfer->resid == sc_xfer->datalen)) {
2021: sc_xfer->error = XS_SHORTSENSE;
1.58 jdolecek 2022: sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd);
1.16 bouyer 2023: if ((sc_xfer->xs_periph->periph_quirks &
2024: PQUIRK_NOSENSE) == 0) {
2025: /* ask scsipi to send a REQUEST_SENSE */
2026: sc_xfer->error = XS_BUSY;
2027: sc_xfer->status = SCSI_CHECK;
2028: }
1.62.2.2! jdolecek 2029: }
! 2030:
! 2031: KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0);
! 2032: achp->ahcic_cmds_active &= ~(1U << xfer->c_slot);
! 2033: ata_deactivate_xfer(chp, xfer);
! 2034:
1.58 jdolecek 2035: ata_free_xfer(chp, xfer);
1.8 bouyer 2036: scsipi_done(sc_xfer);
1.58 jdolecek 2037: if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0)
2038: atastart(chp);
1.8 bouyer 2039: return 0;
2040: }
2041:
1.29 jakllsch 2042: static void
1.8 bouyer 2043: ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
2044: {
1.58 jdolecek 2045: struct scsipi_xfer *sc_xfer = xfer->c_scsipi;
1.8 bouyer 2046: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.58 jdolecek 2047: bool deactivate = true;
1.8 bouyer 2048:
2049: /* remove this command from xfer queue */
2050: switch (reason) {
1.58 jdolecek 2051: case KILL_GONE_INACTIVE:
2052: deactivate = false;
2053: /* FALLTHROUGH */
1.8 bouyer 2054: case KILL_GONE:
2055: sc_xfer->error = XS_DRIVER_STUFFUP;
2056: break;
2057: case KILL_RESET:
2058: sc_xfer->error = XS_RESET;
2059: break;
1.58 jdolecek 2060: case KILL_REQUEUE:
2061: sc_xfer->error = XS_REQUEUE;
2062: break;
1.8 bouyer 2063: default:
2064: printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason);
2065: panic("ahci_ata_atapi_kill_xfer");
2066: }
1.58 jdolecek 2067:
2068: if (deactivate) {
1.62 kamil 2069: KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0);
2070: achp->ahcic_cmds_active &= ~(1U << xfer->c_slot);
1.58 jdolecek 2071: ata_deactivate_xfer(chp, xfer);
2072: }
2073:
1.8 bouyer 2074: ata_free_xfer(chp, xfer);
2075: scsipi_done(sc_xfer);
2076: }
2077:
1.29 jakllsch 2078: static void
1.8 bouyer 2079: ahci_atapi_probe_device(struct atapibus_softc *sc, int target)
2080: {
2081: struct scsipi_channel *chan = sc->sc_channel;
2082: struct scsipi_periph *periph;
2083: struct ataparams ids;
2084: struct ataparams *id = &ids;
1.13 cube 2085: struct ahci_softc *ahcic =
2086: device_private(chan->chan_adapter->adapt_dev);
1.8 bouyer 2087: struct atac_softc *atac = &ahcic->sc_atac;
2088: struct ata_channel *chp = atac->atac_channels[chan->chan_channel];
2089: struct ata_drive_datas *drvp = &chp->ch_drive[target];
2090: struct scsipibus_attach_args sa;
2091: char serial_number[21], model[41], firmware_revision[9];
2092: int s;
2093:
2094: /* skip if already attached */
2095: if (scsipi_lookup_periph(chan, target, 0) != NULL)
2096: return;
2097:
2098: /* if no ATAPI device detected at attach time, skip */
1.40 bouyer 2099: if (drvp->drive_type != ATA_DRIVET_ATAPI) {
1.8 bouyer 2100: AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d "
2101: "not present\n", target), DEBUG_PROBE);
2102: return;
2103: }
2104:
2105: /* Some ATAPI devices need a bit more time after software reset. */
2106: delay(5000);
2107: if (ata_get_params(drvp, AT_WAIT, id) == 0) {
2108: #ifdef ATAPI_DEBUG_PROBE
2109: printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n",
1.14 cube 2110: AHCINAME(ahcic), target,
1.8 bouyer 2111: id->atap_config & ATAPI_CFG_CMD_MASK,
2112: id->atap_config & ATAPI_CFG_DRQ_MASK);
2113: #endif
2114: periph = scsipi_alloc_periph(M_NOWAIT);
2115: if (periph == NULL) {
1.14 cube 2116: aprint_error_dev(sc->sc_dev,
2117: "unable to allocate periph for drive %d\n",
2118: target);
1.8 bouyer 2119: return;
2120: }
2121: periph->periph_dev = NULL;
2122: periph->periph_channel = chan;
2123: periph->periph_switch = &atapi_probe_periphsw;
2124: periph->periph_target = target;
2125: periph->periph_lun = 0;
2126: periph->periph_quirks = PQUIRK_ONLYBIG;
2127:
2128: #ifdef SCSIPI_DEBUG
2129: if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI &&
2130: SCSIPI_DEBUG_TARGET == target)
2131: periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS;
2132: #endif
2133: periph->periph_type = ATAPI_CFG_TYPE(id->atap_config);
2134: if (id->atap_config & ATAPI_CFG_REMOV)
2135: periph->periph_flags |= PERIPH_REMOVABLE;
2136: if (periph->periph_type == T_SEQUENTIAL) {
2137: s = splbio();
1.40 bouyer 2138: drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW;
1.8 bouyer 2139: splx(s);
2140: }
2141:
2142: sa.sa_periph = periph;
2143: sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config);
2144: sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ?
2145: T_REMOV : T_FIXED;
1.56 christos 2146: strnvisx(model, sizeof(model), id->atap_model, 40,
2147: VIS_TRIM|VIS_SAFE|VIS_OCTAL);
2148: strnvisx(serial_number, sizeof(serial_number), id->atap_serial,
2149: 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL);
2150: strnvisx(firmware_revision, sizeof(firmware_revision),
2151: id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL);
1.8 bouyer 2152: sa.sa_inqbuf.vendor = model;
2153: sa.sa_inqbuf.product = serial_number;
2154: sa.sa_inqbuf.revision = firmware_revision;
2155:
2156: /*
2157: * Determine the operating mode capabilities of the device.
2158: */
2159: if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16)
2160: periph->periph_cap |= PERIPH_CAP_CMD16;
2161: /* XXX This is gross. */
2162: periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK);
2163:
2164: drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa);
2165:
2166: if (drvp->drv_softc)
2167: ata_probe_caps(drvp);
2168: else {
2169: s = splbio();
1.40 bouyer 2170: drvp->drive_type = ATA_DRIVET_NONE;
1.8 bouyer 2171: splx(s);
2172: }
2173: } else {
2174: AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE "
1.58 jdolecek 2175: "failed for drive %s:%d:%d\n",
2176: AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE);
1.8 bouyer 2177: s = splbio();
1.40 bouyer 2178: drvp->drive_type = ATA_DRIVET_NONE;
1.8 bouyer 2179: splx(s);
2180: }
2181: }
2182: #endif /* NATAPIBUS */
CVSweb <webmaster@jp.NetBSD.org>