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Annotation of src/sys/dev/ic/ahcisata_core.c, Revision 1.24

1.24    ! bouyer      1: /*     $NetBSD: ahcisata_core.c,v 1.23 2010/02/23 21:38:36 bouyer Exp $        */
1.1       bouyer      2:
                      3: /*
                      4:  * Copyright (c) 2006 Manuel Bouyer.
                      5:  *
                      6:  * Redistribution and use in source and binary forms, with or without
                      7:  * modification, are permitted provided that the following conditions
                      8:  * are met:
                      9:  * 1. Redistributions of source code must retain the above copyright
                     10:  *    notice, this list of conditions and the following disclaimer.
                     11:  * 2. Redistributions in binary form must reproduce the above copyright
                     12:  *    notice, this list of conditions and the following disclaimer in the
                     13:  *    documentation and/or other materials provided with the distribution.
                     14:  *
                     15:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
                     16:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
                     17:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
                     18:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
                     19:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
                     20:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
                     21:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
                     22:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
                     23:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
                     24:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                     25:  *
                     26:  */
                     27:
                     28: #include <sys/cdefs.h>
1.24    ! bouyer     29: __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.23 2010/02/23 21:38:36 bouyer Exp $");
1.1       bouyer     30:
                     31: #include <sys/types.h>
                     32: #include <sys/malloc.h>
                     33: #include <sys/param.h>
                     34: #include <sys/kernel.h>
                     35: #include <sys/systm.h>
                     36: #include <sys/disklabel.h>
1.4       ad         37: #include <sys/proc.h>
1.8       bouyer     38: #include <sys/buf.h>
1.1       bouyer     39:
                     40: #include <uvm/uvm_extern.h>
                     41:
                     42: #include <dev/ic/wdcreg.h>
                     43: #include <dev/ata/atareg.h>
                     44: #include <dev/ata/satavar.h>
                     45: #include <dev/ata/satareg.h>
1.20      jakllsch   46: #include <dev/ata/satafisreg.h>
                     47: #include <dev/ata/satafisvar.h>
1.1       bouyer     48: #include <dev/ic/ahcisatavar.h>
                     49:
1.16      bouyer     50: #include <dev/scsipi/scsi_all.h> /* for SCSI status */
                     51:
1.8       bouyer     52: #include "atapibus.h"
                     53:
1.1       bouyer     54: #ifdef AHCI_DEBUG
                     55: int ahcidebug_mask = 0x0;
                     56: #endif
                     57:
                     58: void ahci_probe_drive(struct ata_channel *);
                     59: void ahci_setup_channel(struct ata_channel *);
                     60:
                     61: int  ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *);
                     62: void ahci_reset_drive(struct ata_drive_datas *, int);
                     63: void ahci_reset_channel(struct ata_channel *, int);
                     64: int  ahci_exec_command(struct ata_drive_datas *, struct ata_command *);
                     65: int  ahci_ata_addref(struct ata_drive_datas *);
                     66: void ahci_ata_delref(struct ata_drive_datas *);
                     67: void ahci_killpending(struct ata_drive_datas *);
                     68:
                     69: void ahci_cmd_start(struct ata_channel *, struct ata_xfer *);
                     70: int  ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int);
                     71: void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int);
                     72: void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ;
                     73: void ahci_bio_start(struct ata_channel *, struct ata_xfer *);
                     74: int  ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int);
                     75: void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ;
1.5       bouyer     76: void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int);
1.1       bouyer     77: void ahci_channel_start(struct ahci_softc *, struct ata_channel *);
                     78: void ahci_timeout(void *);
                     79: int  ahci_dma_setup(struct ata_channel *, int, void *, size_t, int);
                     80:
1.8       bouyer     81: #if NATAPIBUS > 0
                     82: void ahci_atapibus_attach(struct atabus_softc *);
                     83: void ahci_atapi_kill_pending(struct scsipi_periph *);
                     84: void ahci_atapi_minphys(struct buf *);
                     85: void ahci_atapi_scsipi_request(struct scsipi_channel *,
                     86:     scsipi_adapter_req_t, void *);
                     87: void ahci_atapi_start(struct ata_channel *, struct ata_xfer *);
                     88: int  ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int);
                     89: void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int);
                     90: void ahci_atapi_probe_device(struct atapibus_softc *, int);
                     91:
                     92: static const struct scsipi_bustype ahci_atapi_bustype = {
                     93:        SCSIPI_BUSTYPE_ATAPI,
                     94:        atapi_scsipi_cmd,
                     95:        atapi_interpret_sense,
                     96:        atapi_print_addr,
                     97:        ahci_atapi_kill_pending,
                     98: };
                     99: #endif /* NATAPIBUS */
                    100:
1.1       bouyer    101: #define ATA_DELAY 10000 /* 10s for a drive I/O */
1.24    ! bouyer    102: #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */
        !           103: #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10)
1.1       bouyer    104:
                    105: const struct ata_bustype ahci_ata_bustype = {
                    106:        SCSIPI_BUSTYPE_ATA,
                    107:        ahci_ata_bio,
                    108:        ahci_reset_drive,
                    109:        ahci_reset_channel,
                    110:        ahci_exec_command,
                    111:        ata_get_params,
                    112:        ahci_ata_addref,
                    113:        ahci_ata_delref,
                    114:        ahci_killpending
                    115: };
                    116:
                    117: void ahci_intr_port(struct ahci_softc *, struct ahci_channel *);
                    118:
1.7       joerg     119: static void ahci_setup_port(struct ahci_softc *sc, int i);
                    120:
                    121: int
                    122: ahci_reset(struct ahci_softc *sc)
1.1       bouyer    123: {
1.7       joerg     124:        int i;
1.1       bouyer    125:
                    126:        /* reset controller */
                    127:        AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR);
                    128:        /* wait up to 1s for reset to complete */
                    129:        for (i = 0; i < 1000; i++) {
1.6       bouyer    130:                delay(1000);
1.1       bouyer    131:                if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0)
                    132:                        break;
                    133:        }
                    134:        if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) {
                    135:                aprint_error("%s: reset failed\n", AHCINAME(sc));
1.7       joerg     136:                return -1;
1.1       bouyer    137:        }
                    138:        /* enable ahci mode */
                    139:        AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE);
1.7       joerg     140:        return 0;
                    141: }
1.1       bouyer    142:
1.7       joerg     143: void
                    144: ahci_setup_ports(struct ahci_softc *sc)
                    145: {
                    146:        u_int32_t ahci_ports;
                    147:        int i, port;
                    148:
                    149:        ahci_ports = AHCI_READ(sc, AHCI_PI);
                    150:        for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
                    151:                if ((ahci_ports & (1 << i)) == 0)
                    152:                        continue;
                    153:                if (port >= sc->sc_atac.atac_nchannels) {
                    154:                        aprint_error("%s: more ports than announced\n",
                    155:                            AHCINAME(sc));
                    156:                        break;
                    157:                }
                    158:                ahci_setup_port(sc, i);
                    159:        }
                    160: }
                    161:
                    162: void
                    163: ahci_reprobe_drives(struct ahci_softc *sc)
                    164: {
                    165:        u_int32_t ahci_ports;
                    166:        int i, port;
                    167:        struct ahci_channel *achp;
                    168:        struct ata_channel *chp;
                    169:
                    170:        ahci_ports = AHCI_READ(sc, AHCI_PI);
                    171:        for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
                    172:                if ((ahci_ports & (1 << i)) == 0)
                    173:                        continue;
                    174:                if (port >= sc->sc_atac.atac_nchannels) {
                    175:                        aprint_error("%s: more ports than announced\n",
                    176:                            AHCINAME(sc));
                    177:                        break;
                    178:                }
                    179:                achp = &sc->sc_channels[i];
                    180:                chp = &achp->ata_channel;
                    181:
                    182:                ahci_probe_drive(chp);
                    183:        }
                    184: }
                    185:
                    186: static void
                    187: ahci_setup_port(struct ahci_softc *sc, int i)
                    188: {
                    189:        struct ahci_channel *achp;
                    190:
                    191:        achp = &sc->sc_channels[i];
                    192:
                    193:        AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh);
                    194:        AHCI_WRITE(sc, AHCI_P_CLBU(i), 0);
                    195:        AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis);
                    196:        AHCI_WRITE(sc, AHCI_P_FBU(i), 0);
                    197: }
                    198:
                    199: void
                    200: ahci_enable_intrs(struct ahci_softc *sc)
                    201: {
                    202:
                    203:        /* clear interrupts */
                    204:        AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS));
                    205:        /* enable interrupts */
                    206:        AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
                    207: }
                    208:
                    209: void
                    210: ahci_attach(struct ahci_softc *sc)
                    211: {
                    212:        u_int32_t ahci_cap, ahci_rev, ahci_ports;
                    213:        int i, j, port;
                    214:        struct ahci_channel *achp;
                    215:        struct ata_channel *chp;
                    216:        int error;
                    217:        bus_dma_segment_t seg;
                    218:        int rseg;
                    219:        int dmasize;
                    220:        void *cmdhp;
                    221:        void *cmdtblp;
                    222:
                    223:        if (ahci_reset(sc) != 0)
                    224:                return;
1.1       bouyer    225:
                    226:        ahci_cap = AHCI_READ(sc, AHCI_CAP);
                    227:        sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1;
                    228:        sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1;
                    229:        ahci_rev = AHCI_READ(sc, AHCI_VS);
                    230:        aprint_normal("%s: AHCI revision ", AHCINAME(sc));
                    231:        switch(ahci_rev) {
                    232:        case AHCI_VS_10:
                    233:                aprint_normal("1.0");
                    234:                break;
                    235:        case AHCI_VS_11:
                    236:                aprint_normal("1.1");
                    237:                break;
1.11      xtraeme   238:        case AHCI_VS_12:
                    239:                aprint_normal("1.2");
                    240:                break;
1.1       bouyer    241:        default:
                    242:                aprint_normal("0x%x", ahci_rev);
                    243:                break;
                    244:        }
                    245:
                    246:        aprint_normal(", %d ports, %d command slots, features 0x%x\n",
                    247:            sc->sc_atac.atac_nchannels, sc->sc_ncmds,
                    248:            ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS));
                    249:        sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA;
1.12      xtraeme   250:        sc->sc_atac.atac_cap |= sc->sc_atac_capflags;
1.1       bouyer    251:        sc->sc_atac.atac_pio_cap = 4;
                    252:        sc->sc_atac.atac_dma_cap = 2;
                    253:        sc->sc_atac.atac_udma_cap = 6;
                    254:        sc->sc_atac.atac_channels = sc->sc_chanarray;
                    255:        sc->sc_atac.atac_probe = ahci_probe_drive;
                    256:        sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype;
                    257:        sc->sc_atac.atac_set_modes = ahci_setup_channel;
1.8       bouyer    258: #if NATAPIBUS > 0
                    259:        sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach;
                    260: #endif
1.1       bouyer    261:
                    262:        dmasize =
                    263:            (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels;
                    264:        error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
                    265:            &seg, 1, &rseg, BUS_DMA_NOWAIT);
                    266:        if (error) {
                    267:                aprint_error("%s: unable to allocate command header memory"
                    268:                    ", error=%d\n", AHCINAME(sc), error);
                    269:                return;
                    270:        }
                    271:        error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize,
                    272:            &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
                    273:        if (error) {
                    274:                aprint_error("%s: unable to map command header memory"
                    275:                    ", error=%d\n", AHCINAME(sc), error);
                    276:                return;
                    277:        }
                    278:        error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
                    279:            BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd);
                    280:        if (error) {
                    281:                aprint_error("%s: unable to create command header map"
                    282:                    ", error=%d\n", AHCINAME(sc), error);
                    283:                return;
                    284:        }
                    285:        error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd,
                    286:            cmdhp, dmasize, NULL, BUS_DMA_NOWAIT);
                    287:        if (error) {
                    288:                aprint_error("%s: unable to load command header map"
                    289:                    ", error=%d\n", AHCINAME(sc), error);
                    290:                return;
                    291:        }
                    292:        sc->sc_cmd_hdr = cmdhp;
                    293:
1.7       joerg     294:        ahci_enable_intrs(sc);
1.1       bouyer    295:
                    296:        ahci_ports = AHCI_READ(sc, AHCI_PI);
                    297:        for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
                    298:                if ((ahci_ports & (1 << i)) == 0)
                    299:                        continue;
                    300:                if (port >= sc->sc_atac.atac_nchannels) {
                    301:                        aprint_error("%s: more ports than announced\n",
                    302:                            AHCINAME(sc));
                    303:                        break;
                    304:                }
                    305:                achp = &sc->sc_channels[i];
                    306:                chp = (struct ata_channel *)achp;
                    307:                sc->sc_chanarray[i] = chp;
                    308:                chp->ch_channel = i;
                    309:                chp->ch_atac = &sc->sc_atac;
                    310:                chp->ch_queue = malloc(sizeof(struct ata_queue),
                    311:                    M_DEVBUF, M_NOWAIT);
                    312:                if (chp->ch_queue == NULL) {
                    313:                        aprint_error("%s port %d: can't allocate memory for "
                    314:                            "command queue", AHCINAME(sc), i);
                    315:                        break;
                    316:                }
                    317:                dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds;
                    318:                error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
                    319:                    &seg, 1, &rseg, BUS_DMA_NOWAIT);
                    320:                if (error) {
                    321:                        aprint_error("%s: unable to allocate command table "
                    322:                            "memory, error=%d\n", AHCINAME(sc), error);
                    323:                        break;
                    324:                }
                    325:                error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize,
                    326:                    &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
                    327:                if (error) {
                    328:                        aprint_error("%s: unable to map command table memory"
                    329:                            ", error=%d\n", AHCINAME(sc), error);
                    330:                        break;
                    331:                }
                    332:                error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
                    333:                    BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld);
                    334:                if (error) {
                    335:                        aprint_error("%s: unable to create command table map"
                    336:                            ", error=%d\n", AHCINAME(sc), error);
                    337:                        break;
                    338:                }
                    339:                error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld,
                    340:                    cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT);
                    341:                if (error) {
                    342:                        aprint_error("%s: unable to load command table map"
                    343:                            ", error=%d\n", AHCINAME(sc), error);
                    344:                        break;
                    345:                }
                    346:                achp->ahcic_cmdh  = (struct ahci_cmd_header *)
                    347:                    ((char *)cmdhp + AHCI_CMDH_SIZE * port);
                    348:                achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
                    349:                    AHCI_CMDH_SIZE * port;
                    350:                achp->ahcic_rfis = (struct ahci_r_fis *)
                    351:                    ((char *)cmdhp +
                    352:                     AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
                    353:                     AHCI_RFIS_SIZE * port);
                    354:                achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
                    355:                     AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
                    356:                     AHCI_RFIS_SIZE * port;
                    357:                AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i,
                    358:                   achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh,
                    359:                   achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis),
                    360:                   DEBUG_PROBE);
                    361:
                    362:                for (j = 0; j < sc->sc_ncmds; j++) {
                    363:                        achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *)
                    364:                            ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j);
                    365:                        achp->ahcic_bus_cmd_tbl[j] =
                    366:                             achp->ahcic_cmd_tbld->dm_segs[0].ds_addr +
                    367:                             AHCI_CMDTBL_SIZE * j;
                    368:                        achp->ahcic_cmdh[j].cmdh_cmdtba =
                    369:                            htole32(achp->ahcic_bus_cmd_tbl[j]);
                    370:                        achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0);
                    371:                        AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j,
                    372:                            achp->ahcic_cmd_tbl[j],
                    373:                            (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE);
                    374:                        /* The xfer DMA map */
                    375:                        error = bus_dmamap_create(sc->sc_dmat, MAXPHYS,
                    376:                            AHCI_NPRD, 0x400000 /* 4MB */, 0,
                    377:                            BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
                    378:                            &achp->ahcic_datad[j]);
                    379:                        if (error) {
                    380:                                aprint_error("%s: couldn't alloc xfer DMA map, "
                    381:                                    "error=%d\n", AHCINAME(sc), error);
                    382:                                goto end;
                    383:                        }
                    384:                }
1.7       joerg     385:                ahci_setup_port(sc, i);
1.1       bouyer    386:                chp->ch_ndrive = 1;
                    387:                if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
1.22      jakllsch  388:                    AHCI_P_SSTS(i), 4,  &achp->ahcic_sstatus) != 0) {
1.1       bouyer    389:                        aprint_error("%s: couldn't map channel %d "
                    390:                            "sata_status regs\n", AHCINAME(sc), i);
                    391:                        break;
                    392:                }
                    393:                if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
1.22      jakllsch  394:                    AHCI_P_SCTL(i), 4,  &achp->ahcic_scontrol) != 0) {
1.1       bouyer    395:                        aprint_error("%s: couldn't map channel %d "
                    396:                            "sata_control regs\n", AHCINAME(sc), i);
                    397:                        break;
                    398:                }
                    399:                if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
1.22      jakllsch  400:                    AHCI_P_SERR(i), 4,  &achp->ahcic_serror) != 0) {
1.1       bouyer    401:                        aprint_error("%s: couldn't map channel %d "
                    402:                            "sata_error regs\n", AHCINAME(sc), i);
                    403:                        break;
                    404:                }
                    405:                ata_channel_attach(chp);
                    406:                port++;
                    407: end:
                    408:                continue;
                    409:        }
                    410: }
                    411:
                    412: int
                    413: ahci_intr(void *v)
                    414: {
                    415:        struct ahci_softc *sc = v;
                    416:        u_int32_t is;
                    417:        int i, r = 0;
                    418:
                    419:        while ((is = AHCI_READ(sc, AHCI_IS))) {
                    420:                AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is),
                    421:                    DEBUG_INTR);
                    422:                r = 1;
                    423:                AHCI_WRITE(sc, AHCI_IS, is);
                    424:                for (i = 0; i < AHCI_MAX_PORTS; i++)
                    425:                        if (is & (1 << i))
                    426:                                ahci_intr_port(sc, &sc->sc_channels[i]);
                    427:        }
                    428:        return r;
                    429: }
                    430:
                    431: void
                    432: ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp)
                    433: {
                    434:        u_int32_t is, tfd;
                    435:        struct ata_channel *chp = &achp->ata_channel;
                    436:        struct ata_xfer *xfer = chp->ch_queue->active_xfer;
                    437:        int slot;
                    438:
                    439:        is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
                    440:        AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is);
                    441:        AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc),
                    442:            chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
                    443:            DEBUG_INTR);
                    444:
                    445:        if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
                    446:            AHCI_P_IX_OFS | AHCI_P_IX_UFS)) {
                    447:                slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))
                    448:                        & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
                    449:                if ((achp->ahcic_cmds_active & (1 << slot)) == 0)
                    450:                        return;
                    451:                /* stop channel */
1.5       bouyer    452:                ahci_channel_stop(sc, chp, 0);
1.1       bouyer    453:                if (slot != 0) {
                    454:                        printf("ahci_intr_port: slot %d\n", slot);
                    455:                        panic("ahci_intr_port");
                    456:                }
                    457:                if (is & AHCI_P_IX_TFES) {
                    458:                        tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
                    459:                        chp->ch_error =
                    460:                            (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT;
                    461:                        chp->ch_status = (tfd & 0xff);
                    462:                } else {
                    463:                        /* emulate a CRC error */
                    464:                        chp->ch_error = WDCE_CRC;
                    465:                        chp->ch_status = WDCS_ERR;
                    466:                }
                    467:                xfer->c_intr(chp, xfer, is);
1.5       bouyer    468:                /* if channel has not been restarted, do it now */
                    469:                if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR)
                    470:                    == 0)
                    471:                        ahci_channel_start(sc, chp);
1.1       bouyer    472:        } else {
                    473:                slot = 0; /* XXX */
                    474:                is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
                    475:                AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n",
                    476:                    chp->ch_channel, is, achp->ahcic_cmds_active,
                    477:                    AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR);
                    478:                if ((achp->ahcic_cmds_active & (1 << slot)) == 0)
                    479:                        return;
                    480:                if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot))
                    481:                    == 0) {
                    482:                        xfer->c_intr(chp, xfer, 0);
                    483:                }
                    484:        }
                    485: }
                    486:
                    487: void
                    488: ahci_reset_drive(struct ata_drive_datas *drvp, int flags)
                    489: {
                    490:        struct ata_channel *chp = drvp->chnl_softc;
                    491:        ata_reset_channel(chp, flags);
                    492:        return;
                    493: }
                    494:
                    495: void
                    496: ahci_reset_channel(struct ata_channel *chp, int flags)
                    497: {
                    498:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                    499:        struct ahci_channel *achp = (struct ahci_channel *)chp;
1.18      bouyer    500:        int i, tfd;
1.1       bouyer    501:
1.5       bouyer    502:        ahci_channel_stop(sc, chp, flags);
1.1       bouyer    503:        if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
                    504:            achp->ahcic_sstatus) != SStatus_DET_DEV) {
                    505:                printf("%s: port reset failed\n", AHCINAME(sc));
                    506:                /* XXX and then ? */
                    507:        }
                    508:        if (chp->ch_queue->active_xfer) {
                    509:                chp->ch_queue->active_xfer->c_kill_xfer(chp,
                    510:                    chp->ch_queue->active_xfer, KILL_RESET);
                    511:        }
1.24    ! bouyer    512:        tsleep(&sc, PRIBIO, "ahcirst", mstohz(500));
        !           513:        /* clear port interrupt register */
        !           514:        AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
        !           515:        /* clear SErrors and start operations */
        !           516:        ahci_channel_start(sc, chp);
1.18      bouyer    517:        /* wait 31s for BSY to clear */
1.24    ! bouyer    518:        for (i = 0; i <AHCI_RST_WAIT; i++) {
1.18      bouyer    519:                tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
                    520:                if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT)
                    521:                    & WDCS_BSY) == 0)
1.8       bouyer    522:                        break;
1.18      bouyer    523:                tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10));
1.8       bouyer    524:        }
1.24    ! bouyer    525:        if (i == AHCI_RST_WAIT)
1.18      bouyer    526:                aprint_error("%s: BSY never cleared, TD 0x%x\n",
                    527:                    AHCINAME(sc), tfd);
                    528:        AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
                    529:            DEBUG_PROBE);
1.8       bouyer    530:        /* clear port interrupt register */
                    531:        AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
                    532:
1.1       bouyer    533:        return;
                    534: }
                    535:
                    536: int
                    537: ahci_ata_addref(struct ata_drive_datas *drvp)
                    538: {
                    539:        return 0;
                    540: }
                    541:
                    542: void
                    543: ahci_ata_delref(struct ata_drive_datas *drvp)
                    544: {
                    545:        return;
                    546: }
                    547:
                    548: void
                    549: ahci_killpending(struct ata_drive_datas *drvp)
                    550: {
                    551:        return;
                    552: }
                    553:
                    554: void
                    555: ahci_probe_drive(struct ata_channel *chp)
                    556: {
                    557:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                    558:        struct ahci_channel *achp = (struct ahci_channel *)chp;
                    559:        int i, s;
                    560:        u_int32_t sig;
                    561:
                    562:        /* XXX This should be done by other code. */
                    563:        for (i = 0; i < chp->ch_ndrive; i++) {
                    564:                chp->ch_drive[i].chnl_softc = chp;
                    565:                chp->ch_drive[i].drive = i;
                    566:        }
                    567:
1.18      bouyer    568:        /* bring interface up, accept FISs, power up and spin up device */
1.1       bouyer    569:        AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1.18      bouyer    570:            AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE |
                    571:            AHCI_P_CMD_POD | AHCI_P_CMD_SUD);
1.1       bouyer    572:        /* reset the PHY and bring online */
                    573:        switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
                    574:            achp->ahcic_sstatus)) {
                    575:        case SStatus_DET_DEV:
1.24    ! bouyer    576:                tsleep(&sc, PRIBIO, "ahcidv", mstohz(500));
        !           577:                /* clear port interrupt register */
        !           578:                AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
        !           579:                /* clear SErrors and start operations */
        !           580:                ahci_channel_start(sc, chp);
1.18      bouyer    581:                /* wait 31s for BSY to clear */
1.24    ! bouyer    582:                for (i = 0; i <AHCI_RST_WAIT; i++) {
1.18      bouyer    583:                        sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
                    584:                        if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT)
                    585:                            & WDCS_BSY) == 0)
1.8       bouyer    586:                                break;
                    587:                        tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10));
                    588:                }
1.24    ! bouyer    589:                if (i == AHCI_RST_WAIT) {
1.18      bouyer    590:                        aprint_error("%s: BSY never cleared, TD 0x%x\n",
                    591:                            AHCINAME(sc), sig);
1.23      bouyer    592:                        return;
                    593:                }
1.18      bouyer    594:                AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
                    595:                    DEBUG_PROBE);
1.1       bouyer    596:                sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel));
                    597:                AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n",
                    598:                    AHCINAME(sc), chp->ch_channel, sig,
                    599:                    AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE);
                    600:                /*
                    601:                 * scnt and sn are supposed to be 0x1 for ATAPI, but in some
                    602:                 * cases we get wrong values here, so ignore it.
                    603:                 */
                    604:                s = splbio();
1.3       bouyer    605:                if ((sig & 0xffff0000) == 0xeb140000) {
1.8       bouyer    606:                        chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
1.3       bouyer    607:                } else
1.1       bouyer    608:                        chp->ch_drive[0].drive_flags |= DRIVE_ATA;
                    609:                splx(s);
1.23      bouyer    610:                /* clear port interrupt register */
                    611:                AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
                    612:                /* and enable interrupts */
1.1       bouyer    613:                AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel),
                    614:                    AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
                    615:                    AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS |
                    616:                    AHCI_P_IX_DHRS);
1.17      dillo     617:                /* wait 500ms before actually starting operations */
                    618:                tsleep(&sc, PRIBIO, "ahciprb", mstohz(500));
1.1       bouyer    619:                break;
                    620:
                    621:        default:
                    622:                break;
                    623:        }
                    624: }
                    625:
                    626: void
                    627: ahci_setup_channel(struct ata_channel *chp)
                    628: {
                    629:        return;
                    630: }
                    631:
                    632: int
                    633: ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c)
                    634: {
                    635:        struct ata_channel *chp = drvp->chnl_softc;
                    636:        struct ata_xfer *xfer;
                    637:        int ret;
                    638:        int s;
                    639:
                    640:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                    641:        AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n",
                    642:            chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
                    643:            DEBUG_XFERS);
                    644:        xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP :
                    645:            ATAXF_NOSLEEP);
                    646:        if (xfer == NULL) {
                    647:                return ATACMD_TRY_AGAIN;
                    648:        }
                    649:        if (ata_c->flags & AT_POLL)
                    650:                xfer->c_flags |= C_POLL;
                    651:        if (ata_c->flags & AT_WAIT)
                    652:                xfer->c_flags |= C_WAIT;
                    653:        xfer->c_drive = drvp->drive;
                    654:        xfer->c_databuf = ata_c->data;
                    655:        xfer->c_bcount = ata_c->bcount;
                    656:        xfer->c_cmd = ata_c;
                    657:        xfer->c_start = ahci_cmd_start;
                    658:        xfer->c_intr = ahci_cmd_complete;
                    659:        xfer->c_kill_xfer = ahci_cmd_kill_xfer;
                    660:        s = splbio();
                    661:        ata_exec_xfer(chp, xfer);
                    662: #ifdef DIAGNOSTIC
                    663:        if ((ata_c->flags & AT_POLL) != 0 &&
                    664:            (ata_c->flags & AT_DONE) == 0)
                    665:                panic("ahci_exec_command: polled command not done");
                    666: #endif
                    667:        if (ata_c->flags & AT_DONE) {
                    668:                ret = ATACMD_COMPLETE;
                    669:        } else {
                    670:                if (ata_c->flags & AT_WAIT) {
                    671:                        while ((ata_c->flags & AT_DONE) == 0) {
                    672:                                tsleep(ata_c, PRIBIO, "ahcicmd", 0);
                    673:                        }
                    674:                        ret = ATACMD_COMPLETE;
                    675:                } else {
                    676:                        ret = ATACMD_QUEUED;
                    677:                }
                    678:        }
                    679:        splx(s);
                    680:        return ret;
                    681: }
                    682:
                    683: void
                    684: ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer)
                    685: {
                    686:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                    687:        struct ahci_channel *achp = (struct ahci_channel *)chp;
                    688:        struct ata_command *ata_c = xfer->c_cmd;
                    689:        int slot = 0 /* XXX slot */;
                    690:        struct ahci_cmd_tbl *cmd_tbl;
                    691:        struct ahci_cmd_header *cmd_h;
                    692:        int i;
                    693:        int channel = chp->ch_channel;
                    694:
                    695:        AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n",
                    696:            AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
                    697:
                    698:        cmd_tbl = achp->ahcic_cmd_tbl[slot];
                    699:        AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
                    700:              cmd_tbl), DEBUG_XFERS);
                    701:
1.20      jakllsch  702:        satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis);
1.1       bouyer    703:
                    704:        cmd_h = &achp->ahcic_cmdh[slot];
                    705:        AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
                    706:            chp->ch_channel, cmd_h), DEBUG_XFERS);
                    707:        if (ahci_dma_setup(chp, slot,
                    708:            (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL,
                    709:            ata_c->bcount,
                    710:            (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
                    711:                ata_c->flags |= AT_DF;
                    712:                ahci_cmd_complete(chp, xfer, slot);
                    713:                return;
                    714:        }
                    715:        cmd_h->cmdh_flags = htole16(
                    716:            ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) |
1.20      jakllsch  717:            RHD_FISLEN / 4);
1.1       bouyer    718:        cmd_h->cmdh_prdbc = 0;
                    719:        AHCI_CMDH_SYNC(sc, achp, slot,
                    720:            BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
                    721:
                    722:        if (ata_c->flags & AT_POLL) {
                    723:                /* polled command, disable interrupts */
                    724:                AHCI_WRITE(sc, AHCI_GHC,
                    725:                    AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
                    726:        }
                    727:        chp->ch_flags |= ATACH_IRQ_WAIT;
1.5       bouyer    728:        chp->ch_status = 0;
1.1       bouyer    729:        /* start command */
                    730:        AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
                    731:        /* and says we started this command */
                    732:        achp->ahcic_cmds_active |= 1 << slot;
                    733:
                    734:        if ((ata_c->flags & AT_POLL) == 0) {
                    735:                chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
                    736:                callout_reset(&chp->ch_callout, mstohz(ata_c->timeout),
                    737:                    ahci_timeout, chp);
                    738:                return;
                    739:        }
                    740:        /*
                    741:         * Polled command.
                    742:         */
                    743:        for (i = 0; i < ata_c->timeout / 10; i++) {
                    744:                if (ata_c->flags & AT_DONE)
                    745:                        break;
                    746:                ahci_intr_port(sc, achp);
                    747:                if (ata_c->flags & AT_WAIT)
                    748:                        tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10));
                    749:                else
                    750:                        delay(10000);
                    751:        }
                    752:        AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
                    753:            AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
                    754:            AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
                    755:            AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
                    756:            AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
                    757:            DEBUG_XFERS);
                    758:        if ((ata_c->flags & AT_DONE) == 0) {
                    759:                ata_c->flags |= AT_TIMEOU;
                    760:                ahci_cmd_complete(chp, xfer, slot);
                    761:        }
                    762:        /* reenable interrupts */
                    763:        AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
                    764: }
                    765:
                    766: void
                    767: ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
                    768: {
                    769:        struct ata_command *ata_c = xfer->c_cmd;
                    770:        AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel),
                    771:            DEBUG_FUNCS);
                    772:
                    773:        switch (reason) {
                    774:        case KILL_GONE:
                    775:                ata_c->flags |= AT_GONE;
                    776:                break;
                    777:        case KILL_RESET:
                    778:                ata_c->flags |= AT_RESET;
                    779:                break;
                    780:        default:
                    781:                printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason);
                    782:                panic("ahci_cmd_kill_xfer");
                    783:        }
                    784:        ahci_cmd_done(chp, xfer, 0 /* XXX slot */);
                    785: }
                    786:
                    787: int
                    788: ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is)
                    789: {
                    790:        int slot = 0; /* XXX slot */
                    791:        struct ata_command *ata_c = xfer->c_cmd;
                    792:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                    793:
                    794:        AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n",
                    795:            chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)),
                    796:            AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
                    797:            DEBUG_FUNCS);
                    798:        chp->ch_flags &= ~ATACH_IRQ_WAIT;
                    799:        if (xfer->c_flags & C_TIMEOU) {
                    800:                ata_c->flags |= AT_TIMEOU;
                    801:        } else
                    802:                callout_stop(&chp->ch_callout);
                    803:
                    804:        chp->ch_queue->active_xfer = NULL;
                    805:
                    806:        if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) {
                    807:                ahci_cmd_kill_xfer(chp, xfer, KILL_GONE);
                    808:                chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN;
                    809:                wakeup(&chp->ch_queue->active_xfer);
                    810:                return 0;
                    811:        }
                    812:        if (is) {
                    813:                ata_c->r_head = 0;
                    814:                ata_c->r_count = 0;
                    815:                ata_c->r_sector = 0;
                    816:                ata_c->r_cyl = 0;
                    817:                if (chp->ch_status & WDCS_BSY) {
                    818:                        ata_c->flags |= AT_TIMEOU;
                    819:                } else if (chp->ch_status & WDCS_ERR) {
                    820:                        ata_c->r_error = chp->ch_error;
                    821:                        ata_c->flags |= AT_ERROR;
                    822:                }
                    823:        }
                    824:        ahci_cmd_done(chp, xfer, slot);
                    825:        return 0;
                    826: }
                    827:
                    828: void
                    829: ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot)
                    830: {
                    831:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                    832:        struct ahci_channel *achp = (struct ahci_channel *)chp;
                    833:        struct ata_command *ata_c = xfer->c_cmd;
                    834:
                    835:        AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel),
                    836:            DEBUG_FUNCS);
                    837:
                    838:        /* this comamnd is not active any more */
                    839:        achp->ahcic_cmds_active &= ~(1 << slot);
                    840:
                    841:        if (ata_c->flags & (AT_READ|AT_WRITE)) {
                    842:                bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
                    843:                    achp->ahcic_datad[slot]->dm_mapsize,
                    844:                    (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD :
                    845:                    BUS_DMASYNC_POSTWRITE);
                    846:                bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
                    847:        }
                    848:
1.2       fvdl      849:        AHCI_CMDH_SYNC(sc, achp, slot,
                    850:            BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
                    851:
1.1       bouyer    852:        ata_c->flags |= AT_DONE;
                    853:        if (achp->ahcic_cmdh[slot].cmdh_prdbc)
                    854:                ata_c->flags |= AT_XFDONE;
                    855:
                    856:        ata_free_xfer(chp, xfer);
                    857:        if (ata_c->flags & AT_WAIT)
                    858:                wakeup(ata_c);
                    859:        else if (ata_c->callback)
                    860:                ata_c->callback(ata_c->callback_arg);
                    861:        atastart(chp);
                    862:        return;
                    863: }
                    864:
                    865: int
                    866: ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio)
                    867: {
                    868:        struct ata_channel *chp = drvp->chnl_softc;
                    869:        struct ata_xfer *xfer;
                    870:
                    871:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                    872:        AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n",
                    873:            chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
                    874:            DEBUG_XFERS);
                    875:        xfer = ata_get_xfer(ATAXF_NOSLEEP);
                    876:        if (xfer == NULL) {
                    877:                return ATACMD_TRY_AGAIN;
                    878:        }
                    879:        if (ata_bio->flags & ATA_POLL)
                    880:                xfer->c_flags |= C_POLL;
                    881:        xfer->c_drive = drvp->drive;
                    882:        xfer->c_cmd = ata_bio;
                    883:        xfer->c_databuf = ata_bio->databuf;
                    884:        xfer->c_bcount = ata_bio->bcount;
                    885:        xfer->c_start = ahci_bio_start;
                    886:        xfer->c_intr = ahci_bio_complete;
                    887:        xfer->c_kill_xfer = ahci_bio_kill_xfer;
                    888:        ata_exec_xfer(chp, xfer);
                    889:        return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED;
                    890: }
                    891:
                    892: void
                    893: ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer)
                    894: {
                    895:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                    896:        struct ahci_channel *achp = (struct ahci_channel *)chp;
                    897:        struct ata_bio *ata_bio = xfer->c_cmd;
                    898:        int slot = 0 /* XXX slot */;
                    899:        struct ahci_cmd_tbl *cmd_tbl;
                    900:        struct ahci_cmd_header *cmd_h;
1.20      jakllsch  901:        int i;
1.1       bouyer    902:        int channel = chp->ch_channel;
                    903:
                    904:        AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n",
                    905:            AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
                    906:
                    907:        cmd_tbl = achp->ahcic_cmd_tbl[slot];
                    908:        AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
                    909:              cmd_tbl), DEBUG_XFERS);
                    910:
1.20      jakllsch  911:        satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis);
1.1       bouyer    912:
                    913:        cmd_h = &achp->ahcic_cmdh[slot];
                    914:        AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
                    915:            chp->ch_channel, cmd_h), DEBUG_XFERS);
                    916:        if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount,
                    917:            (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
                    918:                ata_bio->error = ERR_DMA;
                    919:                ata_bio->r_error = 0;
                    920:                ahci_bio_complete(chp, xfer, slot);
                    921:                return;
                    922:        }
                    923:        cmd_h->cmdh_flags = htole16(
                    924:            ((ata_bio->flags & ATA_READ) ? 0 :  AHCI_CMDH_F_WR) |
1.20      jakllsch  925:            RHD_FISLEN / 4);
1.1       bouyer    926:        cmd_h->cmdh_prdbc = 0;
1.2       fvdl      927:        AHCI_CMDH_SYNC(sc, achp, slot,
                    928:            BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1.1       bouyer    929:
                    930:        if (xfer->c_flags & C_POLL) {
                    931:                /* polled command, disable interrupts */
                    932:                AHCI_WRITE(sc, AHCI_GHC,
                    933:                    AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
                    934:        }
                    935:        chp->ch_flags |= ATACH_IRQ_WAIT;
1.5       bouyer    936:        chp->ch_status = 0;
1.1       bouyer    937:        /* start command */
                    938:        AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
                    939:        /* and says we started this command */
                    940:        achp->ahcic_cmds_active |= 1 << slot;
                    941:
                    942:        if ((xfer->c_flags & C_POLL) == 0) {
                    943:                chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
                    944:                callout_reset(&chp->ch_callout, mstohz(ATA_DELAY),
                    945:                    ahci_timeout, chp);
                    946:                return;
                    947:        }
                    948:        /*
                    949:         * Polled command.
                    950:         */
                    951:        for (i = 0; i < ATA_DELAY / 10; i++) {
                    952:                if (ata_bio->flags & ATA_ITSDONE)
                    953:                        break;
                    954:                ahci_intr_port(sc, achp);
                    955:                if (ata_bio->flags & ATA_NOSLEEP)
                    956:                        delay(10000);
                    957:                else
                    958:                        tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10));
                    959:        }
                    960:        AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
                    961:            AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
                    962:            AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
                    963:            AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
                    964:            AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
                    965:            DEBUG_XFERS);
                    966:        if ((ata_bio->flags & ATA_ITSDONE) == 0) {
                    967:                ata_bio->error = TIMEOUT;
                    968:                ahci_bio_complete(chp, xfer, slot);
                    969:        }
                    970:        /* reenable interrupts */
                    971:        AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
                    972: }
                    973:
                    974: void
                    975: ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
                    976: {
                    977:        int slot = 0;  /* XXX slot */
                    978:        int drive = xfer->c_drive;
                    979:        struct ata_bio *ata_bio = xfer->c_cmd;
                    980:        struct ahci_channel *achp = (struct ahci_channel *)chp;
                    981:        AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel),
                    982:            DEBUG_FUNCS);
                    983:
                    984:        achp->ahcic_cmds_active &= ~(1 << slot);
                    985:        ata_free_xfer(chp, xfer);
                    986:        ata_bio->flags |= ATA_ITSDONE;
                    987:        switch (reason) {
                    988:        case KILL_GONE:
                    989:                ata_bio->error = ERR_NODEV;
                    990:                break;
                    991:        case KILL_RESET:
                    992:                ata_bio->error = ERR_RESET;
                    993:                break;
                    994:        default:
                    995:                printf("ahci_bio_kill_xfer: unknown reason %d\n", reason);
                    996:                panic("ahci_bio_kill_xfer");
                    997:        }
                    998:        ata_bio->r_error = WDCE_ABRT;
                    999:        (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
                   1000: }
                   1001:
                   1002: int
                   1003: ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is)
                   1004: {
                   1005:        int slot = 0; /* XXX slot */
                   1006:        struct ata_bio *ata_bio = xfer->c_cmd;
                   1007:        int drive = xfer->c_drive;
                   1008:        struct ahci_channel *achp = (struct ahci_channel *)chp;
                   1009:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                   1010:
                   1011:        AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel),
                   1012:            DEBUG_FUNCS);
                   1013:
                   1014:        achp->ahcic_cmds_active &= ~(1 << slot);
                   1015:        chp->ch_flags &= ~ATACH_IRQ_WAIT;
1.5       bouyer   1016:        if (xfer->c_flags & C_TIMEOU) {
                   1017:                ata_bio->error = TIMEOUT;
                   1018:        } else {
                   1019:                callout_stop(&chp->ch_callout);
1.19      bouyer   1020:                ata_bio->error = NOERROR;
1.5       bouyer   1021:        }
1.1       bouyer   1022:
                   1023:        chp->ch_queue->active_xfer = NULL;
                   1024:        bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
                   1025:            achp->ahcic_datad[slot]->dm_mapsize,
                   1026:            (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD :
                   1027:            BUS_DMASYNC_POSTWRITE);
                   1028:        bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
                   1029:
                   1030:        if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) {
                   1031:                ahci_bio_kill_xfer(chp, xfer, KILL_GONE);
                   1032:                chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN;
                   1033:                wakeup(&chp->ch_queue->active_xfer);
                   1034:                return 0;
                   1035:        }
                   1036:        ata_free_xfer(chp, xfer);
                   1037:        ata_bio->flags |= ATA_ITSDONE;
                   1038:        if (chp->ch_status & WDCS_DWF) {
                   1039:                ata_bio->error = ERR_DF;
                   1040:        } else if (chp->ch_status & WDCS_ERR) {
                   1041:                ata_bio->error = ERROR;
                   1042:                ata_bio->r_error = chp->ch_error;
                   1043:        } else if (chp->ch_status & WDCS_CORR)
                   1044:                ata_bio->flags |= ATA_CORR;
                   1045:
                   1046:        AHCI_CMDH_SYNC(sc, achp, slot,
                   1047:            BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
                   1048:        AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld",
                   1049:            ata_bio->bcount), DEBUG_XFERS);
1.19      bouyer   1050:        /*
                   1051:         * if it was a write, complete data buffer may have been transfered
                   1052:         * before error detection; in this case don't use cmdh_prdbc
                   1053:         * as it won't reflect what was written to media. Assume nothing
                   1054:         * was transfered and leave bcount as-is.
                   1055:         */
                   1056:        if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR)
                   1057:                ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc);
1.1       bouyer   1058:        AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS);
                   1059:        (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
                   1060:        atastart(chp);
                   1061:        return 0;
                   1062: }
                   1063:
                   1064: void
1.5       bouyer   1065: ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags)
                   1066: {
                   1067:        int i;
                   1068:        /* stop channel */
                   1069:        AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
                   1070:            AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST);
                   1071:        /* wait 1s for channel to stop */
                   1072:        for (i = 0; i <100; i++) {
                   1073:                if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR)
                   1074:                    == 0)
                   1075:                        break;
                   1076:                if (flags & AT_WAIT)
                   1077:                        tsleep(&sc, PRIBIO, "ahcirst", mstohz(10));
                   1078:                else
                   1079:                        delay(10000);
                   1080:        }
                   1081:        if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) {
                   1082:                printf("%s: channel wouldn't stop\n", AHCINAME(sc));
                   1083:                /* XXX controller reset ? */
                   1084:                return;
                   1085:        }
                   1086: }
                   1087:
                   1088: void
1.1       bouyer   1089: ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp)
                   1090: {
                   1091:        /* clear error */
1.18      bouyer   1092:        AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel),
                   1093:            AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel)));
1.1       bouyer   1094:
                   1095:        /* and start controller */
                   1096:        AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
                   1097:            AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
                   1098:            AHCI_P_CMD_FRE | AHCI_P_CMD_ST);
                   1099: }
                   1100:
                   1101: void
                   1102: ahci_timeout(void *v)
                   1103: {
                   1104:        struct ata_channel *chp = (struct ata_channel *)v;
                   1105:        struct ata_xfer *xfer = chp->ch_queue->active_xfer;
                   1106:        int s = splbio();
                   1107:        AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR);
                   1108:        if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) {
                   1109:                xfer->c_flags |= C_TIMEOU;
                   1110:                xfer->c_intr(chp, xfer, 0);
                   1111:        }
                   1112:        splx(s);
                   1113: }
                   1114:
                   1115: int
                   1116: ahci_dma_setup(struct ata_channel *chp, int slot, void *data,
                   1117:     size_t count, int op)
                   1118: {
                   1119:        int error, seg;
                   1120:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                   1121:        struct ahci_channel *achp = (struct ahci_channel *)chp;
                   1122:        struct ahci_cmd_tbl *cmd_tbl;
                   1123:        struct ahci_cmd_header *cmd_h;
                   1124:
                   1125:        cmd_h = &achp->ahcic_cmdh[slot];
                   1126:        cmd_tbl = achp->ahcic_cmd_tbl[slot];
                   1127:
                   1128:        if (data == NULL) {
                   1129:                cmd_h->cmdh_prdtl = 0;
                   1130:                goto end;
                   1131:        }
                   1132:
                   1133:        error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot],
                   1134:            data, count, NULL,
                   1135:            BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op);
                   1136:        if (error) {
                   1137:                printf("%s port %d: failed to load xfer: %d\n",
                   1138:                    AHCINAME(sc), chp->ch_channel, error);
                   1139:                return error;
                   1140:        }
                   1141:        bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
                   1142:            achp->ahcic_datad[slot]->dm_mapsize,
                   1143:            (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
                   1144:        for (seg = 0; seg <  achp->ahcic_datad[slot]->dm_nsegs; seg++) {
                   1145:                cmd_tbl->cmdt_prd[seg].prd_dba = htole32(
                   1146:                     achp->ahcic_datad[slot]->dm_segs[seg].ds_addr);
                   1147:                cmd_tbl->cmdt_prd[seg].prd_dbau = 0;
                   1148:                cmd_tbl->cmdt_prd[seg].prd_dbc = htole32(
                   1149:                    achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1);
                   1150:        }
                   1151:        cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC);
                   1152:        cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs);
                   1153: end:
                   1154:        AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE);
                   1155:        return 0;
                   1156: }
1.8       bouyer   1157:
                   1158: #if NATAPIBUS > 0
                   1159: void
                   1160: ahci_atapibus_attach(struct atabus_softc * ata_sc)
                   1161: {
                   1162:        struct ata_channel *chp = ata_sc->sc_chan;
                   1163:        struct atac_softc *atac = chp->ch_atac;
                   1164:        struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
                   1165:        struct scsipi_channel *chan = &chp->ch_atapi_channel;
                   1166:        /*
                   1167:         * Fill in the scsipi_adapter.
                   1168:         */
1.13      cube     1169:        adapt->adapt_dev = atac->atac_dev;
1.8       bouyer   1170:        adapt->adapt_nchannels = atac->atac_nchannels;
                   1171:        adapt->adapt_request = ahci_atapi_scsipi_request;
                   1172:        adapt->adapt_minphys = ahci_atapi_minphys;
                   1173:        atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device;
                   1174:
                   1175:        /*
                   1176:         * Fill in the scsipi_channel.
                   1177:         */
                   1178:        memset(chan, 0, sizeof(*chan));
                   1179:        chan->chan_adapter = adapt;
                   1180:        chan->chan_bustype = &ahci_atapi_bustype;
                   1181:        chan->chan_channel = chp->ch_channel;
                   1182:        chan->chan_flags = SCSIPI_CHAN_OPENINGS;
                   1183:        chan->chan_openings = 1;
                   1184:        chan->chan_max_periph = 1;
                   1185:        chan->chan_ntargets = 1;
                   1186:        chan->chan_nluns = 1;
1.13      cube     1187:        chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan,
1.8       bouyer   1188:                atapiprint);
                   1189: }
                   1190:
                   1191: void
                   1192: ahci_atapi_minphys(struct buf *bp)
                   1193: {
                   1194:        if (bp->b_bcount > MAXPHYS)
                   1195:                bp->b_bcount = MAXPHYS;
                   1196:        minphys(bp);
                   1197: }
                   1198:
                   1199: /*
                   1200:  * Kill off all pending xfers for a periph.
                   1201:  *
                   1202:  * Must be called at splbio().
                   1203:  */
                   1204: void
                   1205: ahci_atapi_kill_pending(struct scsipi_periph *periph)
                   1206: {
                   1207:        struct atac_softc *atac =
1.13      cube     1208:            device_private(periph->periph_channel->chan_adapter->adapt_dev);
1.8       bouyer   1209:        struct ata_channel *chp =
                   1210:            atac->atac_channels[periph->periph_channel->chan_channel];
                   1211:
                   1212:        ata_kill_pending(&chp->ch_drive[periph->periph_target]);
                   1213: }
                   1214:
                   1215: void
                   1216: ahci_atapi_scsipi_request(struct scsipi_channel *chan,
                   1217:     scsipi_adapter_req_t req, void *arg)
                   1218: {
                   1219:        struct scsipi_adapter *adapt = chan->chan_adapter;
                   1220:        struct scsipi_periph *periph;
                   1221:        struct scsipi_xfer *sc_xfer;
1.13      cube     1222:        struct ahci_softc *sc = device_private(adapt->adapt_dev);
1.8       bouyer   1223:        struct atac_softc *atac = &sc->sc_atac;
                   1224:        struct ata_xfer *xfer;
                   1225:        int channel = chan->chan_channel;
                   1226:        int drive, s;
                   1227:
                   1228:        switch (req) {
                   1229:        case ADAPTER_REQ_RUN_XFER:
                   1230:                sc_xfer = arg;
                   1231:                periph = sc_xfer->xs_periph;
                   1232:                drive = periph->periph_target;
1.13      cube     1233:                if (!device_is_active(atac->atac_dev)) {
1.8       bouyer   1234:                        sc_xfer->error = XS_DRIVER_STUFFUP;
                   1235:                        scsipi_done(sc_xfer);
                   1236:                        return;
                   1237:                }
                   1238:                xfer = ata_get_xfer(ATAXF_NOSLEEP);
                   1239:                if (xfer == NULL) {
                   1240:                        sc_xfer->error = XS_RESOURCE_SHORTAGE;
                   1241:                        scsipi_done(sc_xfer);
                   1242:                        return;
                   1243:                }
                   1244:
                   1245:                if (sc_xfer->xs_control & XS_CTL_POLL)
                   1246:                        xfer->c_flags |= C_POLL;
                   1247:                xfer->c_drive = drive;
                   1248:                xfer->c_flags |= C_ATAPI;
                   1249:                xfer->c_cmd = sc_xfer;
                   1250:                xfer->c_databuf = sc_xfer->data;
                   1251:                xfer->c_bcount = sc_xfer->datalen;
                   1252:                xfer->c_start = ahci_atapi_start;
                   1253:                xfer->c_intr = ahci_atapi_complete;
                   1254:                xfer->c_kill_xfer = ahci_atapi_kill_xfer;
                   1255:                xfer->c_dscpoll = 0;
                   1256:                s = splbio();
                   1257:                ata_exec_xfer(atac->atac_channels[channel], xfer);
                   1258: #ifdef DIAGNOSTIC
                   1259:                if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 &&
                   1260:                    (sc_xfer->xs_status & XS_STS_DONE) == 0)
                   1261:                        panic("ahci_atapi_scsipi_request: polled command "
                   1262:                            "not done");
                   1263: #endif
                   1264:                splx(s);
                   1265:                return;
                   1266:        default:
                   1267:                /* Not supported, nothing to do. */
                   1268:                ;
                   1269:        }
                   1270: }
                   1271:
                   1272: void
                   1273: ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer)
                   1274: {
                   1275:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                   1276:        struct ahci_channel *achp = (struct ahci_channel *)chp;
                   1277:        struct scsipi_xfer *sc_xfer = xfer->c_cmd;
                   1278:        int slot = 0 /* XXX slot */;
                   1279:        struct ahci_cmd_tbl *cmd_tbl;
                   1280:        struct ahci_cmd_header *cmd_h;
                   1281:        int i;
                   1282:        int channel = chp->ch_channel;
                   1283:
                   1284:        AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n",
                   1285:            AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
                   1286:
                   1287:        cmd_tbl = achp->ahcic_cmd_tbl[slot];
                   1288:        AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
                   1289:              cmd_tbl), DEBUG_XFERS);
                   1290:
1.20      jakllsch 1291:        satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis);
1.8       bouyer   1292:        memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd));
                   1293:        memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen);
                   1294:
                   1295:        cmd_h = &achp->ahcic_cmdh[slot];
                   1296:        AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
                   1297:            chp->ch_channel, cmd_h), DEBUG_XFERS);
                   1298:        if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL,
                   1299:            sc_xfer->datalen,
                   1300:            (sc_xfer->xs_control & XS_CTL_DATA_IN) ?
                   1301:            BUS_DMA_READ : BUS_DMA_WRITE)) {
                   1302:                sc_xfer->error = XS_DRIVER_STUFFUP;
                   1303:                ahci_atapi_complete(chp, xfer, slot);
                   1304:                return;
                   1305:        }
                   1306:        cmd_h->cmdh_flags = htole16(
                   1307:            ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) |
1.20      jakllsch 1308:            RHD_FISLEN / 4 | AHCI_CMDH_F_A);
1.8       bouyer   1309:        cmd_h->cmdh_prdbc = 0;
                   1310:        AHCI_CMDH_SYNC(sc, achp, slot,
                   1311:            BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
                   1312:
                   1313:        if (xfer->c_flags & C_POLL) {
                   1314:                /* polled command, disable interrupts */
                   1315:                AHCI_WRITE(sc, AHCI_GHC,
                   1316:                    AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
                   1317:        }
                   1318:        chp->ch_flags |= ATACH_IRQ_WAIT;
                   1319:        chp->ch_status = 0;
                   1320:        /* start command */
                   1321:        AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
                   1322:        /* and says we started this command */
                   1323:        achp->ahcic_cmds_active |= 1 << slot;
                   1324:
                   1325:        if ((xfer->c_flags & C_POLL) == 0) {
                   1326:                chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
                   1327:                callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout),
                   1328:                    ahci_timeout, chp);
                   1329:                return;
                   1330:        }
                   1331:        /*
                   1332:         * Polled command.
                   1333:         */
                   1334:        for (i = 0; i < ATA_DELAY / 10; i++) {
                   1335:                if (sc_xfer->xs_status & XS_STS_DONE)
                   1336:                        break;
                   1337:                ahci_intr_port(sc, achp);
                   1338:                delay(10000);
                   1339:        }
                   1340:        AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
                   1341:            AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
                   1342:            AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
                   1343:            AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
                   1344:            AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
                   1345:            DEBUG_XFERS);
                   1346:        if ((sc_xfer->xs_status & XS_STS_DONE) == 0) {
                   1347:                sc_xfer->error = XS_TIMEOUT;
                   1348:                ahci_atapi_complete(chp, xfer, slot);
                   1349:        }
                   1350:        /* reenable interrupts */
                   1351:        AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
                   1352: }
                   1353:
                   1354: int
                   1355: ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
                   1356: {
                   1357:        int slot = 0; /* XXX slot */
                   1358:        struct scsipi_xfer *sc_xfer = xfer->c_cmd;
                   1359:        int drive = xfer->c_drive;
                   1360:        struct ahci_channel *achp = (struct ahci_channel *)chp;
                   1361:        struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
                   1362:
                   1363:        AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel),
                   1364:            DEBUG_FUNCS);
                   1365:
                   1366:        achp->ahcic_cmds_active &= ~(1 << slot);
                   1367:        chp->ch_flags &= ~ATACH_IRQ_WAIT;
                   1368:        if (xfer->c_flags & C_TIMEOU) {
                   1369:                sc_xfer->error = XS_TIMEOUT;
                   1370:        } else {
                   1371:                callout_stop(&chp->ch_callout);
                   1372:                sc_xfer->error = 0;
                   1373:        }
                   1374:
                   1375:        chp->ch_queue->active_xfer = NULL;
                   1376:        bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
                   1377:            achp->ahcic_datad[slot]->dm_mapsize,
                   1378:            (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD :
                   1379:            BUS_DMASYNC_POSTWRITE);
                   1380:        bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
                   1381:
                   1382:        if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) {
                   1383:                ahci_atapi_kill_xfer(chp, xfer, KILL_GONE);
                   1384:                chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN;
                   1385:                wakeup(&chp->ch_queue->active_xfer);
                   1386:                return 0;
                   1387:        }
                   1388:        ata_free_xfer(chp, xfer);
                   1389:
                   1390:        AHCI_CMDH_SYNC(sc, achp, slot,
                   1391:            BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
                   1392:        sc_xfer->resid = sc_xfer->datalen;
                   1393:        sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc);
                   1394:        AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n",
                   1395:            sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS);
1.16      bouyer   1396:        if (chp->ch_status & WDCS_ERR &&
                   1397:            ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 ||
                   1398:            sc_xfer->resid == sc_xfer->datalen)) {
                   1399:                sc_xfer->error = XS_SHORTSENSE;
                   1400:                sc_xfer->sense.atapi_sense = chp->ch_error;
                   1401:                if ((sc_xfer->xs_periph->periph_quirks &
                   1402:                    PQUIRK_NOSENSE) == 0) {
                   1403:                        /* ask scsipi to send a REQUEST_SENSE */
                   1404:                        sc_xfer->error = XS_BUSY;
                   1405:                        sc_xfer->status = SCSI_CHECK;
                   1406:                }
                   1407:        }
1.8       bouyer   1408:        scsipi_done(sc_xfer);
                   1409:        atastart(chp);
                   1410:        return 0;
                   1411: }
                   1412:
                   1413: void
                   1414: ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
                   1415: {
                   1416:        struct scsipi_xfer *sc_xfer = xfer->c_cmd;
                   1417:        struct ahci_channel *achp = (struct ahci_channel *)chp;
                   1418:        int slot = 0; /* XXX slot */
                   1419:
                   1420:        achp->ahcic_cmds_active &= ~(1 << slot);
                   1421:
                   1422:        /* remove this command from xfer queue */
                   1423:        switch (reason) {
                   1424:        case KILL_GONE:
                   1425:                sc_xfer->error = XS_DRIVER_STUFFUP;
                   1426:                break;
                   1427:        case KILL_RESET:
                   1428:                sc_xfer->error = XS_RESET;
                   1429:                break;
                   1430:        default:
                   1431:                printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason);
                   1432:                panic("ahci_ata_atapi_kill_xfer");
                   1433:        }
                   1434:        ata_free_xfer(chp, xfer);
                   1435:        scsipi_done(sc_xfer);
                   1436: }
                   1437:
                   1438: void
                   1439: ahci_atapi_probe_device(struct atapibus_softc *sc, int target)
                   1440: {
                   1441:        struct scsipi_channel *chan = sc->sc_channel;
                   1442:        struct scsipi_periph *periph;
                   1443:        struct ataparams ids;
                   1444:        struct ataparams *id = &ids;
1.13      cube     1445:        struct ahci_softc *ahcic =
                   1446:            device_private(chan->chan_adapter->adapt_dev);
1.8       bouyer   1447:        struct atac_softc *atac = &ahcic->sc_atac;
                   1448:        struct ata_channel *chp = atac->atac_channels[chan->chan_channel];
                   1449:        struct ata_drive_datas *drvp = &chp->ch_drive[target];
                   1450:        struct scsipibus_attach_args sa;
                   1451:        char serial_number[21], model[41], firmware_revision[9];
                   1452:        int s;
                   1453:
                   1454:        /* skip if already attached */
                   1455:        if (scsipi_lookup_periph(chan, target, 0) != NULL)
                   1456:                return;
                   1457:
                   1458:        /* if no ATAPI device detected at attach time, skip */
                   1459:        if ((drvp->drive_flags & DRIVE_ATAPI) == 0) {
                   1460:                AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d "
                   1461:                    "not present\n", target), DEBUG_PROBE);
                   1462:                return;
                   1463:        }
                   1464:
                   1465:        /* Some ATAPI devices need a bit more time after software reset. */
                   1466:        delay(5000);
                   1467:        if (ata_get_params(drvp,  AT_WAIT, id) == 0) {
                   1468: #ifdef ATAPI_DEBUG_PROBE
                   1469:                printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n",
1.14      cube     1470:                    AHCINAME(ahcic), target,
1.8       bouyer   1471:                    id->atap_config & ATAPI_CFG_CMD_MASK,
                   1472:                    id->atap_config & ATAPI_CFG_DRQ_MASK);
                   1473: #endif
                   1474:                periph = scsipi_alloc_periph(M_NOWAIT);
                   1475:                if (periph == NULL) {
1.14      cube     1476:                        aprint_error_dev(sc->sc_dev,
                   1477:                            "unable to allocate periph for drive %d\n",
                   1478:                            target);
1.8       bouyer   1479:                        return;
                   1480:                }
                   1481:                periph->periph_dev = NULL;
                   1482:                periph->periph_channel = chan;
                   1483:                periph->periph_switch = &atapi_probe_periphsw;
                   1484:                periph->periph_target = target;
                   1485:                periph->periph_lun = 0;
                   1486:                periph->periph_quirks = PQUIRK_ONLYBIG;
                   1487:
                   1488: #ifdef SCSIPI_DEBUG
                   1489:                if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI &&
                   1490:                    SCSIPI_DEBUG_TARGET == target)
                   1491:                        periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS;
                   1492: #endif
                   1493:                periph->periph_type = ATAPI_CFG_TYPE(id->atap_config);
                   1494:                if (id->atap_config & ATAPI_CFG_REMOV)
                   1495:                        periph->periph_flags |= PERIPH_REMOVABLE;
                   1496:                if (periph->periph_type == T_SEQUENTIAL) {
                   1497:                        s = splbio();
                   1498:                        drvp->drive_flags |= DRIVE_ATAPIST;
                   1499:                        splx(s);
                   1500:                }
                   1501:
                   1502:                sa.sa_periph = periph;
                   1503:                sa.sa_inqbuf.type =  ATAPI_CFG_TYPE(id->atap_config);
                   1504:                sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ?
                   1505:                    T_REMOV : T_FIXED;
                   1506:                scsipi_strvis((u_char *)model, 40, id->atap_model, 40);
                   1507:                scsipi_strvis((u_char *)serial_number, 20, id->atap_serial,
                   1508:                    20);
                   1509:                scsipi_strvis((u_char *)firmware_revision, 8,
                   1510:                    id->atap_revision, 8);
                   1511:                sa.sa_inqbuf.vendor = model;
                   1512:                sa.sa_inqbuf.product = serial_number;
                   1513:                sa.sa_inqbuf.revision = firmware_revision;
                   1514:
                   1515:                /*
                   1516:                 * Determine the operating mode capabilities of the device.
                   1517:                 */
                   1518:                if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16)
                   1519:                        periph->periph_cap |= PERIPH_CAP_CMD16;
                   1520:                /* XXX This is gross. */
                   1521:                periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK);
                   1522:
                   1523:                drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa);
                   1524:
                   1525:                if (drvp->drv_softc)
                   1526:                        ata_probe_caps(drvp);
                   1527:                else {
                   1528:                        s = splbio();
                   1529:                        drvp->drive_flags &= ~DRIVE_ATAPI;
                   1530:                        splx(s);
                   1531:                }
                   1532:        } else {
                   1533:                AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE "
                   1534:                    "failed for drive %s:%d:%d: error 0x%x\n",
                   1535:                    AHCINAME(ahcic), chp->ch_channel, target,
                   1536:                    chp->ch_error), DEBUG_PROBE);
                   1537:                s = splbio();
                   1538:                drvp->drive_flags &= ~DRIVE_ATAPI;
                   1539:                splx(s);
                   1540:        }
                   1541: }
                   1542: #endif /* NATAPIBUS */

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