Annotation of src/sys/dev/ic/ahcisata_core.c, Revision 1.18.8.2
1.18.8.2! jym 1: /* $NetBSD: ahcisata_core.c,v 1.20 2009/06/17 03:55:04 jakllsch Exp $ */
1.1 bouyer 2:
3: /*
4: * Copyright (c) 2006 Manuel Bouyer.
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: * 3. All advertising materials mentioning features or use of this software
15: * must display the following acknowledgement:
16: * This product includes software developed by Manuel Bouyer.
17: * 4. The name of the author may not be used to endorse or promote products
18: * derived from this software without specific prior written permission.
19: *
20: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30: *
31: */
32:
33: #include <sys/cdefs.h>
1.18.8.2! jym 34: __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.20 2009/06/17 03:55:04 jakllsch Exp $");
1.1 bouyer 35:
36: #include <sys/types.h>
37: #include <sys/malloc.h>
38: #include <sys/param.h>
39: #include <sys/kernel.h>
40: #include <sys/systm.h>
41: #include <sys/disklabel.h>
1.4 ad 42: #include <sys/proc.h>
1.8 bouyer 43: #include <sys/buf.h>
1.1 bouyer 44:
45: #include <uvm/uvm_extern.h>
46:
47: #include <dev/ic/wdcreg.h>
48: #include <dev/ata/atareg.h>
49: #include <dev/ata/satavar.h>
50: #include <dev/ata/satareg.h>
1.18.8.2! jym 51: #include <dev/ata/satafisreg.h>
! 52: #include <dev/ata/satafisvar.h>
1.1 bouyer 53: #include <dev/ic/ahcisatavar.h>
54:
1.16 bouyer 55: #include <dev/scsipi/scsi_all.h> /* for SCSI status */
56:
1.8 bouyer 57: #include "atapibus.h"
58:
1.1 bouyer 59: #ifdef AHCI_DEBUG
60: int ahcidebug_mask = 0x0;
61: #endif
62:
63: void ahci_probe_drive(struct ata_channel *);
64: void ahci_setup_channel(struct ata_channel *);
65:
66: int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *);
67: void ahci_reset_drive(struct ata_drive_datas *, int);
68: void ahci_reset_channel(struct ata_channel *, int);
69: int ahci_exec_command(struct ata_drive_datas *, struct ata_command *);
70: int ahci_ata_addref(struct ata_drive_datas *);
71: void ahci_ata_delref(struct ata_drive_datas *);
72: void ahci_killpending(struct ata_drive_datas *);
73:
74: void ahci_cmd_start(struct ata_channel *, struct ata_xfer *);
75: int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int);
76: void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int);
77: void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ;
78: void ahci_bio_start(struct ata_channel *, struct ata_xfer *);
79: int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int);
80: void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ;
1.5 bouyer 81: void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int);
1.1 bouyer 82: void ahci_channel_start(struct ahci_softc *, struct ata_channel *);
83: void ahci_timeout(void *);
84: int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int);
85:
1.8 bouyer 86: #if NATAPIBUS > 0
87: void ahci_atapibus_attach(struct atabus_softc *);
88: void ahci_atapi_kill_pending(struct scsipi_periph *);
89: void ahci_atapi_minphys(struct buf *);
90: void ahci_atapi_scsipi_request(struct scsipi_channel *,
91: scsipi_adapter_req_t, void *);
92: void ahci_atapi_start(struct ata_channel *, struct ata_xfer *);
93: int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int);
94: void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int);
95: void ahci_atapi_probe_device(struct atapibus_softc *, int);
96:
97: static const struct scsipi_bustype ahci_atapi_bustype = {
98: SCSIPI_BUSTYPE_ATAPI,
99: atapi_scsipi_cmd,
100: atapi_interpret_sense,
101: atapi_print_addr,
102: ahci_atapi_kill_pending,
103: };
104: #endif /* NATAPIBUS */
105:
1.1 bouyer 106: #define ATA_DELAY 10000 /* 10s for a drive I/O */
107:
108: const struct ata_bustype ahci_ata_bustype = {
109: SCSIPI_BUSTYPE_ATA,
110: ahci_ata_bio,
111: ahci_reset_drive,
112: ahci_reset_channel,
113: ahci_exec_command,
114: ata_get_params,
115: ahci_ata_addref,
116: ahci_ata_delref,
117: ahci_killpending
118: };
119:
120: void ahci_intr_port(struct ahci_softc *, struct ahci_channel *);
121:
1.7 joerg 122: static void ahci_setup_port(struct ahci_softc *sc, int i);
123:
124: int
125: ahci_reset(struct ahci_softc *sc)
1.1 bouyer 126: {
1.7 joerg 127: int i;
1.1 bouyer 128:
129: /* reset controller */
130: AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR);
131: /* wait up to 1s for reset to complete */
132: for (i = 0; i < 1000; i++) {
1.6 bouyer 133: delay(1000);
1.1 bouyer 134: if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0)
135: break;
136: }
137: if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) {
138: aprint_error("%s: reset failed\n", AHCINAME(sc));
1.7 joerg 139: return -1;
1.1 bouyer 140: }
141: /* enable ahci mode */
142: AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE);
1.7 joerg 143: return 0;
144: }
1.1 bouyer 145:
1.7 joerg 146: void
147: ahci_setup_ports(struct ahci_softc *sc)
148: {
149: u_int32_t ahci_ports;
150: int i, port;
151:
152: ahci_ports = AHCI_READ(sc, AHCI_PI);
153: for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
154: if ((ahci_ports & (1 << i)) == 0)
155: continue;
156: if (port >= sc->sc_atac.atac_nchannels) {
157: aprint_error("%s: more ports than announced\n",
158: AHCINAME(sc));
159: break;
160: }
161: ahci_setup_port(sc, i);
162: }
163: }
164:
165: void
166: ahci_reprobe_drives(struct ahci_softc *sc)
167: {
168: u_int32_t ahci_ports;
169: int i, port;
170: struct ahci_channel *achp;
171: struct ata_channel *chp;
172:
173: ahci_ports = AHCI_READ(sc, AHCI_PI);
174: for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
175: if ((ahci_ports & (1 << i)) == 0)
176: continue;
177: if (port >= sc->sc_atac.atac_nchannels) {
178: aprint_error("%s: more ports than announced\n",
179: AHCINAME(sc));
180: break;
181: }
182: achp = &sc->sc_channels[i];
183: chp = &achp->ata_channel;
184:
185: ahci_probe_drive(chp);
186: }
187: }
188:
189: static void
190: ahci_setup_port(struct ahci_softc *sc, int i)
191: {
192: struct ahci_channel *achp;
193:
194: achp = &sc->sc_channels[i];
195:
196: AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh);
197: AHCI_WRITE(sc, AHCI_P_CLBU(i), 0);
198: AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis);
199: AHCI_WRITE(sc, AHCI_P_FBU(i), 0);
200: }
201:
202: void
203: ahci_enable_intrs(struct ahci_softc *sc)
204: {
205:
206: /* clear interrupts */
207: AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS));
208: /* enable interrupts */
209: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
210: }
211:
212: void
213: ahci_attach(struct ahci_softc *sc)
214: {
215: u_int32_t ahci_cap, ahci_rev, ahci_ports;
216: int i, j, port;
217: struct ahci_channel *achp;
218: struct ata_channel *chp;
219: int error;
220: bus_dma_segment_t seg;
221: int rseg;
222: int dmasize;
223: void *cmdhp;
224: void *cmdtblp;
225:
226: if (ahci_reset(sc) != 0)
227: return;
1.1 bouyer 228:
229: ahci_cap = AHCI_READ(sc, AHCI_CAP);
230: sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1;
231: sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1;
232: ahci_rev = AHCI_READ(sc, AHCI_VS);
233: aprint_normal("%s: AHCI revision ", AHCINAME(sc));
234: switch(ahci_rev) {
235: case AHCI_VS_10:
236: aprint_normal("1.0");
237: break;
238: case AHCI_VS_11:
239: aprint_normal("1.1");
240: break;
1.11 xtraeme 241: case AHCI_VS_12:
242: aprint_normal("1.2");
243: break;
1.1 bouyer 244: default:
245: aprint_normal("0x%x", ahci_rev);
246: break;
247: }
248:
249: aprint_normal(", %d ports, %d command slots, features 0x%x\n",
250: sc->sc_atac.atac_nchannels, sc->sc_ncmds,
251: ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS));
252: sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA;
1.12 xtraeme 253: sc->sc_atac.atac_cap |= sc->sc_atac_capflags;
1.1 bouyer 254: sc->sc_atac.atac_pio_cap = 4;
255: sc->sc_atac.atac_dma_cap = 2;
256: sc->sc_atac.atac_udma_cap = 6;
257: sc->sc_atac.atac_channels = sc->sc_chanarray;
258: sc->sc_atac.atac_probe = ahci_probe_drive;
259: sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype;
260: sc->sc_atac.atac_set_modes = ahci_setup_channel;
1.8 bouyer 261: #if NATAPIBUS > 0
262: sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach;
263: #endif
1.1 bouyer 264:
265: dmasize =
266: (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels;
267: error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
268: &seg, 1, &rseg, BUS_DMA_NOWAIT);
269: if (error) {
270: aprint_error("%s: unable to allocate command header memory"
271: ", error=%d\n", AHCINAME(sc), error);
272: return;
273: }
274: error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize,
275: &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
276: if (error) {
277: aprint_error("%s: unable to map command header memory"
278: ", error=%d\n", AHCINAME(sc), error);
279: return;
280: }
281: error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
282: BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd);
283: if (error) {
284: aprint_error("%s: unable to create command header map"
285: ", error=%d\n", AHCINAME(sc), error);
286: return;
287: }
288: error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd,
289: cmdhp, dmasize, NULL, BUS_DMA_NOWAIT);
290: if (error) {
291: aprint_error("%s: unable to load command header map"
292: ", error=%d\n", AHCINAME(sc), error);
293: return;
294: }
295: sc->sc_cmd_hdr = cmdhp;
296:
1.7 joerg 297: ahci_enable_intrs(sc);
1.1 bouyer 298:
299: ahci_ports = AHCI_READ(sc, AHCI_PI);
300: for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
301: if ((ahci_ports & (1 << i)) == 0)
302: continue;
303: if (port >= sc->sc_atac.atac_nchannels) {
304: aprint_error("%s: more ports than announced\n",
305: AHCINAME(sc));
306: break;
307: }
308: achp = &sc->sc_channels[i];
309: chp = (struct ata_channel *)achp;
310: sc->sc_chanarray[i] = chp;
311: chp->ch_channel = i;
312: chp->ch_atac = &sc->sc_atac;
313: chp->ch_queue = malloc(sizeof(struct ata_queue),
314: M_DEVBUF, M_NOWAIT);
315: if (chp->ch_queue == NULL) {
316: aprint_error("%s port %d: can't allocate memory for "
317: "command queue", AHCINAME(sc), i);
318: break;
319: }
320: dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds;
321: error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
322: &seg, 1, &rseg, BUS_DMA_NOWAIT);
323: if (error) {
324: aprint_error("%s: unable to allocate command table "
325: "memory, error=%d\n", AHCINAME(sc), error);
326: break;
327: }
328: error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize,
329: &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
330: if (error) {
331: aprint_error("%s: unable to map command table memory"
332: ", error=%d\n", AHCINAME(sc), error);
333: break;
334: }
335: error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
336: BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld);
337: if (error) {
338: aprint_error("%s: unable to create command table map"
339: ", error=%d\n", AHCINAME(sc), error);
340: break;
341: }
342: error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld,
343: cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT);
344: if (error) {
345: aprint_error("%s: unable to load command table map"
346: ", error=%d\n", AHCINAME(sc), error);
347: break;
348: }
349: achp->ahcic_cmdh = (struct ahci_cmd_header *)
350: ((char *)cmdhp + AHCI_CMDH_SIZE * port);
351: achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
352: AHCI_CMDH_SIZE * port;
353: achp->ahcic_rfis = (struct ahci_r_fis *)
354: ((char *)cmdhp +
355: AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
356: AHCI_RFIS_SIZE * port);
357: achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
358: AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
359: AHCI_RFIS_SIZE * port;
360: AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i,
361: achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh,
362: achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis),
363: DEBUG_PROBE);
364:
365: for (j = 0; j < sc->sc_ncmds; j++) {
366: achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *)
367: ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j);
368: achp->ahcic_bus_cmd_tbl[j] =
369: achp->ahcic_cmd_tbld->dm_segs[0].ds_addr +
370: AHCI_CMDTBL_SIZE * j;
371: achp->ahcic_cmdh[j].cmdh_cmdtba =
372: htole32(achp->ahcic_bus_cmd_tbl[j]);
373: achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0);
374: AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j,
375: achp->ahcic_cmd_tbl[j],
376: (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE);
377: /* The xfer DMA map */
378: error = bus_dmamap_create(sc->sc_dmat, MAXPHYS,
379: AHCI_NPRD, 0x400000 /* 4MB */, 0,
380: BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
381: &achp->ahcic_datad[j]);
382: if (error) {
383: aprint_error("%s: couldn't alloc xfer DMA map, "
384: "error=%d\n", AHCINAME(sc), error);
385: goto end;
386: }
387: }
1.7 joerg 388: ahci_setup_port(sc, i);
1.1 bouyer 389: chp->ch_ndrive = 1;
390: if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
391: AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) {
392: aprint_error("%s: couldn't map channel %d "
393: "sata_status regs\n", AHCINAME(sc), i);
394: break;
395: }
396: if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
397: AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) {
398: aprint_error("%s: couldn't map channel %d "
399: "sata_control regs\n", AHCINAME(sc), i);
400: break;
401: }
402: if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
403: AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) {
404: aprint_error("%s: couldn't map channel %d "
405: "sata_error regs\n", AHCINAME(sc), i);
406: break;
407: }
408: ata_channel_attach(chp);
409: port++;
410: end:
411: continue;
412: }
413: }
414:
415: int
416: ahci_intr(void *v)
417: {
418: struct ahci_softc *sc = v;
419: u_int32_t is;
420: int i, r = 0;
421:
422: while ((is = AHCI_READ(sc, AHCI_IS))) {
423: AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is),
424: DEBUG_INTR);
425: r = 1;
426: AHCI_WRITE(sc, AHCI_IS, is);
427: for (i = 0; i < AHCI_MAX_PORTS; i++)
428: if (is & (1 << i))
429: ahci_intr_port(sc, &sc->sc_channels[i]);
430: }
431: return r;
432: }
433:
434: void
435: ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp)
436: {
437: u_int32_t is, tfd;
438: struct ata_channel *chp = &achp->ata_channel;
439: struct ata_xfer *xfer = chp->ch_queue->active_xfer;
440: int slot;
441:
442: is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
443: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is);
444: AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc),
445: chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
446: DEBUG_INTR);
447:
448: if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
449: AHCI_P_IX_OFS | AHCI_P_IX_UFS)) {
450: slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))
451: & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
452: if ((achp->ahcic_cmds_active & (1 << slot)) == 0)
453: return;
454: /* stop channel */
1.5 bouyer 455: ahci_channel_stop(sc, chp, 0);
1.1 bouyer 456: if (slot != 0) {
457: printf("ahci_intr_port: slot %d\n", slot);
458: panic("ahci_intr_port");
459: }
460: if (is & AHCI_P_IX_TFES) {
461: tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
462: chp->ch_error =
463: (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT;
464: chp->ch_status = (tfd & 0xff);
465: } else {
466: /* emulate a CRC error */
467: chp->ch_error = WDCE_CRC;
468: chp->ch_status = WDCS_ERR;
469: }
470: xfer->c_intr(chp, xfer, is);
1.5 bouyer 471: /* if channel has not been restarted, do it now */
472: if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR)
473: == 0)
474: ahci_channel_start(sc, chp);
1.1 bouyer 475: } else {
476: slot = 0; /* XXX */
477: is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
478: AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n",
479: chp->ch_channel, is, achp->ahcic_cmds_active,
480: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR);
481: if ((achp->ahcic_cmds_active & (1 << slot)) == 0)
482: return;
483: if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot))
484: == 0) {
485: xfer->c_intr(chp, xfer, 0);
486: }
487: }
488: }
489:
490: void
491: ahci_reset_drive(struct ata_drive_datas *drvp, int flags)
492: {
493: struct ata_channel *chp = drvp->chnl_softc;
494: ata_reset_channel(chp, flags);
495: return;
496: }
497:
498: void
499: ahci_reset_channel(struct ata_channel *chp, int flags)
500: {
501: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
502: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.18 bouyer 503: int i, tfd;
1.1 bouyer 504:
1.5 bouyer 505: ahci_channel_stop(sc, chp, flags);
1.1 bouyer 506: if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
507: achp->ahcic_sstatus) != SStatus_DET_DEV) {
508: printf("%s: port reset failed\n", AHCINAME(sc));
509: /* XXX and then ? */
510: }
511: if (chp->ch_queue->active_xfer) {
512: chp->ch_queue->active_xfer->c_kill_xfer(chp,
513: chp->ch_queue->active_xfer, KILL_RESET);
514: }
515: ahci_channel_start(sc, chp);
1.18 bouyer 516: /* wait 31s for BSY to clear */
517: for (i = 0; i <3100; i++) {
518: tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
519: if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT)
520: & WDCS_BSY) == 0)
1.8 bouyer 521: break;
1.18 bouyer 522: tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10));
1.8 bouyer 523: }
524: if (i == 1500)
1.18 bouyer 525: aprint_error("%s: BSY never cleared, TD 0x%x\n",
526: AHCINAME(sc), tfd);
527: AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
528: DEBUG_PROBE);
1.8 bouyer 529: /* clear port interrupt register */
530: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
531:
1.1 bouyer 532: return;
533: }
534:
535: int
536: ahci_ata_addref(struct ata_drive_datas *drvp)
537: {
538: return 0;
539: }
540:
541: void
542: ahci_ata_delref(struct ata_drive_datas *drvp)
543: {
544: return;
545: }
546:
547: void
548: ahci_killpending(struct ata_drive_datas *drvp)
549: {
550: return;
551: }
552:
553: void
554: ahci_probe_drive(struct ata_channel *chp)
555: {
556: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
557: struct ahci_channel *achp = (struct ahci_channel *)chp;
558: int i, s;
559: u_int32_t sig;
560:
561: /* XXX This should be done by other code. */
562: for (i = 0; i < chp->ch_ndrive; i++) {
563: chp->ch_drive[i].chnl_softc = chp;
564: chp->ch_drive[i].drive = i;
565: }
566:
1.18 bouyer 567: /* bring interface up, accept FISs, power up and spin up device */
1.1 bouyer 568: AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1.18 bouyer 569: AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE |
570: AHCI_P_CMD_POD | AHCI_P_CMD_SUD);
1.1 bouyer 571: /* reset the PHY and bring online */
572: switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
573: achp->ahcic_sstatus)) {
574: case SStatus_DET_DEV:
1.18 bouyer 575: /* clear SErrors and start operations */
576: ahci_channel_start(sc, chp);
577: /* wait 31s for BSY to clear */
578: for (i = 0; i <3100; i++) {
579: sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
580: if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT)
581: & WDCS_BSY) == 0)
1.8 bouyer 582: break;
583: tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10));
584: }
585: if (i == 1500)
1.18 bouyer 586: aprint_error("%s: BSY never cleared, TD 0x%x\n",
587: AHCINAME(sc), sig);
588: AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
589: DEBUG_PROBE);
1.1 bouyer 590: sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel));
591: AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n",
592: AHCINAME(sc), chp->ch_channel, sig,
593: AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE);
594: /*
595: * scnt and sn are supposed to be 0x1 for ATAPI, but in some
596: * cases we get wrong values here, so ignore it.
597: */
598: s = splbio();
1.3 bouyer 599: if ((sig & 0xffff0000) == 0xeb140000) {
1.8 bouyer 600: chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
1.3 bouyer 601: } else
1.1 bouyer 602: chp->ch_drive[0].drive_flags |= DRIVE_ATA;
603: splx(s);
604: /* enable interrupts */
605: AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel),
606: AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
607: AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS |
608: AHCI_P_IX_DHRS);
1.17 dillo 609: /* wait 500ms before actually starting operations */
610: tsleep(&sc, PRIBIO, "ahciprb", mstohz(500));
1.1 bouyer 611: break;
612:
613: default:
614: break;
615: }
616: }
617:
618: void
619: ahci_setup_channel(struct ata_channel *chp)
620: {
621: return;
622: }
623:
624: int
625: ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c)
626: {
627: struct ata_channel *chp = drvp->chnl_softc;
628: struct ata_xfer *xfer;
629: int ret;
630: int s;
631:
632: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
633: AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n",
634: chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
635: DEBUG_XFERS);
636: xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP :
637: ATAXF_NOSLEEP);
638: if (xfer == NULL) {
639: return ATACMD_TRY_AGAIN;
640: }
641: if (ata_c->flags & AT_POLL)
642: xfer->c_flags |= C_POLL;
643: if (ata_c->flags & AT_WAIT)
644: xfer->c_flags |= C_WAIT;
645: xfer->c_drive = drvp->drive;
646: xfer->c_databuf = ata_c->data;
647: xfer->c_bcount = ata_c->bcount;
648: xfer->c_cmd = ata_c;
649: xfer->c_start = ahci_cmd_start;
650: xfer->c_intr = ahci_cmd_complete;
651: xfer->c_kill_xfer = ahci_cmd_kill_xfer;
652: s = splbio();
653: ata_exec_xfer(chp, xfer);
654: #ifdef DIAGNOSTIC
655: if ((ata_c->flags & AT_POLL) != 0 &&
656: (ata_c->flags & AT_DONE) == 0)
657: panic("ahci_exec_command: polled command not done");
658: #endif
659: if (ata_c->flags & AT_DONE) {
660: ret = ATACMD_COMPLETE;
661: } else {
662: if (ata_c->flags & AT_WAIT) {
663: while ((ata_c->flags & AT_DONE) == 0) {
664: tsleep(ata_c, PRIBIO, "ahcicmd", 0);
665: }
666: ret = ATACMD_COMPLETE;
667: } else {
668: ret = ATACMD_QUEUED;
669: }
670: }
671: splx(s);
672: return ret;
673: }
674:
675: void
676: ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer)
677: {
678: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
679: struct ahci_channel *achp = (struct ahci_channel *)chp;
680: struct ata_command *ata_c = xfer->c_cmd;
681: int slot = 0 /* XXX slot */;
682: struct ahci_cmd_tbl *cmd_tbl;
683: struct ahci_cmd_header *cmd_h;
684: int i;
685: int channel = chp->ch_channel;
686:
687: AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n",
688: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
689:
690: cmd_tbl = achp->ahcic_cmd_tbl[slot];
691: AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
692: cmd_tbl), DEBUG_XFERS);
693:
1.18.8.2! jym 694: satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis);
1.1 bouyer 695:
696: cmd_h = &achp->ahcic_cmdh[slot];
697: AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
698: chp->ch_channel, cmd_h), DEBUG_XFERS);
699: if (ahci_dma_setup(chp, slot,
700: (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL,
701: ata_c->bcount,
702: (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
703: ata_c->flags |= AT_DF;
704: ahci_cmd_complete(chp, xfer, slot);
705: return;
706: }
707: cmd_h->cmdh_flags = htole16(
708: ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) |
1.18.8.2! jym 709: RHD_FISLEN / 4);
1.1 bouyer 710: cmd_h->cmdh_prdbc = 0;
711: AHCI_CMDH_SYNC(sc, achp, slot,
712: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
713:
714: if (ata_c->flags & AT_POLL) {
715: /* polled command, disable interrupts */
716: AHCI_WRITE(sc, AHCI_GHC,
717: AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
718: }
719: chp->ch_flags |= ATACH_IRQ_WAIT;
1.5 bouyer 720: chp->ch_status = 0;
1.1 bouyer 721: /* start command */
722: AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
723: /* and says we started this command */
724: achp->ahcic_cmds_active |= 1 << slot;
725:
726: if ((ata_c->flags & AT_POLL) == 0) {
727: chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
728: callout_reset(&chp->ch_callout, mstohz(ata_c->timeout),
729: ahci_timeout, chp);
730: return;
731: }
732: /*
733: * Polled command.
734: */
735: for (i = 0; i < ata_c->timeout / 10; i++) {
736: if (ata_c->flags & AT_DONE)
737: break;
738: ahci_intr_port(sc, achp);
739: if (ata_c->flags & AT_WAIT)
740: tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10));
741: else
742: delay(10000);
743: }
744: AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
745: AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
746: AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
747: AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
748: AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
749: DEBUG_XFERS);
750: if ((ata_c->flags & AT_DONE) == 0) {
751: ata_c->flags |= AT_TIMEOU;
752: ahci_cmd_complete(chp, xfer, slot);
753: }
754: /* reenable interrupts */
755: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
756: }
757:
758: void
759: ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
760: {
761: struct ata_command *ata_c = xfer->c_cmd;
762: AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel),
763: DEBUG_FUNCS);
764:
765: switch (reason) {
766: case KILL_GONE:
767: ata_c->flags |= AT_GONE;
768: break;
769: case KILL_RESET:
770: ata_c->flags |= AT_RESET;
771: break;
772: default:
773: printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason);
774: panic("ahci_cmd_kill_xfer");
775: }
776: ahci_cmd_done(chp, xfer, 0 /* XXX slot */);
777: }
778:
779: int
780: ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is)
781: {
782: int slot = 0; /* XXX slot */
783: struct ata_command *ata_c = xfer->c_cmd;
784: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
785:
786: AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n",
787: chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)),
788: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
789: DEBUG_FUNCS);
790: chp->ch_flags &= ~ATACH_IRQ_WAIT;
791: if (xfer->c_flags & C_TIMEOU) {
792: ata_c->flags |= AT_TIMEOU;
793: } else
794: callout_stop(&chp->ch_callout);
795:
796: chp->ch_queue->active_xfer = NULL;
797:
798: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) {
799: ahci_cmd_kill_xfer(chp, xfer, KILL_GONE);
800: chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN;
801: wakeup(&chp->ch_queue->active_xfer);
802: return 0;
803: }
804: if (is) {
805: ata_c->r_head = 0;
806: ata_c->r_count = 0;
807: ata_c->r_sector = 0;
808: ata_c->r_cyl = 0;
809: if (chp->ch_status & WDCS_BSY) {
810: ata_c->flags |= AT_TIMEOU;
811: } else if (chp->ch_status & WDCS_ERR) {
812: ata_c->r_error = chp->ch_error;
813: ata_c->flags |= AT_ERROR;
814: }
815: }
816: ahci_cmd_done(chp, xfer, slot);
817: return 0;
818: }
819:
820: void
821: ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot)
822: {
823: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
824: struct ahci_channel *achp = (struct ahci_channel *)chp;
825: struct ata_command *ata_c = xfer->c_cmd;
826:
827: AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel),
828: DEBUG_FUNCS);
829:
830: /* this comamnd is not active any more */
831: achp->ahcic_cmds_active &= ~(1 << slot);
832:
833: if (ata_c->flags & (AT_READ|AT_WRITE)) {
834: bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
835: achp->ahcic_datad[slot]->dm_mapsize,
836: (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD :
837: BUS_DMASYNC_POSTWRITE);
838: bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
839: }
840:
1.2 fvdl 841: AHCI_CMDH_SYNC(sc, achp, slot,
842: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
843:
1.1 bouyer 844: ata_c->flags |= AT_DONE;
845: if (achp->ahcic_cmdh[slot].cmdh_prdbc)
846: ata_c->flags |= AT_XFDONE;
847:
848: ata_free_xfer(chp, xfer);
849: if (ata_c->flags & AT_WAIT)
850: wakeup(ata_c);
851: else if (ata_c->callback)
852: ata_c->callback(ata_c->callback_arg);
853: atastart(chp);
854: return;
855: }
856:
857: int
858: ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio)
859: {
860: struct ata_channel *chp = drvp->chnl_softc;
861: struct ata_xfer *xfer;
862:
863: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
864: AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n",
865: chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
866: DEBUG_XFERS);
867: xfer = ata_get_xfer(ATAXF_NOSLEEP);
868: if (xfer == NULL) {
869: return ATACMD_TRY_AGAIN;
870: }
871: if (ata_bio->flags & ATA_POLL)
872: xfer->c_flags |= C_POLL;
873: xfer->c_drive = drvp->drive;
874: xfer->c_cmd = ata_bio;
875: xfer->c_databuf = ata_bio->databuf;
876: xfer->c_bcount = ata_bio->bcount;
877: xfer->c_start = ahci_bio_start;
878: xfer->c_intr = ahci_bio_complete;
879: xfer->c_kill_xfer = ahci_bio_kill_xfer;
880: ata_exec_xfer(chp, xfer);
881: return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED;
882: }
883:
884: void
885: ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer)
886: {
887: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
888: struct ahci_channel *achp = (struct ahci_channel *)chp;
889: struct ata_bio *ata_bio = xfer->c_cmd;
890: int slot = 0 /* XXX slot */;
891: struct ahci_cmd_tbl *cmd_tbl;
892: struct ahci_cmd_header *cmd_h;
1.18.8.2! jym 893: int i;
1.1 bouyer 894: int channel = chp->ch_channel;
895:
896: AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n",
897: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
898:
899: cmd_tbl = achp->ahcic_cmd_tbl[slot];
900: AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
901: cmd_tbl), DEBUG_XFERS);
902:
1.18.8.2! jym 903: satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis);
1.1 bouyer 904:
905: cmd_h = &achp->ahcic_cmdh[slot];
906: AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
907: chp->ch_channel, cmd_h), DEBUG_XFERS);
908: if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount,
909: (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
910: ata_bio->error = ERR_DMA;
911: ata_bio->r_error = 0;
912: ahci_bio_complete(chp, xfer, slot);
913: return;
914: }
915: cmd_h->cmdh_flags = htole16(
916: ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) |
1.18.8.2! jym 917: RHD_FISLEN / 4);
1.1 bouyer 918: cmd_h->cmdh_prdbc = 0;
1.2 fvdl 919: AHCI_CMDH_SYNC(sc, achp, slot,
920: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1.1 bouyer 921:
922: if (xfer->c_flags & C_POLL) {
923: /* polled command, disable interrupts */
924: AHCI_WRITE(sc, AHCI_GHC,
925: AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
926: }
927: chp->ch_flags |= ATACH_IRQ_WAIT;
1.5 bouyer 928: chp->ch_status = 0;
1.1 bouyer 929: /* start command */
930: AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
931: /* and says we started this command */
932: achp->ahcic_cmds_active |= 1 << slot;
933:
934: if ((xfer->c_flags & C_POLL) == 0) {
935: chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
936: callout_reset(&chp->ch_callout, mstohz(ATA_DELAY),
937: ahci_timeout, chp);
938: return;
939: }
940: /*
941: * Polled command.
942: */
943: for (i = 0; i < ATA_DELAY / 10; i++) {
944: if (ata_bio->flags & ATA_ITSDONE)
945: break;
946: ahci_intr_port(sc, achp);
947: if (ata_bio->flags & ATA_NOSLEEP)
948: delay(10000);
949: else
950: tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10));
951: }
952: AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
953: AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
954: AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
955: AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
956: AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
957: DEBUG_XFERS);
958: if ((ata_bio->flags & ATA_ITSDONE) == 0) {
959: ata_bio->error = TIMEOUT;
960: ahci_bio_complete(chp, xfer, slot);
961: }
962: /* reenable interrupts */
963: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
964: }
965:
966: void
967: ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
968: {
969: int slot = 0; /* XXX slot */
970: int drive = xfer->c_drive;
971: struct ata_bio *ata_bio = xfer->c_cmd;
972: struct ahci_channel *achp = (struct ahci_channel *)chp;
973: AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel),
974: DEBUG_FUNCS);
975:
976: achp->ahcic_cmds_active &= ~(1 << slot);
977: ata_free_xfer(chp, xfer);
978: ata_bio->flags |= ATA_ITSDONE;
979: switch (reason) {
980: case KILL_GONE:
981: ata_bio->error = ERR_NODEV;
982: break;
983: case KILL_RESET:
984: ata_bio->error = ERR_RESET;
985: break;
986: default:
987: printf("ahci_bio_kill_xfer: unknown reason %d\n", reason);
988: panic("ahci_bio_kill_xfer");
989: }
990: ata_bio->r_error = WDCE_ABRT;
991: (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
992: }
993:
994: int
995: ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is)
996: {
997: int slot = 0; /* XXX slot */
998: struct ata_bio *ata_bio = xfer->c_cmd;
999: int drive = xfer->c_drive;
1000: struct ahci_channel *achp = (struct ahci_channel *)chp;
1001: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1002:
1003: AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel),
1004: DEBUG_FUNCS);
1005:
1006: achp->ahcic_cmds_active &= ~(1 << slot);
1007: chp->ch_flags &= ~ATACH_IRQ_WAIT;
1.5 bouyer 1008: if (xfer->c_flags & C_TIMEOU) {
1009: ata_bio->error = TIMEOUT;
1010: } else {
1011: callout_stop(&chp->ch_callout);
1.18.8.1 jym 1012: ata_bio->error = NOERROR;
1.5 bouyer 1013: }
1.1 bouyer 1014:
1015: chp->ch_queue->active_xfer = NULL;
1016: bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1017: achp->ahcic_datad[slot]->dm_mapsize,
1018: (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD :
1019: BUS_DMASYNC_POSTWRITE);
1020: bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
1021:
1022: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) {
1023: ahci_bio_kill_xfer(chp, xfer, KILL_GONE);
1024: chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN;
1025: wakeup(&chp->ch_queue->active_xfer);
1026: return 0;
1027: }
1028: ata_free_xfer(chp, xfer);
1029: ata_bio->flags |= ATA_ITSDONE;
1030: if (chp->ch_status & WDCS_DWF) {
1031: ata_bio->error = ERR_DF;
1032: } else if (chp->ch_status & WDCS_ERR) {
1033: ata_bio->error = ERROR;
1034: ata_bio->r_error = chp->ch_error;
1035: } else if (chp->ch_status & WDCS_CORR)
1036: ata_bio->flags |= ATA_CORR;
1037:
1038: AHCI_CMDH_SYNC(sc, achp, slot,
1039: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1040: AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld",
1041: ata_bio->bcount), DEBUG_XFERS);
1.18.8.1 jym 1042: /*
1043: * if it was a write, complete data buffer may have been transfered
1044: * before error detection; in this case don't use cmdh_prdbc
1045: * as it won't reflect what was written to media. Assume nothing
1046: * was transfered and leave bcount as-is.
1047: */
1048: if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR)
1049: ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc);
1.1 bouyer 1050: AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS);
1051: (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
1052: atastart(chp);
1053: return 0;
1054: }
1055:
1056: void
1.5 bouyer 1057: ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags)
1058: {
1059: int i;
1060: /* stop channel */
1061: AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1062: AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST);
1063: /* wait 1s for channel to stop */
1064: for (i = 0; i <100; i++) {
1065: if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR)
1066: == 0)
1067: break;
1068: if (flags & AT_WAIT)
1069: tsleep(&sc, PRIBIO, "ahcirst", mstohz(10));
1070: else
1071: delay(10000);
1072: }
1073: if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) {
1074: printf("%s: channel wouldn't stop\n", AHCINAME(sc));
1075: /* XXX controller reset ? */
1076: return;
1077: }
1078: }
1079:
1080: void
1.1 bouyer 1081: ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp)
1082: {
1083: /* clear error */
1.18 bouyer 1084: AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel),
1085: AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel)));
1.1 bouyer 1086:
1087: /* and start controller */
1088: AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1089: AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1090: AHCI_P_CMD_FRE | AHCI_P_CMD_ST);
1091: }
1092:
1093: void
1094: ahci_timeout(void *v)
1095: {
1096: struct ata_channel *chp = (struct ata_channel *)v;
1097: struct ata_xfer *xfer = chp->ch_queue->active_xfer;
1098: int s = splbio();
1099: AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR);
1100: if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) {
1101: xfer->c_flags |= C_TIMEOU;
1102: xfer->c_intr(chp, xfer, 0);
1103: }
1104: splx(s);
1105: }
1106:
1107: int
1108: ahci_dma_setup(struct ata_channel *chp, int slot, void *data,
1109: size_t count, int op)
1110: {
1111: int error, seg;
1112: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1113: struct ahci_channel *achp = (struct ahci_channel *)chp;
1114: struct ahci_cmd_tbl *cmd_tbl;
1115: struct ahci_cmd_header *cmd_h;
1116:
1117: cmd_h = &achp->ahcic_cmdh[slot];
1118: cmd_tbl = achp->ahcic_cmd_tbl[slot];
1119:
1120: if (data == NULL) {
1121: cmd_h->cmdh_prdtl = 0;
1122: goto end;
1123: }
1124:
1125: error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot],
1126: data, count, NULL,
1127: BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op);
1128: if (error) {
1129: printf("%s port %d: failed to load xfer: %d\n",
1130: AHCINAME(sc), chp->ch_channel, error);
1131: return error;
1132: }
1133: bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1134: achp->ahcic_datad[slot]->dm_mapsize,
1135: (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1136: for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) {
1137: cmd_tbl->cmdt_prd[seg].prd_dba = htole32(
1138: achp->ahcic_datad[slot]->dm_segs[seg].ds_addr);
1139: cmd_tbl->cmdt_prd[seg].prd_dbau = 0;
1140: cmd_tbl->cmdt_prd[seg].prd_dbc = htole32(
1141: achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1);
1142: }
1143: cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC);
1144: cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs);
1145: end:
1146: AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE);
1147: return 0;
1148: }
1.8 bouyer 1149:
1150: #if NATAPIBUS > 0
1151: void
1152: ahci_atapibus_attach(struct atabus_softc * ata_sc)
1153: {
1154: struct ata_channel *chp = ata_sc->sc_chan;
1155: struct atac_softc *atac = chp->ch_atac;
1156: struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
1157: struct scsipi_channel *chan = &chp->ch_atapi_channel;
1158: /*
1159: * Fill in the scsipi_adapter.
1160: */
1.13 cube 1161: adapt->adapt_dev = atac->atac_dev;
1.8 bouyer 1162: adapt->adapt_nchannels = atac->atac_nchannels;
1163: adapt->adapt_request = ahci_atapi_scsipi_request;
1164: adapt->adapt_minphys = ahci_atapi_minphys;
1165: atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device;
1166:
1167: /*
1168: * Fill in the scsipi_channel.
1169: */
1170: memset(chan, 0, sizeof(*chan));
1171: chan->chan_adapter = adapt;
1172: chan->chan_bustype = &ahci_atapi_bustype;
1173: chan->chan_channel = chp->ch_channel;
1174: chan->chan_flags = SCSIPI_CHAN_OPENINGS;
1175: chan->chan_openings = 1;
1176: chan->chan_max_periph = 1;
1177: chan->chan_ntargets = 1;
1178: chan->chan_nluns = 1;
1.13 cube 1179: chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan,
1.8 bouyer 1180: atapiprint);
1181: }
1182:
1183: void
1184: ahci_atapi_minphys(struct buf *bp)
1185: {
1186: if (bp->b_bcount > MAXPHYS)
1187: bp->b_bcount = MAXPHYS;
1188: minphys(bp);
1189: }
1190:
1191: /*
1192: * Kill off all pending xfers for a periph.
1193: *
1194: * Must be called at splbio().
1195: */
1196: void
1197: ahci_atapi_kill_pending(struct scsipi_periph *periph)
1198: {
1199: struct atac_softc *atac =
1.13 cube 1200: device_private(periph->periph_channel->chan_adapter->adapt_dev);
1.8 bouyer 1201: struct ata_channel *chp =
1202: atac->atac_channels[periph->periph_channel->chan_channel];
1203:
1204: ata_kill_pending(&chp->ch_drive[periph->periph_target]);
1205: }
1206:
1207: void
1208: ahci_atapi_scsipi_request(struct scsipi_channel *chan,
1209: scsipi_adapter_req_t req, void *arg)
1210: {
1211: struct scsipi_adapter *adapt = chan->chan_adapter;
1212: struct scsipi_periph *periph;
1213: struct scsipi_xfer *sc_xfer;
1.13 cube 1214: struct ahci_softc *sc = device_private(adapt->adapt_dev);
1.8 bouyer 1215: struct atac_softc *atac = &sc->sc_atac;
1216: struct ata_xfer *xfer;
1217: int channel = chan->chan_channel;
1218: int drive, s;
1219:
1220: switch (req) {
1221: case ADAPTER_REQ_RUN_XFER:
1222: sc_xfer = arg;
1223: periph = sc_xfer->xs_periph;
1224: drive = periph->periph_target;
1.13 cube 1225: if (!device_is_active(atac->atac_dev)) {
1.8 bouyer 1226: sc_xfer->error = XS_DRIVER_STUFFUP;
1227: scsipi_done(sc_xfer);
1228: return;
1229: }
1230: xfer = ata_get_xfer(ATAXF_NOSLEEP);
1231: if (xfer == NULL) {
1232: sc_xfer->error = XS_RESOURCE_SHORTAGE;
1233: scsipi_done(sc_xfer);
1234: return;
1235: }
1236:
1237: if (sc_xfer->xs_control & XS_CTL_POLL)
1238: xfer->c_flags |= C_POLL;
1239: xfer->c_drive = drive;
1240: xfer->c_flags |= C_ATAPI;
1241: xfer->c_cmd = sc_xfer;
1242: xfer->c_databuf = sc_xfer->data;
1243: xfer->c_bcount = sc_xfer->datalen;
1244: xfer->c_start = ahci_atapi_start;
1245: xfer->c_intr = ahci_atapi_complete;
1246: xfer->c_kill_xfer = ahci_atapi_kill_xfer;
1247: xfer->c_dscpoll = 0;
1248: s = splbio();
1249: ata_exec_xfer(atac->atac_channels[channel], xfer);
1250: #ifdef DIAGNOSTIC
1251: if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 &&
1252: (sc_xfer->xs_status & XS_STS_DONE) == 0)
1253: panic("ahci_atapi_scsipi_request: polled command "
1254: "not done");
1255: #endif
1256: splx(s);
1257: return;
1258: default:
1259: /* Not supported, nothing to do. */
1260: ;
1261: }
1262: }
1263:
1264: void
1265: ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer)
1266: {
1267: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1268: struct ahci_channel *achp = (struct ahci_channel *)chp;
1269: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1270: int slot = 0 /* XXX slot */;
1271: struct ahci_cmd_tbl *cmd_tbl;
1272: struct ahci_cmd_header *cmd_h;
1273: int i;
1274: int channel = chp->ch_channel;
1275:
1276: AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n",
1277: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
1278:
1279: cmd_tbl = achp->ahcic_cmd_tbl[slot];
1280: AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
1281: cmd_tbl), DEBUG_XFERS);
1282:
1.18.8.2! jym 1283: satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis);
1.8 bouyer 1284: memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd));
1285: memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen);
1286:
1287: cmd_h = &achp->ahcic_cmdh[slot];
1288: AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
1289: chp->ch_channel, cmd_h), DEBUG_XFERS);
1290: if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL,
1291: sc_xfer->datalen,
1292: (sc_xfer->xs_control & XS_CTL_DATA_IN) ?
1293: BUS_DMA_READ : BUS_DMA_WRITE)) {
1294: sc_xfer->error = XS_DRIVER_STUFFUP;
1295: ahci_atapi_complete(chp, xfer, slot);
1296: return;
1297: }
1298: cmd_h->cmdh_flags = htole16(
1299: ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) |
1.18.8.2! jym 1300: RHD_FISLEN / 4 | AHCI_CMDH_F_A);
1.8 bouyer 1301: cmd_h->cmdh_prdbc = 0;
1302: AHCI_CMDH_SYNC(sc, achp, slot,
1303: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1304:
1305: if (xfer->c_flags & C_POLL) {
1306: /* polled command, disable interrupts */
1307: AHCI_WRITE(sc, AHCI_GHC,
1308: AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
1309: }
1310: chp->ch_flags |= ATACH_IRQ_WAIT;
1311: chp->ch_status = 0;
1312: /* start command */
1313: AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
1314: /* and says we started this command */
1315: achp->ahcic_cmds_active |= 1 << slot;
1316:
1317: if ((xfer->c_flags & C_POLL) == 0) {
1318: chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
1319: callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout),
1320: ahci_timeout, chp);
1321: return;
1322: }
1323: /*
1324: * Polled command.
1325: */
1326: for (i = 0; i < ATA_DELAY / 10; i++) {
1327: if (sc_xfer->xs_status & XS_STS_DONE)
1328: break;
1329: ahci_intr_port(sc, achp);
1330: delay(10000);
1331: }
1332: AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
1333: AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
1334: AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
1335: AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
1336: AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
1337: DEBUG_XFERS);
1338: if ((sc_xfer->xs_status & XS_STS_DONE) == 0) {
1339: sc_xfer->error = XS_TIMEOUT;
1340: ahci_atapi_complete(chp, xfer, slot);
1341: }
1342: /* reenable interrupts */
1343: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
1344: }
1345:
1346: int
1347: ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
1348: {
1349: int slot = 0; /* XXX slot */
1350: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1351: int drive = xfer->c_drive;
1352: struct ahci_channel *achp = (struct ahci_channel *)chp;
1353: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1354:
1355: AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel),
1356: DEBUG_FUNCS);
1357:
1358: achp->ahcic_cmds_active &= ~(1 << slot);
1359: chp->ch_flags &= ~ATACH_IRQ_WAIT;
1360: if (xfer->c_flags & C_TIMEOU) {
1361: sc_xfer->error = XS_TIMEOUT;
1362: } else {
1363: callout_stop(&chp->ch_callout);
1364: sc_xfer->error = 0;
1365: }
1366:
1367: chp->ch_queue->active_xfer = NULL;
1368: bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1369: achp->ahcic_datad[slot]->dm_mapsize,
1370: (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD :
1371: BUS_DMASYNC_POSTWRITE);
1372: bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
1373:
1374: if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) {
1375: ahci_atapi_kill_xfer(chp, xfer, KILL_GONE);
1376: chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN;
1377: wakeup(&chp->ch_queue->active_xfer);
1378: return 0;
1379: }
1380: ata_free_xfer(chp, xfer);
1381:
1382: AHCI_CMDH_SYNC(sc, achp, slot,
1383: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1384: sc_xfer->resid = sc_xfer->datalen;
1385: sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc);
1386: AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n",
1387: sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS);
1.16 bouyer 1388: if (chp->ch_status & WDCS_ERR &&
1389: ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 ||
1390: sc_xfer->resid == sc_xfer->datalen)) {
1391: sc_xfer->error = XS_SHORTSENSE;
1392: sc_xfer->sense.atapi_sense = chp->ch_error;
1393: if ((sc_xfer->xs_periph->periph_quirks &
1394: PQUIRK_NOSENSE) == 0) {
1395: /* ask scsipi to send a REQUEST_SENSE */
1396: sc_xfer->error = XS_BUSY;
1397: sc_xfer->status = SCSI_CHECK;
1398: }
1399: }
1.8 bouyer 1400: scsipi_done(sc_xfer);
1401: atastart(chp);
1402: return 0;
1403: }
1404:
1405: void
1406: ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
1407: {
1408: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1409: struct ahci_channel *achp = (struct ahci_channel *)chp;
1410: int slot = 0; /* XXX slot */
1411:
1412: achp->ahcic_cmds_active &= ~(1 << slot);
1413:
1414: /* remove this command from xfer queue */
1415: switch (reason) {
1416: case KILL_GONE:
1417: sc_xfer->error = XS_DRIVER_STUFFUP;
1418: break;
1419: case KILL_RESET:
1420: sc_xfer->error = XS_RESET;
1421: break;
1422: default:
1423: printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason);
1424: panic("ahci_ata_atapi_kill_xfer");
1425: }
1426: ata_free_xfer(chp, xfer);
1427: scsipi_done(sc_xfer);
1428: }
1429:
1430: void
1431: ahci_atapi_probe_device(struct atapibus_softc *sc, int target)
1432: {
1433: struct scsipi_channel *chan = sc->sc_channel;
1434: struct scsipi_periph *periph;
1435: struct ataparams ids;
1436: struct ataparams *id = &ids;
1.13 cube 1437: struct ahci_softc *ahcic =
1438: device_private(chan->chan_adapter->adapt_dev);
1.8 bouyer 1439: struct atac_softc *atac = &ahcic->sc_atac;
1440: struct ata_channel *chp = atac->atac_channels[chan->chan_channel];
1441: struct ata_drive_datas *drvp = &chp->ch_drive[target];
1442: struct scsipibus_attach_args sa;
1443: char serial_number[21], model[41], firmware_revision[9];
1444: int s;
1445:
1446: /* skip if already attached */
1447: if (scsipi_lookup_periph(chan, target, 0) != NULL)
1448: return;
1449:
1450: /* if no ATAPI device detected at attach time, skip */
1451: if ((drvp->drive_flags & DRIVE_ATAPI) == 0) {
1452: AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d "
1453: "not present\n", target), DEBUG_PROBE);
1454: return;
1455: }
1456:
1457: /* Some ATAPI devices need a bit more time after software reset. */
1458: delay(5000);
1459: if (ata_get_params(drvp, AT_WAIT, id) == 0) {
1460: #ifdef ATAPI_DEBUG_PROBE
1461: printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n",
1.14 cube 1462: AHCINAME(ahcic), target,
1.8 bouyer 1463: id->atap_config & ATAPI_CFG_CMD_MASK,
1464: id->atap_config & ATAPI_CFG_DRQ_MASK);
1465: #endif
1466: periph = scsipi_alloc_periph(M_NOWAIT);
1467: if (periph == NULL) {
1.14 cube 1468: aprint_error_dev(sc->sc_dev,
1469: "unable to allocate periph for drive %d\n",
1470: target);
1.8 bouyer 1471: return;
1472: }
1473: periph->periph_dev = NULL;
1474: periph->periph_channel = chan;
1475: periph->periph_switch = &atapi_probe_periphsw;
1476: periph->periph_target = target;
1477: periph->periph_lun = 0;
1478: periph->periph_quirks = PQUIRK_ONLYBIG;
1479:
1480: #ifdef SCSIPI_DEBUG
1481: if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI &&
1482: SCSIPI_DEBUG_TARGET == target)
1483: periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS;
1484: #endif
1485: periph->periph_type = ATAPI_CFG_TYPE(id->atap_config);
1486: if (id->atap_config & ATAPI_CFG_REMOV)
1487: periph->periph_flags |= PERIPH_REMOVABLE;
1488: if (periph->periph_type == T_SEQUENTIAL) {
1489: s = splbio();
1490: drvp->drive_flags |= DRIVE_ATAPIST;
1491: splx(s);
1492: }
1493:
1494: sa.sa_periph = periph;
1495: sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config);
1496: sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ?
1497: T_REMOV : T_FIXED;
1498: scsipi_strvis((u_char *)model, 40, id->atap_model, 40);
1499: scsipi_strvis((u_char *)serial_number, 20, id->atap_serial,
1500: 20);
1501: scsipi_strvis((u_char *)firmware_revision, 8,
1502: id->atap_revision, 8);
1503: sa.sa_inqbuf.vendor = model;
1504: sa.sa_inqbuf.product = serial_number;
1505: sa.sa_inqbuf.revision = firmware_revision;
1506:
1507: /*
1508: * Determine the operating mode capabilities of the device.
1509: */
1510: if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16)
1511: periph->periph_cap |= PERIPH_CAP_CMD16;
1512: /* XXX This is gross. */
1513: periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK);
1514:
1515: drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa);
1516:
1517: if (drvp->drv_softc)
1518: ata_probe_caps(drvp);
1519: else {
1520: s = splbio();
1521: drvp->drive_flags &= ~DRIVE_ATAPI;
1522: splx(s);
1523: }
1524: } else {
1525: AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE "
1526: "failed for drive %s:%d:%d: error 0x%x\n",
1527: AHCINAME(ahcic), chp->ch_channel, target,
1528: chp->ch_error), DEBUG_PROBE);
1529: s = splbio();
1530: drvp->drive_flags &= ~DRIVE_ATAPI;
1531: splx(s);
1532: }
1533: }
1534: #endif /* NATAPIBUS */
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