Annotation of src/sys/dev/ic/ahcisata_core.c, Revision 1.18.4.1.4.2
1.18.4.1.4.2! matt 1: /* $NetBSD: ahcisata_core.c,v 1.18.4.1.4.1 2010/04/21 00:27:35 matt Exp $ */
1.1 bouyer 2:
3: /*
4: * Copyright (c) 2006 Manuel Bouyer.
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: *
15: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25: *
26: */
27:
28: #include <sys/cdefs.h>
1.18.4.1.4.2! matt 29: __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.18.4.1.4.1 2010/04/21 00:27:35 matt Exp $");
1.1 bouyer 30:
31: #include <sys/types.h>
32: #include <sys/malloc.h>
33: #include <sys/param.h>
34: #include <sys/kernel.h>
35: #include <sys/systm.h>
36: #include <sys/disklabel.h>
1.4 ad 37: #include <sys/proc.h>
1.8 bouyer 38: #include <sys/buf.h>
1.1 bouyer 39:
40: #include <uvm/uvm_extern.h>
41:
42: #include <dev/ata/atareg.h>
43: #include <dev/ata/satavar.h>
44: #include <dev/ata/satareg.h>
1.18.4.1.4.2! matt 45: #include <dev/ata/satafisvar.h>
! 46: #include <dev/ata/satafisreg.h>
1.1 bouyer 47: #include <dev/ic/ahcisatavar.h>
48:
1.16 bouyer 49: #include <dev/scsipi/scsi_all.h> /* for SCSI status */
50:
1.8 bouyer 51: #include "atapibus.h"
52:
1.1 bouyer 53: #ifdef AHCI_DEBUG
54: int ahcidebug_mask = 0x0;
55: #endif
56:
1.18.4.1.4.2! matt 57: static void ahci_probe_drive(struct ata_channel *);
! 58: static void ahci_setup_channel(struct ata_channel *);
1.1 bouyer 59:
1.18.4.1.4.2! matt 60: static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *);
! 61: static void ahci_reset_drive(struct ata_drive_datas *, int);
! 62: static void ahci_reset_channel(struct ata_channel *, int);
! 63: static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *);
! 64: static int ahci_ata_addref(struct ata_drive_datas *);
! 65: static void ahci_ata_delref(struct ata_drive_datas *);
! 66: static void ahci_killpending(struct ata_drive_datas *);
! 67:
! 68: static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *);
! 69: static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int);
! 70: static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int);
! 71: static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ;
! 72: static void ahci_bio_start(struct ata_channel *, struct ata_xfer *);
! 73: static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int);
! 74: static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ;
! 75: static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int);
! 76: static void ahci_channel_start(struct ahci_softc *, struct ata_channel *);
! 77: static void ahci_timeout(void *);
! 78: static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int);
1.1 bouyer 79:
1.8 bouyer 80: #if NATAPIBUS > 0
1.18.4.1.4.2! matt 81: static void ahci_atapibus_attach(struct atabus_softc *);
! 82: static void ahci_atapi_kill_pending(struct scsipi_periph *);
! 83: static void ahci_atapi_minphys(struct buf *);
! 84: static void ahci_atapi_scsipi_request(struct scsipi_channel *,
1.8 bouyer 85: scsipi_adapter_req_t, void *);
1.18.4.1.4.2! matt 86: static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *);
! 87: static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int);
! 88: static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int);
! 89: static void ahci_atapi_probe_device(struct atapibus_softc *, int);
1.8 bouyer 90:
91: static const struct scsipi_bustype ahci_atapi_bustype = {
92: SCSIPI_BUSTYPE_ATAPI,
93: atapi_scsipi_cmd,
94: atapi_interpret_sense,
95: atapi_print_addr,
96: ahci_atapi_kill_pending,
97: };
98: #endif /* NATAPIBUS */
99:
1.1 bouyer 100: #define ATA_DELAY 10000 /* 10s for a drive I/O */
1.18.4.1.4.1 matt 101: #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */
102: #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10)
1.1 bouyer 103:
104: const struct ata_bustype ahci_ata_bustype = {
105: SCSIPI_BUSTYPE_ATA,
106: ahci_ata_bio,
107: ahci_reset_drive,
108: ahci_reset_channel,
109: ahci_exec_command,
110: ata_get_params,
111: ahci_ata_addref,
112: ahci_ata_delref,
113: ahci_killpending
114: };
115:
1.18.4.1.4.2! matt 116: static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *);
1.7 joerg 117: static void ahci_setup_port(struct ahci_softc *sc, int i);
118:
1.18.4.1.4.2! matt 119: static void
! 120: ahci_enable(struct ahci_softc *sc)
! 121: {
! 122: uint32_t ghc;
! 123:
! 124: ghc = AHCI_READ(sc, AHCI_GHC);
! 125: if (!(ghc & AHCI_GHC_AE)) {
! 126: ghc |= AHCI_GHC_AE;
! 127: AHCI_WRITE(sc, AHCI_GHC, ghc);
! 128: }
! 129: }
! 130:
! 131: static int
1.7 joerg 132: ahci_reset(struct ahci_softc *sc)
1.1 bouyer 133: {
1.7 joerg 134: int i;
1.1 bouyer 135:
136: /* reset controller */
137: AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR);
138: /* wait up to 1s for reset to complete */
139: for (i = 0; i < 1000; i++) {
1.6 bouyer 140: delay(1000);
1.1 bouyer 141: if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0)
142: break;
143: }
144: if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) {
145: aprint_error("%s: reset failed\n", AHCINAME(sc));
1.7 joerg 146: return -1;
1.1 bouyer 147: }
148: /* enable ahci mode */
1.18.4.1.4.2! matt 149: ahci_enable(sc);
! 150:
! 151: if (sc->sc_save_init_data) {
! 152: AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap);
! 153: if (sc->sc_init_data.cap2)
! 154: AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2);
! 155: AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports);
! 156: }
! 157:
1.7 joerg 158: return 0;
159: }
1.1 bouyer 160:
1.18.4.1.4.2! matt 161: static void
1.7 joerg 162: ahci_setup_ports(struct ahci_softc *sc)
163: {
164: int i, port;
165:
166: for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
1.18.4.1.4.2! matt 167: if ((sc->sc_ahci_ports & (1 << i)) == 0)
1.7 joerg 168: continue;
169: if (port >= sc->sc_atac.atac_nchannels) {
170: aprint_error("%s: more ports than announced\n",
171: AHCINAME(sc));
172: break;
173: }
174: ahci_setup_port(sc, i);
175: }
176: }
177:
1.18.4.1.4.2! matt 178: static void
1.7 joerg 179: ahci_reprobe_drives(struct ahci_softc *sc)
180: {
181: int i, port;
182: struct ahci_channel *achp;
183: struct ata_channel *chp;
184:
185: for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
1.18.4.1.4.2! matt 186: if ((sc->sc_ahci_ports & (1 << i)) == 0)
1.7 joerg 187: continue;
188: if (port >= sc->sc_atac.atac_nchannels) {
189: aprint_error("%s: more ports than announced\n",
190: AHCINAME(sc));
191: break;
192: }
193: achp = &sc->sc_channels[i];
194: chp = &achp->ata_channel;
195:
196: ahci_probe_drive(chp);
197: }
198: }
199:
200: static void
201: ahci_setup_port(struct ahci_softc *sc, int i)
202: {
203: struct ahci_channel *achp;
204:
205: achp = &sc->sc_channels[i];
206:
207: AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh);
1.18.4.1.4.2! matt 208: AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32);
1.7 joerg 209: AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis);
1.18.4.1.4.2! matt 210: AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32);
1.7 joerg 211: }
212:
1.18.4.1.4.2! matt 213: static void
1.7 joerg 214: ahci_enable_intrs(struct ahci_softc *sc)
215: {
216:
217: /* clear interrupts */
218: AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS));
219: /* enable interrupts */
220: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
221: }
222:
223: void
224: ahci_attach(struct ahci_softc *sc)
225: {
1.18.4.1.4.2! matt 226: uint32_t ahci_rev, ahci_cap;
1.7 joerg 227: int i, j, port;
228: struct ahci_channel *achp;
229: struct ata_channel *chp;
230: int error;
231: int dmasize;
1.18.4.1.4.2! matt 232: char buf[128];
1.7 joerg 233: void *cmdhp;
234: void *cmdtblp;
235:
1.18.4.1.4.2! matt 236: if (sc->sc_save_init_data) {
! 237: ahci_enable(sc);
! 238:
! 239: sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP);
! 240: sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI);
! 241:
! 242: ahci_rev = AHCI_READ(sc, AHCI_VS);
! 243: if (AHCI_VS_MJR(ahci_rev) > 1 ||
! 244: (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) {
! 245: sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2);
! 246: } else {
! 247: sc->sc_init_data.cap2 = 0;
! 248: }
! 249: if (sc->sc_init_data.ports == 0) {
! 250: sc->sc_init_data.ports = sc->sc_ahci_ports;
! 251: }
! 252: }
! 253:
1.7 joerg 254: if (ahci_reset(sc) != 0)
255: return;
1.1 bouyer 256:
257: ahci_cap = AHCI_READ(sc, AHCI_CAP);
258: sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1;
259: sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1;
260: ahci_rev = AHCI_READ(sc, AHCI_VS);
1.18.4.1.4.2! matt 261: #define snprintb(a,b,c,d) bitmask_snprintf((d),(c),(a),(b))
! 262: snprintb(buf, sizeof(buf), "\177\020"
! 263: /* "f\000\005NP\0" */
! 264: "b\005SXS\0"
! 265: "b\006EMS\0"
! 266: "b\007CCCS\0"
! 267: /* "f\010\005NCS\0" */
! 268: "b\015PSC\0"
! 269: "b\016SSC\0"
! 270: "b\017PMD\0"
! 271: "b\020FBSS\0"
! 272: "b\021SPM\0"
! 273: "b\022SAM\0"
! 274: "b\023SNZO\0"
! 275: "f\024\003ISS\0"
! 276: "=\001Gen1\0"
! 277: "=\002Gen2\0"
! 278: "=\003Gen3\0"
! 279: "b\030SCLO\0"
! 280: "b\031SAL\0"
! 281: "b\032SALP\0"
! 282: "b\033SSS\0"
! 283: "b\034SMPS\0"
! 284: "b\035SSNTF\0"
! 285: "b\036SNCQ\0"
! 286: "b\037S64A\0"
! 287: "\0", ahci_cap);
! 288: aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u"
! 289: ", %d port%s, %d slot%s, CAP %s\n",
! 290: AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev),
! 291: sc->sc_atac.atac_nchannels,
! 292: (sc->sc_atac.atac_nchannels == 1 ? "" : "s"),
! 293: sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf);
1.1 bouyer 294:
295: sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA;
1.12 xtraeme 296: sc->sc_atac.atac_cap |= sc->sc_atac_capflags;
1.1 bouyer 297: sc->sc_atac.atac_pio_cap = 4;
298: sc->sc_atac.atac_dma_cap = 2;
299: sc->sc_atac.atac_udma_cap = 6;
300: sc->sc_atac.atac_channels = sc->sc_chanarray;
301: sc->sc_atac.atac_probe = ahci_probe_drive;
302: sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype;
303: sc->sc_atac.atac_set_modes = ahci_setup_channel;
1.8 bouyer 304: #if NATAPIBUS > 0
305: sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach;
306: #endif
1.1 bouyer 307:
308: dmasize =
309: (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels;
310: error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
1.18.4.1.4.2! matt 311: &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT);
1.1 bouyer 312: if (error) {
313: aprint_error("%s: unable to allocate command header memory"
314: ", error=%d\n", AHCINAME(sc), error);
315: return;
316: }
1.18.4.1.4.2! matt 317: error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg,
! 318: sc->sc_cmd_hdr_nseg, dmasize,
1.1 bouyer 319: &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
320: if (error) {
321: aprint_error("%s: unable to map command header memory"
322: ", error=%d\n", AHCINAME(sc), error);
323: return;
324: }
325: error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
326: BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd);
327: if (error) {
328: aprint_error("%s: unable to create command header map"
329: ", error=%d\n", AHCINAME(sc), error);
330: return;
331: }
332: error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd,
333: cmdhp, dmasize, NULL, BUS_DMA_NOWAIT);
334: if (error) {
335: aprint_error("%s: unable to load command header map"
336: ", error=%d\n", AHCINAME(sc), error);
337: return;
338: }
339: sc->sc_cmd_hdr = cmdhp;
340:
1.7 joerg 341: ahci_enable_intrs(sc);
1.1 bouyer 342:
1.18.4.1.4.2! matt 343: if (sc->sc_ahci_ports == 0) {
! 344: sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI);
! 345: AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports),
! 346: DEBUG_PROBE);
! 347: }
1.1 bouyer 348: for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
1.18.4.1.4.2! matt 349: if ((sc->sc_ahci_ports & (1 << i)) == 0)
1.1 bouyer 350: continue;
351: if (port >= sc->sc_atac.atac_nchannels) {
352: aprint_error("%s: more ports than announced\n",
353: AHCINAME(sc));
354: break;
355: }
356: achp = &sc->sc_channels[i];
1.18.4.1.4.2! matt 357: chp = &achp->ata_channel;
1.1 bouyer 358: sc->sc_chanarray[i] = chp;
359: chp->ch_channel = i;
360: chp->ch_atac = &sc->sc_atac;
361: chp->ch_queue = malloc(sizeof(struct ata_queue),
362: M_DEVBUF, M_NOWAIT);
363: if (chp->ch_queue == NULL) {
364: aprint_error("%s port %d: can't allocate memory for "
365: "command queue", AHCINAME(sc), i);
366: break;
367: }
368: dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds;
369: error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
1.18.4.1.4.2! matt 370: &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg,
! 371: BUS_DMA_NOWAIT);
1.1 bouyer 372: if (error) {
373: aprint_error("%s: unable to allocate command table "
374: "memory, error=%d\n", AHCINAME(sc), error);
375: break;
376: }
1.18.4.1.4.2! matt 377: error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg,
! 378: achp->ahcic_cmd_tbl_nseg, dmasize,
1.1 bouyer 379: &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
380: if (error) {
381: aprint_error("%s: unable to map command table memory"
382: ", error=%d\n", AHCINAME(sc), error);
383: break;
384: }
385: error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
386: BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld);
387: if (error) {
388: aprint_error("%s: unable to create command table map"
389: ", error=%d\n", AHCINAME(sc), error);
390: break;
391: }
392: error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld,
393: cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT);
394: if (error) {
395: aprint_error("%s: unable to load command table map"
396: ", error=%d\n", AHCINAME(sc), error);
397: break;
398: }
399: achp->ahcic_cmdh = (struct ahci_cmd_header *)
400: ((char *)cmdhp + AHCI_CMDH_SIZE * port);
401: achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
402: AHCI_CMDH_SIZE * port;
403: achp->ahcic_rfis = (struct ahci_r_fis *)
404: ((char *)cmdhp +
405: AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
406: AHCI_RFIS_SIZE * port);
407: achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
408: AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
409: AHCI_RFIS_SIZE * port;
1.18.4.1.4.2! matt 410: AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") "
! 411: "rfis %p (0x%" PRIx64 ")\n", i,
! 412: achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh,
! 413: achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis),
1.1 bouyer 414: DEBUG_PROBE);
415:
416: for (j = 0; j < sc->sc_ncmds; j++) {
417: achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *)
418: ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j);
419: achp->ahcic_bus_cmd_tbl[j] =
420: achp->ahcic_cmd_tbld->dm_segs[0].ds_addr +
421: AHCI_CMDTBL_SIZE * j;
422: achp->ahcic_cmdh[j].cmdh_cmdtba =
1.18.4.1.4.2! matt 423: htole64(achp->ahcic_bus_cmd_tbl[j]);
! 424: AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j,
1.1 bouyer 425: achp->ahcic_cmd_tbl[j],
1.18.4.1.4.2! matt 426: (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE);
1.1 bouyer 427: /* The xfer DMA map */
428: error = bus_dmamap_create(sc->sc_dmat, MAXPHYS,
429: AHCI_NPRD, 0x400000 /* 4MB */, 0,
430: BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
431: &achp->ahcic_datad[j]);
432: if (error) {
433: aprint_error("%s: couldn't alloc xfer DMA map, "
434: "error=%d\n", AHCINAME(sc), error);
435: goto end;
436: }
437: }
1.7 joerg 438: ahci_setup_port(sc, i);
1.1 bouyer 439: chp->ch_ndrive = 1;
440: if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
1.18.4.1.4.2! matt 441: AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) {
1.1 bouyer 442: aprint_error("%s: couldn't map channel %d "
443: "sata_status regs\n", AHCINAME(sc), i);
444: break;
445: }
446: if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
1.18.4.1.4.2! matt 447: AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) {
1.1 bouyer 448: aprint_error("%s: couldn't map channel %d "
449: "sata_control regs\n", AHCINAME(sc), i);
450: break;
451: }
452: if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
1.18.4.1.4.2! matt 453: AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) {
1.1 bouyer 454: aprint_error("%s: couldn't map channel %d "
455: "sata_error regs\n", AHCINAME(sc), i);
456: break;
457: }
458: ata_channel_attach(chp);
459: port++;
460: end:
461: continue;
462: }
463: }
464:
465: int
1.18.4.1.4.2! matt 466: ahci_detach(struct ahci_softc *sc, int flags)
! 467: {
! 468: struct atac_softc *atac;
! 469: struct ahci_channel *achp;
! 470: struct ata_channel *chp;
! 471: struct scsipi_adapter *adapt;
! 472: int i, j;
! 473: int error;
! 474:
! 475: atac = &sc->sc_atac;
! 476: adapt = &atac->atac_atapi_adapter._generic;
! 477:
! 478: for (i = 0; i < AHCI_MAX_PORTS; i++) {
! 479: achp = &sc->sc_channels[i];
! 480: chp = &achp->ata_channel;
! 481:
! 482: if ((sc->sc_ahci_ports & (1 << i)) == 0)
! 483: continue;
! 484: if (i >= sc->sc_atac.atac_nchannels) {
! 485: aprint_error("%s: more ports than announced\n",
! 486: AHCINAME(sc));
! 487: break;
! 488: }
! 489:
! 490: if (chp->atabus == NULL)
! 491: continue;
! 492: if ((error = config_detach(chp->atabus, flags)) != 0)
! 493: return error;
! 494:
! 495: for (j = 0; j < sc->sc_ncmds; j++)
! 496: bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]);
! 497:
! 498: bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld);
! 499: bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld);
! 500: bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0],
! 501: AHCI_CMDTBL_SIZE * sc->sc_ncmds);
! 502: bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg,
! 503: achp->ahcic_cmd_tbl_nseg);
! 504:
! 505: free(chp->ch_queue, M_DEVBUF);
! 506: chp->atabus = NULL;
! 507: }
! 508:
! 509: bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd);
! 510: bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd);
! 511: bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr,
! 512: (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels);
! 513: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg);
! 514:
! 515: if (adapt->adapt_refcnt != 0)
! 516: return EBUSY;
! 517:
! 518: return 0;
! 519: }
! 520:
! 521: void
! 522: ahci_resume(struct ahci_softc *sc)
! 523: {
! 524: ahci_reset(sc);
! 525: ahci_setup_ports(sc);
! 526: ahci_reprobe_drives(sc);
! 527: ahci_enable_intrs(sc);
! 528: }
! 529:
! 530: int
1.1 bouyer 531: ahci_intr(void *v)
532: {
533: struct ahci_softc *sc = v;
1.18.4.1.4.2! matt 534: uint32_t is;
1.1 bouyer 535: int i, r = 0;
536:
537: while ((is = AHCI_READ(sc, AHCI_IS))) {
538: AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is),
539: DEBUG_INTR);
540: r = 1;
541: AHCI_WRITE(sc, AHCI_IS, is);
542: for (i = 0; i < AHCI_MAX_PORTS; i++)
543: if (is & (1 << i))
544: ahci_intr_port(sc, &sc->sc_channels[i]);
545: }
546: return r;
547: }
548:
1.18.4.1.4.2! matt 549: static void
1.1 bouyer 550: ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp)
551: {
1.18.4.1.4.2! matt 552: uint32_t is, tfd;
1.1 bouyer 553: struct ata_channel *chp = &achp->ata_channel;
554: struct ata_xfer *xfer = chp->ch_queue->active_xfer;
555: int slot;
556:
557: is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
558: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is);
559: AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc),
560: chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
561: DEBUG_INTR);
562:
563: if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
564: AHCI_P_IX_OFS | AHCI_P_IX_UFS)) {
565: slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))
566: & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
567: if ((achp->ahcic_cmds_active & (1 << slot)) == 0)
568: return;
569: /* stop channel */
1.5 bouyer 570: ahci_channel_stop(sc, chp, 0);
1.1 bouyer 571: if (slot != 0) {
572: printf("ahci_intr_port: slot %d\n", slot);
573: panic("ahci_intr_port");
574: }
575: if (is & AHCI_P_IX_TFES) {
576: tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
577: chp->ch_error =
578: (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT;
579: chp->ch_status = (tfd & 0xff);
580: } else {
581: /* emulate a CRC error */
582: chp->ch_error = WDCE_CRC;
583: chp->ch_status = WDCS_ERR;
584: }
585: xfer->c_intr(chp, xfer, is);
1.5 bouyer 586: /* if channel has not been restarted, do it now */
587: if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR)
588: == 0)
589: ahci_channel_start(sc, chp);
1.1 bouyer 590: } else {
591: slot = 0; /* XXX */
592: is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
593: AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n",
594: chp->ch_channel, is, achp->ahcic_cmds_active,
595: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR);
596: if ((achp->ahcic_cmds_active & (1 << slot)) == 0)
597: return;
598: if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot))
599: == 0) {
600: xfer->c_intr(chp, xfer, 0);
601: }
602: }
603: }
604:
1.18.4.1.4.2! matt 605: static void
1.1 bouyer 606: ahci_reset_drive(struct ata_drive_datas *drvp, int flags)
607: {
608: struct ata_channel *chp = drvp->chnl_softc;
609: ata_reset_channel(chp, flags);
610: return;
611: }
612:
1.18.4.1.4.2! matt 613: static void
1.1 bouyer 614: ahci_reset_channel(struct ata_channel *chp, int flags)
615: {
616: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
617: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.18 bouyer 618: int i, tfd;
1.1 bouyer 619:
1.5 bouyer 620: ahci_channel_stop(sc, chp, flags);
1.1 bouyer 621: if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
622: achp->ahcic_sstatus) != SStatus_DET_DEV) {
623: printf("%s: port reset failed\n", AHCINAME(sc));
624: /* XXX and then ? */
625: }
626: if (chp->ch_queue->active_xfer) {
627: chp->ch_queue->active_xfer->c_kill_xfer(chp,
628: chp->ch_queue->active_xfer, KILL_RESET);
629: }
1.18.4.1.4.1 matt 630: tsleep(&sc, PRIBIO, "ahcirst", mstohz(500));
631: /* clear port interrupt register */
632: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
633: /* clear SErrors and start operations */
1.1 bouyer 634: ahci_channel_start(sc, chp);
1.18 bouyer 635: /* wait 31s for BSY to clear */
1.18.4.1.4.1 matt 636: for (i = 0; i <AHCI_RST_WAIT; i++) {
1.18 bouyer 637: tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
638: if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT)
639: & WDCS_BSY) == 0)
1.8 bouyer 640: break;
1.18 bouyer 641: tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10));
1.8 bouyer 642: }
1.18.4.1.4.1 matt 643: if (i == AHCI_RST_WAIT)
1.18 bouyer 644: aprint_error("%s: BSY never cleared, TD 0x%x\n",
645: AHCINAME(sc), tfd);
646: AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
647: DEBUG_PROBE);
1.8 bouyer 648: /* clear port interrupt register */
649: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
650:
1.1 bouyer 651: return;
652: }
653:
1.18.4.1.4.2! matt 654: static int
1.1 bouyer 655: ahci_ata_addref(struct ata_drive_datas *drvp)
656: {
657: return 0;
658: }
659:
1.18.4.1.4.2! matt 660: static void
1.1 bouyer 661: ahci_ata_delref(struct ata_drive_datas *drvp)
662: {
663: return;
664: }
665:
1.18.4.1.4.2! matt 666: static void
1.1 bouyer 667: ahci_killpending(struct ata_drive_datas *drvp)
668: {
669: return;
670: }
671:
1.18.4.1.4.2! matt 672: static void
1.1 bouyer 673: ahci_probe_drive(struct ata_channel *chp)
674: {
675: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
676: struct ahci_channel *achp = (struct ahci_channel *)chp;
677: int i, s;
1.18.4.1.4.2! matt 678: uint32_t sig;
1.1 bouyer 679:
680: /* XXX This should be done by other code. */
681: for (i = 0; i < chp->ch_ndrive; i++) {
682: chp->ch_drive[i].chnl_softc = chp;
683: chp->ch_drive[i].drive = i;
684: }
685:
1.18 bouyer 686: /* bring interface up, accept FISs, power up and spin up device */
1.1 bouyer 687: AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1.18 bouyer 688: AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE |
689: AHCI_P_CMD_POD | AHCI_P_CMD_SUD);
1.1 bouyer 690: /* reset the PHY and bring online */
691: switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
692: achp->ahcic_sstatus)) {
693: case SStatus_DET_DEV:
1.18.4.1.4.1 matt 694: tsleep(&sc, PRIBIO, "ahcidv", mstohz(500));
695: /* clear port interrupt register */
696: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
1.18 bouyer 697: /* clear SErrors and start operations */
698: ahci_channel_start(sc, chp);
699: /* wait 31s for BSY to clear */
1.18.4.1.4.1 matt 700: for (i = 0; i <AHCI_RST_WAIT; i++) {
1.18 bouyer 701: sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
702: if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT)
703: & WDCS_BSY) == 0)
1.8 bouyer 704: break;
705: tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10));
706: }
1.18.4.1.4.1 matt 707: if (i == AHCI_RST_WAIT) {
1.18 bouyer 708: aprint_error("%s: BSY never cleared, TD 0x%x\n",
709: AHCINAME(sc), sig);
1.18.4.1.4.1 matt 710: return;
711: }
1.18 bouyer 712: AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
713: DEBUG_PROBE);
1.1 bouyer 714: sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel));
715: AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n",
716: AHCINAME(sc), chp->ch_channel, sig,
717: AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE);
718: /*
719: * scnt and sn are supposed to be 0x1 for ATAPI, but in some
720: * cases we get wrong values here, so ignore it.
721: */
722: s = splbio();
1.3 bouyer 723: if ((sig & 0xffff0000) == 0xeb140000) {
1.8 bouyer 724: chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
1.3 bouyer 725: } else
1.1 bouyer 726: chp->ch_drive[0].drive_flags |= DRIVE_ATA;
727: splx(s);
1.18.4.1.4.1 matt 728: /* clear port interrupt register */
729: AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
730: /* and enable interrupts */
1.1 bouyer 731: AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel),
732: AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
733: AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS |
734: AHCI_P_IX_DHRS);
1.17 dillo 735: /* wait 500ms before actually starting operations */
736: tsleep(&sc, PRIBIO, "ahciprb", mstohz(500));
1.1 bouyer 737: break;
738:
739: default:
740: break;
741: }
742: }
743:
1.18.4.1.4.2! matt 744: static void
1.1 bouyer 745: ahci_setup_channel(struct ata_channel *chp)
746: {
747: return;
748: }
749:
1.18.4.1.4.2! matt 750: static int
1.1 bouyer 751: ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c)
752: {
753: struct ata_channel *chp = drvp->chnl_softc;
754: struct ata_xfer *xfer;
755: int ret;
756: int s;
757:
758: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
759: AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n",
760: chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
761: DEBUG_XFERS);
762: xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP :
763: ATAXF_NOSLEEP);
764: if (xfer == NULL) {
765: return ATACMD_TRY_AGAIN;
766: }
767: if (ata_c->flags & AT_POLL)
768: xfer->c_flags |= C_POLL;
769: if (ata_c->flags & AT_WAIT)
770: xfer->c_flags |= C_WAIT;
771: xfer->c_drive = drvp->drive;
772: xfer->c_databuf = ata_c->data;
773: xfer->c_bcount = ata_c->bcount;
774: xfer->c_cmd = ata_c;
775: xfer->c_start = ahci_cmd_start;
776: xfer->c_intr = ahci_cmd_complete;
777: xfer->c_kill_xfer = ahci_cmd_kill_xfer;
778: s = splbio();
779: ata_exec_xfer(chp, xfer);
780: #ifdef DIAGNOSTIC
781: if ((ata_c->flags & AT_POLL) != 0 &&
782: (ata_c->flags & AT_DONE) == 0)
783: panic("ahci_exec_command: polled command not done");
784: #endif
785: if (ata_c->flags & AT_DONE) {
786: ret = ATACMD_COMPLETE;
787: } else {
788: if (ata_c->flags & AT_WAIT) {
789: while ((ata_c->flags & AT_DONE) == 0) {
790: tsleep(ata_c, PRIBIO, "ahcicmd", 0);
791: }
792: ret = ATACMD_COMPLETE;
793: } else {
794: ret = ATACMD_QUEUED;
795: }
796: }
797: splx(s);
798: return ret;
799: }
800:
1.18.4.1.4.2! matt 801: static void
1.1 bouyer 802: ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer)
803: {
804: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
805: struct ahci_channel *achp = (struct ahci_channel *)chp;
806: struct ata_command *ata_c = xfer->c_cmd;
807: int slot = 0 /* XXX slot */;
808: struct ahci_cmd_tbl *cmd_tbl;
809: struct ahci_cmd_header *cmd_h;
810: int i;
811: int channel = chp->ch_channel;
812:
813: AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n",
814: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
815:
816: cmd_tbl = achp->ahcic_cmd_tbl[slot];
817: AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
818: cmd_tbl), DEBUG_XFERS);
819:
1.18.4.1.4.2! matt 820: satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis);
1.1 bouyer 821:
822: cmd_h = &achp->ahcic_cmdh[slot];
823: AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
824: chp->ch_channel, cmd_h), DEBUG_XFERS);
825: if (ahci_dma_setup(chp, slot,
1.18.4.1.4.2! matt 826: (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ?
! 827: ata_c->data : NULL,
1.1 bouyer 828: ata_c->bcount,
829: (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
830: ata_c->flags |= AT_DF;
831: ahci_cmd_complete(chp, xfer, slot);
832: return;
833: }
834: cmd_h->cmdh_flags = htole16(
835: ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) |
1.18.4.1.4.2! matt 836: RHD_FISLEN / 4);
1.1 bouyer 837: cmd_h->cmdh_prdbc = 0;
838: AHCI_CMDH_SYNC(sc, achp, slot,
839: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
840:
841: if (ata_c->flags & AT_POLL) {
842: /* polled command, disable interrupts */
843: AHCI_WRITE(sc, AHCI_GHC,
844: AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
845: }
846: chp->ch_flags |= ATACH_IRQ_WAIT;
1.5 bouyer 847: chp->ch_status = 0;
1.1 bouyer 848: /* start command */
849: AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
850: /* and says we started this command */
851: achp->ahcic_cmds_active |= 1 << slot;
852:
853: if ((ata_c->flags & AT_POLL) == 0) {
854: chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
855: callout_reset(&chp->ch_callout, mstohz(ata_c->timeout),
856: ahci_timeout, chp);
857: return;
858: }
859: /*
860: * Polled command.
861: */
862: for (i = 0; i < ata_c->timeout / 10; i++) {
863: if (ata_c->flags & AT_DONE)
864: break;
865: ahci_intr_port(sc, achp);
866: if (ata_c->flags & AT_WAIT)
867: tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10));
868: else
869: delay(10000);
870: }
871: AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
872: AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
873: AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
874: AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
875: AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
876: DEBUG_XFERS);
877: if ((ata_c->flags & AT_DONE) == 0) {
878: ata_c->flags |= AT_TIMEOU;
879: ahci_cmd_complete(chp, xfer, slot);
880: }
881: /* reenable interrupts */
882: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
883: }
884:
1.18.4.1.4.2! matt 885: static void
1.1 bouyer 886: ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
887: {
888: struct ata_command *ata_c = xfer->c_cmd;
889: AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel),
890: DEBUG_FUNCS);
891:
892: switch (reason) {
893: case KILL_GONE:
894: ata_c->flags |= AT_GONE;
895: break;
896: case KILL_RESET:
897: ata_c->flags |= AT_RESET;
898: break;
899: default:
900: printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason);
901: panic("ahci_cmd_kill_xfer");
902: }
903: ahci_cmd_done(chp, xfer, 0 /* XXX slot */);
904: }
905:
1.18.4.1.4.2! matt 906: static int
1.1 bouyer 907: ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is)
908: {
909: int slot = 0; /* XXX slot */
910: struct ata_command *ata_c = xfer->c_cmd;
911: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1.18.4.1.4.2! matt 912: struct ahci_channel *achp = (struct ahci_channel *)chp;
1.1 bouyer 913:
914: AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n",
915: chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)),
916: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
917: DEBUG_FUNCS);
918: chp->ch_flags &= ~ATACH_IRQ_WAIT;
919: if (xfer->c_flags & C_TIMEOU) {
920: ata_c->flags |= AT_TIMEOU;
921: } else
922: callout_stop(&chp->ch_callout);
923:
924: chp->ch_queue->active_xfer = NULL;
925:
926: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) {
927: ahci_cmd_kill_xfer(chp, xfer, KILL_GONE);
928: chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN;
929: wakeup(&chp->ch_queue->active_xfer);
930: return 0;
931: }
1.18.4.1.4.2! matt 932:
! 933: if (chp->ch_status & WDCS_BSY) {
! 934: ata_c->flags |= AT_TIMEOU;
! 935: } else if (chp->ch_status & WDCS_ERR) {
! 936: ata_c->r_error = chp->ch_error;
! 937: ata_c->flags |= AT_ERROR;
1.1 bouyer 938: }
1.18.4.1.4.2! matt 939:
! 940: if (ata_c->flags & AT_READREG)
! 941: satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis);
! 942:
1.1 bouyer 943: ahci_cmd_done(chp, xfer, slot);
944: return 0;
945: }
946:
1.18.4.1.4.2! matt 947: static void
1.1 bouyer 948: ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot)
949: {
950: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
951: struct ahci_channel *achp = (struct ahci_channel *)chp;
952: struct ata_command *ata_c = xfer->c_cmd;
1.18.4.1.4.2! matt 953: uint16_t *idwordbuf;
! 954: int i;
1.1 bouyer 955:
956: AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel),
957: DEBUG_FUNCS);
958:
959: /* this comamnd is not active any more */
960: achp->ahcic_cmds_active &= ~(1 << slot);
961:
1.18.4.1.4.2! matt 962: if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) {
1.1 bouyer 963: bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
964: achp->ahcic_datad[slot]->dm_mapsize,
965: (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD :
966: BUS_DMASYNC_POSTWRITE);
967: bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
968: }
969:
1.2 fvdl 970: AHCI_CMDH_SYNC(sc, achp, slot,
971: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
972:
1.18.4.1.4.2! matt 973: /* ata(4) expects IDENTIFY data to be in host endianess */
! 974: if (ata_c->r_command == WDCC_IDENTIFY ||
! 975: ata_c->r_command == ATAPI_IDENTIFY_DEVICE) {
! 976: idwordbuf = xfer->c_databuf;
! 977: for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) {
! 978: idwordbuf[i] = le16toh(idwordbuf[i]);
! 979: }
! 980: }
! 981:
1.1 bouyer 982: ata_c->flags |= AT_DONE;
983: if (achp->ahcic_cmdh[slot].cmdh_prdbc)
984: ata_c->flags |= AT_XFDONE;
985:
986: ata_free_xfer(chp, xfer);
987: if (ata_c->flags & AT_WAIT)
988: wakeup(ata_c);
989: else if (ata_c->callback)
990: ata_c->callback(ata_c->callback_arg);
991: atastart(chp);
992: return;
993: }
994:
1.18.4.1.4.2! matt 995: static int
1.1 bouyer 996: ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio)
997: {
998: struct ata_channel *chp = drvp->chnl_softc;
999: struct ata_xfer *xfer;
1000:
1001: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1002: AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n",
1003: chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
1004: DEBUG_XFERS);
1005: xfer = ata_get_xfer(ATAXF_NOSLEEP);
1006: if (xfer == NULL) {
1007: return ATACMD_TRY_AGAIN;
1008: }
1009: if (ata_bio->flags & ATA_POLL)
1010: xfer->c_flags |= C_POLL;
1011: xfer->c_drive = drvp->drive;
1012: xfer->c_cmd = ata_bio;
1013: xfer->c_databuf = ata_bio->databuf;
1014: xfer->c_bcount = ata_bio->bcount;
1015: xfer->c_start = ahci_bio_start;
1016: xfer->c_intr = ahci_bio_complete;
1017: xfer->c_kill_xfer = ahci_bio_kill_xfer;
1018: ata_exec_xfer(chp, xfer);
1019: return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED;
1020: }
1021:
1.18.4.1.4.2! matt 1022: static void
1.1 bouyer 1023: ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer)
1024: {
1025: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1026: struct ahci_channel *achp = (struct ahci_channel *)chp;
1027: struct ata_bio *ata_bio = xfer->c_cmd;
1028: int slot = 0 /* XXX slot */;
1029: struct ahci_cmd_tbl *cmd_tbl;
1030: struct ahci_cmd_header *cmd_h;
1.18.4.1.4.2! matt 1031: int i;
1.1 bouyer 1032: int channel = chp->ch_channel;
1033:
1034: AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n",
1035: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
1036:
1037: cmd_tbl = achp->ahcic_cmd_tbl[slot];
1038: AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
1039: cmd_tbl), DEBUG_XFERS);
1040:
1.18.4.1.4.2! matt 1041: satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis);
1.1 bouyer 1042:
1043: cmd_h = &achp->ahcic_cmdh[slot];
1044: AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
1045: chp->ch_channel, cmd_h), DEBUG_XFERS);
1046: if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount,
1047: (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
1048: ata_bio->error = ERR_DMA;
1049: ata_bio->r_error = 0;
1050: ahci_bio_complete(chp, xfer, slot);
1051: return;
1052: }
1053: cmd_h->cmdh_flags = htole16(
1054: ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) |
1.18.4.1.4.2! matt 1055: RHD_FISLEN / 4);
1.1 bouyer 1056: cmd_h->cmdh_prdbc = 0;
1.2 fvdl 1057: AHCI_CMDH_SYNC(sc, achp, slot,
1058: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1.1 bouyer 1059:
1060: if (xfer->c_flags & C_POLL) {
1061: /* polled command, disable interrupts */
1062: AHCI_WRITE(sc, AHCI_GHC,
1063: AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
1064: }
1065: chp->ch_flags |= ATACH_IRQ_WAIT;
1.5 bouyer 1066: chp->ch_status = 0;
1.1 bouyer 1067: /* start command */
1068: AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
1069: /* and says we started this command */
1070: achp->ahcic_cmds_active |= 1 << slot;
1071:
1072: if ((xfer->c_flags & C_POLL) == 0) {
1073: chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
1074: callout_reset(&chp->ch_callout, mstohz(ATA_DELAY),
1075: ahci_timeout, chp);
1076: return;
1077: }
1078: /*
1079: * Polled command.
1080: */
1081: for (i = 0; i < ATA_DELAY / 10; i++) {
1082: if (ata_bio->flags & ATA_ITSDONE)
1083: break;
1084: ahci_intr_port(sc, achp);
1085: if (ata_bio->flags & ATA_NOSLEEP)
1086: delay(10000);
1087: else
1088: tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10));
1089: }
1090: AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
1091: AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
1092: AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
1093: AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
1094: AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
1095: DEBUG_XFERS);
1096: if ((ata_bio->flags & ATA_ITSDONE) == 0) {
1097: ata_bio->error = TIMEOUT;
1098: ahci_bio_complete(chp, xfer, slot);
1099: }
1100: /* reenable interrupts */
1101: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
1102: }
1103:
1.18.4.1.4.2! matt 1104: static void
1.1 bouyer 1105: ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
1106: {
1107: int slot = 0; /* XXX slot */
1108: int drive = xfer->c_drive;
1109: struct ata_bio *ata_bio = xfer->c_cmd;
1110: struct ahci_channel *achp = (struct ahci_channel *)chp;
1111: AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel),
1112: DEBUG_FUNCS);
1113:
1114: achp->ahcic_cmds_active &= ~(1 << slot);
1115: ata_free_xfer(chp, xfer);
1116: ata_bio->flags |= ATA_ITSDONE;
1117: switch (reason) {
1118: case KILL_GONE:
1119: ata_bio->error = ERR_NODEV;
1120: break;
1121: case KILL_RESET:
1122: ata_bio->error = ERR_RESET;
1123: break;
1124: default:
1125: printf("ahci_bio_kill_xfer: unknown reason %d\n", reason);
1126: panic("ahci_bio_kill_xfer");
1127: }
1128: ata_bio->r_error = WDCE_ABRT;
1129: (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
1130: }
1131:
1.18.4.1.4.2! matt 1132: static int
1.1 bouyer 1133: ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is)
1134: {
1135: int slot = 0; /* XXX slot */
1136: struct ata_bio *ata_bio = xfer->c_cmd;
1137: int drive = xfer->c_drive;
1138: struct ahci_channel *achp = (struct ahci_channel *)chp;
1139: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1140:
1141: AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel),
1142: DEBUG_FUNCS);
1143:
1144: achp->ahcic_cmds_active &= ~(1 << slot);
1145: chp->ch_flags &= ~ATACH_IRQ_WAIT;
1.5 bouyer 1146: if (xfer->c_flags & C_TIMEOU) {
1147: ata_bio->error = TIMEOUT;
1148: } else {
1149: callout_stop(&chp->ch_callout);
1.18.4.1 snj 1150: ata_bio->error = NOERROR;
1.5 bouyer 1151: }
1.1 bouyer 1152:
1153: chp->ch_queue->active_xfer = NULL;
1154: bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1155: achp->ahcic_datad[slot]->dm_mapsize,
1156: (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD :
1157: BUS_DMASYNC_POSTWRITE);
1158: bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
1159:
1160: if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) {
1161: ahci_bio_kill_xfer(chp, xfer, KILL_GONE);
1162: chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN;
1163: wakeup(&chp->ch_queue->active_xfer);
1164: return 0;
1165: }
1166: ata_free_xfer(chp, xfer);
1167: ata_bio->flags |= ATA_ITSDONE;
1168: if (chp->ch_status & WDCS_DWF) {
1169: ata_bio->error = ERR_DF;
1170: } else if (chp->ch_status & WDCS_ERR) {
1171: ata_bio->error = ERROR;
1172: ata_bio->r_error = chp->ch_error;
1173: } else if (chp->ch_status & WDCS_CORR)
1174: ata_bio->flags |= ATA_CORR;
1175:
1176: AHCI_CMDH_SYNC(sc, achp, slot,
1177: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1178: AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld",
1179: ata_bio->bcount), DEBUG_XFERS);
1.18.4.1 snj 1180: /*
1181: * if it was a write, complete data buffer may have been transfered
1182: * before error detection; in this case don't use cmdh_prdbc
1183: * as it won't reflect what was written to media. Assume nothing
1184: * was transfered and leave bcount as-is.
1185: */
1186: if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR)
1187: ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc);
1.1 bouyer 1188: AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS);
1189: (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
1190: atastart(chp);
1191: return 0;
1192: }
1193:
1.18.4.1.4.2! matt 1194: static void
1.5 bouyer 1195: ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags)
1196: {
1197: int i;
1198: /* stop channel */
1199: AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1200: AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST);
1201: /* wait 1s for channel to stop */
1202: for (i = 0; i <100; i++) {
1203: if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR)
1204: == 0)
1205: break;
1206: if (flags & AT_WAIT)
1207: tsleep(&sc, PRIBIO, "ahcirst", mstohz(10));
1208: else
1209: delay(10000);
1210: }
1211: if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) {
1212: printf("%s: channel wouldn't stop\n", AHCINAME(sc));
1213: /* XXX controller reset ? */
1214: return;
1215: }
1.18.4.1.4.2! matt 1216:
! 1217: if (sc->sc_channel_stop)
! 1218: sc->sc_channel_stop(sc, chp);
1.5 bouyer 1219: }
1220:
1.18.4.1.4.2! matt 1221: static void
1.1 bouyer 1222: ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp)
1223: {
1224: /* clear error */
1.18 bouyer 1225: AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel),
1226: AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel)));
1.1 bouyer 1227:
1.18.4.1.4.2! matt 1228: if (sc->sc_channel_start)
! 1229: sc->sc_channel_start(sc, chp);
! 1230:
1.1 bouyer 1231: /* and start controller */
1232: AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1233: AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1234: AHCI_P_CMD_FRE | AHCI_P_CMD_ST);
1235: }
1236:
1.18.4.1.4.2! matt 1237: static void
1.1 bouyer 1238: ahci_timeout(void *v)
1239: {
1240: struct ata_channel *chp = (struct ata_channel *)v;
1241: struct ata_xfer *xfer = chp->ch_queue->active_xfer;
1.18.4.1.4.2! matt 1242: #ifdef AHCI_DEBUG
! 1243: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
! 1244: #endif
1.1 bouyer 1245: int s = splbio();
1.18.4.1.4.2! matt 1246: AHCIDEBUG_PRINT(("ahci_timeout xfer %p intr %#x ghc %08x is %08x\n", xfer, AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)), AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS)), DEBUG_INTR);
! 1247:
1.1 bouyer 1248: if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) {
1249: xfer->c_flags |= C_TIMEOU;
1250: xfer->c_intr(chp, xfer, 0);
1251: }
1252: splx(s);
1253: }
1254:
1.18.4.1.4.2! matt 1255: static int
1.1 bouyer 1256: ahci_dma_setup(struct ata_channel *chp, int slot, void *data,
1257: size_t count, int op)
1258: {
1259: int error, seg;
1260: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1261: struct ahci_channel *achp = (struct ahci_channel *)chp;
1262: struct ahci_cmd_tbl *cmd_tbl;
1263: struct ahci_cmd_header *cmd_h;
1264:
1265: cmd_h = &achp->ahcic_cmdh[slot];
1266: cmd_tbl = achp->ahcic_cmd_tbl[slot];
1267:
1268: if (data == NULL) {
1269: cmd_h->cmdh_prdtl = 0;
1270: goto end;
1271: }
1272:
1273: error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot],
1274: data, count, NULL,
1275: BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op);
1276: if (error) {
1277: printf("%s port %d: failed to load xfer: %d\n",
1278: AHCINAME(sc), chp->ch_channel, error);
1279: return error;
1280: }
1281: bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1282: achp->ahcic_datad[slot]->dm_mapsize,
1283: (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1284: for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) {
1.18.4.1.4.2! matt 1285: cmd_tbl->cmdt_prd[seg].prd_dba = htole64(
1.1 bouyer 1286: achp->ahcic_datad[slot]->dm_segs[seg].ds_addr);
1287: cmd_tbl->cmdt_prd[seg].prd_dbc = htole32(
1288: achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1);
1289: }
1290: cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC);
1291: cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs);
1292: end:
1293: AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE);
1294: return 0;
1295: }
1.8 bouyer 1296:
1297: #if NATAPIBUS > 0
1.18.4.1.4.2! matt 1298: static void
1.8 bouyer 1299: ahci_atapibus_attach(struct atabus_softc * ata_sc)
1300: {
1301: struct ata_channel *chp = ata_sc->sc_chan;
1302: struct atac_softc *atac = chp->ch_atac;
1303: struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
1304: struct scsipi_channel *chan = &chp->ch_atapi_channel;
1305: /*
1306: * Fill in the scsipi_adapter.
1307: */
1.13 cube 1308: adapt->adapt_dev = atac->atac_dev;
1.8 bouyer 1309: adapt->adapt_nchannels = atac->atac_nchannels;
1310: adapt->adapt_request = ahci_atapi_scsipi_request;
1311: adapt->adapt_minphys = ahci_atapi_minphys;
1312: atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device;
1313:
1314: /*
1315: * Fill in the scsipi_channel.
1316: */
1317: memset(chan, 0, sizeof(*chan));
1318: chan->chan_adapter = adapt;
1319: chan->chan_bustype = &ahci_atapi_bustype;
1320: chan->chan_channel = chp->ch_channel;
1321: chan->chan_flags = SCSIPI_CHAN_OPENINGS;
1322: chan->chan_openings = 1;
1323: chan->chan_max_periph = 1;
1324: chan->chan_ntargets = 1;
1325: chan->chan_nluns = 1;
1.13 cube 1326: chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan,
1.8 bouyer 1327: atapiprint);
1328: }
1329:
1.18.4.1.4.2! matt 1330: static void
1.8 bouyer 1331: ahci_atapi_minphys(struct buf *bp)
1332: {
1333: if (bp->b_bcount > MAXPHYS)
1334: bp->b_bcount = MAXPHYS;
1335: minphys(bp);
1336: }
1337:
1338: /*
1339: * Kill off all pending xfers for a periph.
1340: *
1341: * Must be called at splbio().
1342: */
1.18.4.1.4.2! matt 1343: static void
1.8 bouyer 1344: ahci_atapi_kill_pending(struct scsipi_periph *periph)
1345: {
1346: struct atac_softc *atac =
1.13 cube 1347: device_private(periph->periph_channel->chan_adapter->adapt_dev);
1.8 bouyer 1348: struct ata_channel *chp =
1349: atac->atac_channels[periph->periph_channel->chan_channel];
1350:
1351: ata_kill_pending(&chp->ch_drive[periph->periph_target]);
1352: }
1353:
1.18.4.1.4.2! matt 1354: static void
1.8 bouyer 1355: ahci_atapi_scsipi_request(struct scsipi_channel *chan,
1356: scsipi_adapter_req_t req, void *arg)
1357: {
1358: struct scsipi_adapter *adapt = chan->chan_adapter;
1359: struct scsipi_periph *periph;
1360: struct scsipi_xfer *sc_xfer;
1.13 cube 1361: struct ahci_softc *sc = device_private(adapt->adapt_dev);
1.8 bouyer 1362: struct atac_softc *atac = &sc->sc_atac;
1363: struct ata_xfer *xfer;
1364: int channel = chan->chan_channel;
1365: int drive, s;
1366:
1367: switch (req) {
1368: case ADAPTER_REQ_RUN_XFER:
1369: sc_xfer = arg;
1370: periph = sc_xfer->xs_periph;
1371: drive = periph->periph_target;
1.13 cube 1372: if (!device_is_active(atac->atac_dev)) {
1.8 bouyer 1373: sc_xfer->error = XS_DRIVER_STUFFUP;
1374: scsipi_done(sc_xfer);
1375: return;
1376: }
1377: xfer = ata_get_xfer(ATAXF_NOSLEEP);
1378: if (xfer == NULL) {
1379: sc_xfer->error = XS_RESOURCE_SHORTAGE;
1380: scsipi_done(sc_xfer);
1381: return;
1382: }
1383:
1384: if (sc_xfer->xs_control & XS_CTL_POLL)
1385: xfer->c_flags |= C_POLL;
1386: xfer->c_drive = drive;
1387: xfer->c_flags |= C_ATAPI;
1388: xfer->c_cmd = sc_xfer;
1389: xfer->c_databuf = sc_xfer->data;
1390: xfer->c_bcount = sc_xfer->datalen;
1391: xfer->c_start = ahci_atapi_start;
1392: xfer->c_intr = ahci_atapi_complete;
1393: xfer->c_kill_xfer = ahci_atapi_kill_xfer;
1394: xfer->c_dscpoll = 0;
1395: s = splbio();
1396: ata_exec_xfer(atac->atac_channels[channel], xfer);
1397: #ifdef DIAGNOSTIC
1398: if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 &&
1399: (sc_xfer->xs_status & XS_STS_DONE) == 0)
1400: panic("ahci_atapi_scsipi_request: polled command "
1401: "not done");
1402: #endif
1403: splx(s);
1404: return;
1405: default:
1406: /* Not supported, nothing to do. */
1407: ;
1408: }
1409: }
1410:
1.18.4.1.4.2! matt 1411: static void
1.8 bouyer 1412: ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer)
1413: {
1414: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1415: struct ahci_channel *achp = (struct ahci_channel *)chp;
1416: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1417: int slot = 0 /* XXX slot */;
1418: struct ahci_cmd_tbl *cmd_tbl;
1419: struct ahci_cmd_header *cmd_h;
1420: int i;
1421: int channel = chp->ch_channel;
1422:
1423: AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n",
1424: AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
1425:
1426: cmd_tbl = achp->ahcic_cmd_tbl[slot];
1427: AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
1428: cmd_tbl), DEBUG_XFERS);
1429:
1.18.4.1.4.2! matt 1430: satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis);
1.8 bouyer 1431: memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd));
1432: memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen);
1433:
1434: cmd_h = &achp->ahcic_cmdh[slot];
1435: AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
1436: chp->ch_channel, cmd_h), DEBUG_XFERS);
1437: if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL,
1438: sc_xfer->datalen,
1439: (sc_xfer->xs_control & XS_CTL_DATA_IN) ?
1440: BUS_DMA_READ : BUS_DMA_WRITE)) {
1441: sc_xfer->error = XS_DRIVER_STUFFUP;
1442: ahci_atapi_complete(chp, xfer, slot);
1443: return;
1444: }
1445: cmd_h->cmdh_flags = htole16(
1446: ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) |
1.18.4.1.4.2! matt 1447: RHD_FISLEN / 4 | AHCI_CMDH_F_A);
1.8 bouyer 1448: cmd_h->cmdh_prdbc = 0;
1449: AHCI_CMDH_SYNC(sc, achp, slot,
1450: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1451:
1452: if (xfer->c_flags & C_POLL) {
1453: /* polled command, disable interrupts */
1454: AHCI_WRITE(sc, AHCI_GHC,
1455: AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
1456: }
1457: chp->ch_flags |= ATACH_IRQ_WAIT;
1458: chp->ch_status = 0;
1459: /* start command */
1460: AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
1461: /* and says we started this command */
1462: achp->ahcic_cmds_active |= 1 << slot;
1463:
1464: if ((xfer->c_flags & C_POLL) == 0) {
1465: chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
1466: callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout),
1467: ahci_timeout, chp);
1468: return;
1469: }
1470: /*
1471: * Polled command.
1472: */
1473: for (i = 0; i < ATA_DELAY / 10; i++) {
1474: if (sc_xfer->xs_status & XS_STS_DONE)
1475: break;
1476: ahci_intr_port(sc, achp);
1477: delay(10000);
1478: }
1479: AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
1480: AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
1481: AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
1482: AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
1483: AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
1484: DEBUG_XFERS);
1485: if ((sc_xfer->xs_status & XS_STS_DONE) == 0) {
1486: sc_xfer->error = XS_TIMEOUT;
1487: ahci_atapi_complete(chp, xfer, slot);
1488: }
1489: /* reenable interrupts */
1490: AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
1491: }
1492:
1.18.4.1.4.2! matt 1493: static int
1.8 bouyer 1494: ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
1495: {
1496: int slot = 0; /* XXX slot */
1497: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1498: int drive = xfer->c_drive;
1499: struct ahci_channel *achp = (struct ahci_channel *)chp;
1500: struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1501:
1502: AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel),
1503: DEBUG_FUNCS);
1504:
1505: achp->ahcic_cmds_active &= ~(1 << slot);
1506: chp->ch_flags &= ~ATACH_IRQ_WAIT;
1507: if (xfer->c_flags & C_TIMEOU) {
1508: sc_xfer->error = XS_TIMEOUT;
1509: } else {
1510: callout_stop(&chp->ch_callout);
1511: sc_xfer->error = 0;
1512: }
1513:
1514: chp->ch_queue->active_xfer = NULL;
1515: bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1516: achp->ahcic_datad[slot]->dm_mapsize,
1517: (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD :
1518: BUS_DMASYNC_POSTWRITE);
1519: bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
1520:
1521: if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) {
1522: ahci_atapi_kill_xfer(chp, xfer, KILL_GONE);
1523: chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN;
1524: wakeup(&chp->ch_queue->active_xfer);
1525: return 0;
1526: }
1527: ata_free_xfer(chp, xfer);
1528:
1529: AHCI_CMDH_SYNC(sc, achp, slot,
1530: BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1531: sc_xfer->resid = sc_xfer->datalen;
1532: sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc);
1533: AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n",
1534: sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS);
1.16 bouyer 1535: if (chp->ch_status & WDCS_ERR &&
1536: ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 ||
1537: sc_xfer->resid == sc_xfer->datalen)) {
1538: sc_xfer->error = XS_SHORTSENSE;
1539: sc_xfer->sense.atapi_sense = chp->ch_error;
1540: if ((sc_xfer->xs_periph->periph_quirks &
1541: PQUIRK_NOSENSE) == 0) {
1542: /* ask scsipi to send a REQUEST_SENSE */
1543: sc_xfer->error = XS_BUSY;
1544: sc_xfer->status = SCSI_CHECK;
1545: }
1546: }
1.8 bouyer 1547: scsipi_done(sc_xfer);
1548: atastart(chp);
1549: return 0;
1550: }
1551:
1.18.4.1.4.2! matt 1552: static void
1.8 bouyer 1553: ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
1554: {
1555: struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1556: struct ahci_channel *achp = (struct ahci_channel *)chp;
1557: int slot = 0; /* XXX slot */
1558:
1559: achp->ahcic_cmds_active &= ~(1 << slot);
1560:
1561: /* remove this command from xfer queue */
1562: switch (reason) {
1563: case KILL_GONE:
1564: sc_xfer->error = XS_DRIVER_STUFFUP;
1565: break;
1566: case KILL_RESET:
1567: sc_xfer->error = XS_RESET;
1568: break;
1569: default:
1570: printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason);
1571: panic("ahci_ata_atapi_kill_xfer");
1572: }
1573: ata_free_xfer(chp, xfer);
1574: scsipi_done(sc_xfer);
1575: }
1576:
1.18.4.1.4.2! matt 1577: static void
1.8 bouyer 1578: ahci_atapi_probe_device(struct atapibus_softc *sc, int target)
1579: {
1580: struct scsipi_channel *chan = sc->sc_channel;
1581: struct scsipi_periph *periph;
1582: struct ataparams ids;
1583: struct ataparams *id = &ids;
1.13 cube 1584: struct ahci_softc *ahcic =
1585: device_private(chan->chan_adapter->adapt_dev);
1.8 bouyer 1586: struct atac_softc *atac = &ahcic->sc_atac;
1587: struct ata_channel *chp = atac->atac_channels[chan->chan_channel];
1588: struct ata_drive_datas *drvp = &chp->ch_drive[target];
1589: struct scsipibus_attach_args sa;
1590: char serial_number[21], model[41], firmware_revision[9];
1591: int s;
1592:
1593: /* skip if already attached */
1594: if (scsipi_lookup_periph(chan, target, 0) != NULL)
1595: return;
1596:
1597: /* if no ATAPI device detected at attach time, skip */
1598: if ((drvp->drive_flags & DRIVE_ATAPI) == 0) {
1599: AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d "
1600: "not present\n", target), DEBUG_PROBE);
1601: return;
1602: }
1603:
1604: /* Some ATAPI devices need a bit more time after software reset. */
1605: delay(5000);
1606: if (ata_get_params(drvp, AT_WAIT, id) == 0) {
1607: #ifdef ATAPI_DEBUG_PROBE
1608: printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n",
1.14 cube 1609: AHCINAME(ahcic), target,
1.8 bouyer 1610: id->atap_config & ATAPI_CFG_CMD_MASK,
1611: id->atap_config & ATAPI_CFG_DRQ_MASK);
1612: #endif
1613: periph = scsipi_alloc_periph(M_NOWAIT);
1614: if (periph == NULL) {
1.14 cube 1615: aprint_error_dev(sc->sc_dev,
1616: "unable to allocate periph for drive %d\n",
1617: target);
1.8 bouyer 1618: return;
1619: }
1620: periph->periph_dev = NULL;
1621: periph->periph_channel = chan;
1622: periph->periph_switch = &atapi_probe_periphsw;
1623: periph->periph_target = target;
1624: periph->periph_lun = 0;
1625: periph->periph_quirks = PQUIRK_ONLYBIG;
1626:
1627: #ifdef SCSIPI_DEBUG
1628: if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI &&
1629: SCSIPI_DEBUG_TARGET == target)
1630: periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS;
1631: #endif
1632: periph->periph_type = ATAPI_CFG_TYPE(id->atap_config);
1633: if (id->atap_config & ATAPI_CFG_REMOV)
1634: periph->periph_flags |= PERIPH_REMOVABLE;
1635: if (periph->periph_type == T_SEQUENTIAL) {
1636: s = splbio();
1637: drvp->drive_flags |= DRIVE_ATAPIST;
1638: splx(s);
1639: }
1640:
1641: sa.sa_periph = periph;
1642: sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config);
1643: sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ?
1644: T_REMOV : T_FIXED;
1645: scsipi_strvis((u_char *)model, 40, id->atap_model, 40);
1646: scsipi_strvis((u_char *)serial_number, 20, id->atap_serial,
1647: 20);
1648: scsipi_strvis((u_char *)firmware_revision, 8,
1649: id->atap_revision, 8);
1650: sa.sa_inqbuf.vendor = model;
1651: sa.sa_inqbuf.product = serial_number;
1652: sa.sa_inqbuf.revision = firmware_revision;
1653:
1654: /*
1655: * Determine the operating mode capabilities of the device.
1656: */
1657: if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16)
1658: periph->periph_cap |= PERIPH_CAP_CMD16;
1659: /* XXX This is gross. */
1660: periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK);
1661:
1662: drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa);
1663:
1664: if (drvp->drv_softc)
1665: ata_probe_caps(drvp);
1666: else {
1667: s = splbio();
1668: drvp->drive_flags &= ~DRIVE_ATAPI;
1669: splx(s);
1670: }
1671: } else {
1672: AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE "
1673: "failed for drive %s:%d:%d: error 0x%x\n",
1674: AHCINAME(ahcic), chp->ch_channel, target,
1675: chp->ch_error), DEBUG_PROBE);
1676: s = splbio();
1677: drvp->drive_flags &= ~DRIVE_ATAPI;
1678: splx(s);
1679: }
1680: }
1681: #endif /* NATAPIBUS */
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