CVS log for src/sys/dev/i2c/gttwsivar.h

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Keyword substitution: kv
Default branch: MAIN

Merge changes from current as of 20200406

Sync with head.

Clean up gttwsi's register access stuff:
- Garbage-collect the obsolete GTTWSI_ALLWINNER option; it hasn't been
  needed since FDT'ization of the Allwinner support code.
- Redefine thw "TWSI_*" register definitions to clearly call out:
  -> The Marvell flavor of the offsets
  -> The Allwinner flavor of the offsets
  ...and make the regular definitions indices into a register map.
- Pass the appropriate register map from the front-end to the core.
- Remove the customer register read/write callbacks -- they are no longer
  needed now that each front-end passes an appropriate register map to
  the core.

Remove assertions that no longer make sense now that the bus acquire / release
logic is handled by the upper layer.

Pull up following revision(s) (requested by bouyer in ticket #1061):
	sys/dev/i2c/gttwsi_core.c: revision 1.4-1.8 via patch
	sys/dev/i2c/gttwsivar.h: revision 1.4 via patch
Use IPL_VM for bus lock so we can do i2c xfers from interrupt context
Don't sleep with IPL_VM lock held.
When initiating a transfer, if a device isn't present, we won't
get an ACK after sending the address.  Check for this alternate
state and suppress the error message when it occurs.
Fixes PR kern/53356.
Bail early if gttwsi_send_start() fails in gttwsi_initiate_xfer() to
avoid unexpected state error message later (on Allwinner H5).
Expand code covered by sc->sc_mtx, to make sure an interrupt would not be
handled before the cv_timedwait_sig() call, or while polling.
Seems to fix "sunxitwi0: send STOP failed" messages frequently seen related
to axp20x0 sensors.

Sync with HEAD

Don't sleep with IPL_VM lock held.

update from HEAD

Allow drivers to provide their own read/write register functions. While
here, sprinkle KASSERTs to verify that the i2c lock is held where it
should be.

Pull up following revision(s) (requested by jmcneill in ticket #257):
	sys/arch/arm/allwinner/awin_twi.c: revision 1.5
	sys/arch/arm/allwinner/awin_reg.h: revision 1.53
	sys/arch/evbarm/conf/HUMMINGBIRD_A31: revision 1.20
	sys/dev/i2c/gttwsi_core.c: revision 1.2
	sys/dev/i2c/gttwsivar.h: revision 1.2
On Allwinner A31 you need to set the CONTROL_IFLG bit to clear it. Add
a "iflg-rwc" property to enable this behaviour.
--
Don't assume that U-Boot has enabled the TWI clock. Also, for A31, set
the "iflg-rwc" device property for gttwsi.
--
The SoC RTC works on this board but does not seem to be hooked up to the
battery. Thankfully, there is a PCF8563 attached to TWI2 at address 51h,
so use that instead.

On Allwinner A31 you need to set the CONTROL_IFLG bit to clear it. Add
a "iflg-rwc" property to enable this behaviour.

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Merge mvi2c from HEAD

file gttwsivar.h was added on branch tls-maxphys on 2014-08-20 00:03:37 +0000

file gttwsivar.h was added on branch yamt-pagecache on 2014-05-22 11:40:21 +0000

file gttwsivar.h was added on branch rmind-smpnet on 2014-05-18 17:45:37 +0000

file gttwsivar.h was added on branch matt-nb5-mips64 on 2014-03-24 18:48:52 +0000

Make gttswi MI and usuable from non-Marvell SoCs.
(should rename to mvi2c but ...)