CVS log for src/sys/dev/acpi/acpi_pci.h

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Default branch: MAIN
Current tag: ad-namecache-base1

Revision 1.11 / (download) - annotate - [select for diffs], Fri Jan 17 17:06:32 2020 UTC (4 years, 3 months ago) by jmcneill
Branch: MAIN
CVS Tags: phil-wifi-20200421, phil-wifi-20200411, phil-wifi-20200406, is-mlppp-base, is-mlppp, bouyer-xenpvh-base2, bouyer-xenpvh-base1, bouyer-xenpvh-base, bouyer-xenpvh, ad-namecache-base3, ad-namecache-base2, ad-namecache-base1
Changes since 1.10: +5 -2 lines
Diff to previous 1.10 (colored)

Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
 - PCIe root port config space lives in a non-standard location.
 - Access to PCIe config space of devices that do not exist results in
   an sync SError. Firmware creates a "known devices" table at a fixed
   physical address that we use to filter PCI conf access to only known
   devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.

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