CVS log for src/sys/arch/x86/x86/tsc.h

Up to [cvs.NetBSD.org] / src / sys / arch / x86 / x86

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Sync w/ HEAD.

x86: Reset cached tsc in every lwp to 0 on suspend/resume.

This avoids spuriously warning about tsc going backwards, which is to
be expected after a suspend/resume cycle.

Serialize rdtsc using with lfence, mfence or cpuid to read TSC more precisely.

 x86/x86/tsc.c rev. 1.67 reduced cache problem and got big improvement, but it
 still has room. I measured the effect of lfence, mfence, cpuid and rdtscp.
The impact to TSC skew and/or drift is:

	AMD:   mfence > rdtscp > cpuid > lfence-serialize > lfence = nomodify
	Intel: lfence > rdtscp > cpuid > nomodify

So, mfence is the best on AMD and lfence is the best on Intel. If it has no
SSE2, we can use cpuid.

NOTE:
  - An AMD's document says DE_CFG_LFENCE_SERIALIZE bit can be used for
    serializing, but it's not so good.
  - On Intel i386(not amd64), it seems the improvement is very little.
  - rdtscp instruct can be used as serializing instruction + rdtsc, but
    it's not good as [lm]fence. Both Intel and AMD's document say that
    the latency of rdtscp is bigger than rdtsc, so I suspect the difference
    of the result comes from it.

update from HEAD

Add a machdep.tsc_user_enable sysctl, to enable/disable the rdtsc
instruction in usermode. It defaults to enabled.

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

 Make new function named tsc_is_invariant() to avoid code duplication.
The behavior of acpicpu_md_flags() will change on some CPUs because
the detecting code of invariant TSC is replaced with newer code.

Sync w/ -current. 34 merge conflicts to follow.

Sync with HEAD.

sync with head.

sync with head.

Improve x86 tsc handling:

- Ditch the cross-CPU calibration stuff. It didn't work properly, and it's
  near impossible to synchronize the CPUs in a running system, because bus
  traffic will interfere with any calibration attempt, messing up the
  timings.

- Only enable the TSC on CPUs where we are sure it does not drift. If we are
  On a known good CPU, give the TSC high timecounter quality, making it the
  default.

- When booting CPUs, detect TSC skew and account for it. Most Intel MP
  systems have synchronized counters, but that need not be true if the
  system has a complicated bus structure. As far as I know, AMD systems
  do not have synchronized TSCs and so we need to handle skew.

- While an AP is waiting to be set running, try and make the TSC drift by
  entering a reduced power state. If we detect drift, ensure that the TSC
  does not get a high timecounter quality. This should not happen and is
  only for safety.

- Make cpu_counter() stuff LKM safe.

Remove clause 3 and 4 from TNF licenses

sync with head

sync with head.

sync with head.

Sync with head.

file tsc.h was added on branch rpaulo-netinet-merge-pcb on 2006-09-09 02:44:49 +0000

file tsc.h was added on branch yamt-pdpolicy on 2006-06-26 12:45:40 +0000

file tsc.h was added on branch yamt-lazymbuf on 2006-06-21 14:58:06 +0000

file tsc.h was added on branch chap-midi on 2006-06-19 03:45:15 +0000

add timecounter support (from branch simonb-timecounters)

- provide TSC for UNI and MP systems
  (shared between i386 and amd64)

file tsc.h was initially added on branch simonb-timecounters.