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Diff for /src/sys/arch/x86/x86/tsc.c between version 1.15.2.3 and 1.16

version 1.15.2.3, 2008/09/18 04:33:38 version 1.16, 2008/05/10 16:12:32
Line 85  tsc_tc_init(void)
Line 85  tsc_tc_init(void)
                  * Core Solo and Core Duo processors (family 06, model 0e)                   * Core Solo and Core Duo processors (family 06, model 0e)
                  * Xeon 5100 series and Core 2 Duo (family 06, model 0f)                   * Xeon 5100 series and Core 2 Duo (family 06, model 0f)
                  *                   *
                  * We'll also assume that it's safe on the Pentium, and                   * We'll also assume that it's safe on the Pentium.  It
                  * that it's safe on P-II and P-III Xeons due to the                   * can probably be assumed for the earlier P-II and P-III
                  * typical configuration of those systems.                   * Xeons, but for now, punt.
                  */                   */
                 switch (CPUID2FAMILY(ci->ci_signature)) {                  switch (CPUID2FAMILY(ci->ci_signature)) {
                 case 0x05:                  case 0x05:
Line 95  tsc_tc_init(void)
Line 95  tsc_tc_init(void)
                         break;                          break;
                 case 0x06:                  case 0x06:
                         safe = CPUID2MODEL(ci->ci_signature) == 0x0e ||                          safe = CPUID2MODEL(ci->ci_signature) == 0x0e ||
                             CPUID2MODEL(ci->ci_signature) == 0x0f ||                              CPUID2MODEL(ci->ci_signature) == 0x0f;
                             CPUID2MODEL(ci->ci_signature) == 0x0a;  
                         break;                          break;
                 case 0x0f:                  case 0x0f:
                         safe = CPUID2MODEL(ci->ci_signature) >= 0x03;                          safe = CPUID2MODEL(ci->ci_signature) > 0x03;
                         break;                          break;
                 }                  }
         } else if (cpu_vendor == CPUVENDOR_AMD) {          } else if (cpu_vendor == CPUVENDOR_AMD) {
Line 140  tsc_tc_init(void)
Line 139  tsc_tc_init(void)
                 safe = false;                  safe = false;
         }          }
   
         if (tsc_freq != 0) {          tsc_timecounter.tc_frequency = tsc_freq;
                 tsc_timecounter.tc_frequency = tsc_freq;          tc_init(&tsc_timecounter);
                 tc_init(&tsc_timecounter);  
         }  
 }  }
   
 /*  /*
Line 169  tsc_sync_bp(struct cpu_info *ci)
Line 166  tsc_sync_bp(struct cpu_info *ci)
         uint64_t tsc;          uint64_t tsc;
   
         /* Clear remote result, pending later update. */          /* Clear remote result, pending later update. */
         ci->ci_data.cpu_cc_skew = 0x7fffffffffffffffLL;          ci->ci_data.cpu_cc_skew = ~0LL;
   
         /* Flag it and read our TSC. */          /* Flag it and read our TSC. */
         atomic_or_uint(&ci->ci_flags, CPUF_SYNCTSC);          atomic_or_uint(&ci->ci_flags, CPUF_SYNCTSC);
Line 182  tsc_sync_bp(struct cpu_info *ci)
Line 179  tsc_sync_bp(struct cpu_info *ci)
         tsc += (rdmsr(MSR_TSC) >> 1);          tsc += (rdmsr(MSR_TSC) >> 1);
   
         /* Wait for the results to come in. */          /* Wait for the results to come in. */
         while (ci->ci_data.cpu_cc_skew == 0x7fffffffffffffffLL) {          while (ci->ci_data.cpu_cc_skew == ~0LL) {
                 x86_pause();                  x86_pause();
         }          }
   
Legend:
Removed from v.1.15.2.3  
changed lines
  Added in v.1.16
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