CVS log for src/sys/arch/x86/x86/fpu.c

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Default branch: MAIN
Current tag: rmind-smpnet-base

Revision 1.9 / (download) - annotate - [select for diffs], Tue Feb 25 22:16:52 2014 UTC (10 years, 1 month ago) by dsl
Branch: MAIN
CVS Tags: yamt-pagecache-base9, tls-maxphys-base, tls-earlyentropy-base, tls-earlyentropy, rmind-smpnet-nbase, rmind-smpnet-base, riastradh-xf86-video-intel-2-7-1-pre-2-21-15, riastradh-drm2-base3, netbsd-7-nhusb-base-20170116, netbsd-7-nhusb-base, netbsd-7-nhusb, netbsd-7-base, netbsd-7-1-RELEASE, netbsd-7-1-RC2, netbsd-7-1-RC1, netbsd-7-0-RELEASE, netbsd-7-0-RC3, netbsd-7-0-RC2, netbsd-7-0-RC1, netbsd-7-0-2-RELEASE, netbsd-7-0-1-RELEASE
Branch point for: yamt-pagecache, tls-maxphys, rmind-smpnet, netbsd-7-1, netbsd-7-0, netbsd-7
Changes since 1.8: +45 -19 lines
Diff to previous 1.8 (colored)

Add support for saving the AVX-256 ymm registers during FPU context switches.
Add support for the forthcoming AVX-512 registers.
Code compiled with -mavx seems to work, but I've not tested context
  switches with live ymm registers.
There is a small cost on fork/exec (a larger area is copied/zerod),
  but I don't think the ymm registers are read/written unless they
  have been used.
The code use XSAVE on all cpus, I'm not brave enough to enable XSAVEOPT.

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