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CVS log for src/sys/arch/x86/x86/fpu.c

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Request diff between arbitrary revisions


Default branch: MAIN


Revision 1.28.2.4 / (download) - annotate - [select for diffs], Sat Oct 20 06:58:29 2018 UTC (3 weeks, 5 days ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.28.2.3: +5 -6 lines
Diff to previous 1.28.2.3 (colored) to branchpoint 1.28 (colored) next main 1.29 (colored)

Sync with head

Revision 1.48 / (download) - annotate - [select for diffs], Fri Oct 5 18:51:52 2018 UTC (5 weeks, 5 days ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-1020, HEAD
Changes since 1.47: +5 -6 lines
Diff to previous 1.47 (colored)

export x86_fpu_mxcsr_mask, fpu_area_save and fpu_area_restore

Revision 1.28.2.3 / (download) - annotate - [select for diffs], Sun Sep 30 01:45:48 2018 UTC (6 weeks, 4 days ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.28.2.2: +131 -159 lines
Diff to previous 1.28.2.2 (colored) to branchpoint 1.28 (colored)

Ssync with HEAD

Revision 1.47 / (download) - annotate - [select for diffs], Mon Sep 17 15:53:06 2018 UTC (8 weeks, 2 days ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-0930
Changes since 1.46: +131 -159 lines
Diff to previous 1.46 (colored)

Reduce the noise, reorder and rename some things for clarity.

Revision 1.28.2.2 / (download) - annotate - [select for diffs], Sat Jul 28 04:37:42 2018 UTC (3 months, 2 weeks ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.28.2.1: +40 -21 lines
Diff to previous 1.28.2.1 (colored) to branchpoint 1.28 (colored)

Sync with HEAD

Revision 1.12.8.3 / (download) - annotate - [select for diffs], Tue Jul 10 15:35:26 2018 UTC (4 months ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-0-RELEASE
Changes since 1.12.8.2: +16 -2 lines
Diff to previous 1.12.8.2 (colored) to branchpoint 1.12 (colored) next main 1.13 (colored)

Pull up the following, requested by maxv in ticket #910:

	sys/arch/amd64/amd64/locore.S	r1.167 (patch)
	sys/arch/i386/i386/locore.S	r1.158 (patch)
	sys/arch/x86/x86/fpu.c		r1.44 (patch)

Don't switch the FPU when leaving a softint. This fixes
several problems when EagerFPU is enabled.

Revision 1.46 / (download) - annotate - [select for diffs], Sun Jul 1 08:32:41 2018 UTC (4 months, 2 weeks ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-0906, pgoyette-compat-0728
Changes since 1.45: +5 -12 lines
Diff to previous 1.45 (colored)

Use a variable-sized memcpy, instead of copying the PCB and then adding
the extra bytes. The PCB embeds the biggest static FPU state, but our
real FPU state may be smaller (FNSAVE), so we don't need to memcpy the
extra unused bytes.

Revision 1.45 / (download) - annotate - [select for diffs], Sun Jul 1 07:18:56 2018 UTC (4 months, 2 weeks ago) by maxv
Branch: MAIN
Changes since 1.44: +23 -11 lines
Diff to previous 1.44 (colored)

Use a switch, we can (and will) optimize each case separately. No
functional change.

Revision 1.44 / (download) - annotate - [select for diffs], Fri Jun 29 19:34:35 2018 UTC (4 months, 2 weeks ago) by maxv
Branch: MAIN
Changes since 1.43: +16 -2 lines
Diff to previous 1.43 (colored)

Add more KASSERTs.

Should help PR/53399.

Revision 1.28.2.1 / (download) - annotate - [select for diffs], Mon Jun 25 07:25:47 2018 UTC (4 months, 3 weeks ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.28: +373 -52 lines
Diff to previous 1.28 (colored)

Sync with HEAD

Revision 1.12.8.2 / (download) - annotate - [select for diffs], Sat Jun 23 11:39:02 2018 UTC (4 months, 3 weeks ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-0-RC2
Changes since 1.12.8.1: +231 -37 lines
Diff to previous 1.12.8.1 (colored) to branchpoint 1.12 (colored)

Pull up the following, via patch, requested by maxv in ticket #897:

	sys/arch/amd64/amd64/locore.S           1.166 (patch)
	sys/arch/i386/i386/locore.S             1.157 (patch)
	sys/arch/x86/include/cpu.h              1.92 (patch)
	sys/arch/x86/include/fpu.h              1.9 (patch)
	sys/arch/x86/x86/fpu.c                  1.33-1.39 (patch)
	sys/arch/x86/x86/identcpu.c             1.72 (patch)
	sys/arch/x86/x86/vm_machdep.c           1.34 (patch)
	sys/arch/x86/x86/x86_machdep.c          1.116,1.117 (patch)

Support eager fpu switch, to work around INTEL-SA-00145.
Provide a sysctl machdep.fpu_eager, which gets automatically
initialized to 1 on affected CPUs.

Revision 1.43 / (download) - annotate - [select for diffs], Sat Jun 23 10:06:02 2018 UTC (4 months, 3 weeks ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-base, phil-wifi, pgoyette-compat-0625
Changes since 1.42: +7 -2 lines
Diff to previous 1.42 (colored)

Add XXX in fpuinit_mxcsr_mask.

Revision 1.42 / (download) - annotate - [select for diffs], Fri Jun 22 06:22:37 2018 UTC (4 months, 3 weeks ago) by maxv
Branch: MAIN
Changes since 1.41: +7 -9 lines
Diff to previous 1.41 (colored)

Revert jdolecek's changes related to FXSAVE. They just didn't make any
sense and were trying to hide a real bug, which is, that there is for some
reason a wrong stack alignment that causes FXSAVE to fault in
fpuinit_mxcsr_mask. As seen in current-users@ yesterday, rdi % 16 = 8. And
as seen several months ago, as well.

The rest of the changes in XSAVE are wrong too, but I'll let him fix these
ones.

Revision 1.41 / (download) - annotate - [select for diffs], Wed Jun 20 20:43:21 2018 UTC (4 months, 3 weeks ago) by jdolecek
Branch: MAIN
Changes since 1.40: +4 -4 lines
Diff to previous 1.40 (colored)

as a stop-gap, make fpuinit_mxcsr_mask() for native independant of
XSAVE as it should be, only xen case checks the flag now; need to
investigate further why exactly the fault happens for the xen
no-xsave case

pointed out by maxv

Revision 1.40 / (download) - annotate - [select for diffs], Tue Jun 19 19:50:19 2018 UTC (4 months, 3 weeks ago) by jdolecek
Branch: MAIN
Changes since 1.39: +9 -7 lines
Diff to previous 1.39 (colored)

fix FPU initialization on Xen to allow e.g. AVX when supported by hardware;
only use XSAVE when the the CPUID OSXSAVE bit is set, as this seems to be
reliable indication

tested with Xen 4.2.6 DOM0/DOMU on Intel CPU, without and with no-xsave flag,
so should work also on those AMD CPUs, which have XSAVE disabled by default;
also tested with Xen DOM0 4.8.3

fixes PR kern/50332 by Torbjorn Granlund; sorry it took three years to address

XXX pullup netbsd-8

Revision 1.39 / (download) - annotate - [select for diffs], Tue Jun 19 09:25:13 2018 UTC (4 months, 3 weeks ago) by maxv
Branch: MAIN
Changes since 1.38: +17 -9 lines
Diff to previous 1.38 (colored)

When using EagerFPU, create the fpu state in execve at IPL_HIGH.

A preemption could occur in the middle, and we don't want that to happen,
because the context switch would use the partially-constructed fpu state.

The procedure becomes:

	splhigh
	unbusy the current cpu's fpu
	create a new fpu state in memory
	install the state on the current cpu's fpu
	splx

Disabling preemption also ensures that x86_fpu_eager doesn't change in
the middle.

In LazyFPU mode we drop IPL_HIGH right away.

Add more KASSERTs.

Revision 1.38 / (download) - annotate - [select for diffs], Mon Jun 18 20:20:27 2018 UTC (4 months, 3 weeks ago) by maxv
Branch: MAIN
Changes since 1.37: +6 -2 lines
Diff to previous 1.37 (colored)

Add more KASSERTs, see if they help PR/53383.

Revision 1.37 / (download) - annotate - [select for diffs], Sun Jun 17 06:03:40 2018 UTC (4 months, 4 weeks ago) by maxv
Branch: MAIN
Changes since 1.36: +12 -6 lines
Diff to previous 1.36 (colored)

No, I meant to put the panic in fpudna not fputrap. Also appease it: panic
only if the fpu already has a state. We're fine with getting a DNA, what
we're not fine with is if the DNA is received while the FPU is busy.

I believe (even though I couldn't trigger it) that the panic would
otherwise fire if PT_SETFPREGS is used. And also ACPI sleep/wakeup,
probably.

Revision 1.36 / (download) - annotate - [select for diffs], Sat Jun 16 17:11:13 2018 UTC (4 months, 4 weeks ago) by maxv
Branch: MAIN
Changes since 1.35: +117 -2 lines
Diff to previous 1.35 (colored)

Need IPIs when enabling eager fpu switch, to clear each fpu and get us
started. Otherwise it is possible that the first context switch on one of
the cpus will restore an invalid fpu state in the new lwp, if that lwp
had its fpu state stored on another cpu that didn't have time to do an
fpu save since eager-fpu was enabled.

Use barriers and all the related crap. The point is that we want to
ensure that no context switch occurs between [each fpu is cleared] and
[x86_fpu_eager is set to 'true'].

Also add KASSERTs.

Revision 1.35 / (download) - annotate - [select for diffs], Sat Jun 16 05:52:17 2018 UTC (5 months ago) by maxv
Branch: MAIN
Changes since 1.34: +3 -13 lines
Diff to previous 1.34 (colored)

Actually, don't do anything if we switch to a kernel thread. When the cpu
switches back to a user thread the fpu is restored, so no point calling
fninit (which doesn't clear all the states anyway).

Revision 1.34 / (download) - annotate - [select for diffs], Thu Jun 14 18:00:15 2018 UTC (5 months ago) by maxv
Branch: MAIN
Changes since 1.33: +10 -2 lines
Diff to previous 1.33 (colored)

Install the FPU state on the current CPU in setregs (execve).

Revision 1.33 / (download) - annotate - [select for diffs], Thu Jun 14 14:36:46 2018 UTC (5 months ago) by maxv
Branch: MAIN
Changes since 1.32: +110 -57 lines
Diff to previous 1.32 (colored)

Add some code to support eager fpu switch, INTEL-SA-00145. We restore the
FPU state of the lwp right away during context switches. This guarantees
that when the CPU executes in userland, the FPU doesn't contain secrets.

Maybe we also need to clear the FPU in setregs(), not sure about this one.

Can be enabled/disabled via:

	machdep.fpu_eager = {0/1}

Not yet turned on automatically on affected CPUs (Intel Family 6).

More generally it would be good to turn it on automatically when XSAVEOPT
is supported, because in this case there is probably a non-negligible
performance gain; but we need to fix PR/52966.

Revision 1.32 / (download) - annotate - [select for diffs], Wed May 23 10:21:43 2018 UTC (5 months, 3 weeks ago) by maxv
Branch: MAIN
Changes since 1.31: +6 -2 lines
Diff to previous 1.31 (colored)

Add a comment about recent AMD CPUs.

Revision 1.31 / (download) - annotate - [select for diffs], Wed May 23 10:00:27 2018 UTC (5 months, 3 weeks ago) by maxv
Branch: MAIN
Changes since 1.30: +27 -14 lines
Diff to previous 1.30 (colored)

Clarify and extend the fix for the AMD FPU leaks. We were clearing the x87
state only on FXRSTOR, but the same problem exists on XRSTOR, so clear the
state there too.

Revision 1.30 / (download) - annotate - [select for diffs], Wed May 23 07:45:35 2018 UTC (5 months, 3 weeks ago) by maxv
Branch: MAIN
Changes since 1.29: +122 -2 lines
Diff to previous 1.29 (colored)

Merge convert_xmm_s87.c into fpu.c. It contains only two functions, that
are used only in fpu.c.

Revision 1.29 / (download) - annotate - [select for diffs], Wed May 23 07:34:40 2018 UTC (5 months, 3 weeks ago) by maxv
Branch: MAIN
Changes since 1.28: +41 -46 lines
Diff to previous 1.28 (colored)

style

Revision 1.28 / (download) - annotate - [select for diffs], Fri Feb 9 08:58:01 2018 UTC (9 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-base, pgoyette-compat-0521, pgoyette-compat-0502, pgoyette-compat-0422, pgoyette-compat-0415, pgoyette-compat-0407, pgoyette-compat-0330, pgoyette-compat-0322, pgoyette-compat-0315
Branch point for: pgoyette-compat
Changes since 1.27: +13 -4 lines
Diff to previous 1.27 (colored)

Force a reload of CW in fpu_set_default_cw(). This function is used only
in COMPAT_FREEBSD, it really needs to die.

Revision 1.12.8.1 / (download) - annotate - [select for diffs], Thu Dec 21 19:33:15 2017 UTC (10 months, 3 weeks ago) by snj
Branch: netbsd-8
CVS Tags: netbsd-8-0-RC1
Changes since 1.12: +3 -2 lines
Diff to previous 1.12 (colored)

Pull up following revision(s) (requested by maxv in ticket #442):
	sys/arch/x86/x86/fpu.c: 1.19 via patch
Mask mxcsr, otherwise userland could set reserved bits to 1 and make
xrstor fault.

Revision 1.9.8.1 / (download) - annotate - [select for diffs], Tue Dec 12 09:12:57 2017 UTC (11 months ago) by snj
Branch: netbsd-7
CVS Tags: netbsd-7-2-RELEASE
Changes since 1.9: +3 -2 lines
Diff to previous 1.9 (colored) next main 1.10 (colored)

Pull up following revision(s) (requested by maxv in ticket #1540):
	sys/arch/x86/x86/fpu.c: 1.19 via patch
Mask mxcsr, otherwise userland could set reserved bits to 1 and make
xrstor fault.

Revision 1.9.16.1 / (download) - annotate - [select for diffs], Tue Dec 12 09:12:53 2017 UTC (11 months ago) by snj
Branch: netbsd-7-1
CVS Tags: netbsd-7-1-2-RELEASE, netbsd-7-1-1-RELEASE
Changes since 1.9: +3 -2 lines
Diff to previous 1.9 (colored) next main 1.10 (colored)

Pull up following revision(s) (requested by maxv in ticket #1540):
	sys/arch/x86/x86/fpu.c: 1.19 via patch
Mask mxcsr, otherwise userland could set reserved bits to 1 and make
xrstor fault.

Revision 1.9.12.1 / (download) - annotate - [select for diffs], Tue Dec 12 09:12:50 2017 UTC (11 months ago) by snj
Branch: netbsd-7-0
Changes since 1.9: +3 -2 lines
Diff to previous 1.9 (colored) next main 1.10 (colored)

Pull up following revision(s) (requested by maxv in ticket #1540):
	sys/arch/x86/x86/fpu.c: 1.19 via patch
Mask mxcsr, otherwise userland could set reserved bits to 1 and make
xrstor fault.

Revision 1.9.10.3 / (download) - annotate - [select for diffs], Sun Dec 3 11:36:50 2017 UTC (11 months, 1 week ago) by jdolecek
Branch: tls-maxphys
Changes since 1.9.10.2: +163 -136 lines
Diff to previous 1.9.10.2 (colored) to branchpoint 1.9 (colored) next main 1.10 (colored)

update from HEAD

Revision 1.27 / (download) - annotate - [select for diffs], Sat Nov 11 11:00:46 2017 UTC (12 months ago) by maxv
Branch: MAIN
CVS Tags: tls-maxphys-base-20171202
Changes since 1.26: +5 -9 lines
Diff to previous 1.26 (colored)

Recommit

http://mail-index.netbsd.org/source-changes/2017/11/08/msg089525.html

but use __INITIAL_MXCSR_MASK__ on Xen until someone figures out what's
wrong with the Xen fpu.

Revision 1.26 / (download) - annotate - [select for diffs], Sat Nov 11 09:10:19 2017 UTC (12 months ago) by bouyer
Branch: MAIN
Changes since 1.25: +13 -5 lines
Diff to previous 1.25 (colored)

Revert http://mail-index.netbsd.org/source-changes/2017/11/08/msg089525.html,
it breaks Xen:
http://www-soc.lip6.fr/~bouyer/NetBSD-tests/xen/HEAD/amd64/201711082340Z_anita.txt

Revision 1.25 / (download) - annotate - [select for diffs], Wed Nov 8 17:52:22 2017 UTC (12 months ago) by maxv
Branch: MAIN
Changes since 1.24: +3 -11 lines
Diff to previous 1.24 (colored)

Call fpuinit_mxcsr_mask in cpu_init, after cr4 is initialized, but before
touching xcr0. Then use clts/stts instead of modifying cr0, and enable the
mxcsr_mask detection on Xen.

Revision 1.24 / (download) - annotate - [select for diffs], Sat Nov 4 08:58:30 2017 UTC (12 months, 1 week ago) by maxv
Branch: MAIN
Changes since 1.23: +7 -3 lines
Diff to previous 1.23 (colored)

Add support for xsaveopt. It is basically an instruction that optimizes
context switch performance by not saving to memory FPU registers that are
known to be in their initial state or known not to have changed since the
last time they were saved to memory.

Our code is now compatible with the internal state tracking engine:
 - We don't modify the in-memory FPU state after doing an XSAVE/XSAVEOPT.
   That is to say, we always call XRSTOR first.
 - During a fork, the whole in-memory FPU state area is memcopied in the
   new PCB, and CR0_TS is set. Next time the forked thread uses the FPU it
   will fault, we migrate the area, call XRSTOR and clear CR0_TS. During
   this XRSTOR XSTATE_BV still contains the initial values, and it forces
   a reload of XINUSE.
 - Whenever software wants to change the in-memory FPU state, it manually
   sets XSTATE_BV[i]=1, which forces XINUSE[i]=1.
 - The address of the state passed to xrstor is always the same for a
   given LWP.

fpu_save_area_clear is changed not to force a reload of CW if fx_cw is
the standard FPU value. This way we have XINUSE[i]=0 for x87, and xsaveopt
will optimize this state.

Small benchmark:
	switch lwp to cpu2
	do float operation
	switch lwp to cpu3
	do float operation
Doing this 10^6 times in a loop, my cpu goes on average from 28,2 seconds
to 20,8 seconds.

Revision 1.23 / (download) - annotate - [select for diffs], Sat Nov 4 07:38:42 2017 UTC (12 months, 1 week ago) by maxv
Branch: MAIN
Changes since 1.22: +7 -0 lines
Diff to previous 1.22 (colored)

Always set XCR0_X87, to force a reload of CW. That's needed for compat
options where fx_cw is not the standard fpu value.

Revision 1.22 / (download) - annotate - [select for diffs], Sat Nov 4 07:35:00 2017 UTC (12 months, 1 week ago) by maxv
Branch: MAIN
Changes since 1.21: +9 -2 lines
Diff to previous 1.21 (colored)

Fix xen. Not tested, but seems fine enough.

Revision 1.21 / (download) - annotate - [select for diffs], Fri Nov 3 07:14:24 2017 UTC (12 months, 1 week ago) by maxv
Branch: MAIN
Changes since 1.20: +36 -3 lines
Diff to previous 1.20 (colored)

Fix MXCSR_MASK, it needs to be detected dynamically, otherwise when masking
MXCSR we are losing some features (eg DAZ).

Revision 1.20 / (download) - annotate - [select for diffs], Tue Oct 31 18:23:29 2017 UTC (12 months, 2 weeks ago) by maxv
Branch: MAIN
Changes since 1.19: +1 -1 lines
Diff to previous 1.19 (colored)

Zero out the buffer entirely.

Revision 1.19 / (download) - annotate - [select for diffs], Tue Oct 31 18:13:37 2017 UTC (12 months, 2 weeks ago) by maxv
Branch: MAIN
Changes since 1.18: +7 -3 lines
Diff to previous 1.18 (colored)

Mask mxcsr, otherwise userland could set reserved bits to 1 and make
xrstor fault.

Revision 1.18 / (download) - annotate - [select for diffs], Tue Oct 31 15:16:10 2017 UTC (12 months, 2 weeks ago) by maxv
Branch: MAIN
Changes since 1.17: +22 -2 lines
Diff to previous 1.17 (colored)

Initialize xstate_bv with the structures that were just filled in,
otherwise xrstor does not restore them. This can happen only if userland
calls setcontext without having used the FPU before.

Until rev1.15 xstate_bv was implicitly initialized because the xsave area
was not zeroed out properly.

Revision 1.17 / (download) - annotate - [select for diffs], Tue Oct 31 12:02:20 2017 UTC (12 months, 2 weeks ago) by maxv
Branch: MAIN
Changes since 1.16: +10 -6 lines
Diff to previous 1.16 (colored)

Don't embed our own values in the reserved fields of the XSAVE area, it
really is a bad idea. Move them into the PCB.

Revision 1.16 / (download) - annotate - [select for diffs], Tue Oct 31 11:37:05 2017 UTC (12 months, 2 weeks ago) by maxv
Branch: MAIN
Changes since 1.15: +27 -16 lines
Diff to previous 1.15 (colored)

Always use x86_fpu_save, clearer.

Revision 1.15 / (download) - annotate - [select for diffs], Tue Oct 31 10:35:58 2017 UTC (12 months, 2 weeks ago) by maxv
Branch: MAIN
Changes since 1.14: +13 -25 lines
Diff to previous 1.14 (colored)

Remove comments that are more misleading than anything else. While here
make sure we zero out the FPU area entirely, and not just its legacy
region.

Revision 1.14 / (download) - annotate - [select for diffs], Mon Oct 9 17:49:28 2017 UTC (13 months ago) by maya
Branch: MAIN
Changes since 1.13: +2 -28 lines
Diff to previous 1.13 (colored)

GC i386_fpu_present. no FPU x86 is not supported.

Also delete newly unused send_sigill

Revision 1.13 / (download) - annotate - [select for diffs], Sun Sep 17 09:41:35 2017 UTC (13 months, 4 weeks ago) by maxv
Branch: MAIN
Changes since 1.12: +4 -4 lines
Diff to previous 1.12 (colored)

Remove the second argument from USERMODE and KERNELMODE, it is unused
now that we don't have vm86 anymore.

Revision 1.10.4.1 / (download) - annotate - [select for diffs], Fri Nov 4 14:49:06 2016 UTC (2 years ago) by pgoyette
Branch: pgoyette-localcount
Changes since 1.10: +44 -62 lines
Diff to previous 1.10 (colored) next main 1.11 (colored)

Sync with HEAD

Revision 1.10.2.1 / (download) - annotate - [select for diffs], Wed Oct 5 20:55:37 2016 UTC (2 years, 1 month ago) by skrll
Branch: nick-nhusb
Changes since 1.10: +49 -70 lines
Diff to previous 1.10 (colored) next main 1.11 (colored)

Sync with HEAD

Revision 1.12 / (download) - annotate - [select for diffs], Thu Sep 29 17:01:43 2016 UTC (2 years, 1 month ago) by maxv
Branch: MAIN
CVS Tags: prg-localcount2-base3, prg-localcount2-base2, prg-localcount2-base1, prg-localcount2-base, prg-localcount2, pgoyette-localcount-20170426, pgoyette-localcount-20170320, pgoyette-localcount-20170107, pgoyette-localcount-20161104, perseant-stdc-iso10646-base, perseant-stdc-iso10646, nick-nhusb-base-20170825, nick-nhusb-base-20170204, nick-nhusb-base-20161204, nick-nhusb-base-20161004, netbsd-8-base, matt-nb8-mediatek-base, matt-nb8-mediatek, jdolecek-ncq-base, jdolecek-ncq, bouyer-socketcan-base1, bouyer-socketcan-base, bouyer-socketcan
Branch point for: netbsd-8
Changes since 1.11: +40 -63 lines
Diff to previous 1.11 (colored)

Remove outdated comments, typos, rename and reorder a few things.

Revision 1.11 / (download) - annotate - [select for diffs], Thu Aug 18 12:36:35 2016 UTC (2 years, 2 months ago) by maxv
Branch: MAIN
CVS Tags: localcount-20160914
Changes since 1.10: +13 -11 lines
Diff to previous 1.10 (colored)

Simplify.

Revision 1.10 / (download) - annotate - [select for diffs], Thu Nov 27 14:22:09 2014 UTC (3 years, 11 months ago) by uebayasi
Branch: MAIN
CVS Tags: pgoyette-localcount-base, pgoyette-localcount-20160806, pgoyette-localcount-20160726, nick-nhusb-base-20160907, nick-nhusb-base-20160529, nick-nhusb-base-20160422, nick-nhusb-base-20160319, nick-nhusb-base-20151226, nick-nhusb-base-20150921, nick-nhusb-base-20150606, nick-nhusb-base-20150406, nick-nhusb-base
Branch point for: pgoyette-localcount, nick-nhusb
Changes since 1.9: +4 -4 lines
Diff to previous 1.9 (colored)

Consistently use kpreempt_*() outside scheduler path.

Revision 1.9.10.2 / (download) - annotate - [select for diffs], Wed Aug 20 00:03:29 2014 UTC (4 years, 2 months ago) by tls
Branch: tls-maxphys
Changes since 1.9.10.1: +673 -0 lines
Diff to previous 1.9.10.1 (colored) to branchpoint 1.9 (colored)

Rebase to HEAD as of a few days ago.

Revision 1.9.6.2 / (download) - annotate - [select for diffs], Thu May 22 11:40:14 2014 UTC (4 years, 5 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.9.6.1: +673 -0 lines
Diff to previous 1.9.6.1 (colored) to branchpoint 1.9 (colored) next main 1.10 (colored)

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

Revision 1.9.4.2 / (download) - annotate - [select for diffs], Sun May 18 17:45:30 2014 UTC (4 years, 5 months ago) by rmind
Branch: rmind-smpnet
Changes since 1.9.4.1: +673 -0 lines
Diff to previous 1.9.4.1 (colored) to branchpoint 1.9 (colored) next main 1.10 (colored)

sync with head

Revision 1.9.10.1, Tue Feb 25 22:16:52 2014 UTC (4 years, 8 months ago) by tls
Branch: tls-maxphys
Changes since 1.9: +0 -673 lines
FILE REMOVED

file fpu.c was added on branch tls-maxphys on 2014-08-20 00:03:29 +0000

Revision 1.9.6.1, Tue Feb 25 22:16:52 2014 UTC (4 years, 8 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.9: +0 -673 lines
FILE REMOVED

file fpu.c was added on branch yamt-pagecache on 2014-05-22 11:40:14 +0000

Revision 1.9.4.1, Tue Feb 25 22:16:52 2014 UTC (4 years, 8 months ago) by rmind
Branch: rmind-smpnet
Changes since 1.9: +0 -673 lines
FILE REMOVED

file fpu.c was added on branch rmind-smpnet on 2014-05-18 17:45:30 +0000

Revision 1.9 / (download) - annotate - [select for diffs], Tue Feb 25 22:16:52 2014 UTC (4 years, 8 months ago) by dsl
Branch: MAIN
CVS Tags: yamt-pagecache-base9, tls-maxphys-base, tls-earlyentropy-base, tls-earlyentropy, rmind-smpnet-nbase, rmind-smpnet-base, riastradh-xf86-video-intel-2-7-1-pre-2-21-15, riastradh-drm2-base3, netbsd-7-nhusb-base-20170116, netbsd-7-nhusb-base, netbsd-7-nhusb, netbsd-7-base, netbsd-7-1-RELEASE, netbsd-7-1-RC2, netbsd-7-1-RC1, netbsd-7-0-RELEASE, netbsd-7-0-RC3, netbsd-7-0-RC2, netbsd-7-0-RC1, netbsd-7-0-2-RELEASE, netbsd-7-0-1-RELEASE
Branch point for: yamt-pagecache, tls-maxphys, rmind-smpnet, netbsd-7-1, netbsd-7-0, netbsd-7
Changes since 1.8: +45 -19 lines
Diff to previous 1.8 (colored)

Add support for saving the AVX-256 ymm registers during FPU context switches.
Add support for the forthcoming AVX-512 registers.
Code compiled with -mavx seems to work, but I've not tested context
  switches with live ymm registers.
There is a small cost on fork/exec (a larger area is copied/zerod),
  but I don't think the ymm registers are read/written unless they
  have been used.
The code use XSAVE on all cpus, I'm not brave enough to enable XSAVEOPT.

Revision 1.8 / (download) - annotate - [select for diffs], Sun Feb 23 22:35:28 2014 UTC (4 years, 8 months ago) by dsl
Branch: MAIN
Changes since 1.7: +14 -2 lines
Diff to previous 1.7 (colored)

Add fpu_set_default_cw() and use it in the emulations to set the default
  x87 control word.
This means that nothing outside fpu.c cares about the internals of the
  fpu save area.
New kernel modules won't load with the old kernel - but that won't matter.

Revision 1.7 / (download) - annotate - [select for diffs], Sun Feb 23 12:56:40 2014 UTC (4 years, 8 months ago) by dsl
Branch: MAIN
Changes since 1.6: +5 -28 lines
Diff to previous 1.6 (colored)

Determine whether the cpu supports xsave (and hence AVX).
The result is only written to sysctl nodes at the moment.
I see:
machdep.fpu_save = 3 (implies xsaveopt)
machdep.xsave_size = 832
machdep.xsave_features = 7
Completely common up the i386 and amd64 machdep sysctl creation.

Revision 1.6 / (download) - annotate - [select for diffs], Sat Feb 15 22:20:42 2014 UTC (4 years, 8 months ago) by dsl
Branch: MAIN
Changes since 1.5: +83 -7 lines
Diff to previous 1.5 (colored)

Load and save the fpu registers (for copies to/from userspace) using
  helper functions in arch/x86/x86/fpu.c
They (hopefully) ensure that we write to the entire buffer and don't load
  values that might cause faults in kernel.
Also zero out the 'pad' field of the i386 mcontext fp area that I think
  once contained the registers of any Weitek fpu.
  Dunno why it wasn't pasrt of the union.
Some of these copies could be removed if the code directly copied the save
  area to/from userspace addresses.

Revision 1.5 / (download) - annotate - [select for diffs], Sat Feb 15 10:11:15 2014 UTC (4 years, 9 months ago) by dsl
Branch: MAIN
Changes since 1.4: +55 -27 lines
Diff to previous 1.4 (colored)

Remove all references to MDL_USEDFPU and deferred fpu initialisation.
The cost of zeroing the save area on exec is minimal.
This stops the FP registers of a random process being used the first
  time an lwp uses the fpu.
sendsig_siginfo() and get_mcontext() now unconditionally copy the FP
registers.
I'll remove the double-copy for signal handlers soon.
get_mcontext() might have been leaking kernel memory to userspace - and
  may still do so if i386_use_fxsave is false (short copies).

Revision 1.4 / (download) - annotate - [select for diffs], Thu Feb 13 19:37:08 2014 UTC (4 years, 9 months ago) by dsl
Branch: MAIN
Changes since 1.3: +4 -4 lines
Diff to previous 1.3 (colored)

Check the argument types for the fpu asm functions.

Revision 1.3 / (download) - annotate - [select for diffs], Wed Feb 12 23:24:09 2014 UTC (4 years, 9 months ago) by dsl
Branch: MAIN
Changes since 1.2: +81 -23 lines
Diff to previous 1.2 (colored)

Change i386 to use x86/fpu.c instead of i386/isa/npx.c
This changes the trap10 and trap13 code to call directly into fpu.c,
  removing all the code for T_ARITHTRAP, T_XMM and T_FPUNDA from i386/trap.c
Not all of the code thate appeared to handle fpu traps was ever called!
Most of the changes just replace the include of machine/npx.h with x86/fpu.h
  (or remove it entirely).

Revision 1.2 / (download) - annotate - [select for diffs], Wed Feb 12 19:53:49 2014 UTC (4 years, 9 months ago) by dsl
Branch: MAIN
Changes since 1.1: +20 -8 lines
Diff to previous 1.1 (colored)

Change the argument to fpudna() to be the trapframe.
Move the checks for fpu traps in kernel into x86/fpu.c.
Remove the code from amd64/trap.c related to fpu traps (they've not gone
  there for ages - expect to panic in kernel mode).
In fpudna():
- Don't actually enable hardware interrupts unless we need to
  allow in IPIs.
- There is no point in enabling them when they are blocked in software
  (by splhigh()).
- Keep the splhigh() to avoid a load of the KASSERTS() firing.

Revision 1.1 / (download) - annotate - [select for diffs], Tue Feb 11 20:17:16 2014 UTC (4 years, 9 months ago) by dsl
Branch: MAIN

Move sys/arch/amd64/amd64/fpu.c and sys/arch/amd64/include/fpu.h
into sys/arch/x86 in preparation for using the same code for i386.

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