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CVS log for src/sys/arch/x86/x86/fpu.c

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Default branch: MAIN

Revision 1.86 / (download) - annotate - [select for diffs], Fri Mar 3 14:40:16 2023 UTC (3 months ago) by riastradh
Branch: MAIN
CVS Tags: HEAD
Changes since 1.85: +3 -3 lines
Diff to previous 1.85 (colored) 

x86/fpu: Align savefpu to 64 bytes in fpuinit_mxcsr_mask.

16 bytes is not enough.

(Is this why it never worked on Xen some years back?  Got lucky and
accidentally had 64-byte alignment on native x86, but not in the call
stack in Xen?)

XXX pullup-10

Revision 1.85 / (download) - annotate - [select for diffs], Fri Mar 3 14:32:48 2023 UTC (3 months ago) by riastradh
Branch: MAIN
Changes since 1.84: +14 -68 lines
Diff to previous 1.84 (colored) 

Revert "x86: Add kthread_fpu_enter/exit support, take two."

kthread_fpu_enter/exit changes broke some hardware, unclear why, to
investigate before fixing and reapplying these changes.

Revision 1.84 / (download) - annotate - [select for diffs], Fri Mar 3 14:32:38 2023 UTC (3 months ago) by riastradh
Branch: MAIN
Changes since 1.83: +19 -33 lines
Diff to previous 1.83 (colored) 

Revert "x86/fpu.c: Sprinkle KNF."

kthread_fpu_enter/exit changes broke some hardware, unclear why, to
investigate before fixing and reapplying these changes.

Revision 1.83 / (download) - annotate - [select for diffs], Sat Feb 25 18:28:57 2023 UTC (3 months ago) by riastradh
Branch: MAIN
Changes since 1.82: +33 -19 lines
Diff to previous 1.82 (colored) 

x86/fpu.c: Sprinkle KNF.

No functional change intended.

Revision 1.82 / (download) - annotate - [select for diffs], Sat Feb 25 18:04:42 2023 UTC (3 months ago) by riastradh
Branch: MAIN
Changes since 1.81: +68 -14 lines
Diff to previous 1.81 (colored) 

x86: Add kthread_fpu_enter/exit support, take two.

This time, make sure to restore the FPU state when switching to a
kthread in the middle of kthread_fpu_enter/exit.

This adds a single predicted-taken branch for the case of kthreads
that are not in kthread_fpu_enter/exit, so it incurs a penalty only
for threads that actually use it.  Since it avoids FPU state
switching in kthreads that do use the FPU, namely cgd worker threads,
this should be a net performance win on systems using it and have
negligible impact otherwise.

XXX pullup-10

Revision 1.81 / (download) - annotate - [select for diffs], Sat Feb 25 18:04:25 2023 UTC (3 months ago) by riastradh
Branch: MAIN
Changes since 1.80: +4 -4 lines
Diff to previous 1.80 (colored) 

x86: Label boolean is_64bit argument to fpu_area_restore.

No functional change intended.

Revision 1.80 / (download) - annotate - [select for diffs], Sat Feb 25 13:57:37 2023 UTC (3 months ago) by riastradh
Branch: MAIN
Changes since 1.79: +12 -2 lines
Diff to previous 1.79 (colored) 

x86: Mitigate MXCSR Configuration Dependent Timing in kernel FPU use.

In fpu_kern_enter, make sure all the MXCSR exception status bits are
set when we start using the FPU, so that instructions which exhibit
MCDT are unaffected by it.

While here, zero all the other FPU registers in fpu_kern_enter.

In principle we could skip this step on future CPUs that fix the MCDT
bug, but there's probably not much benefit -- workloads that do a lot
of crypto in the kernel are probably better off using
kthread_fpu_enter or WQ_FPU to skip the fpu_kern_enter/leave cycles
in the first place.

For details, see:
https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/mxcsr-configuration-dependent-timing.html

Revision 1.79 / (download) - annotate - [select for diffs], Sat Aug 20 11:34:08 2022 UTC (9 months, 1 week ago) by riastradh
Branch: MAIN
CVS Tags: netbsd-10-base, netbsd-10, bouyer-sunxi-drm-base, bouyer-sunxi-drm
Changes since 1.78: +16 -2 lines
Diff to previous 1.78 (colored) 

fpu_kern_enter/leave: Disable IPL assertions.

These don't work because mutex_enter/exit on a spin lock may raise an
IPL but not lower it, if another spin lock was already held.  For
example,

	mutex_enter(some_lock_at_IPL_VM);
	printf("foo\n");
	fpu_kern_enter();
	...
	fpu_kern_leave();
	mutex_exit(some_lock_at_IPL_VM);

will trigger the panic, because printf takes a lock at IPL_HIGH where
the IPL wil remain until the mutex_exit.  (This was a nightmare to
track down before I remembered that detail of spin lock IPL
semantics...)

Revision 1.78 / (download) - annotate - [select for diffs], Tue May 24 06:28:00 2022 UTC (12 months, 1 week ago) by andvar
Branch: MAIN
Changes since 1.77: +3 -3 lines
Diff to previous 1.77 (colored) 

fix various typos in comments, docs and log messages.

Revision 1.77 / (download) - annotate - [select for diffs], Fri Apr 1 19:57:22 2022 UTC (14 months ago) by riastradh
Branch: MAIN
Changes since 1.76: +5 -4 lines
Diff to previous 1.76 (colored) 

x86, arm: Allow fpu_kern_enter/leave while cold.

Normally these are forbidden above IPL_VM, so that FPU usage doesn't
block IPL_SCHED or IPL_HIGH interrupts.  But while cold, e.g. during
builtin module initialization at boot, all interrupts are blocked
anyway so it's a moot point.

Also initialize x86 cpu_info_primary.ci_kfpu_spl to -1 so we don't
trip over an assertion about it while cold -- the assertion is meant
to detect reentrance into fpu_kern_enter/leave, which is prohibited.

Also initialize cpu0's ci_kfpu_spl.

Revision 1.76 / (download) - annotate - [select for diffs], Sat Oct 24 07:14:30 2020 UTC (2 years, 7 months ago) by mgorny
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base, thorpej-i2c-spi-conf2, thorpej-i2c-spi-conf-base, thorpej-i2c-spi-conf, thorpej-futex2-base, thorpej-futex2, thorpej-futex-base, thorpej-futex, thorpej-cfargs2-base, thorpej-cfargs2, thorpej-cfargs-base, thorpej-cfargs, cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x
Changes since 1.75: +21 -13 lines
Diff to previous 1.75 (colored) 

Issue 64-bit versions of *XSAVE* for 64-bit amd64 programs

When calling FXSAVE, XSAVE, FXRSTOR, ... for 64-bit programs on amd64
use the 64-suffixed variant in order to include the complete FIP/FDP
registers in the x87 area.

The difference between the two variants is that the FXSAVE64 (new)
variant represents FIP/FDP as 64-bit fields (union fp_addr.fa_64),
while the legacy FXSAVE variant uses split fields: 32-bit offset,
16-bit segment and 16-bit reserved field (union fp_addr.fa_32).
The latter implies that the actual addresses are truncated to 32 bits
which is insufficient in modern programs.

The change is applied only to 64-bit programs on amd64.  Plain i386
and compat32 continue using plain FXSAVE.  Similarly, NVMM is not
changed as I am not familiar with that code.

This is a potentially breaking change.  However, I don't think it likely
to actually break anything because the data provided by the old variant
were not meaningful (because of the truncated pointer).

Revision 1.55.2.1 / (download) - annotate - [select for diffs], Sun Oct 18 18:42:10 2020 UTC (2 years, 7 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-3-RELEASE, netbsd-9-2-RELEASE, netbsd-9-1-RELEASE
Changes since 1.55: +24 -8 lines
Diff to previous 1.55 (colored) next main 1.56 (colored) 

Pull up following revision(s) (requested by kamil in ticket #1117):

	sys/arch/sh3/include/ptrace.h: revision 1.19
	sys/arch/amd64/amd64/process_machdep.c: revision 1.48
	sys/arch/sh3/sh3/process_machdep.c: revision 1.23
	sys/arch/sh3/sh3/process_machdep.c: revision 1.24
	sys/arch/i386/i386/process_machdep.c: revision 1.95
	sys/arch/x86/x86/fpu.c (apply patch)
	sys/kern/sys_ptrace_common.c: revision 1.84
	sys/arch/powerpc/powerpc/process_machdep.c: revision 1.40
	sys/sys/ptrace.h: revision 1.71
	sys/arch/powerpc/powerpc/process_machdep.c: revision 1.41
	(all via patch, adapted)

Fix s87_tw reconstruction to correctly indicate register states

Fix the code reconstructing s87_tw (full tag word) from fx_sw (abridged
tag word) to correctly represent all register states.  The previous code
only distinguished between empty/non-empty registers, and assigned
'regular value' to all non-empty registers.  The new code explicitly
distinguishes the two other tag word values: empty and special.

Fix the machine-dependent ptrace register-related requests (e.g.
PT_GETXMMREGS, PT_GETXSTATE on x86) to correctly respect the LWP number
passed as the data argument.  Before this change, these requests
did not operate on the requested LWP of a multithreaded program.
This change required moving ptrace_update_lwp() out of unit scope,
and changing ptrace_machdep_dorequest() function to take a pointer
to pointer as the second argument, consistently with ptrace_regs().

I am planning to extend the ATF ptrace() register tests in the future
to check for regressions in multithreaded programs, as time permits.

Reviewed by kamil.

Add missing 'error' declaration

Revision 1.75 / (download) - annotate - [select for diffs], Thu Oct 15 17:40:14 2020 UTC (2 years, 7 months ago) by mgorny
Branch: MAIN
Changes since 1.74: +2 -122 lines
Diff to previous 1.74 (colored) 

Revert "Merge convert_xmm_s87.c into fpu.c"

I am going to add ATF tests for these two functions, and having them
in a separate file will make it more convenient to build and run them
in userspace.

Revision 1.74 / (download) - annotate - [select for diffs], Sun Aug 2 18:23:33 2020 UTC (2 years, 10 months ago) by riastradh
Branch: MAIN
Changes since 1.73: +9 -62 lines
Diff to previous 1.73 (colored) 

Revert "Add kthread_fpu_enter/exit support to x86." for now.

Need to find all the paths out of interrupts back into _kernel_
context to add HANDLE_DEFERRED_FPU, I think, before this can be
enabled.

Revision 1.73 / (download) - annotate - [select for diffs], Sat Aug 1 02:13:34 2020 UTC (2 years, 10 months ago) by riastradh
Branch: MAIN
Changes since 1.72: +62 -9 lines
Diff to previous 1.72 (colored) 

Add kthread_fpu_enter/exit support to x86.

Revision 1.72 / (download) - annotate - [select for diffs], Mon Jul 20 16:43:03 2020 UTC (2 years, 10 months ago) by riastradh
Branch: MAIN
Changes since 1.71: +5 -7 lines
Diff to previous 1.71 (colored) 

Fix fpu_kern_enter in a softint that interrupted a softint.

We need to find the lwp that was originally interrupted to save its
fpu state.

With this, fpu-heavy programs (like firefox) are once again stable,
at least under modest stress testing, on systems configured to use
wifi with WPA2 and CCMP.

Revision 1.71 / (download) - annotate - [select for diffs], Mon Jul 20 16:41:18 2020 UTC (2 years, 10 months ago) by riastradh
Branch: MAIN
Changes since 1.70: +13 -6 lines
Diff to previous 1.70 (colored) 

Save fpu state at IPL_VM to exclude fpu_kern_enter/leave.

This way fpu_kern_enter/leave cannot interrupt the transition, so the
transition from state-on-CPU to state-in-memory (with TS set) is
atomic whether in an interrupt or not.

(I am not 100% convinced that this is necessary, but it makes
reasoning about the transition simpler.)

Revision 1.70 / (download) - annotate - [select for diffs], Mon Jul 20 16:38:47 2020 UTC (2 years, 10 months ago) by riastradh
Branch: MAIN
Changes since 1.69: +5 -29 lines
Diff to previous 1.69 (colored) 

Revert 1.66 "Fix race in fpu save with fpu_kern_enter in softint."

This only fixed part of the race, and we can do it more simply.

Revision 1.69 / (download) - annotate - [select for diffs], Mon Jul 20 16:37:34 2020 UTC (2 years, 10 months ago) by riastradh
Branch: MAIN
Changes since 1.68: +12 -16 lines
Diff to previous 1.68 (colored) 

Revert 1.67 "Restore the lwp's fpu state, not zeros, and leave with fpu enabled."

This didn't actually avoid double-restore, and it doesn't solve the
problem anyway, and made it harder to detect in-kernel fpu abuse.

Revision 1.68 / (download) - annotate - [select for diffs], Mon Jul 13 16:51:51 2020 UTC (2 years, 10 months ago) by riastradh
Branch: MAIN
Changes since 1.67: +9 -5 lines
Diff to previous 1.67 (colored) 

Limit x86 fpu_kern_enter/leave to IPL_VM or below.

There are no users of crypto at IPL_SCHED or IPL_HIGH as far as I
know, and although we generally limit the amount of time spent in any
one crypto operation -- e.g., cgd is usually limited to processing
512 or 4096 bytes at a time -- it's better not to block IPL_SCHED and
IPL_HIGH interrupts at all.  This should make ddb a little more
accessible during crypto-heavy workloads.

This means the aes_* API cannot be used at IPL_SCHED or IPL_HIGH; the
same will go for any new crypto subsystems, like the ChaCha and
Poly1305 ones I'm drafting.  It might be better to prohibit them
altogether in hard interrupt context, but right now cprng_fast and
cprng_strong are both technically allowed at IPL_VM and are sometimes
used there (e.g., for opencrypto CBC IV generation).

KASSERT the ilevel to detect violation of this constraint in case I'm
wrong.

Revision 1.67 / (download) - annotate - [select for diffs], Mon Jul 6 18:30:48 2020 UTC (2 years, 10 months ago) by riastradh
Branch: MAIN
Changes since 1.66: +16 -12 lines
Diff to previous 1.66 (colored) 

Restore the lwp's fpu state, not zeros, and leave with fpu enabled.

We need to clear the fpu state anyway because it is likely to contain
secrets at this point.  Previously we set it to zeros, and then issued
stts to disable the fpu in order to detect the mistake of further use
of the fpu in kernel.  But there must be some path I haven't identified
yet that doesn't do fpu_handle_deferred, leading to fpudna panics.

In any case, there's no benefit to restoring the fpu state twice
(once with zeros and once with the real data).  The downside is,
although this avoids spurious fpudna traps, using fpu_kern_enter in a
softint has the side effect that -- until the next userland context
switch triggering stts -- we no longer detect misuse of fpu in the
kernel in that lwp.  This will serve for now, but we should find
another way to issue clts/stts judiciously to detect such misuse.

May improve the continued symptoms of
https://mail-index.netbsd.org/current-users/2020/07/02/msg039051.html
although may not fix everything.

Revision 1.66 / (download) - annotate - [select for diffs], Mon Jul 6 01:08:15 2020 UTC (2 years, 10 months ago) by riastradh
Branch: MAIN
Changes since 1.65: +29 -5 lines
Diff to previous 1.65 (colored) 

Fix race in fpu save with fpu_kern_enter in softint.

Likely source of:

https://mail-index.netbsd.org/current-users/2020/07/02/msg039051.html

Revision 1.65 / (download) - annotate - [select for diffs], Sun Jun 14 16:12:05 2020 UTC (2 years, 11 months ago) by riastradh
Branch: MAIN
Changes since 1.64: +4 -5 lines
Diff to previous 1.64 (colored) 

Use static constant rather than stack memset buffer for zero fpregs.

Revision 1.64 / (download) - annotate - [select for diffs], Sat Jun 13 19:01:11 2020 UTC (2 years, 11 months ago) by riastradh
Branch: MAIN
Changes since 1.63: +16 -2 lines
Diff to previous 1.63 (colored) 

Add comments over fpu_kern_enter/leave.

Revision 1.63 / (download) - annotate - [select for diffs], Sat Jun 13 19:00:18 2020 UTC (2 years, 11 months ago) by riastradh
Branch: MAIN
Changes since 1.62: +11 -2 lines
Diff to previous 1.62 (colored) 

Zero the fpu registers on fpu_kern_leave.

Avoid Spectre-class attacks on any values left in them.

Revision 1.62 / (download) - annotate - [select for diffs], Thu Jun 4 19:53:55 2020 UTC (2 years, 11 months ago) by riastradh
Branch: MAIN
Changes since 1.61: +17 -2 lines
Diff to previous 1.61 (colored) 

Call clts/stts in fpu_kern_enter/leave so they work.

Revision 1.43.2.2 / (download) - annotate - [select for diffs], Mon Apr 13 08:04:11 2020 UTC (3 years, 1 month ago) by martin
Branch: phil-wifi
Changes since 1.43.2.1: +274 -347 lines
Diff to previous 1.43.2.1 (colored) to branchpoint 1.43 (colored) next main 1.44 (colored) 

Mostly merge changes from HEAD upto 20200411

Revision 1.60.2.1 / (download) - annotate - [select for diffs], Sat Feb 29 20:18:33 2020 UTC (3 years, 3 months ago) by ad
Branch: ad-namecache
Changes since 1.60: +3 -3 lines
Diff to previous 1.60 (colored) next main 1.61 (colored) 

Sync with head.

Revision 1.61 / (download) - annotate - [select for diffs], Fri Jan 31 08:55:38 2020 UTC (3 years, 4 months ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20200421, phil-wifi-20200411, phil-wifi-20200406, is-mlppp-base, is-mlppp, bouyer-xenpvh-base2, bouyer-xenpvh-base1, bouyer-xenpvh-base, bouyer-xenpvh, ad-namecache-base3
Changes since 1.60: +3 -3 lines
Diff to previous 1.60 (colored) 

'oldlwp' is never NULL now, so remove the NULL checks.

Revision 1.60 / (download) - annotate - [select for diffs], Wed Nov 27 06:24:33 2019 UTC (3 years, 6 months ago) by maxv
Branch: MAIN
CVS Tags: ad-namecache-base2, ad-namecache-base1, ad-namecache-base
Branch point for: ad-namecache
Changes since 1.59: +53 -9 lines
Diff to previous 1.59 (colored) 

Add a small API for in-kernel FPU operations.

	fpu_kern_enter();
	/* do FPU stuff */
	fpu_kern_leave();

Revision 1.59 / (download) - annotate - [select for diffs], Wed Oct 30 16:32:04 2019 UTC (3 years, 7 months ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20191119
Changes since 1.58: +24 -27 lines
Diff to previous 1.58 (colored) 

Style.

Revision 1.58 / (download) - annotate - [select for diffs], Sat Oct 12 06:31:04 2019 UTC (3 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.57: +93 -186 lines
Diff to previous 1.57 (colored) 

Rewrite the FPU code on x86. This greatly simplifies the logic and removes
the dependency on IPL_HIGH. NVMM is updated accordingly. Posted on
port-amd64 a week ago.

Bump the kernel version to 9.99.16.

Revision 1.57 / (download) - annotate - [select for diffs], Fri Oct 4 11:47:08 2019 UTC (3 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.56: +21 -36 lines
Diff to previous 1.56 (colored) 

Rename fpu_eagerswitch to fpu_switch, and add fpu_xstate_reload to
simplify.

Revision 1.56 / (download) - annotate - [select for diffs], Thu Oct 3 05:06:29 2019 UTC (3 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.55: +11 -179 lines
Diff to previous 1.55 (colored) 

Remove the LazyFPU code, as posted 5 months ago on port-amd64@.

Revision 1.55 / (download) - annotate - [select for diffs], Fri Jul 5 17:08:56 2019 UTC (3 years, 10 months ago) by maxv
Branch: MAIN
CVS Tags: netbsd-9-base, netbsd-9-0-RELEASE, netbsd-9-0-RC2, netbsd-9-0-RC1
Branch point for: netbsd-9
Changes since 1.54: +6 -3 lines
Diff to previous 1.54 (colored) 

More inlines, prerequisites for future changes. Also, remove fngetsw(),
which was a duplicate of fnstsw().

Revision 1.54 / (download) - annotate - [select for diffs], Wed Jun 26 12:30:13 2019 UTC (3 years, 11 months ago) by mgorny
Branch: MAIN
Changes since 1.53: +161 -2 lines
Diff to previous 1.53 (colored) 

Implement PT_GETXSTATE and PT_SETXSTATE

Introduce two new ptrace() requests: PT_GETXSTATE and PT_SETXSTATE,
that provide access to the extended (and extensible) set of FPU
registers on amd64 and i386.  At the moment, this covers AVX (YMM)
and AVX-512 (ZMM, opmask) registers.  It can be easily extended
to cover further register types without breaking backwards
compatibility.

PT_GETXSTATE issues the XSAVE instruction with all kernel-supported
extended components enabled.  The data is copied into 'struct xstate'
(which -- unlike the XSAVE area itself -- has stable format
and offsets).

PT_SETXSTATE issues the XRSTOR instruction to restore the register
values from user-provided 'struct xstate'.  The function replaces only
the specific XSAVE components that are listed in 'xs_rfbm' field,
making it possible to issue partial updates.

Both syscalls take a 'struct iovec' pointer rather than a direct
argument.  This requires the caller to explicitly specify the buffer
size.  As a result, existing code will continue to work correctly
when the structure is extended (performing partial reads/updates).

Revision 1.43.2.1 / (download) - annotate - [select for diffs], Mon Jun 10 22:06:53 2019 UTC (3 years, 11 months ago) by christos
Branch: phil-wifi
Changes since 1.43: +182 -192 lines
Diff to previous 1.43 (colored) 

Sync with HEAD

Revision 1.53 / (download) - annotate - [select for diffs], Sat May 25 21:02:32 2019 UTC (4 years ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20190609
Changes since 1.52: +3 -3 lines
Diff to previous 1.52 (colored) 

Fix bug. We must fetch the whole FPU state, otherwise XSTATE_BV could be
outdated, and we could be filling the AVX registers with garbage.

Revision 1.52 / (download) - annotate - [select for diffs], Sun May 19 08:46:15 2019 UTC (4 years ago) by maxv
Branch: MAIN
Changes since 1.51: +4 -4 lines
Diff to previous 1.51 (colored) 

Rename

	fpu_save_area_clear -> fpu_clear
	fpu_save_area_reset -> fpu_sigreset

Clearer, and reduces a future diff. No real functional change.

Revision 1.51 / (download) - annotate - [select for diffs], Sun May 19 08:17:02 2019 UTC (4 years ago) by maxv
Branch: MAIN
Changes since 1.50: +6 -6 lines
Diff to previous 1.50 (colored) 

Misc changes in the x86 FPU code. Reduces a future diff. No real functional
change.

Revision 1.50 / (download) - annotate - [select for diffs], Mon Feb 11 14:59:33 2019 UTC (4 years, 3 months ago) by cherry
Branch: MAIN
CVS Tags: isaki-audio2-base, isaki-audio2
Changes since 1.49: +5 -5 lines
Diff to previous 1.49 (colored) 

We reorganise definitions for XEN source support as follows:

XEN - common sources required for baseline XEN support.
XENPV - sources required for support of XEN in PV mode.
XENPVHVM - sources required for support for XEN in HVM mode.
XENPVH - sources required for support for XEN in PVH mode.

Revision 1.28.2.5 / (download) - annotate - [select for diffs], Sat Jan 26 22:00:05 2019 UTC (4 years, 4 months ago) by pgoyette
Branch: pgoyette-compat
CVS Tags: pgoyette-compat-merge-20190127
Changes since 1.28.2.4: +9 -9 lines
Diff to previous 1.28.2.4 (colored) to branchpoint 1.28 (colored) next main 1.29 (colored) 

Sync with HEAD

Revision 1.49 / (download) - annotate - [select for diffs], Sun Jan 20 16:55:21 2019 UTC (4 years, 4 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-20190127
Changes since 1.48: +9 -9 lines
Diff to previous 1.48 (colored) 

Improvements in NVMM

 * Handle the FPU differently, limit the states via the given mask rather
   than via XCR0. Align to 64 bytes. Provide an initial gXCR0, to be sure
   that XCR0_X87 is set. Reset XSTATE_BV when the state is modified by
   the virtualizer, to force a reload from memory.

 * Hide RDTSCP.

 * Zero-extend RBX/RCX/RDX when handling the NVMM CPUID signature.

 * Take ECX and not RCX on MSR instructions.

Revision 1.28.2.4 / (download) - annotate - [select for diffs], Sat Oct 20 06:58:29 2018 UTC (4 years, 7 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.28.2.3: +5 -6 lines
Diff to previous 1.28.2.3 (colored) to branchpoint 1.28 (colored) 

Sync with head

Revision 1.48 / (download) - annotate - [select for diffs], Fri Oct 5 18:51:52 2018 UTC (4 years, 7 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-20190118, pgoyette-compat-1226, pgoyette-compat-1126, pgoyette-compat-1020
Changes since 1.47: +5 -6 lines
Diff to previous 1.47 (colored) 

export x86_fpu_mxcsr_mask, fpu_area_save and fpu_area_restore

Revision 1.28.2.3 / (download) - annotate - [select for diffs], Sun Sep 30 01:45:48 2018 UTC (4 years, 8 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.28.2.2: +131 -159 lines
Diff to previous 1.28.2.2 (colored) to branchpoint 1.28 (colored) 

Ssync with HEAD

Revision 1.47 / (download) - annotate - [select for diffs], Mon Sep 17 15:53:06 2018 UTC (4 years, 8 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-0930
Changes since 1.46: +131 -159 lines
Diff to previous 1.46 (colored) 

Reduce the noise, reorder and rename some things for clarity.

Revision 1.28.2.2 / (download) - annotate - [select for diffs], Sat Jul 28 04:37:42 2018 UTC (4 years, 10 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.28.2.1: +40 -21 lines
Diff to previous 1.28.2.1 (colored) to branchpoint 1.28 (colored) 

Sync with HEAD

Revision 1.12.8.3 / (download) - annotate - [select for diffs], Tue Jul 10 15:35:26 2018 UTC (4 years, 10 months ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-2-RELEASE, netbsd-8-1-RELEASE, netbsd-8-1-RC1, netbsd-8-0-RELEASE
Changes since 1.12.8.2: +16 -2 lines
Diff to previous 1.12.8.2 (colored) to branchpoint 1.12 (colored) next main 1.13 (colored) 

Pull up the following, requested by maxv in ticket #910:

	sys/arch/amd64/amd64/locore.S	r1.167 (patch)
	sys/arch/i386/i386/locore.S	r1.158 (patch)
	sys/arch/x86/x86/fpu.c		r1.44 (patch)

Don't switch the FPU when leaving a softint. This fixes
several problems when EagerFPU is enabled.

Revision 1.46 / (download) - annotate - [select for diffs], Sun Jul 1 08:32:41 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-0906, pgoyette-compat-0728
Changes since 1.45: +5 -12 lines
Diff to previous 1.45 (colored) 

Use a variable-sized memcpy, instead of copying the PCB and then adding
the extra bytes. The PCB embeds the biggest static FPU state, but our
real FPU state may be smaller (FNSAVE), so we don't need to memcpy the
extra unused bytes.

Revision 1.45 / (download) - annotate - [select for diffs], Sun Jul 1 07:18:56 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.44: +23 -11 lines
Diff to previous 1.44 (colored) 

Use a switch, we can (and will) optimize each case separately. No
functional change.

Revision 1.44 / (download) - annotate - [select for diffs], Fri Jun 29 19:34:35 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.43: +16 -2 lines
Diff to previous 1.43 (colored) 

Add more KASSERTs.

Should help PR/53399.

Revision 1.28.2.1 / (download) - annotate - [select for diffs], Mon Jun 25 07:25:47 2018 UTC (4 years, 11 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.28: +373 -52 lines
Diff to previous 1.28 (colored) 

Sync with HEAD

Revision 1.12.8.2 / (download) - annotate - [select for diffs], Sat Jun 23 11:39:02 2018 UTC (4 years, 11 months ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-0-RC2
Changes since 1.12.8.1: +231 -37 lines
Diff to previous 1.12.8.1 (colored) to branchpoint 1.12 (colored) 

Pull up the following, via patch, requested by maxv in ticket #897:

	sys/arch/amd64/amd64/locore.S           1.166 (patch)
	sys/arch/i386/i386/locore.S             1.157 (patch)
	sys/arch/x86/include/cpu.h              1.92 (patch)
	sys/arch/x86/include/fpu.h              1.9 (patch)
	sys/arch/x86/x86/fpu.c                  1.33-1.39 (patch)
	sys/arch/x86/x86/identcpu.c             1.72 (patch)
	sys/arch/x86/x86/vm_machdep.c           1.34 (patch)
	sys/arch/x86/x86/x86_machdep.c          1.116,1.117 (patch)

Support eager fpu switch, to work around INTEL-SA-00145.
Provide a sysctl machdep.fpu_eager, which gets automatically
initialized to 1 on affected CPUs.

Revision 1.43 / (download) - annotate - [select for diffs], Sat Jun 23 10:06:02 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-base, pgoyette-compat-0625
Branch point for: phil-wifi
Changes since 1.42: +7 -2 lines
Diff to previous 1.42 (colored) 

Add XXX in fpuinit_mxcsr_mask.

Revision 1.42 / (download) - annotate - [select for diffs], Fri Jun 22 06:22:37 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.41: +7 -9 lines
Diff to previous 1.41 (colored) 

Revert jdolecek's changes related to FXSAVE. They just didn't make any
sense and were trying to hide a real bug, which is, that there is for some
reason a wrong stack alignment that causes FXSAVE to fault in
fpuinit_mxcsr_mask. As seen in current-users@ yesterday, rdi % 16 = 8. And
as seen several months ago, as well.

The rest of the changes in XSAVE are wrong too, but I'll let him fix these
ones.

Revision 1.41 / (download) - annotate - [select for diffs], Wed Jun 20 20:43:21 2018 UTC (4 years, 11 months ago) by jdolecek
Branch: MAIN
Changes since 1.40: +4 -4 lines
Diff to previous 1.40 (colored) 

as a stop-gap, make fpuinit_mxcsr_mask() for native independant of
XSAVE as it should be, only xen case checks the flag now; need to
investigate further why exactly the fault happens for the xen
no-xsave case

pointed out by maxv

Revision 1.40 / (download) - annotate - [select for diffs], Tue Jun 19 19:50:19 2018 UTC (4 years, 11 months ago) by jdolecek
Branch: MAIN
Changes since 1.39: +9 -7 lines
Diff to previous 1.39 (colored) 

fix FPU initialization on Xen to allow e.g. AVX when supported by hardware;
only use XSAVE when the the CPUID OSXSAVE bit is set, as this seems to be
reliable indication

tested with Xen 4.2.6 DOM0/DOMU on Intel CPU, without and with no-xsave flag,
so should work also on those AMD CPUs, which have XSAVE disabled by default;
also tested with Xen DOM0 4.8.3

fixes PR kern/50332 by Torbjorn Granlund; sorry it took three years to address

XXX pullup netbsd-8

Revision 1.39 / (download) - annotate - [select for diffs], Tue Jun 19 09:25:13 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.38: +17 -9 lines
Diff to previous 1.38 (colored) 

When using EagerFPU, create the fpu state in execve at IPL_HIGH.

A preemption could occur in the middle, and we don't want that to happen,
because the context switch would use the partially-constructed fpu state.

The procedure becomes:

	splhigh
	unbusy the current cpu's fpu
	create a new fpu state in memory
	install the state on the current cpu's fpu
	splx

Disabling preemption also ensures that x86_fpu_eager doesn't change in
the middle.

In LazyFPU mode we drop IPL_HIGH right away.

Add more KASSERTs.

Revision 1.38 / (download) - annotate - [select for diffs], Mon Jun 18 20:20:27 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.37: +6 -2 lines
Diff to previous 1.37 (colored) 

Add more KASSERTs, see if they help PR/53383.

Revision 1.37 / (download) - annotate - [select for diffs], Sun Jun 17 06:03:40 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.36: +12 -6 lines
Diff to previous 1.36 (colored) 

No, I meant to put the panic in fpudna not fputrap. Also appease it: panic
only if the fpu already has a state. We're fine with getting a DNA, what
we're not fine with is if the DNA is received while the FPU is busy.

I believe (even though I couldn't trigger it) that the panic would
otherwise fire if PT_SETFPREGS is used. And also ACPI sleep/wakeup,
probably.

Revision 1.36 / (download) - annotate - [select for diffs], Sat Jun 16 17:11:13 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.35: +117 -2 lines
Diff to previous 1.35 (colored) 

Need IPIs when enabling eager fpu switch, to clear each fpu and get us
started. Otherwise it is possible that the first context switch on one of
the cpus will restore an invalid fpu state in the new lwp, if that lwp
had its fpu state stored on another cpu that didn't have time to do an
fpu save since eager-fpu was enabled.

Use barriers and all the related crap. The point is that we want to
ensure that no context switch occurs between [each fpu is cleared] and
[x86_fpu_eager is set to 'true'].

Also add KASSERTs.

Revision 1.35 / (download) - annotate - [select for diffs], Sat Jun 16 05:52:17 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.34: +3 -13 lines
Diff to previous 1.34 (colored) 

Actually, don't do anything if we switch to a kernel thread. When the cpu
switches back to a user thread the fpu is restored, so no point calling
fninit (which doesn't clear all the states anyway).

Revision 1.34 / (download) - annotate - [select for diffs], Thu Jun 14 18:00:15 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.33: +10 -2 lines
Diff to previous 1.33 (colored) 

Install the FPU state on the current CPU in setregs (execve).

Revision 1.33 / (download) - annotate - [select for diffs], Thu Jun 14 14:36:46 2018 UTC (4 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.32: +110 -57 lines
Diff to previous 1.32 (colored) 

Add some code to support eager fpu switch, INTEL-SA-00145. We restore the
FPU state of the lwp right away during context switches. This guarantees
that when the CPU executes in userland, the FPU doesn't contain secrets.

Maybe we also need to clear the FPU in setregs(), not sure about this one.

Can be enabled/disabled via:

	machdep.fpu_eager = {0/1}

Not yet turned on automatically on affected CPUs (Intel Family 6).

More generally it would be good to turn it on automatically when XSAVEOPT
is supported, because in this case there is probably a non-negligible
performance gain; but we need to fix PR/52966.

Revision 1.32 / (download) - annotate - [select for diffs], Wed May 23 10:21:43 2018 UTC (5 years ago) by maxv
Branch: MAIN
Changes since 1.31: +6 -2 lines
Diff to previous 1.31 (colored) 

Add a comment about recent AMD CPUs.

Revision 1.31 / (download) - annotate - [select for diffs], Wed May 23 10:00:27 2018 UTC (5 years ago) by maxv
Branch: MAIN
Changes since 1.30: +27 -14 lines
Diff to previous 1.30 (colored) 

Clarify and extend the fix for the AMD FPU leaks. We were clearing the x87
state only on FXRSTOR, but the same problem exists on XRSTOR, so clear the
state there too.

Revision 1.30 / (download) - annotate - [select for diffs], Wed May 23 07:45:35 2018 UTC (5 years ago) by maxv
Branch: MAIN
Changes since 1.29: +122 -2 lines
Diff to previous 1.29 (colored) 

Merge convert_xmm_s87.c into fpu.c. It contains only two functions, that
are used only in fpu.c.

Revision 1.29 / (download) - annotate - [select for diffs], Wed May 23 07:34:40 2018 UTC (5 years ago) by maxv
Branch: MAIN
Changes since 1.28: +41 -46 lines
Diff to previous 1.28 (colored) 

style

Revision 1.28 / (download) - annotate - [select for diffs], Fri Feb 9 08:58:01 2018 UTC (5 years, 3 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-base, pgoyette-compat-0521, pgoyette-compat-0502, pgoyette-compat-0422, pgoyette-compat-0415, pgoyette-compat-0407, pgoyette-compat-0330, pgoyette-compat-0322, pgoyette-compat-0315
Branch point for: pgoyette-compat
Changes since 1.27: +13 -4 lines
Diff to previous 1.27 (colored) 

Force a reload of CW in fpu_set_default_cw(). This function is used only
in COMPAT_FREEBSD, it really needs to die.

Revision 1.12.8.1 / (download) - annotate - [select for diffs], Thu Dec 21 19:33:15 2017 UTC (5 years, 5 months ago) by snj
Branch: netbsd-8
CVS Tags: netbsd-8-0-RC1
Changes since 1.12: +3 -2 lines
Diff to previous 1.12 (colored) 

Pull up following revision(s) (requested by maxv in ticket #442):
	sys/arch/x86/x86/fpu.c: 1.19 via patch
Mask mxcsr, otherwise userland could set reserved bits to 1 and make
xrstor fault.

Revision 1.9.8.1 / (download) - annotate - [select for diffs], Tue Dec 12 09:12:57 2017 UTC (5 years, 5 months ago) by snj
Branch: netbsd-7
CVS Tags: netbsd-7-2-RELEASE
Changes since 1.9: +3 -2 lines
Diff to previous 1.9 (colored) next main 1.10 (colored) 

Pull up following revision(s) (requested by maxv in ticket #1540):
	sys/arch/x86/x86/fpu.c: 1.19 via patch
Mask mxcsr, otherwise userland could set reserved bits to 1 and make
xrstor fault.

Revision 1.9.16.1 / (download) - annotate - [select for diffs], Tue Dec 12 09:12:53 2017 UTC (5 years, 5 months ago) by snj
Branch: netbsd-7-1
CVS Tags: netbsd-7-1-2-RELEASE, netbsd-7-1-1-RELEASE
Changes since 1.9: +3 -2 lines
Diff to previous 1.9 (colored) next main 1.10 (colored) 

Pull up following revision(s) (requested by maxv in ticket #1540):
	sys/arch/x86/x86/fpu.c: 1.19 via patch
Mask mxcsr, otherwise userland could set reserved bits to 1 and make
xrstor fault.

Revision 1.9.12.1 / (download) - annotate - [select for diffs], Tue Dec 12 09:12:50 2017 UTC (5 years, 5 months ago) by snj
Branch: netbsd-7-0
Changes since 1.9: +3 -2 lines
Diff to previous 1.9 (colored) next main 1.10 (colored) 

Pull up following revision(s) (requested by maxv in ticket #1540):
	sys/arch/x86/x86/fpu.c: 1.19 via patch
Mask mxcsr, otherwise userland could set reserved bits to 1 and make
xrstor fault.

Revision 1.9.10.3 / (download) - annotate - [select for diffs], Sun Dec 3 11:36:50 2017 UTC (5 years, 6 months ago) by jdolecek
Branch: tls-maxphys
Changes since 1.9.10.2: +163 -136 lines
Diff to previous 1.9.10.2 (colored) to branchpoint 1.9 (colored) next main 1.10 (colored) 

update from HEAD

Revision 1.27 / (download) - annotate - [select for diffs], Sat Nov 11 11:00:46 2017 UTC (5 years, 6 months ago) by maxv
Branch: MAIN
CVS Tags: tls-maxphys-base-20171202
Changes since 1.26: +5 -9 lines
Diff to previous 1.26 (colored) 

Recommit

http://mail-index.netbsd.org/source-changes/2017/11/08/msg089525.html

but use __INITIAL_MXCSR_MASK__ on Xen until someone figures out what's
wrong with the Xen fpu.

Revision 1.26 / (download) - annotate - [select for diffs], Sat Nov 11 09:10:19 2017 UTC (5 years, 6 months ago) by bouyer
Branch: MAIN
Changes since 1.25: +13 -5 lines
Diff to previous 1.25 (colored) 

Revert http://mail-index.netbsd.org/source-changes/2017/11/08/msg089525.html,
it breaks Xen:
http://www-soc.lip6.fr/~bouyer/NetBSD-tests/xen/HEAD/amd64/201711082340Z_anita.txt

Revision 1.25 / (download) - annotate - [select for diffs], Wed Nov 8 17:52:22 2017 UTC (5 years, 6 months ago) by maxv
Branch: MAIN
Changes since 1.24: +3 -11 lines
Diff to previous 1.24 (colored) 

Call fpuinit_mxcsr_mask in cpu_init, after cr4 is initialized, but before
touching xcr0. Then use clts/stts instead of modifying cr0, and enable the
mxcsr_mask detection on Xen.

Revision 1.24 / (download) - annotate - [select for diffs], Sat Nov 4 08:58:30 2017 UTC (5 years, 6 months ago) by maxv
Branch: MAIN
Changes since 1.23: +7 -3 lines
Diff to previous 1.23 (colored) 

Add support for xsaveopt. It is basically an instruction that optimizes
context switch performance by not saving to memory FPU registers that are
known to be in their initial state or known not to have changed since the
last time they were saved to memory.

Our code is now compatible with the internal state tracking engine:
 - We don't modify the in-memory FPU state after doing an XSAVE/XSAVEOPT.
   That is to say, we always call XRSTOR first.
 - During a fork, the whole in-memory FPU state area is memcopied in the
   new PCB, and CR0_TS is set. Next time the forked thread uses the FPU it
   will fault, we migrate the area, call XRSTOR and clear CR0_TS. During
   this XRSTOR XSTATE_BV still contains the initial values, and it forces
   a reload of XINUSE.
 - Whenever software wants to change the in-memory FPU state, it manually
   sets XSTATE_BV[i]=1, which forces XINUSE[i]=1.
 - The address of the state passed to xrstor is always the same for a
   given LWP.

fpu_save_area_clear is changed not to force a reload of CW if fx_cw is
the standard FPU value. This way we have XINUSE[i]=0 for x87, and xsaveopt
will optimize this state.

Small benchmark:
	switch lwp to cpu2
	do float operation
	switch lwp to cpu3
	do float operation
Doing this 10^6 times in a loop, my cpu goes on average from 28,2 seconds
to 20,8 seconds.

Revision 1.23 / (download) - annotate - [select for diffs], Sat Nov 4 07:38:42 2017 UTC (5 years, 6 months ago) by maxv
Branch: MAIN
Changes since 1.22: +7 -0 lines
Diff to previous 1.22 (colored) 

Always set XCR0_X87, to force a reload of CW. That's needed for compat
options where fx_cw is not the standard fpu value.

Revision 1.22 / (download) - annotate - [select for diffs], Sat Nov 4 07:35:00 2017 UTC (5 years, 6 months ago) by maxv
Branch: MAIN
Changes since 1.21: +9 -2 lines
Diff to previous 1.21 (colored) 

Fix xen. Not tested, but seems fine enough.

Revision 1.21 / (download) - annotate - [select for diffs], Fri Nov 3 07:14:24 2017 UTC (5 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.20: +36 -3 lines
Diff to previous 1.20 (colored) 

Fix MXCSR_MASK, it needs to be detected dynamically, otherwise when masking
MXCSR we are losing some features (eg DAZ).

Revision 1.20 / (download) - annotate - [select for diffs], Tue Oct 31 18:23:29 2017 UTC (5 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.19: +1 -1 lines
Diff to previous 1.19 (colored) 

Zero out the buffer entirely.

Revision 1.19 / (download) - annotate - [select for diffs], Tue Oct 31 18:13:37 2017 UTC (5 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.18: +7 -3 lines
Diff to previous 1.18 (colored) 

Mask mxcsr, otherwise userland could set reserved bits to 1 and make
xrstor fault.

Revision 1.18 / (download) - annotate - [select for diffs], Tue Oct 31 15:16:10 2017 UTC (5 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.17: +22 -2 lines
Diff to previous 1.17 (colored) 

Initialize xstate_bv with the structures that were just filled in,
otherwise xrstor does not restore them. This can happen only if userland
calls setcontext without having used the FPU before.

Until rev1.15 xstate_bv was implicitly initialized because the xsave area
was not zeroed out properly.

Revision 1.17 / (download) - annotate - [select for diffs], Tue Oct 31 12:02:20 2017 UTC (5 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.16: +10 -6 lines
Diff to previous 1.16 (colored) 

Don't embed our own values in the reserved fields of the XSAVE area, it
really is a bad idea. Move them into the PCB.

Revision 1.16 / (download) - annotate - [select for diffs], Tue Oct 31 11:37:05 2017 UTC (5 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.15: +27 -16 lines
Diff to previous 1.15 (colored) 

Always use x86_fpu_save, clearer.

Revision 1.15 / (download) - annotate - [select for diffs], Tue Oct 31 10:35:58 2017 UTC (5 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.14: +13 -25 lines
Diff to previous 1.14 (colored) 

Remove comments that are more misleading than anything else. While here
make sure we zero out the FPU area entirely, and not just its legacy
region.

Revision 1.14 / (download) - annotate - [select for diffs], Mon Oct 9 17:49:28 2017 UTC (5 years, 7 months ago) by maya
Branch: MAIN
Changes since 1.13: +2 -28 lines
Diff to previous 1.13 (colored) 

GC i386_fpu_present. no FPU x86 is not supported.

Also delete newly unused send_sigill

Revision 1.13 / (download) - annotate - [select for diffs], Sun Sep 17 09:41:35 2017 UTC (5 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.12: +4 -4 lines
Diff to previous 1.12 (colored) 

Remove the second argument from USERMODE and KERNELMODE, it is unused
now that we don't have vm86 anymore.

Revision 1.10.4.1 / (download) - annotate - [select for diffs], Fri Nov 4 14:49:06 2016 UTC (6 years, 6 months ago) by pgoyette
Branch: pgoyette-localcount
Changes since 1.10: +44 -62 lines
Diff to previous 1.10 (colored) next main 1.11 (colored) 

Sync with HEAD

Revision 1.10.2.1 / (download) - annotate - [select for diffs], Wed Oct 5 20:55:37 2016 UTC (6 years, 7 months ago) by skrll
Branch: nick-nhusb
Changes since 1.10: +49 -70 lines
Diff to previous 1.10 (colored) next main 1.11 (colored) 

Sync with HEAD

Revision 1.12 / (download) - annotate - [select for diffs], Thu Sep 29 17:01:43 2016 UTC (6 years, 8 months ago) by maxv
Branch: MAIN
CVS Tags: prg-localcount2-base3, prg-localcount2-base2, prg-localcount2-base1, prg-localcount2-base, prg-localcount2, pgoyette-localcount-20170426, pgoyette-localcount-20170320, pgoyette-localcount-20170107, pgoyette-localcount-20161104, perseant-stdc-iso10646-base, perseant-stdc-iso10646, nick-nhusb-base-20170825, nick-nhusb-base-20170204, nick-nhusb-base-20161204, nick-nhusb-base-20161004, netbsd-8-base, matt-nb8-mediatek-base, matt-nb8-mediatek, jdolecek-ncq-base, jdolecek-ncq, bouyer-socketcan-base1, bouyer-socketcan-base, bouyer-socketcan
Branch point for: netbsd-8
Changes since 1.11: +40 -63 lines
Diff to previous 1.11 (colored) 

Remove outdated comments, typos, rename and reorder a few things.

Revision 1.11 / (download) - annotate - [select for diffs], Thu Aug 18 12:36:35 2016 UTC (6 years, 9 months ago) by maxv
Branch: MAIN
CVS Tags: localcount-20160914
Changes since 1.10: +13 -11 lines
Diff to previous 1.10 (colored) 

Simplify.

Revision 1.10 / (download) - annotate - [select for diffs], Thu Nov 27 14:22:09 2014 UTC (8 years, 6 months ago) by uebayasi
Branch: MAIN
CVS Tags: pgoyette-localcount-base, pgoyette-localcount-20160806, pgoyette-localcount-20160726, nick-nhusb-base-20160907, nick-nhusb-base-20160529, nick-nhusb-base-20160422, nick-nhusb-base-20160319, nick-nhusb-base-20151226, nick-nhusb-base-20150921, nick-nhusb-base-20150606, nick-nhusb-base-20150406, nick-nhusb-base
Branch point for: pgoyette-localcount, nick-nhusb
Changes since 1.9: +4 -4 lines
Diff to previous 1.9 (colored) 

Consistently use kpreempt_*() outside scheduler path.

Revision 1.9.10.2 / (download) - annotate - [select for diffs], Wed Aug 20 00:03:29 2014 UTC (8 years, 9 months ago) by tls
Branch: tls-maxphys
Changes since 1.9.10.1: +673 -0 lines
Diff to previous 1.9.10.1 (colored) to branchpoint 1.9 (colored) 

Rebase to HEAD as of a few days ago.

Revision 1.9.6.2 / (download) - annotate - [select for diffs], Thu May 22 11:40:14 2014 UTC (9 years ago) by yamt
Branch: yamt-pagecache
Changes since 1.9.6.1: +673 -0 lines
Diff to previous 1.9.6.1 (colored) to branchpoint 1.9 (colored) next main 1.10 (colored) 

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

Revision 1.9.4.2 / (download) - annotate - [select for diffs], Sun May 18 17:45:30 2014 UTC (9 years ago) by rmind
Branch: rmind-smpnet
Changes since 1.9.4.1: +673 -0 lines
Diff to previous 1.9.4.1 (colored) to branchpoint 1.9 (colored) next main 1.10 (colored) 

sync with head

Revision 1.9.10.1, Tue Feb 25 22:16:52 2014 UTC (9 years, 3 months ago) by tls
Branch: tls-maxphys
Changes since 1.9: +0 -673 lines
FILE REMOVED 

file fpu.c was added on branch tls-maxphys on 2014-08-20 00:03:29 +0000

Revision 1.9.6.1, Tue Feb 25 22:16:52 2014 UTC (9 years, 3 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.9: +0 -673 lines
FILE REMOVED 

file fpu.c was added on branch yamt-pagecache on 2014-05-22 11:40:14 +0000

Revision 1.9.4.1, Tue Feb 25 22:16:52 2014 UTC (9 years, 3 months ago) by rmind
Branch: rmind-smpnet
Changes since 1.9: +0 -673 lines
FILE REMOVED 

file fpu.c was added on branch rmind-smpnet on 2014-05-18 17:45:30 +0000

Revision 1.9 / (download) - annotate - [select for diffs], Tue Feb 25 22:16:52 2014 UTC (9 years, 3 months ago) by dsl
Branch: MAIN
CVS Tags: yamt-pagecache-base9, tls-maxphys-base, tls-earlyentropy-base, tls-earlyentropy, rmind-smpnet-nbase, rmind-smpnet-base, riastradh-xf86-video-intel-2-7-1-pre-2-21-15, riastradh-drm2-base3, netbsd-7-nhusb-base-20170116, netbsd-7-nhusb-base, netbsd-7-nhusb, netbsd-7-base, netbsd-7-1-RELEASE, netbsd-7-1-RC2, netbsd-7-1-RC1, netbsd-7-0-RELEASE, netbsd-7-0-RC3, netbsd-7-0-RC2, netbsd-7-0-RC1, netbsd-7-0-2-RELEASE, netbsd-7-0-1-RELEASE
Branch point for: yamt-pagecache, tls-maxphys, rmind-smpnet, netbsd-7-1, netbsd-7-0, netbsd-7
Changes since 1.8: +45 -19 lines
Diff to previous 1.8 (colored) 

Add support for saving the AVX-256 ymm registers during FPU context switches.
Add support for the forthcoming AVX-512 registers.
Code compiled with -mavx seems to work, but I've not tested context
  switches with live ymm registers.
There is a small cost on fork/exec (a larger area is copied/zerod),
  but I don't think the ymm registers are read/written unless they
  have been used.
The code use XSAVE on all cpus, I'm not brave enough to enable XSAVEOPT.

Revision 1.8 / (download) - annotate - [select for diffs], Sun Feb 23 22:35:28 2014 UTC (9 years, 3 months ago) by dsl
Branch: MAIN
Changes since 1.7: +14 -2 lines
Diff to previous 1.7 (colored) 

Add fpu_set_default_cw() and use it in the emulations to set the default
  x87 control word.
This means that nothing outside fpu.c cares about the internals of the
  fpu save area.
New kernel modules won't load with the old kernel - but that won't matter.

Revision 1.7 / (download) - annotate - [select for diffs], Sun Feb 23 12:56:40 2014 UTC (9 years, 3 months ago) by dsl
Branch: MAIN
Changes since 1.6: +5 -28 lines
Diff to previous 1.6 (colored) 

Determine whether the cpu supports xsave (and hence AVX).
The result is only written to sysctl nodes at the moment.
I see:
machdep.fpu_save = 3 (implies xsaveopt)
machdep.xsave_size = 832
machdep.xsave_features = 7
Completely common up the i386 and amd64 machdep sysctl creation.

Revision 1.6 / (download) - annotate - [select for diffs], Sat Feb 15 22:20:42 2014 UTC (9 years, 3 months ago) by dsl
Branch: MAIN
Changes since 1.5: +83 -7 lines
Diff to previous 1.5 (colored) 

Load and save the fpu registers (for copies to/from userspace) using
  helper functions in arch/x86/x86/fpu.c
They (hopefully) ensure that we write to the entire buffer and don't load
  values that might cause faults in kernel.
Also zero out the 'pad' field of the i386 mcontext fp area that I think
  once contained the registers of any Weitek fpu.
  Dunno why it wasn't pasrt of the union.
Some of these copies could be removed if the code directly copied the save
  area to/from userspace addresses.

Revision 1.5 / (download) - annotate - [select for diffs], Sat Feb 15 10:11:15 2014 UTC (9 years, 3 months ago) by dsl
Branch: MAIN
Changes since 1.4: +55 -27 lines
Diff to previous 1.4 (colored) 

Remove all references to MDL_USEDFPU and deferred fpu initialisation.
The cost of zeroing the save area on exec is minimal.
This stops the FP registers of a random process being used the first
  time an lwp uses the fpu.
sendsig_siginfo() and get_mcontext() now unconditionally copy the FP
registers.
I'll remove the double-copy for signal handlers soon.
get_mcontext() might have been leaking kernel memory to userspace - and
  may still do so if i386_use_fxsave is false (short copies).

Revision 1.4 / (download) - annotate - [select for diffs], Thu Feb 13 19:37:08 2014 UTC (9 years, 3 months ago) by dsl
Branch: MAIN
Changes since 1.3: +4 -4 lines
Diff to previous 1.3 (colored) 

Check the argument types for the fpu asm functions.

Revision 1.3 / (download) - annotate - [select for diffs], Wed Feb 12 23:24:09 2014 UTC (9 years, 3 months ago) by dsl
Branch: MAIN
Changes since 1.2: +81 -23 lines
Diff to previous 1.2 (colored) 

Change i386 to use x86/fpu.c instead of i386/isa/npx.c
This changes the trap10 and trap13 code to call directly into fpu.c,
  removing all the code for T_ARITHTRAP, T_XMM and T_FPUNDA from i386/trap.c
Not all of the code thate appeared to handle fpu traps was ever called!
Most of the changes just replace the include of machine/npx.h with x86/fpu.h
  (or remove it entirely).

Revision 1.2 / (download) - annotate - [select for diffs], Wed Feb 12 19:53:49 2014 UTC (9 years, 3 months ago) by dsl
Branch: MAIN
Changes since 1.1: +20 -8 lines
Diff to previous 1.1 (colored) 

Change the argument to fpudna() to be the trapframe.
Move the checks for fpu traps in kernel into x86/fpu.c.
Remove the code from amd64/trap.c related to fpu traps (they've not gone
  there for ages - expect to panic in kernel mode).
In fpudna():
- Don't actually enable hardware interrupts unless we need to
  allow in IPIs.
- There is no point in enabling them when they are blocked in software
  (by splhigh()).
- Keep the splhigh() to avoid a load of the KASSERTS() firing.

Revision 1.1 / (download) - annotate - [select for diffs], Tue Feb 11 20:17:16 2014 UTC (9 years, 3 months ago) by dsl
Branch: MAIN 

Move sys/arch/amd64/amd64/fpu.c and sys/arch/amd64/include/fpu.h
into sys/arch/x86 in preparation for using the same code for i386.

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