Annotation of src/sys/arch/x86/pci/pci_machdep.c, Revision 1.91
1.91 ! bouyer 1: /* $NetBSD: pci_machdep.c,v 1.90 2022/05/23 15:03:05 bouyer Exp $ */
1.1 fvdl 2:
3: /*-
4: * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
5: * All rights reserved.
6: *
7: * This code is derived from software contributed to The NetBSD Foundation
8: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9: * NASA Ames Research Center.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: *
20: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30: * POSSIBILITY OF SUCH DAMAGE.
31: */
32:
33: /*
34: * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
35: * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
36: *
37: * Redistribution and use in source and binary forms, with or without
38: * modification, are permitted provided that the following conditions
39: * are met:
40: * 1. Redistributions of source code must retain the above copyright
41: * notice, this list of conditions and the following disclaimer.
42: * 2. Redistributions in binary form must reproduce the above copyright
43: * notice, this list of conditions and the following disclaimer in the
44: * documentation and/or other materials provided with the distribution.
45: * 3. All advertising materials mentioning features or use of this software
46: * must display the following acknowledgement:
47: * This product includes software developed by Charles M. Hannum.
48: * 4. The name of the author may not be used to endorse or promote products
49: * derived from this software without specific prior written permission.
50: *
51: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
52: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
53: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
54: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
55: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
56: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
60: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61: */
62:
63: /*
64: * Machine-specific functions for PCI autoconfiguration.
65: *
66: * On PCs, there are two methods of generating PCI configuration cycles.
67: * We try to detect the appropriate mechanism for this machine and set
68: * up a few function pointers to access the correct method directly.
69: *
70: * The configuration method can be hard-coded in the config file by
71: * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
1.55 jakllsch 72: * as defined in section 3.6.4.1, `Generating Configuration Cycles'.
1.1 fvdl 73: */
74:
75: #include <sys/cdefs.h>
1.91 ! bouyer 76: __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.90 2022/05/23 15:03:05 bouyer Exp $");
1.1 fvdl 77:
78: #include <sys/types.h>
79: #include <sys/param.h>
80: #include <sys/time.h>
81: #include <sys/systm.h>
82: #include <sys/errno.h>
83: #include <sys/device.h>
1.29 ad 84: #include <sys/bus.h>
1.42 dyoung 85: #include <sys/cpu.h>
1.43 dyoung 86: #include <sys/kmem.h>
1.1 fvdl 87:
88: #include <uvm/uvm_extern.h>
89:
1.10 yamt 90: #include <machine/bus_private.h>
1.1 fvdl 91:
92: #include <machine/pio.h>
1.30 ad 93: #include <machine/lock.h>
1.1 fvdl 94:
1.3 fvdl 95: #include <dev/isa/isareg.h>
1.1 fvdl 96: #include <dev/isa/isavar.h>
97: #include <dev/pci/pcivar.h>
98: #include <dev/pci/pcireg.h>
1.43 dyoung 99: #include <dev/pci/pccbbreg.h>
1.1 fvdl 100: #include <dev/pci/pcidevs.h>
1.80 nonaka 101: #include <dev/pci/ppbvar.h>
1.52 dyoung 102: #include <dev/pci/genfb_pcivar.h>
103:
104: #include <dev/wsfb/genfbvar.h>
105: #include <arch/x86/include/genfb_machdep.h>
106: #include <dev/ic/vgareg.h>
1.1 fvdl 107:
1.37 jmcneill 108: #include "acpica.h"
1.52 dyoung 109: #include "genfb.h"
110: #include "isa.h"
111: #include "opt_acpi.h"
112: #include "opt_ddb.h"
1.14 bouyer 113: #include "opt_mpbios.h"
1.64 msaitoh 114: #include "opt_puc.h"
1.52 dyoung 115: #include "opt_vga.h"
116: #include "pci.h"
117: #include "wsdisplay.h"
1.58 soren 118: #include "com.h"
1.52 dyoung 119:
120: #ifdef DDB
121: #include <machine/db_machdep.h>
122: #include <ddb/db_sym.h>
123: #include <ddb/db_extern.h>
124: #endif
125:
126: #ifdef VGA_POST
127: #include <x86/vga_post.h>
128: #endif
129:
1.70 knakahar 130: #include <x86/cpuvar.h>
131:
1.52 dyoung 132: #include <machine/autoconf.h>
133: #include <machine/bootinfo.h>
1.14 bouyer 134:
135: #ifdef MPBIOS
136: #include <machine/mpbiosvar.h>
137: #endif
138:
1.37 jmcneill 139: #if NACPICA > 0
1.14 bouyer 140: #include <machine/mpacpi.h>
1.71 msaitoh 141: #if !defined(NO_PCI_EXTENDED_CONFIG)
142: #include <dev/acpi/acpivar.h>
143: #include <dev/acpi/acpi_mcfg.h>
144: #endif
1.14 bouyer 145: #endif
146:
1.16 christos 147: #include <machine/mpconfig.h>
148:
1.58 soren 149: #if NCOM > 0
150: #include <dev/pci/puccn.h>
151: #endif
152:
1.84 cherry 153: #ifndef XENPV
1.80 nonaka 154: #include <x86/efi.h>
155: #endif
156:
1.1 fvdl 157: #include "opt_pci_conf_mode.h"
158:
1.38 dyoung 159: #ifdef PCI_CONF_MODE
160: #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2)
161: static int pci_mode = PCI_CONF_MODE;
162: #else
163: #error Invalid PCI configuration mode.
164: #endif
165: #else
166: static int pci_mode = -1;
167: #endif
1.1 fvdl 168:
1.42 dyoung 169: struct pci_conf_lock {
170: uint32_t cl_cpuno; /* 0: unlocked
171: * 1 + n: locked by CPU n (0 <= n)
172: */
173: uint32_t cl_sel; /* the address that's being read. */
174: };
175:
176: static void pci_conf_unlock(struct pci_conf_lock *);
177: static uint32_t pci_conf_selector(pcitag_t, int);
178: static unsigned int pci_conf_port(pcitag_t, int);
179: static void pci_conf_select(uint32_t);
180: static void pci_conf_lock(struct pci_conf_lock *, uint32_t);
1.11 sekiya 181: static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *);
182: struct pci_bridge_hook_arg {
1.55 jakllsch 183: void (*func)(pci_chipset_tag_t, pcitag_t, void *);
184: void *arg;
185: };
1.11 sekiya 186:
1.1 fvdl 187: #define PCI_MODE1_ENABLE 0x80000000UL
188: #define PCI_MODE1_ADDRESS_REG 0x0cf8
189: #define PCI_MODE1_DATA_REG 0x0cfc
190:
191: #define PCI_MODE2_ENABLE_REG 0x0cf8
192: #define PCI_MODE2_FORWARD_REG 0x0cfa
193:
1.56 jakllsch 194: #define _tag(b, d, f) \
195: {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)}
1.1 fvdl 196: #define _qe(bus, dev, fcn, vend, prod) \
1.56 jakllsch 197: {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)}
198: const struct {
199: pcitag_t tag;
1.1 fvdl 200: pcireg_t id;
201: } pcim1_quirk_tbl[] = {
1.56 jakllsch 202: _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */
1.1 fvdl 203: _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1),
204: /* XXX Triflex2 not tested */
205: _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2),
206: _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4),
1.82 jakllsch 207: #if 0
1.1 fvdl 208: /* Triton needed for Connectix Virtual PC */
209: _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX),
210: /* Connectix Virtual PC 5 has a 440BX */
211: _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP),
1.15 soren 212: /* Parallels Desktop for Mac */
213: _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO),
214: _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS),
1.36 drochner 215: /* SIS 740 */
216: _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740),
1.12 christos 217: /* SIS 741 */
218: _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741),
1.54 tsutsui 219: /* VIA Technologies VX900 */
1.56 jakllsch 220: _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB)
1.82 jakllsch 221: #endif
1.1 fvdl 222: };
1.56 jakllsch 223: #undef _tag
1.1 fvdl 224: #undef _qe
225:
1.70 knakahar 226: /* arch/xen does not support MSI/MSI-X yet. */
227: #ifdef __HAVE_PCI_MSI_MSIX
228: #define PCI_QUIRK_DISABLE_MSI 1 /* Neigher MSI nor MSI-X work */
229: #define PCI_QUIRK_DISABLE_MSIX 2 /* MSI-X does not work */
230: #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI and MSI-X works */
231:
232: #define _dme(vend, prod) \
233: { PCI_QUIRK_DISABLE_MSI, PCI_ID_CODE(vend, prod) }
234: #define _dmxe(vend, prod) \
235: { PCI_QUIRK_DISABLE_MSIX, PCI_ID_CODE(vend, prod) }
236: #define _emve(vend, prod) \
237: { PCI_QUIRK_ENABLE_MSI_VM, PCI_ID_CODE(vend, prod) }
238: const struct {
239: int type;
240: pcireg_t id;
241: } pci_msi_quirk_tbl[] = {
242: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCMC),
243: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX),
244: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437MX),
245: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437VX),
246: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439HX),
247: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439TX),
248: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX),
249: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_AGP),
250: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX),
251: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX),
252: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX),
253: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_AGP),
254: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP),
255: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_NOAGP),
256: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX),
257: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX_AGP),
258: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810_MCH),
259: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810E_MCH),
260: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82815_FULL_HUB),
261: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82820_MCH),
262: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82830MP_IO_1),
263: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82840_HB),
264: _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_PCHB),
265: _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_PCHB),
266: _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC751_SC),
267: _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC761_SC),
268: _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC762_NB),
269:
270: _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), /* QEMU */
271: _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), /* VMWare */
272: };
273: #undef _dme
274: #undef _dmxe
275: #undef _emve
276: #endif /* __HAVE_PCI_MSI_MSIX */
277:
1.1 fvdl 278: /*
279: * PCI doesn't have any special needs; just use the generic versions
280: * of these functions.
281: */
282: struct x86_bus_dma_tag pci_bus_dma_tag = {
1.46 christos 283: ._tag_needs_free = 0,
1.3 fvdl 284: #if defined(_LP64) || defined(PAE)
1.46 christos 285: ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD,
286: ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD,
287: ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD,
1.3 fvdl 288: #else
1.46 christos 289: ._bounce_thresh = 0,
290: ._bounce_alloc_lo = 0,
291: ._bounce_alloc_hi = 0,
292: #endif
293: ._may_bounce = NULL,
1.1 fvdl 294: };
1.5 fvdl 295:
296: #ifdef _LP64
297: struct x86_bus_dma_tag pci_bus_dma64_tag = {
1.46 christos 298: ._tag_needs_free = 0,
299: ._bounce_thresh = 0,
300: ._bounce_alloc_lo = 0,
301: ._bounce_alloc_hi = 0,
302: ._may_bounce = NULL,
1.5 fvdl 303: };
304: #endif
1.1 fvdl 305:
1.42 dyoung 306: static struct pci_conf_lock cl0 = {
307: .cl_cpuno = 0UL
308: , .cl_sel = 0UL
309: };
310:
311: static struct pci_conf_lock * const cl = &cl0;
312:
1.52 dyoung 313: #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST)
314: extern int acpi_md_vbios_reset;
315: extern int acpi_md_vesa_modenum;
316: #endif
317:
318: static struct genfb_colormap_callback gfb_cb;
319: static struct genfb_pmf_callback pmf_cb;
320: static struct genfb_mode_callback mode_cb;
321: #ifdef VGA_POST
322: static struct vga_post *vga_posth = NULL;
323: #endif
324:
1.42 dyoung 325: static void
326: pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel)
327: {
328: uint32_t cpuno;
329:
330: KASSERT(sel != 0);
331:
332: kpreempt_disable();
333: cpuno = cpu_number() + 1;
334: /* If the kernel enters pci_conf_lock() through an interrupt
335: * handler, then the CPU may already hold the lock.
336: *
337: * If the CPU does not already hold the lock, spin until
338: * we can acquire it.
339: */
340: if (cpuno == cl->cl_cpuno) {
341: ocl->cl_cpuno = cpuno;
342: } else {
1.83 maxv 343: #ifdef LOCKDEBUG
344: u_int spins = 0;
345: #endif
346: u_int count;
347: count = SPINLOCK_BACKOFF_MIN;
1.44 dyoung 348:
1.42 dyoung 349: ocl->cl_cpuno = 0;
1.44 dyoung 350:
351: while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) {
1.83 maxv 352: SPINLOCK_BACKOFF(count);
1.44 dyoung 353: #ifdef LOCKDEBUG
354: if (SPINLOCK_SPINOUT(spins)) {
355: panic("%s: cpu %" PRId32
356: " spun out waiting for cpu %" PRId32,
357: __func__, cpuno, cl->cl_cpuno);
358: }
1.83 maxv 359: #endif
1.44 dyoung 360: }
1.42 dyoung 361: }
362:
363: /* Only one CPU can be here, so an interlocked atomic_swap(3)
364: * is not necessary.
365: *
366: * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel,
367: * and applying atomic_cas_32_ni() is not an atomic operation,
368: * however, any interrupt that, in the middle of the
369: * operation, modifies cl->cl_sel, will also restore
370: * cl->cl_sel. So cl->cl_sel will have the same value when
371: * we apply atomic_cas_32_ni() as when we evaluated it,
372: * before.
373: */
374: ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel);
375: pci_conf_select(sel);
376: }
377:
378: static void
379: pci_conf_unlock(struct pci_conf_lock *ocl)
380: {
1.62 christos 381: atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel);
1.42 dyoung 382: pci_conf_select(ocl->cl_sel);
383: if (ocl->cl_cpuno != cl->cl_cpuno)
384: atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno);
385: kpreempt_enable();
386: }
387:
1.39 dyoung 388: static uint32_t
389: pci_conf_selector(pcitag_t tag, int reg)
390: {
391: static const pcitag_t mode2_mask = {
392: .mode2 = {
393: .enable = 0xff
394: , .forward = 0xff
395: }
396: };
397:
398: switch (pci_mode) {
399: case 1:
400: return tag.mode1 | reg;
401: case 2:
402: return tag.mode1 & mode2_mask.mode1;
403: default:
1.69 christos 404: panic("%s: mode %d not configured", __func__, pci_mode);
1.39 dyoung 405: }
406: }
407:
408: static unsigned int
409: pci_conf_port(pcitag_t tag, int reg)
410: {
411: switch (pci_mode) {
412: case 1:
413: return PCI_MODE1_DATA_REG;
414: case 2:
415: return tag.mode2.port | reg;
416: default:
1.69 christos 417: panic("%s: mode %d not configured", __func__, pci_mode);
1.39 dyoung 418: }
419: }
420:
421: static void
1.42 dyoung 422: pci_conf_select(uint32_t sel)
1.39 dyoung 423: {
424: pcitag_t tag;
425:
426: switch (pci_mode) {
427: case 1:
1.42 dyoung 428: outl(PCI_MODE1_ADDRESS_REG, sel);
1.39 dyoung 429: return;
430: case 2:
1.42 dyoung 431: tag.mode1 = sel;
1.39 dyoung 432: outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
433: if (tag.mode2.enable != 0)
434: outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
435: return;
436: default:
1.69 christos 437: panic("%s: mode %d not configured", __func__, pci_mode);
1.39 dyoung 438: }
439: }
440:
1.81 jakllsch 441: static int
442: pci_mode_check(void)
443: {
444: pcireg_t x;
445: pcitag_t t;
446: int device;
447: const int maxdev = pci_bus_maxdevs(NULL, 0);
448:
449: for (device = 0; device < maxdev; device++) {
450: t = pci_make_tag(NULL, 0, device, 0);
451: x = pci_conf_read(NULL, t, PCI_CLASS_REG);
452: if (PCI_CLASS(x) == PCI_CLASS_BRIDGE &&
453: PCI_SUBCLASS(x) == PCI_SUBCLASS_BRIDGE_HOST)
454: return 0;
455: x = pci_conf_read(NULL, t, PCI_ID_REG);
456: switch (PCI_VENDOR(x)) {
457: case PCI_VENDOR_COMPAQ:
458: case PCI_VENDOR_INTEL:
459: case PCI_VENDOR_VIATECH:
460: return 0;
461: }
462: }
463: return -1;
464: }
1.70 knakahar 465: #ifdef __HAVE_PCI_MSI_MSIX
466: static int
467: pci_has_msi_quirk(pcireg_t id, int type)
468: {
469: int i;
470:
471: for (i = 0; i < __arraycount(pci_msi_quirk_tbl); i++) {
472: if (id == pci_msi_quirk_tbl[i].id &&
473: type == pci_msi_quirk_tbl[i].type)
474: return 1;
475: }
476:
477: return 0;
478: }
479: #endif
480:
1.1 fvdl 481: void
1.32 dyoung 482: pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba)
1.1 fvdl 483: {
1.70 knakahar 484: #ifdef __HAVE_PCI_MSI_MSIX
485: pci_chipset_tag_t pc = pba->pba_pc;
486: pcitag_t tag;
487: pcireg_t id, class;
488: #endif
1.1 fvdl 489:
490: if (pba->pba_bus == 0)
1.26 mjf 491: aprint_normal(": configuration mode %d", pci_mode);
1.4 fvdl 492: #ifdef MPBIOS
493: mpbios_pci_attach_hook(parent, self, pba);
494: #endif
1.37 jmcneill 495: #if NACPICA > 0
1.4 fvdl 496: mpacpi_pci_attach_hook(parent, self, pba);
497: #endif
1.73 jakllsch 498: #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG)
499: acpimcfg_map_bus(self, pba->pba_pc, pba->pba_bus);
500: #endif
1.70 knakahar 501:
502: #ifdef __HAVE_PCI_MSI_MSIX
503: /*
504: * In order to decide whether the system supports MSI we look
505: * at the host bridge, which should be device 0 function 0 on
506: * bus 0. It is better to not enable MSI on systems that
507: * support it than the other way around, so be conservative
508: * here. So we don't enable MSI if we don't find a host
509: * bridge there. We also deliberately don't enable MSI on
510: * chipsets from low-end manifacturers like VIA and SiS.
511: */
512: tag = pci_make_tag(pc, 0, 0, 0);
513: id = pci_conf_read(pc, tag, PCI_ID_REG);
514: class = pci_conf_read(pc, tag, PCI_CLASS_REG);
515:
516: if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
517: PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST)
518: return;
519:
1.77 msaitoh 520: /* VMware and KVM use old chipset, but they can use MSI/MSI-X */
521: if ((cpu_feature[1] & CPUID2_RAZ)
522: && (pci_has_msi_quirk(id, PCI_QUIRK_ENABLE_MSI_VM))) {
523: pba->pba_flags |= PCI_FLAGS_MSI_OKAY;
524: pba->pba_flags |= PCI_FLAGS_MSIX_OKAY;
525: } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSI)) {
1.70 knakahar 526: pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY;
527: pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
1.76 nonaka 528: aprint_verbose("\n");
529: aprint_verbose_dev(self,
530: "This pci host supports neither MSI nor MSI-X.");
1.70 knakahar 531: } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSIX)) {
532: pba->pba_flags |= PCI_FLAGS_MSI_OKAY;
533: pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
1.76 nonaka 534: aprint_verbose("\n");
535: aprint_verbose_dev(self,
536: "This pci host does not support MSI-X.");
1.89 jmcneill 537: #if NACPICA > 0
538: } else if (acpi_active &&
539: AcpiGbl_FADT.Header.Revision >= 4 &&
540: (AcpiGbl_FADT.BootFlags & ACPI_FADT_NO_MSI) != 0) {
541: pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY;
542: pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
543: aprint_verbose("\n");
544: aprint_verbose_dev(self,
545: "MSI support disabled via ACPI IAPC_BOOT_ARCH flag.\n");
546: #endif
1.70 knakahar 547: } else {
548: pba->pba_flags |= PCI_FLAGS_MSI_OKAY;
549: pba->pba_flags |= PCI_FLAGS_MSIX_OKAY;
550: }
551:
552: /*
553: * Don't enable MSI on a HyperTransport bus. In order to
554: * determine that bus 0 is a HyperTransport bus, we look at
555: * device 24 function 0, which is the HyperTransport
556: * host/primary interface integrated on most 64-bit AMD CPUs.
557: * If that device has a HyperTransport capability, bus 0 must
558: * be a HyperTransport bus and we disable MSI.
559: */
1.74 jakllsch 560: if (24 < pci_bus_maxdevs(pc, 0)) {
561: tag = pci_make_tag(pc, 0, 24, 0);
562: if (pci_get_capability(pc, tag, PCI_CAP_LDT, NULL, NULL)) {
563: pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY;
564: pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
565: }
1.70 knakahar 566: }
1.87 jdolecek 567:
1.70 knakahar 568: #endif /* __HAVE_PCI_MSI_MSIX */
1.1 fvdl 569: }
570:
571: int
1.18 christos 572: pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
1.1 fvdl 573: {
574: /*
575: * Bus number is irrelevant. If Configuration Mechanism 2 is in
576: * use, can only have devices 0-15 on any bus. If Configuration
577: * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal'
578: * range).
579: */
580: if (pci_mode == 2)
581: return (16);
582: else
583: return (32);
584: }
585:
586: pcitag_t
1.18 christos 587: pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
1.1 fvdl 588: {
1.47 dyoung 589: pci_chipset_tag_t ipc;
1.1 fvdl 590: pcitag_t tag;
591:
1.47 dyoung 592: for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
593: if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0)
594: continue;
595: return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx,
596: pc, bus, device, function);
1.41 dyoung 597: }
1.40 dyoung 598:
1.1 fvdl 599: switch (pci_mode) {
600: case 1:
1.38 dyoung 601: if (bus >= 256 || device >= 32 || function >= 8)
1.69 christos 602: panic("%s: bad request(%d, %d, %d)", __func__,
603: bus, device, function);
1.38 dyoung 604:
605: tag.mode1 = PCI_MODE1_ENABLE |
606: (bus << 16) | (device << 11) | (function << 8);
607: return tag;
1.1 fvdl 608: case 2:
1.38 dyoung 609: if (bus >= 256 || device >= 16 || function >= 8)
1.69 christos 610: panic("%s: bad request(%d, %d, %d)", __func__,
611: bus, device, function);
1.38 dyoung 612:
613: tag.mode2.port = 0xc000 | (device << 8);
614: tag.mode2.enable = 0xf0 | (function << 1);
615: tag.mode2.forward = bus;
616: return tag;
1.1 fvdl 617: default:
1.69 christos 618: panic("%s: mode %d not configured", __func__, pci_mode);
1.1 fvdl 619: }
620: }
621:
622: void
1.18 christos 623: pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
1.17 christos 624: int *bp, int *dp, int *fp)
1.1 fvdl 625: {
1.47 dyoung 626: pci_chipset_tag_t ipc;
1.1 fvdl 627:
1.47 dyoung 628: for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
629: if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0)
630: continue;
631: (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx,
632: pc, tag, bp, dp, fp);
633: return;
1.40 dyoung 634: }
635:
1.1 fvdl 636: switch (pci_mode) {
637: case 1:
1.38 dyoung 638: if (bp != NULL)
639: *bp = (tag.mode1 >> 16) & 0xff;
640: if (dp != NULL)
641: *dp = (tag.mode1 >> 11) & 0x1f;
642: if (fp != NULL)
643: *fp = (tag.mode1 >> 8) & 0x7;
644: return;
1.1 fvdl 645: case 2:
1.38 dyoung 646: if (bp != NULL)
647: *bp = tag.mode2.forward & 0xff;
648: if (dp != NULL)
649: *dp = (tag.mode2.port >> 8) & 0xf;
650: if (fp != NULL)
651: *fp = (tag.mode2.enable >> 1) & 0x7;
652: return;
1.1 fvdl 653: default:
1.69 christos 654: panic("%s: mode %d not configured", __func__, pci_mode);
1.1 fvdl 655: }
656: }
657:
658: pcireg_t
1.43 dyoung 659: pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
1.1 fvdl 660: {
1.47 dyoung 661: pci_chipset_tag_t ipc;
1.1 fvdl 662: pcireg_t data;
1.42 dyoung 663: struct pci_conf_lock ocl;
1.71 msaitoh 664: int dev;
1.1 fvdl 665:
1.31 dyoung 666: KASSERT((reg & 0x3) == 0);
1.40 dyoung 667:
1.47 dyoung 668: for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
669: if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0)
670: continue;
671: return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg);
1.41 dyoung 672: }
1.40 dyoung 673:
1.71 msaitoh 674: pci_decompose_tag(pc, tag, NULL, &dev, NULL);
675: if (__predict_false(pci_mode == 2 && dev >= 16))
676: return (pcireg_t) -1;
677:
678: if (reg < 0)
679: return (pcireg_t) -1;
680: if (reg >= PCI_CONF_SIZE) {
681: #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG)
682: if (reg >= PCI_EXTCONF_SIZE)
683: return (pcireg_t) -1;
684: acpimcfg_conf_read(pc, tag, reg, &data);
685: return data;
686: #else
687: return (pcireg_t) -1;
688: #endif
689: }
690:
1.42 dyoung 691: pci_conf_lock(&ocl, pci_conf_selector(tag, reg));
1.39 dyoung 692: data = inl(pci_conf_port(tag, reg));
1.42 dyoung 693: pci_conf_unlock(&ocl);
1.39 dyoung 694: return data;
1.1 fvdl 695: }
696:
697: void
1.43 dyoung 698: pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
1.1 fvdl 699: {
1.47 dyoung 700: pci_chipset_tag_t ipc;
1.42 dyoung 701: struct pci_conf_lock ocl;
1.71 msaitoh 702: int dev;
1.1 fvdl 703:
1.31 dyoung 704: KASSERT((reg & 0x3) == 0);
1.40 dyoung 705:
1.47 dyoung 706: for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
707: if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0)
708: continue;
709: (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg,
710: data);
711: return;
1.40 dyoung 712: }
713:
1.71 msaitoh 714: pci_decompose_tag(pc, tag, NULL, &dev, NULL);
715: if (__predict_false(pci_mode == 2 && dev >= 16)) {
716: return;
717: }
718:
719: if (reg < 0)
720: return;
721: if (reg >= PCI_CONF_SIZE) {
722: #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG)
723: if (reg >= PCI_EXTCONF_SIZE)
724: return;
725: acpimcfg_conf_write(pc, tag, reg, data);
726: #endif
727: return;
728: }
729:
1.42 dyoung 730: pci_conf_lock(&ocl, pci_conf_selector(tag, reg));
1.39 dyoung 731: outl(pci_conf_port(tag, reg), data);
1.42 dyoung 732: pci_conf_unlock(&ocl);
1.38 dyoung 733: }
1.1 fvdl 734:
1.90 bouyer 735: #ifdef XENPV
736: void
737: pci_conf_write16(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint16_t data)
738: {
739: pci_chipset_tag_t ipc;
740: struct pci_conf_lock ocl;
741: int dev;
742:
743: KASSERT((reg & 0x1) == 0);
744:
745: for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
746: if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0)
747: continue;
748: panic("pci_conf_write16 and override");
749: }
750:
751: pci_decompose_tag(pc, tag, NULL, &dev, NULL);
752: if (__predict_false(pci_mode == 2 && dev >= 16)) {
753: return;
754: }
755:
756: if (reg < 0)
757: return;
758: if (reg >= PCI_CONF_SIZE) {
759: #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG)
760: if (reg >= PCI_EXTCONF_SIZE)
761: return;
762: panic("pci_conf_write16 and reg >= PCI_CONF_SIZE");
763: #endif
764: return;
765: }
766:
767: pci_conf_lock(&ocl, pci_conf_selector(tag, reg & ~0x3));
768: outl(pci_conf_port(tag, reg & ~0x3) + (reg & 0x3), data);
769: pci_conf_unlock(&ocl);
770: }
771: #endif /* XENPV */
772:
1.38 dyoung 773: void
774: pci_mode_set(int mode)
775: {
776: KASSERT(pci_mode == -1 || pci_mode == mode);
1.1 fvdl 777:
1.38 dyoung 778: pci_mode = mode;
1.1 fvdl 779: }
780:
781: int
1.33 cegger 782: pci_mode_detect(void)
1.1 fvdl 783: {
1.33 cegger 784: uint32_t sav, val;
1.1 fvdl 785: int i;
786: pcireg_t idreg;
787:
788: if (pci_mode != -1)
789: return pci_mode;
790:
791: /*
792: * We try to divine which configuration mode the host bridge wants.
793: */
794:
795: sav = inl(PCI_MODE1_ADDRESS_REG);
796:
797: pci_mode = 1; /* assume this for now */
798: /*
799: * catch some known buggy implementations of mode 1
800: */
1.27 dyoung 801: for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) {
1.1 fvdl 802: pcitag_t t;
803:
1.56 jakllsch 804: if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID)
805: continue;
806: t.mode1 = pcim1_quirk_tbl[i].tag.mode1;
807: idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */
1.1 fvdl 808: if (idreg == pcim1_quirk_tbl[i].id) {
809: #ifdef DEBUG
1.67 christos 810: printf("%s: known mode 1 PCI chipset (%08x)\n",
811: __func__, idreg);
1.1 fvdl 812: #endif
813: return (pci_mode);
814: }
815: }
1.66 sborrill 816:
1.82 jakllsch 817: #if 0
818: extern char cpu_brand_string[];
1.67 christos 819: const char *reason, *system_vendor, *system_product;
820: if (memcmp(cpu_brand_string, "QEMU", 4) == 0)
1.61 gson 821: /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */
1.67 christos 822: reason = "QEMU";
823: else if ((system_vendor = pmf_get_platform("system-vendor")) != NULL &&
824: strcmp(system_vendor, "Xen") == 0 &&
825: (system_product = pmf_get_platform("system-product")) != NULL &&
826: strcmp(system_product, "HVM domU") == 0)
827: reason = "Xen";
828: else
829: reason = NULL;
830:
831: if (reason) {
1.61 gson 832: #ifdef DEBUG
1.67 christos 833: printf("%s: forcing PCI mode 1 for %s\n", __func__, reason);
1.61 gson 834: #endif
835: return (pci_mode);
836: }
1.82 jakllsch 837: #endif
1.1 fvdl 838: /*
839: * Strong check for standard compliant mode 1:
840: * 1. bit 31 ("enable") can be set
841: * 2. byte/word access does not affect register
842: */
843: outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE);
844: outb(PCI_MODE1_ADDRESS_REG + 3, 0);
845: outw(PCI_MODE1_ADDRESS_REG + 2, 0);
846: val = inl(PCI_MODE1_ADDRESS_REG);
847: if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) {
848: #ifdef DEBUG
1.67 christos 849: printf("%s: mode 1 enable failed (%x)\n", __func__, val);
1.1 fvdl 850: #endif
1.81 jakllsch 851: /* Try out mode 1 to see if we can find a host bridge. */
852: if (pci_mode_check() == 0) {
853: #ifdef DEBUG
854: printf("%s: mode 1 functional, using\n", __func__);
855: #endif
856: return (pci_mode);
857: }
1.1 fvdl 858: goto not1;
859: }
860: outl(PCI_MODE1_ADDRESS_REG, 0);
861: val = inl(PCI_MODE1_ADDRESS_REG);
862: if ((val & 0x80fffffc) != 0)
863: goto not1;
864: return (pci_mode);
865: not1:
866: outl(PCI_MODE1_ADDRESS_REG, sav);
867:
868: /*
869: * This mode 2 check is quite weak (and known to give false
870: * positives on some Compaq machines).
871: * However, this doesn't matter, because this is the
872: * last test, and simply no PCI devices will be found if
873: * this happens.
874: */
875: outb(PCI_MODE2_ENABLE_REG, 0);
876: outb(PCI_MODE2_FORWARD_REG, 0);
877: if (inb(PCI_MODE2_ENABLE_REG) != 0 ||
878: inb(PCI_MODE2_FORWARD_REG) != 0)
879: goto not2;
880: return (pci_mode = 2);
881: not2:
882:
883: return (pci_mode = 0);
884: }
885:
1.11 sekiya 886: void
887: pci_device_foreach(pci_chipset_tag_t pc, int maxbus,
888: void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context)
889: {
890: pci_device_foreach_min(pc, 0, maxbus, func, context);
891: }
892:
893: void
894: pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus,
895: void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context)
896: {
897: const struct pci_quirkdata *qd;
898: int bus, device, function, maxdevs, nfuncs;
899: pcireg_t id, bhlcr;
900: pcitag_t tag;
901:
902: for (bus = minbus; bus <= maxbus; bus++) {
903: maxdevs = pci_bus_maxdevs(pc, bus);
904: for (device = 0; device < maxdevs; device++) {
905: tag = pci_make_tag(pc, bus, device, 0);
906: id = pci_conf_read(pc, tag, PCI_ID_REG);
907:
908: /* Invalid vendor ID value? */
909: if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
910: continue;
911: /* XXX Not invalid, but we've done this ~forever. */
912: if (PCI_VENDOR(id) == 0)
913: continue;
914:
915: qd = pci_lookup_quirkdata(PCI_VENDOR(id),
916: PCI_PRODUCT(id));
917:
918: bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
919: if (PCI_HDRTYPE_MULTIFN(bhlcr) ||
920: (qd != NULL &&
1.55 jakllsch 921: (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0))
1.11 sekiya 922: nfuncs = 8;
923: else
924: nfuncs = 1;
925:
926: for (function = 0; function < nfuncs; function++) {
927: tag = pci_make_tag(pc, bus, device, function);
928: id = pci_conf_read(pc, tag, PCI_ID_REG);
929:
930: /* Invalid vendor ID value? */
931: if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
932: continue;
933: /*
934: * XXX Not invalid, but we've done this
935: * ~forever.
936: */
937: if (PCI_VENDOR(id) == 0)
938: continue;
939: (*func)(pc, tag, context);
940: }
941: }
942: }
943: }
944:
945: void
946: pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus,
947: void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx)
948: {
949: struct pci_bridge_hook_arg bridge_hook;
950:
951: bridge_hook.func = func;
1.55 jakllsch 952: bridge_hook.arg = ctx;
1.11 sekiya 953:
954: pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook,
1.55 jakllsch 955: &bridge_hook);
1.11 sekiya 956: }
957:
958: static void
959: pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx)
960: {
961: struct pci_bridge_hook_arg *bridge_hook = (void *)ctx;
962: pcireg_t reg;
963:
964: reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
965: if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
1.55 jakllsch 966: (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI ||
1.11 sekiya 967: PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {
968: (*bridge_hook->func)(pc, tag, bridge_hook->arg);
969: }
970: }
1.43 dyoung 971:
972: static const void *
973: bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit)
974: {
975: switch (bit) {
976: case PCI_OVERRIDE_CONF_READ:
977: return ov->ov_conf_read;
978: case PCI_OVERRIDE_CONF_WRITE:
979: return ov->ov_conf_write;
980: case PCI_OVERRIDE_INTR_MAP:
981: return ov->ov_intr_map;
982: case PCI_OVERRIDE_INTR_STRING:
983: return ov->ov_intr_string;
984: case PCI_OVERRIDE_INTR_EVCNT:
985: return ov->ov_intr_evcnt;
986: case PCI_OVERRIDE_INTR_ESTABLISH:
987: return ov->ov_intr_establish;
988: case PCI_OVERRIDE_INTR_DISESTABLISH:
989: return ov->ov_intr_disestablish;
990: case PCI_OVERRIDE_MAKE_TAG:
991: return ov->ov_make_tag;
992: case PCI_OVERRIDE_DECOMPOSE_TAG:
993: return ov->ov_decompose_tag;
994: default:
995: return NULL;
996: }
997: }
998:
999: void
1000: pci_chipset_tag_destroy(pci_chipset_tag_t pc)
1001: {
1002: kmem_free(pc, sizeof(struct pci_chipset_tag));
1003: }
1004:
1005: int
1006: pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present,
1007: const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp)
1008: {
1009: uint64_t bit, bits, nbits;
1010: pci_chipset_tag_t pc;
1011: const void *fp;
1012:
1013: if (ov == NULL || present == 0)
1014: return EINVAL;
1015:
1016: pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP);
1017: pc->pc_super = opc;
1018:
1019: for (bits = present; bits != 0; bits = nbits) {
1020: nbits = bits & (bits - 1);
1021: bit = nbits ^ bits;
1022: if ((fp = bit_to_function_pointer(ov, bit)) == NULL) {
1.51 dyoung 1023: #ifdef DEBUG
1.43 dyoung 1024: printf("%s: missing bit %" PRIx64 "\n", __func__, bit);
1.51 dyoung 1025: #endif
1.43 dyoung 1026: goto einval;
1027: }
1028: }
1029:
1030: pc->pc_ov = ov;
1031: pc->pc_present = present;
1032: pc->pc_ctx = ctx;
1033:
1034: *pcp = pc;
1035:
1036: return 0;
1037: einval:
1038: kmem_free(pc, sizeof(struct pci_chipset_tag));
1039: return EINVAL;
1040: }
1.52 dyoung 1041:
1042: static void
1043: x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b)
1044: {
1.57 jakllsch 1045: outb(IO_VGA + VGA_DAC_ADDRW, index);
1046: outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2);
1047: outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2);
1048: outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2);
1.52 dyoung 1049: }
1050:
1051: static bool
1052: x86_genfb_setmode(struct genfb_softc *sc, int newmode)
1053: {
1054: #if NGENFB > 0
1.68 christos 1055: # if NACPICA > 0 && defined(VGA_POST)
1.52 dyoung 1056: static int curmode = WSDISPLAYIO_MODE_EMUL;
1.68 christos 1057: # endif
1.52 dyoung 1058:
1059: switch (newmode) {
1060: case WSDISPLAYIO_MODE_EMUL:
1.68 christos 1061: # if NACPICA > 0 && defined(VGA_POST)
1.52 dyoung 1062: if (curmode != newmode) {
1063: if (vga_posth != NULL && acpi_md_vesa_modenum != 0) {
1064: vga_post_set_vbe(vga_posth,
1065: acpi_md_vesa_modenum);
1066: }
1067: }
1.68 christos 1068: # endif
1.52 dyoung 1069: break;
1070: }
1071:
1.68 christos 1072: # if NACPICA > 0 && defined(VGA_POST)
1.52 dyoung 1073: curmode = newmode;
1.68 christos 1074: # endif
1.52 dyoung 1075: #endif
1076: return true;
1077: }
1078:
1079: static bool
1080: x86_genfb_suspend(device_t dev, const pmf_qual_t *qual)
1081: {
1082: return true;
1083: }
1084:
1085: static bool
1086: x86_genfb_resume(device_t dev, const pmf_qual_t *qual)
1087: {
1088: #if NGENFB > 0
1089: struct pci_genfb_softc *psc = device_private(dev);
1090:
1091: #if NACPICA > 0 && defined(VGA_POST)
1092: if (vga_posth != NULL && acpi_md_vbios_reset == 2) {
1093: vga_post_call(vga_posth);
1094: if (acpi_md_vesa_modenum != 0)
1095: vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum);
1096: }
1097: #endif
1098: genfb_restore_palette(&psc->sc_gen);
1099: #endif
1100:
1101: return true;
1102: }
1103:
1.85 christos 1104: static void
1105: populate_fbinfo(device_t dev, prop_dictionary_t dict)
1106: {
1107: #if NWSDISPLAY > 0 && NGENFB > 0
1108: extern struct vcons_screen x86_genfb_console_screen;
1109: struct rasops_info *ri = &x86_genfb_console_screen.scr_ri;
1110: #endif
1111: const void *fbptr = lookup_bootinfo(BTINFO_FRAMEBUFFER);
1112: struct btinfo_framebuffer fbinfo;
1113:
1114: if (fbptr == NULL)
1115: return;
1116:
1117: memcpy(&fbinfo, fbptr, sizeof(fbinfo));
1118:
1119: if (fbinfo.physaddr != 0) {
1120: prop_dictionary_set_uint32(dict, "width", fbinfo.width);
1121: prop_dictionary_set_uint32(dict, "height", fbinfo.height);
1122: prop_dictionary_set_uint8(dict, "depth", fbinfo.depth);
1123: prop_dictionary_set_uint16(dict, "linebytes", fbinfo.stride);
1124:
1125: prop_dictionary_set_uint64(dict, "address", fbinfo.physaddr);
1126: #if NWSDISPLAY > 0 && NGENFB > 0
1127: if (ri->ri_bits != NULL) {
1128: prop_dictionary_set_uint64(dict, "virtual_address",
1129: ri->ri_hwbits != NULL ?
1130: (vaddr_t)ri->ri_hworigbits :
1131: (vaddr_t)ri->ri_origbits);
1132: }
1133: #endif
1134: }
1135: #if notyet
1136: prop_dictionary_set_bool(dict, "splash",
1137: (fbinfo.flags & BI_FB_SPLASH) != 0);
1138: #endif
1139: if (fbinfo.depth == 8) {
1140: gfb_cb.gcc_cookie = NULL;
1141: gfb_cb.gcc_set_mapreg = x86_genfb_set_mapreg;
1142: prop_dictionary_set_uint64(dict, "cmap_callback",
1143: (uint64_t)(uintptr_t)&gfb_cb);
1144: }
1145: if (fbinfo.physaddr != 0) {
1146: mode_cb.gmc_setmode = x86_genfb_setmode;
1147: prop_dictionary_set_uint64(dict, "mode_callback",
1148: (uint64_t)(uintptr_t)&mode_cb);
1149: }
1150:
1151: #if NWSDISPLAY > 0 && NGENFB > 0
1152: if (device_is_a(dev, "genfb")) {
1153: prop_dictionary_set_bool(dict, "enable_shadowfb",
1154: ri->ri_hwbits != NULL);
1155:
1156: x86_genfb_set_console_dev(dev);
1157: #ifdef DDB
1158: db_trap_callback = x86_genfb_ddb_trap_callback;
1159: #endif
1160: }
1161: #endif
1162: }
1163:
1.52 dyoung 1164: device_t
1165: device_pci_register(device_t dev, void *aux)
1166: {
1.80 nonaka 1167: device_t parent = device_parent(dev);
1.52 dyoung 1168:
1169: device_pci_props_register(dev, aux);
1170:
1171: /*
1172: * Handle network interfaces here, the attachment information is
1173: * not available driver-independently later.
1174: *
1175: * For disks, there is nothing useful available at attach time.
1176: */
1177: if (device_class(dev) == DV_IFNET) {
1178: struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF);
1179: if (bin == NULL)
1180: return NULL;
1181:
1182: /*
1183: * We don't check the driver name against the device name
1184: * passed by the boot ROM. The ROM should stay usable if
1185: * the driver becomes obsolete. The physical attachment
1186: * information (checked below) must be sufficient to
1.55 jakllsch 1187: * identify the device.
1.52 dyoung 1188: */
1.80 nonaka 1189: if (bin->bus == BI_BUS_PCI && device_is_a(parent, "pci")) {
1.52 dyoung 1190: struct pci_attach_args *paa = aux;
1191: int b, d, f;
1192:
1193: /*
1194: * Calculate BIOS representation of:
1195: *
1196: * <bus,device,function>
1197: *
1198: * and compare.
1199: */
1200: pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f);
1201: if (bin->addr.tag == ((b << 8) | (d << 3) | f))
1202: return dev;
1.80 nonaka 1203:
1.84 cherry 1204: #ifndef XENPV
1.80 nonaka 1205: /*
1206: * efiboot reports parent ppb bus/device/function.
1207: */
1208: device_t grand = device_parent(parent);
1209: if (efi_probe() && grand && device_is_a(grand, "ppb")) {
1210: struct ppb_softc *ppb_sc = device_private(grand);
1211: pci_decompose_tag(ppb_sc->sc_pc, ppb_sc->sc_tag,
1212: &b, &d, &f);
1213: if (bin->addr.tag == ((b << 8) | (d << 3) | f))
1214: return dev;
1215: }
1216: #endif
1.52 dyoung 1217: }
1218: }
1.80 nonaka 1219: if (parent && device_is_a(parent, "pci") &&
1.86 nonaka 1220: x86_found_console == false) {
1.52 dyoung 1221: struct pci_attach_args *pa = aux;
1222:
1223: if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) {
1.85 christos 1224: prop_dictionary_t dict = device_properties(dev);
1.52 dyoung 1225: /*
1226: * framebuffer drivers other than genfb can work
1227: * without the address property
1228: */
1.85 christos 1229: populate_fbinfo(dev, dict);
1.78 nonaka 1230:
1.65 jakllsch 1231: #if 1 && NWSDISPLAY > 0 && NGENFB > 0
1232: /* XXX */
1233: if (device_is_a(dev, "genfb")) {
1234: prop_dictionary_set_bool(dict, "is_console",
1235: genfb_is_console());
1236: } else
1237: #endif
1.52 dyoung 1238: prop_dictionary_set_bool(dict, "is_console", true);
1.60 macallan 1239:
1.52 dyoung 1240: prop_dictionary_set_bool(dict, "clear-screen", false);
1241: #if NWSDISPLAY > 0 && NGENFB > 0
1.85 christos 1242: extern struct vcons_screen x86_genfb_console_screen;
1.52 dyoung 1243: prop_dictionary_set_uint16(dict, "cursor-row",
1244: x86_genfb_console_screen.scr_ri.ri_crow);
1245: #endif
1246: #if notyet
1247: prop_dictionary_set_bool(dict, "splash",
1.85 christos 1248: (fbinfo->flags & BI_FB_SPLASH) != 0);
1.52 dyoung 1249: #endif
1250: pmf_cb.gpc_suspend = x86_genfb_suspend;
1251: pmf_cb.gpc_resume = x86_genfb_resume;
1252: prop_dictionary_set_uint64(dict,
1253: "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb);
1254: #ifdef VGA_POST
1255: vga_posth = vga_post_init(pa->pa_bus, pa->pa_device,
1256: pa->pa_function);
1257: #endif
1.86 nonaka 1258: x86_found_console = true;
1.52 dyoung 1259: return NULL;
1260: }
1261: }
1262: return NULL;
1263: }
1.58 soren 1264:
1.64 msaitoh 1265: #ifndef PUC_CNBUS
1266: #define PUC_CNBUS 0
1267: #endif
1268:
1.58 soren 1269: #if NCOM > 0
1270: int
1.64 msaitoh 1271: cpu_puc_cnprobe(struct consdev *cn, struct pci_attach_args *pa)
1.58 soren 1272: {
1273: pci_mode_detect();
1274: pa->pa_iot = x86_bus_space_io;
1.64 msaitoh 1275: pa->pa_memt = x86_bus_space_mem;
1.58 soren 1276: pa->pa_pc = 0;
1.64 msaitoh 1277: pa->pa_tag = pci_make_tag(0, PUC_CNBUS, pci_bus_maxdevs(NULL, 0) - 1,
1278: 0);
1279:
1.58 soren 1280: return 0;
1281: }
1282: #endif
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