Annotation of src/sys/arch/x86/pci/pci_machdep.c, Revision 1.79.8.2
1.79.8.2! pgoyette 1: /* $NetBSD: pci_machdep.c,v 1.82 2018/06/23 16:09:53 jakllsch Exp $ */
1.1 fvdl 2:
3: /*-
4: * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
5: * All rights reserved.
6: *
7: * This code is derived from software contributed to The NetBSD Foundation
8: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9: * NASA Ames Research Center.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: *
20: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30: * POSSIBILITY OF SUCH DAMAGE.
31: */
32:
33: /*
34: * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
35: * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
36: *
37: * Redistribution and use in source and binary forms, with or without
38: * modification, are permitted provided that the following conditions
39: * are met:
40: * 1. Redistributions of source code must retain the above copyright
41: * notice, this list of conditions and the following disclaimer.
42: * 2. Redistributions in binary form must reproduce the above copyright
43: * notice, this list of conditions and the following disclaimer in the
44: * documentation and/or other materials provided with the distribution.
45: * 3. All advertising materials mentioning features or use of this software
46: * must display the following acknowledgement:
47: * This product includes software developed by Charles M. Hannum.
48: * 4. The name of the author may not be used to endorse or promote products
49: * derived from this software without specific prior written permission.
50: *
51: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
52: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
53: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
54: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
55: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
56: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
60: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61: */
62:
63: /*
64: * Machine-specific functions for PCI autoconfiguration.
65: *
66: * On PCs, there are two methods of generating PCI configuration cycles.
67: * We try to detect the appropriate mechanism for this machine and set
68: * up a few function pointers to access the correct method directly.
69: *
70: * The configuration method can be hard-coded in the config file by
71: * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
1.55 jakllsch 72: * as defined in section 3.6.4.1, `Generating Configuration Cycles'.
1.1 fvdl 73: */
74:
75: #include <sys/cdefs.h>
1.79.8.2! pgoyette 76: __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.82 2018/06/23 16:09:53 jakllsch Exp $");
1.1 fvdl 77:
78: #include <sys/types.h>
79: #include <sys/param.h>
80: #include <sys/time.h>
81: #include <sys/systm.h>
82: #include <sys/errno.h>
83: #include <sys/device.h>
1.29 ad 84: #include <sys/bus.h>
1.42 dyoung 85: #include <sys/cpu.h>
1.43 dyoung 86: #include <sys/kmem.h>
1.1 fvdl 87:
88: #include <uvm/uvm_extern.h>
89:
1.10 yamt 90: #include <machine/bus_private.h>
1.1 fvdl 91:
92: #include <machine/pio.h>
1.30 ad 93: #include <machine/lock.h>
1.1 fvdl 94:
1.3 fvdl 95: #include <dev/isa/isareg.h>
1.1 fvdl 96: #include <dev/isa/isavar.h>
97: #include <dev/pci/pcivar.h>
98: #include <dev/pci/pcireg.h>
1.43 dyoung 99: #include <dev/pci/pccbbreg.h>
1.1 fvdl 100: #include <dev/pci/pcidevs.h>
1.79.8.1 pgoyette 101: #include <dev/pci/ppbvar.h>
1.52 dyoung 102: #include <dev/pci/genfb_pcivar.h>
103:
104: #include <dev/wsfb/genfbvar.h>
105: #include <arch/x86/include/genfb_machdep.h>
106: #include <dev/ic/vgareg.h>
1.1 fvdl 107:
1.37 jmcneill 108: #include "acpica.h"
1.52 dyoung 109: #include "genfb.h"
110: #include "isa.h"
111: #include "opt_acpi.h"
112: #include "opt_ddb.h"
1.14 bouyer 113: #include "opt_mpbios.h"
1.64 msaitoh 114: #include "opt_puc.h"
1.52 dyoung 115: #include "opt_vga.h"
116: #include "pci.h"
117: #include "wsdisplay.h"
1.58 soren 118: #include "com.h"
1.52 dyoung 119:
120: #ifdef DDB
121: #include <machine/db_machdep.h>
122: #include <ddb/db_sym.h>
123: #include <ddb/db_extern.h>
124: #endif
125:
126: #ifdef VGA_POST
127: #include <x86/vga_post.h>
128: #endif
129:
1.70 knakahar 130: #include <x86/cpuvar.h>
131:
1.52 dyoung 132: #include <machine/autoconf.h>
133: #include <machine/bootinfo.h>
1.14 bouyer 134:
135: #ifdef MPBIOS
136: #include <machine/mpbiosvar.h>
137: #endif
138:
1.37 jmcneill 139: #if NACPICA > 0
1.14 bouyer 140: #include <machine/mpacpi.h>
1.71 msaitoh 141: #if !defined(NO_PCI_EXTENDED_CONFIG)
142: #include <dev/acpi/acpivar.h>
143: #include <dev/acpi/acpi_mcfg.h>
144: #endif
1.14 bouyer 145: #endif
146:
1.16 christos 147: #include <machine/mpconfig.h>
148:
1.58 soren 149: #if NCOM > 0
150: #include <dev/pci/puccn.h>
151: #endif
152:
1.79.8.1 pgoyette 153: #ifndef XEN
154: #include <x86/efi.h>
155: #endif
156:
1.1 fvdl 157: #include "opt_pci_conf_mode.h"
158:
1.38 dyoung 159: #ifdef PCI_CONF_MODE
160: #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2)
161: static int pci_mode = PCI_CONF_MODE;
162: #else
163: #error Invalid PCI configuration mode.
164: #endif
165: #else
166: static int pci_mode = -1;
167: #endif
1.1 fvdl 168:
1.42 dyoung 169: struct pci_conf_lock {
170: uint32_t cl_cpuno; /* 0: unlocked
171: * 1 + n: locked by CPU n (0 <= n)
172: */
173: uint32_t cl_sel; /* the address that's being read. */
174: };
175:
176: static void pci_conf_unlock(struct pci_conf_lock *);
177: static uint32_t pci_conf_selector(pcitag_t, int);
178: static unsigned int pci_conf_port(pcitag_t, int);
179: static void pci_conf_select(uint32_t);
180: static void pci_conf_lock(struct pci_conf_lock *, uint32_t);
1.11 sekiya 181: static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *);
182: struct pci_bridge_hook_arg {
1.55 jakllsch 183: void (*func)(pci_chipset_tag_t, pcitag_t, void *);
184: void *arg;
185: };
1.11 sekiya 186:
1.1 fvdl 187: #define PCI_MODE1_ENABLE 0x80000000UL
188: #define PCI_MODE1_ADDRESS_REG 0x0cf8
189: #define PCI_MODE1_DATA_REG 0x0cfc
190:
191: #define PCI_MODE2_ENABLE_REG 0x0cf8
192: #define PCI_MODE2_FORWARD_REG 0x0cfa
193:
1.56 jakllsch 194: #define _tag(b, d, f) \
195: {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)}
1.1 fvdl 196: #define _qe(bus, dev, fcn, vend, prod) \
1.56 jakllsch 197: {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)}
198: const struct {
199: pcitag_t tag;
1.1 fvdl 200: pcireg_t id;
201: } pcim1_quirk_tbl[] = {
1.56 jakllsch 202: _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */
1.1 fvdl 203: _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1),
204: /* XXX Triflex2 not tested */
205: _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2),
206: _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4),
1.79.8.2! pgoyette 207: #if 0
1.1 fvdl 208: /* Triton needed for Connectix Virtual PC */
209: _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX),
210: /* Connectix Virtual PC 5 has a 440BX */
211: _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP),
1.15 soren 212: /* Parallels Desktop for Mac */
213: _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO),
214: _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS),
1.36 drochner 215: /* SIS 740 */
216: _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740),
1.12 christos 217: /* SIS 741 */
218: _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741),
1.54 tsutsui 219: /* VIA Technologies VX900 */
1.56 jakllsch 220: _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB)
1.79.8.2! pgoyette 221: #endif
1.1 fvdl 222: };
1.56 jakllsch 223: #undef _tag
1.1 fvdl 224: #undef _qe
225:
1.70 knakahar 226: /* arch/xen does not support MSI/MSI-X yet. */
227: #ifdef __HAVE_PCI_MSI_MSIX
228: #define PCI_QUIRK_DISABLE_MSI 1 /* Neigher MSI nor MSI-X work */
229: #define PCI_QUIRK_DISABLE_MSIX 2 /* MSI-X does not work */
230: #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI and MSI-X works */
231:
232: #define _dme(vend, prod) \
233: { PCI_QUIRK_DISABLE_MSI, PCI_ID_CODE(vend, prod) }
234: #define _dmxe(vend, prod) \
235: { PCI_QUIRK_DISABLE_MSIX, PCI_ID_CODE(vend, prod) }
236: #define _emve(vend, prod) \
237: { PCI_QUIRK_ENABLE_MSI_VM, PCI_ID_CODE(vend, prod) }
238: const struct {
239: int type;
240: pcireg_t id;
241: } pci_msi_quirk_tbl[] = {
242: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCMC),
243: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX),
244: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437MX),
245: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437VX),
246: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439HX),
247: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439TX),
248: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX),
249: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_AGP),
250: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX),
251: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX),
252: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX),
253: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_AGP),
254: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP),
255: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_NOAGP),
256: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX),
257: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX_AGP),
258: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810_MCH),
259: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810E_MCH),
260: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82815_FULL_HUB),
261: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82820_MCH),
262: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82830MP_IO_1),
263: _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82840_HB),
264: _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_PCHB),
265: _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_PCHB),
266: _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC751_SC),
267: _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC761_SC),
268: _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC762_NB),
269:
270: _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), /* QEMU */
271: _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), /* VMWare */
272: };
273: #undef _dme
274: #undef _dmxe
275: #undef _emve
276: #endif /* __HAVE_PCI_MSI_MSIX */
277:
1.1 fvdl 278: /*
279: * PCI doesn't have any special needs; just use the generic versions
280: * of these functions.
281: */
282: struct x86_bus_dma_tag pci_bus_dma_tag = {
1.46 christos 283: ._tag_needs_free = 0,
1.3 fvdl 284: #if defined(_LP64) || defined(PAE)
1.46 christos 285: ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD,
286: ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD,
287: ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD,
1.3 fvdl 288: #else
1.46 christos 289: ._bounce_thresh = 0,
290: ._bounce_alloc_lo = 0,
291: ._bounce_alloc_hi = 0,
292: #endif
293: ._may_bounce = NULL,
1.1 fvdl 294: };
1.5 fvdl 295:
296: #ifdef _LP64
297: struct x86_bus_dma_tag pci_bus_dma64_tag = {
1.46 christos 298: ._tag_needs_free = 0,
299: ._bounce_thresh = 0,
300: ._bounce_alloc_lo = 0,
301: ._bounce_alloc_hi = 0,
302: ._may_bounce = NULL,
1.5 fvdl 303: };
304: #endif
1.1 fvdl 305:
1.42 dyoung 306: static struct pci_conf_lock cl0 = {
307: .cl_cpuno = 0UL
308: , .cl_sel = 0UL
309: };
310:
311: static struct pci_conf_lock * const cl = &cl0;
312:
1.52 dyoung 313: #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST)
314: extern int acpi_md_vbios_reset;
315: extern int acpi_md_vesa_modenum;
316: #endif
317:
318: static struct genfb_colormap_callback gfb_cb;
319: static struct genfb_pmf_callback pmf_cb;
320: static struct genfb_mode_callback mode_cb;
321: #ifdef VGA_POST
322: static struct vga_post *vga_posth = NULL;
323: #endif
324:
1.42 dyoung 325: static void
326: pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel)
327: {
328: uint32_t cpuno;
329:
330: KASSERT(sel != 0);
331:
332: kpreempt_disable();
333: cpuno = cpu_number() + 1;
334: /* If the kernel enters pci_conf_lock() through an interrupt
335: * handler, then the CPU may already hold the lock.
336: *
337: * If the CPU does not already hold the lock, spin until
338: * we can acquire it.
339: */
340: if (cpuno == cl->cl_cpuno) {
341: ocl->cl_cpuno = cpuno;
342: } else {
1.44 dyoung 343: u_int spins;
344:
1.42 dyoung 345: ocl->cl_cpuno = 0;
1.44 dyoung 346:
347: spins = SPINLOCK_BACKOFF_MIN;
348: while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) {
349: SPINLOCK_BACKOFF(spins);
350: #ifdef LOCKDEBUG
351: if (SPINLOCK_SPINOUT(spins)) {
352: panic("%s: cpu %" PRId32
353: " spun out waiting for cpu %" PRId32,
354: __func__, cpuno, cl->cl_cpuno);
355: }
356: #endif /* LOCKDEBUG */
357: }
1.42 dyoung 358: }
359:
360: /* Only one CPU can be here, so an interlocked atomic_swap(3)
361: * is not necessary.
362: *
363: * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel,
364: * and applying atomic_cas_32_ni() is not an atomic operation,
365: * however, any interrupt that, in the middle of the
366: * operation, modifies cl->cl_sel, will also restore
367: * cl->cl_sel. So cl->cl_sel will have the same value when
368: * we apply atomic_cas_32_ni() as when we evaluated it,
369: * before.
370: */
371: ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel);
372: pci_conf_select(sel);
373: }
374:
375: static void
376: pci_conf_unlock(struct pci_conf_lock *ocl)
377: {
1.62 christos 378: atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel);
1.42 dyoung 379: pci_conf_select(ocl->cl_sel);
380: if (ocl->cl_cpuno != cl->cl_cpuno)
381: atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno);
382: kpreempt_enable();
383: }
384:
1.39 dyoung 385: static uint32_t
386: pci_conf_selector(pcitag_t tag, int reg)
387: {
388: static const pcitag_t mode2_mask = {
389: .mode2 = {
390: .enable = 0xff
391: , .forward = 0xff
392: }
393: };
394:
395: switch (pci_mode) {
396: case 1:
397: return tag.mode1 | reg;
398: case 2:
399: return tag.mode1 & mode2_mask.mode1;
400: default:
1.69 christos 401: panic("%s: mode %d not configured", __func__, pci_mode);
1.39 dyoung 402: }
403: }
404:
405: static unsigned int
406: pci_conf_port(pcitag_t tag, int reg)
407: {
408: switch (pci_mode) {
409: case 1:
410: return PCI_MODE1_DATA_REG;
411: case 2:
412: return tag.mode2.port | reg;
413: default:
1.69 christos 414: panic("%s: mode %d not configured", __func__, pci_mode);
1.39 dyoung 415: }
416: }
417:
418: static void
1.42 dyoung 419: pci_conf_select(uint32_t sel)
1.39 dyoung 420: {
421: pcitag_t tag;
422:
423: switch (pci_mode) {
424: case 1:
1.42 dyoung 425: outl(PCI_MODE1_ADDRESS_REG, sel);
1.39 dyoung 426: return;
427: case 2:
1.42 dyoung 428: tag.mode1 = sel;
1.39 dyoung 429: outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
430: if (tag.mode2.enable != 0)
431: outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
432: return;
433: default:
1.69 christos 434: panic("%s: mode %d not configured", __func__, pci_mode);
1.39 dyoung 435: }
436: }
437:
1.79.8.2! pgoyette 438: static int
! 439: pci_mode_check(void)
! 440: {
! 441: pcireg_t x;
! 442: pcitag_t t;
! 443: int device;
! 444: const int maxdev = pci_bus_maxdevs(NULL, 0);
! 445:
! 446: for (device = 0; device < maxdev; device++) {
! 447: t = pci_make_tag(NULL, 0, device, 0);
! 448: x = pci_conf_read(NULL, t, PCI_CLASS_REG);
! 449: if (PCI_CLASS(x) == PCI_CLASS_BRIDGE &&
! 450: PCI_SUBCLASS(x) == PCI_SUBCLASS_BRIDGE_HOST)
! 451: return 0;
! 452: x = pci_conf_read(NULL, t, PCI_ID_REG);
! 453: switch (PCI_VENDOR(x)) {
! 454: case PCI_VENDOR_COMPAQ:
! 455: case PCI_VENDOR_INTEL:
! 456: case PCI_VENDOR_VIATECH:
! 457: return 0;
! 458: }
! 459: }
! 460: return -1;
! 461: }
1.70 knakahar 462: #ifdef __HAVE_PCI_MSI_MSIX
463: static int
464: pci_has_msi_quirk(pcireg_t id, int type)
465: {
466: int i;
467:
468: for (i = 0; i < __arraycount(pci_msi_quirk_tbl); i++) {
469: if (id == pci_msi_quirk_tbl[i].id &&
470: type == pci_msi_quirk_tbl[i].type)
471: return 1;
472: }
473:
474: return 0;
475: }
476: #endif
477:
1.1 fvdl 478: void
1.32 dyoung 479: pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba)
1.1 fvdl 480: {
1.70 knakahar 481: #ifdef __HAVE_PCI_MSI_MSIX
482: pci_chipset_tag_t pc = pba->pba_pc;
483: pcitag_t tag;
484: pcireg_t id, class;
485: #endif
1.1 fvdl 486:
487: if (pba->pba_bus == 0)
1.26 mjf 488: aprint_normal(": configuration mode %d", pci_mode);
1.4 fvdl 489: #ifdef MPBIOS
490: mpbios_pci_attach_hook(parent, self, pba);
491: #endif
1.37 jmcneill 492: #if NACPICA > 0
1.4 fvdl 493: mpacpi_pci_attach_hook(parent, self, pba);
494: #endif
1.73 jakllsch 495: #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG)
496: acpimcfg_map_bus(self, pba->pba_pc, pba->pba_bus);
497: #endif
1.70 knakahar 498:
499: #ifdef __HAVE_PCI_MSI_MSIX
500: /*
501: * In order to decide whether the system supports MSI we look
502: * at the host bridge, which should be device 0 function 0 on
503: * bus 0. It is better to not enable MSI on systems that
504: * support it than the other way around, so be conservative
505: * here. So we don't enable MSI if we don't find a host
506: * bridge there. We also deliberately don't enable MSI on
507: * chipsets from low-end manifacturers like VIA and SiS.
508: */
509: tag = pci_make_tag(pc, 0, 0, 0);
510: id = pci_conf_read(pc, tag, PCI_ID_REG);
511: class = pci_conf_read(pc, tag, PCI_CLASS_REG);
512:
513: if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
514: PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST)
515: return;
516:
1.77 msaitoh 517: /* VMware and KVM use old chipset, but they can use MSI/MSI-X */
518: if ((cpu_feature[1] & CPUID2_RAZ)
519: && (pci_has_msi_quirk(id, PCI_QUIRK_ENABLE_MSI_VM))) {
520: pba->pba_flags |= PCI_FLAGS_MSI_OKAY;
521: pba->pba_flags |= PCI_FLAGS_MSIX_OKAY;
522: } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSI)) {
1.70 knakahar 523: pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY;
524: pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
1.76 nonaka 525: aprint_verbose("\n");
526: aprint_verbose_dev(self,
527: "This pci host supports neither MSI nor MSI-X.");
1.70 knakahar 528: } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSIX)) {
529: pba->pba_flags |= PCI_FLAGS_MSI_OKAY;
530: pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
1.76 nonaka 531: aprint_verbose("\n");
532: aprint_verbose_dev(self,
533: "This pci host does not support MSI-X.");
1.70 knakahar 534: } else {
535: pba->pba_flags |= PCI_FLAGS_MSI_OKAY;
536: pba->pba_flags |= PCI_FLAGS_MSIX_OKAY;
537: }
538:
539: /*
540: * Don't enable MSI on a HyperTransport bus. In order to
541: * determine that bus 0 is a HyperTransport bus, we look at
542: * device 24 function 0, which is the HyperTransport
543: * host/primary interface integrated on most 64-bit AMD CPUs.
544: * If that device has a HyperTransport capability, bus 0 must
545: * be a HyperTransport bus and we disable MSI.
546: */
1.74 jakllsch 547: if (24 < pci_bus_maxdevs(pc, 0)) {
548: tag = pci_make_tag(pc, 0, 24, 0);
549: if (pci_get_capability(pc, tag, PCI_CAP_LDT, NULL, NULL)) {
550: pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY;
551: pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
552: }
1.70 knakahar 553: }
554: #endif /* __HAVE_PCI_MSI_MSIX */
1.1 fvdl 555: }
556:
557: int
1.18 christos 558: pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
1.1 fvdl 559: {
560: /*
561: * Bus number is irrelevant. If Configuration Mechanism 2 is in
562: * use, can only have devices 0-15 on any bus. If Configuration
563: * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal'
564: * range).
565: */
566: if (pci_mode == 2)
567: return (16);
568: else
569: return (32);
570: }
571:
572: pcitag_t
1.18 christos 573: pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
1.1 fvdl 574: {
1.47 dyoung 575: pci_chipset_tag_t ipc;
1.1 fvdl 576: pcitag_t tag;
577:
1.47 dyoung 578: for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
579: if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0)
580: continue;
581: return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx,
582: pc, bus, device, function);
1.41 dyoung 583: }
1.40 dyoung 584:
1.1 fvdl 585: switch (pci_mode) {
586: case 1:
1.38 dyoung 587: if (bus >= 256 || device >= 32 || function >= 8)
1.69 christos 588: panic("%s: bad request(%d, %d, %d)", __func__,
589: bus, device, function);
1.38 dyoung 590:
591: tag.mode1 = PCI_MODE1_ENABLE |
592: (bus << 16) | (device << 11) | (function << 8);
593: return tag;
1.1 fvdl 594: case 2:
1.38 dyoung 595: if (bus >= 256 || device >= 16 || function >= 8)
1.69 christos 596: panic("%s: bad request(%d, %d, %d)", __func__,
597: bus, device, function);
1.38 dyoung 598:
599: tag.mode2.port = 0xc000 | (device << 8);
600: tag.mode2.enable = 0xf0 | (function << 1);
601: tag.mode2.forward = bus;
602: return tag;
1.1 fvdl 603: default:
1.69 christos 604: panic("%s: mode %d not configured", __func__, pci_mode);
1.1 fvdl 605: }
606: }
607:
608: void
1.18 christos 609: pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
1.17 christos 610: int *bp, int *dp, int *fp)
1.1 fvdl 611: {
1.47 dyoung 612: pci_chipset_tag_t ipc;
1.1 fvdl 613:
1.47 dyoung 614: for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
615: if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0)
616: continue;
617: (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx,
618: pc, tag, bp, dp, fp);
619: return;
1.40 dyoung 620: }
621:
1.1 fvdl 622: switch (pci_mode) {
623: case 1:
1.38 dyoung 624: if (bp != NULL)
625: *bp = (tag.mode1 >> 16) & 0xff;
626: if (dp != NULL)
627: *dp = (tag.mode1 >> 11) & 0x1f;
628: if (fp != NULL)
629: *fp = (tag.mode1 >> 8) & 0x7;
630: return;
1.1 fvdl 631: case 2:
1.38 dyoung 632: if (bp != NULL)
633: *bp = tag.mode2.forward & 0xff;
634: if (dp != NULL)
635: *dp = (tag.mode2.port >> 8) & 0xf;
636: if (fp != NULL)
637: *fp = (tag.mode2.enable >> 1) & 0x7;
638: return;
1.1 fvdl 639: default:
1.69 christos 640: panic("%s: mode %d not configured", __func__, pci_mode);
1.1 fvdl 641: }
642: }
643:
644: pcireg_t
1.43 dyoung 645: pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
1.1 fvdl 646: {
1.47 dyoung 647: pci_chipset_tag_t ipc;
1.1 fvdl 648: pcireg_t data;
1.42 dyoung 649: struct pci_conf_lock ocl;
1.71 msaitoh 650: int dev;
1.1 fvdl 651:
1.31 dyoung 652: KASSERT((reg & 0x3) == 0);
1.40 dyoung 653:
1.47 dyoung 654: for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
655: if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0)
656: continue;
657: return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg);
1.41 dyoung 658: }
1.40 dyoung 659:
1.71 msaitoh 660: pci_decompose_tag(pc, tag, NULL, &dev, NULL);
661: if (__predict_false(pci_mode == 2 && dev >= 16))
662: return (pcireg_t) -1;
663:
664: if (reg < 0)
665: return (pcireg_t) -1;
666: if (reg >= PCI_CONF_SIZE) {
667: #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG)
668: if (reg >= PCI_EXTCONF_SIZE)
669: return (pcireg_t) -1;
670: acpimcfg_conf_read(pc, tag, reg, &data);
671: return data;
672: #else
673: return (pcireg_t) -1;
674: #endif
675: }
676:
1.42 dyoung 677: pci_conf_lock(&ocl, pci_conf_selector(tag, reg));
1.39 dyoung 678: data = inl(pci_conf_port(tag, reg));
1.42 dyoung 679: pci_conf_unlock(&ocl);
1.39 dyoung 680: return data;
1.1 fvdl 681: }
682:
683: void
1.43 dyoung 684: pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
1.1 fvdl 685: {
1.47 dyoung 686: pci_chipset_tag_t ipc;
1.42 dyoung 687: struct pci_conf_lock ocl;
1.71 msaitoh 688: int dev;
1.1 fvdl 689:
1.31 dyoung 690: KASSERT((reg & 0x3) == 0);
1.40 dyoung 691:
1.47 dyoung 692: for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
693: if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0)
694: continue;
695: (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg,
696: data);
697: return;
1.40 dyoung 698: }
699:
1.71 msaitoh 700: pci_decompose_tag(pc, tag, NULL, &dev, NULL);
701: if (__predict_false(pci_mode == 2 && dev >= 16)) {
702: return;
703: }
704:
705: if (reg < 0)
706: return;
707: if (reg >= PCI_CONF_SIZE) {
708: #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG)
709: if (reg >= PCI_EXTCONF_SIZE)
710: return;
711: acpimcfg_conf_write(pc, tag, reg, data);
712: #endif
713: return;
714: }
715:
1.42 dyoung 716: pci_conf_lock(&ocl, pci_conf_selector(tag, reg));
1.39 dyoung 717: outl(pci_conf_port(tag, reg), data);
1.42 dyoung 718: pci_conf_unlock(&ocl);
1.38 dyoung 719: }
1.1 fvdl 720:
1.38 dyoung 721: void
722: pci_mode_set(int mode)
723: {
724: KASSERT(pci_mode == -1 || pci_mode == mode);
1.1 fvdl 725:
1.38 dyoung 726: pci_mode = mode;
1.1 fvdl 727: }
728:
729: int
1.33 cegger 730: pci_mode_detect(void)
1.1 fvdl 731: {
1.33 cegger 732: uint32_t sav, val;
1.1 fvdl 733: int i;
734: pcireg_t idreg;
735:
736: if (pci_mode != -1)
737: return pci_mode;
738:
739: /*
740: * We try to divine which configuration mode the host bridge wants.
741: */
742:
743: sav = inl(PCI_MODE1_ADDRESS_REG);
744:
745: pci_mode = 1; /* assume this for now */
746: /*
747: * catch some known buggy implementations of mode 1
748: */
1.27 dyoung 749: for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) {
1.1 fvdl 750: pcitag_t t;
751:
1.56 jakllsch 752: if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID)
753: continue;
754: t.mode1 = pcim1_quirk_tbl[i].tag.mode1;
755: idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */
1.1 fvdl 756: if (idreg == pcim1_quirk_tbl[i].id) {
757: #ifdef DEBUG
1.67 christos 758: printf("%s: known mode 1 PCI chipset (%08x)\n",
759: __func__, idreg);
1.1 fvdl 760: #endif
761: return (pci_mode);
762: }
763: }
1.66 sborrill 764:
1.79.8.2! pgoyette 765: #if 0
! 766: extern char cpu_brand_string[];
1.67 christos 767: const char *reason, *system_vendor, *system_product;
768: if (memcmp(cpu_brand_string, "QEMU", 4) == 0)
1.61 gson 769: /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */
1.67 christos 770: reason = "QEMU";
771: else if ((system_vendor = pmf_get_platform("system-vendor")) != NULL &&
772: strcmp(system_vendor, "Xen") == 0 &&
773: (system_product = pmf_get_platform("system-product")) != NULL &&
774: strcmp(system_product, "HVM domU") == 0)
775: reason = "Xen";
776: else
777: reason = NULL;
778:
779: if (reason) {
1.61 gson 780: #ifdef DEBUG
1.67 christos 781: printf("%s: forcing PCI mode 1 for %s\n", __func__, reason);
1.61 gson 782: #endif
783: return (pci_mode);
784: }
1.79.8.2! pgoyette 785: #endif
1.1 fvdl 786: /*
787: * Strong check for standard compliant mode 1:
788: * 1. bit 31 ("enable") can be set
789: * 2. byte/word access does not affect register
790: */
791: outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE);
792: outb(PCI_MODE1_ADDRESS_REG + 3, 0);
793: outw(PCI_MODE1_ADDRESS_REG + 2, 0);
794: val = inl(PCI_MODE1_ADDRESS_REG);
795: if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) {
796: #ifdef DEBUG
1.67 christos 797: printf("%s: mode 1 enable failed (%x)\n", __func__, val);
1.1 fvdl 798: #endif
1.79.8.2! pgoyette 799: /* Try out mode 1 to see if we can find a host bridge. */
! 800: if (pci_mode_check() == 0) {
! 801: #ifdef DEBUG
! 802: printf("%s: mode 1 functional, using\n", __func__);
! 803: #endif
! 804: return (pci_mode);
! 805: }
1.1 fvdl 806: goto not1;
807: }
808: outl(PCI_MODE1_ADDRESS_REG, 0);
809: val = inl(PCI_MODE1_ADDRESS_REG);
810: if ((val & 0x80fffffc) != 0)
811: goto not1;
812: return (pci_mode);
813: not1:
814: outl(PCI_MODE1_ADDRESS_REG, sav);
815:
816: /*
817: * This mode 2 check is quite weak (and known to give false
818: * positives on some Compaq machines).
819: * However, this doesn't matter, because this is the
820: * last test, and simply no PCI devices will be found if
821: * this happens.
822: */
823: outb(PCI_MODE2_ENABLE_REG, 0);
824: outb(PCI_MODE2_FORWARD_REG, 0);
825: if (inb(PCI_MODE2_ENABLE_REG) != 0 ||
826: inb(PCI_MODE2_FORWARD_REG) != 0)
827: goto not2;
828: return (pci_mode = 2);
829: not2:
830:
831: return (pci_mode = 0);
832: }
833:
1.11 sekiya 834: void
835: pci_device_foreach(pci_chipset_tag_t pc, int maxbus,
836: void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context)
837: {
838: pci_device_foreach_min(pc, 0, maxbus, func, context);
839: }
840:
841: void
842: pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus,
843: void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context)
844: {
845: const struct pci_quirkdata *qd;
846: int bus, device, function, maxdevs, nfuncs;
847: pcireg_t id, bhlcr;
848: pcitag_t tag;
849:
850: for (bus = minbus; bus <= maxbus; bus++) {
851: maxdevs = pci_bus_maxdevs(pc, bus);
852: for (device = 0; device < maxdevs; device++) {
853: tag = pci_make_tag(pc, bus, device, 0);
854: id = pci_conf_read(pc, tag, PCI_ID_REG);
855:
856: /* Invalid vendor ID value? */
857: if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
858: continue;
859: /* XXX Not invalid, but we've done this ~forever. */
860: if (PCI_VENDOR(id) == 0)
861: continue;
862:
863: qd = pci_lookup_quirkdata(PCI_VENDOR(id),
864: PCI_PRODUCT(id));
865:
866: bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
867: if (PCI_HDRTYPE_MULTIFN(bhlcr) ||
868: (qd != NULL &&
1.55 jakllsch 869: (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0))
1.11 sekiya 870: nfuncs = 8;
871: else
872: nfuncs = 1;
873:
874: for (function = 0; function < nfuncs; function++) {
875: tag = pci_make_tag(pc, bus, device, function);
876: id = pci_conf_read(pc, tag, PCI_ID_REG);
877:
878: /* Invalid vendor ID value? */
879: if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
880: continue;
881: /*
882: * XXX Not invalid, but we've done this
883: * ~forever.
884: */
885: if (PCI_VENDOR(id) == 0)
886: continue;
887: (*func)(pc, tag, context);
888: }
889: }
890: }
891: }
892:
893: void
894: pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus,
895: void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx)
896: {
897: struct pci_bridge_hook_arg bridge_hook;
898:
899: bridge_hook.func = func;
1.55 jakllsch 900: bridge_hook.arg = ctx;
1.11 sekiya 901:
902: pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook,
1.55 jakllsch 903: &bridge_hook);
1.11 sekiya 904: }
905:
906: static void
907: pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx)
908: {
909: struct pci_bridge_hook_arg *bridge_hook = (void *)ctx;
910: pcireg_t reg;
911:
912: reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
913: if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
1.55 jakllsch 914: (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI ||
1.11 sekiya 915: PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {
916: (*bridge_hook->func)(pc, tag, bridge_hook->arg);
917: }
918: }
1.43 dyoung 919:
920: static const void *
921: bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit)
922: {
923: switch (bit) {
924: case PCI_OVERRIDE_CONF_READ:
925: return ov->ov_conf_read;
926: case PCI_OVERRIDE_CONF_WRITE:
927: return ov->ov_conf_write;
928: case PCI_OVERRIDE_INTR_MAP:
929: return ov->ov_intr_map;
930: case PCI_OVERRIDE_INTR_STRING:
931: return ov->ov_intr_string;
932: case PCI_OVERRIDE_INTR_EVCNT:
933: return ov->ov_intr_evcnt;
934: case PCI_OVERRIDE_INTR_ESTABLISH:
935: return ov->ov_intr_establish;
936: case PCI_OVERRIDE_INTR_DISESTABLISH:
937: return ov->ov_intr_disestablish;
938: case PCI_OVERRIDE_MAKE_TAG:
939: return ov->ov_make_tag;
940: case PCI_OVERRIDE_DECOMPOSE_TAG:
941: return ov->ov_decompose_tag;
942: default:
943: return NULL;
944: }
945: }
946:
947: void
948: pci_chipset_tag_destroy(pci_chipset_tag_t pc)
949: {
950: kmem_free(pc, sizeof(struct pci_chipset_tag));
951: }
952:
953: int
954: pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present,
955: const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp)
956: {
957: uint64_t bit, bits, nbits;
958: pci_chipset_tag_t pc;
959: const void *fp;
960:
961: if (ov == NULL || present == 0)
962: return EINVAL;
963:
964: pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP);
965: pc->pc_super = opc;
966:
967: for (bits = present; bits != 0; bits = nbits) {
968: nbits = bits & (bits - 1);
969: bit = nbits ^ bits;
970: if ((fp = bit_to_function_pointer(ov, bit)) == NULL) {
1.51 dyoung 971: #ifdef DEBUG
1.43 dyoung 972: printf("%s: missing bit %" PRIx64 "\n", __func__, bit);
1.51 dyoung 973: #endif
1.43 dyoung 974: goto einval;
975: }
976: }
977:
978: pc->pc_ov = ov;
979: pc->pc_present = present;
980: pc->pc_ctx = ctx;
981:
982: *pcp = pc;
983:
984: return 0;
985: einval:
986: kmem_free(pc, sizeof(struct pci_chipset_tag));
987: return EINVAL;
988: }
1.52 dyoung 989:
990: static void
991: x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b)
992: {
1.57 jakllsch 993: outb(IO_VGA + VGA_DAC_ADDRW, index);
994: outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2);
995: outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2);
996: outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2);
1.52 dyoung 997: }
998:
999: static bool
1000: x86_genfb_setmode(struct genfb_softc *sc, int newmode)
1001: {
1002: #if NGENFB > 0
1.68 christos 1003: # if NACPICA > 0 && defined(VGA_POST)
1.52 dyoung 1004: static int curmode = WSDISPLAYIO_MODE_EMUL;
1.68 christos 1005: # endif
1.52 dyoung 1006:
1007: switch (newmode) {
1008: case WSDISPLAYIO_MODE_EMUL:
1009: x86_genfb_mtrr_init(sc->sc_fboffset,
1010: sc->sc_height * sc->sc_stride);
1.68 christos 1011: # if NACPICA > 0 && defined(VGA_POST)
1.52 dyoung 1012: if (curmode != newmode) {
1013: if (vga_posth != NULL && acpi_md_vesa_modenum != 0) {
1014: vga_post_set_vbe(vga_posth,
1015: acpi_md_vesa_modenum);
1016: }
1017: }
1.68 christos 1018: # endif
1.52 dyoung 1019: break;
1020: }
1021:
1.68 christos 1022: # if NACPICA > 0 && defined(VGA_POST)
1.52 dyoung 1023: curmode = newmode;
1.68 christos 1024: # endif
1.52 dyoung 1025: #endif
1026: return true;
1027: }
1028:
1029: static bool
1030: x86_genfb_suspend(device_t dev, const pmf_qual_t *qual)
1031: {
1032: return true;
1033: }
1034:
1035: static bool
1036: x86_genfb_resume(device_t dev, const pmf_qual_t *qual)
1037: {
1038: #if NGENFB > 0
1039: struct pci_genfb_softc *psc = device_private(dev);
1040:
1041: #if NACPICA > 0 && defined(VGA_POST)
1042: if (vga_posth != NULL && acpi_md_vbios_reset == 2) {
1043: vga_post_call(vga_posth);
1044: if (acpi_md_vesa_modenum != 0)
1045: vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum);
1046: }
1047: #endif
1048: genfb_restore_palette(&psc->sc_gen);
1049: #endif
1050:
1051: return true;
1052: }
1053:
1054: device_t
1055: device_pci_register(device_t dev, void *aux)
1056: {
1057: static bool found_console = false;
1.79.8.1 pgoyette 1058: device_t parent = device_parent(dev);
1.52 dyoung 1059:
1060: device_pci_props_register(dev, aux);
1061:
1062: /*
1063: * Handle network interfaces here, the attachment information is
1064: * not available driver-independently later.
1065: *
1066: * For disks, there is nothing useful available at attach time.
1067: */
1068: if (device_class(dev) == DV_IFNET) {
1069: struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF);
1070: if (bin == NULL)
1071: return NULL;
1072:
1073: /*
1074: * We don't check the driver name against the device name
1075: * passed by the boot ROM. The ROM should stay usable if
1076: * the driver becomes obsolete. The physical attachment
1077: * information (checked below) must be sufficient to
1.55 jakllsch 1078: * identify the device.
1.52 dyoung 1079: */
1.79.8.1 pgoyette 1080: if (bin->bus == BI_BUS_PCI && device_is_a(parent, "pci")) {
1.52 dyoung 1081: struct pci_attach_args *paa = aux;
1082: int b, d, f;
1083:
1084: /*
1085: * Calculate BIOS representation of:
1086: *
1087: * <bus,device,function>
1088: *
1089: * and compare.
1090: */
1091: pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f);
1092: if (bin->addr.tag == ((b << 8) | (d << 3) | f))
1093: return dev;
1.79.8.1 pgoyette 1094:
1095: #ifndef XEN
1096: /*
1097: * efiboot reports parent ppb bus/device/function.
1098: */
1099: device_t grand = device_parent(parent);
1100: if (efi_probe() && grand && device_is_a(grand, "ppb")) {
1101: struct ppb_softc *ppb_sc = device_private(grand);
1102: pci_decompose_tag(ppb_sc->sc_pc, ppb_sc->sc_tag,
1103: &b, &d, &f);
1104: if (bin->addr.tag == ((b << 8) | (d << 3) | f))
1105: return dev;
1106: }
1107: #endif
1.52 dyoung 1108: }
1109: }
1.79.8.1 pgoyette 1110: if (parent && device_is_a(parent, "pci") &&
1.52 dyoung 1111: found_console == false) {
1112: struct btinfo_framebuffer *fbinfo;
1113: struct pci_attach_args *pa = aux;
1114: prop_dictionary_t dict;
1115:
1116: if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) {
1117: #if NWSDISPLAY > 0 && NGENFB > 0
1118: extern struct vcons_screen x86_genfb_console_screen;
1119: struct rasops_info *ri;
1120:
1121: ri = &x86_genfb_console_screen.scr_ri;
1122: #endif
1123:
1124: fbinfo = lookup_bootinfo(BTINFO_FRAMEBUFFER);
1125: dict = device_properties(dev);
1126: /*
1127: * framebuffer drivers other than genfb can work
1128: * without the address property
1129: */
1130: if (fbinfo != NULL) {
1131: if (fbinfo->physaddr != 0) {
1132: prop_dictionary_set_uint32(dict, "width",
1133: fbinfo->width);
1134: prop_dictionary_set_uint32(dict, "height",
1135: fbinfo->height);
1136: prop_dictionary_set_uint8(dict, "depth",
1137: fbinfo->depth);
1138: prop_dictionary_set_uint16(dict, "linebytes",
1139: fbinfo->stride);
1140:
1141: prop_dictionary_set_uint64(dict, "address",
1142: fbinfo->physaddr);
1143: #if NWSDISPLAY > 0 && NGENFB > 0
1144: if (ri->ri_bits != NULL) {
1145: prop_dictionary_set_uint64(dict,
1146: "virtual_address",
1.78 nonaka 1147: ri->ri_hwbits != NULL ?
1148: (vaddr_t)ri->ri_hworigbits :
1.60 macallan 1149: (vaddr_t)ri->ri_origbits);
1.52 dyoung 1150: }
1151: #endif
1152: }
1153: #if notyet
1154: prop_dictionary_set_bool(dict, "splash",
1155: fbinfo->flags & BI_FB_SPLASH ?
1156: true : false);
1157: #endif
1158: if (fbinfo->depth == 8) {
1159: gfb_cb.gcc_cookie = NULL;
1.55 jakllsch 1160: gfb_cb.gcc_set_mapreg =
1.52 dyoung 1161: x86_genfb_set_mapreg;
1162: prop_dictionary_set_uint64(dict,
1163: "cmap_callback",
1164: (uint64_t)(uintptr_t)&gfb_cb);
1165: }
1166: if (fbinfo->physaddr != 0) {
1167: mode_cb.gmc_setmode = x86_genfb_setmode;
1168: prop_dictionary_set_uint64(dict,
1169: "mode_callback",
1170: (uint64_t)(uintptr_t)&mode_cb);
1171: }
1172:
1173: #if NWSDISPLAY > 0 && NGENFB > 0
1174: if (device_is_a(dev, "genfb")) {
1.78 nonaka 1175: prop_dictionary_set_bool(dict,
1176: "enable_shadowfb",
1177: ri->ri_hwbits != NULL ?
1178: true : false);
1179:
1.52 dyoung 1180: x86_genfb_set_console_dev(dev);
1181: #ifdef DDB
1182: db_trap_callback =
1183: x86_genfb_ddb_trap_callback;
1184: #endif
1185: }
1186: #endif
1187: }
1.65 jakllsch 1188: #if 1 && NWSDISPLAY > 0 && NGENFB > 0
1189: /* XXX */
1190: if (device_is_a(dev, "genfb")) {
1191: prop_dictionary_set_bool(dict, "is_console",
1192: genfb_is_console());
1193: } else
1194: #endif
1.52 dyoung 1195: prop_dictionary_set_bool(dict, "is_console", true);
1.60 macallan 1196:
1.52 dyoung 1197: prop_dictionary_set_bool(dict, "clear-screen", false);
1198: #if NWSDISPLAY > 0 && NGENFB > 0
1199: prop_dictionary_set_uint16(dict, "cursor-row",
1200: x86_genfb_console_screen.scr_ri.ri_crow);
1201: #endif
1202: #if notyet
1203: prop_dictionary_set_bool(dict, "splash",
1204: fbinfo->flags & BI_FB_SPLASH ? true : false);
1205: #endif
1206: pmf_cb.gpc_suspend = x86_genfb_suspend;
1207: pmf_cb.gpc_resume = x86_genfb_resume;
1208: prop_dictionary_set_uint64(dict,
1209: "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb);
1210: #ifdef VGA_POST
1211: vga_posth = vga_post_init(pa->pa_bus, pa->pa_device,
1212: pa->pa_function);
1213: #endif
1214: found_console = true;
1215: return NULL;
1216: }
1217: }
1218: return NULL;
1219: }
1.58 soren 1220:
1.64 msaitoh 1221: #ifndef PUC_CNBUS
1222: #define PUC_CNBUS 0
1223: #endif
1224:
1.58 soren 1225: #if NCOM > 0
1226: int
1.64 msaitoh 1227: cpu_puc_cnprobe(struct consdev *cn, struct pci_attach_args *pa)
1.58 soren 1228: {
1229: pci_mode_detect();
1230: pa->pa_iot = x86_bus_space_io;
1.64 msaitoh 1231: pa->pa_memt = x86_bus_space_mem;
1.58 soren 1232: pa->pa_pc = 0;
1.64 msaitoh 1233: pa->pa_tag = pci_make_tag(0, PUC_CNBUS, pci_bus_maxdevs(NULL, 0) - 1,
1234: 0);
1235:
1.58 soren 1236: return 0;
1237: }
1238: #endif
CVSweb <webmaster@jp.NetBSD.org>
![[BACK]](/icons/back.gif){kind=icon}
Return to pci_machdep.c CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [cvs.NetBSD.org] / src / sys / arch / x86 / pci