CVS log for src/sys/arch/x86/pci/ichlpcib.c

Up to [cvs.NetBSD.org] / src / sys / arch / x86 / pci

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Add support for the Braswell PCU LPC to ichlpcib.

Pull up following revision(s) (requested by riastradh in ticket #282):

	sys/dev/pci/ichsmb.c: revision 1.82
	sys/arch/amd64/conf/GENERIC: revision 1.602
	sys/arch/x86/pci/tco.c: revision 1.10
	sys/arch/x86/pci/tco.h: revision 1.5
	sys/arch/x86/pci/ichlpcib.c: revision 1.59
	sys/dev/ic/i82801lpcreg.h: revision 1.17
	sys/arch/x86/pci/files.pci: revision 1.27
	sys/dev/pci/files.pci: revision 1.446

ichsmb(4), tco(4): Add support for TCO on newer Intel chipsets.

TCO (`Total Cost of Ownership', Intel's bizarre name for a watchdog
timer) used to hang off the Intel I/O platform controller hub's (ICH)
low-pin-count interface bridge (LPC IB), or ichlpcib(4).  On newer
devices, it hangs off the ICH SMBus instead.
Tested on INTEL 100SERIES_SMB (works) and INTEL 100SERIES_LP_SMB
(doesn't work, still not sure why).

XXX kernel revbump: This breaks the module ABI -- tco(4) modules
older than the change to make ta_has_rcba into ta_version will
incorrectly attach at buses they do not understand.  (However, the
tco(4) driver is statically built into GENERIC, so maybe it's safe
for pullup since the module wouldn't have worked anyway.)

ichlpcib(4): Use config_detach_children.

Delete a lot of unnecessary code with broken error branches involving
config_detach which have probably seldom if ever been exercised.

No substantive functional change intended.  Low risk because
ichlpcib(4) is not a removable device, so you have to go out of your
way to exercise detach.

ichlpcib(4): KNF.  No functional change intended.

ichsmb(4), tco(4): Add support for TCO on newer Intel chipsets.

TCO (`Total Cost of Ownership', Intel's bizarre name for a watchdog
timer) used to hang off the Intel I/O platform controller hub's (ICH)
low-pin-count interface bridge (LPC IB), or ichlpcib(4).  On newer
devices, it hangs off the ICH SMBus instead.

Tested on INTEL 100SERIES_SMB (works) and INTEL 100SERIES_LP_SMB
(doesn't work, still not sure why).

XXX kernel revbump: This breaks the module ABI -- tco(4) modules
older than the change to make ta_has_rcba into ta_version will
incorrectly attach at buses they do not understand.  (However, the
tco(4) driver is statically built into GENERIC, so maybe it's safe
for pullup since the module wouldn't have worked anyway.)

ichlpcib(4), tco(4): Rename iot -> pmt, ioh -> pmh.

Makes it clearer that this is specifically about the power management
controller (PMC) registers relative to PMBASE.

ichlpcib(4), tco(4): Take `lpcib_' off various names.

For PMC-specific ones, change `lpcib_' to `pmc_'.  These are in a
separate PCI device in newer chipsets.

For TCO-specific ones, which may live in different places, whether at
their own base address or as an offset from PMBASE, just leave it as
`tco_' or `tcotimer'.

No functional change intended.

tco(4): Rename lpcib_tco_attach_args -> tco_attach_args.

No longer hangs off LPC bus, newer devices hang it off SMBus.

tco(4): Change has_rcba bit into version number.

Will be useful for newer Intel platform controller hubs.

No functional change intended.  Module ABI is unchanged, although older
modules will do something nonseneical when confronted with versions
above 1 -- that will require a revbump (but with any luck, it will make
life easier for versions above 2 easier once we do that).

Merge thorpej-cfargs2.

Adapt to CFARGS().

Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
  actually needed.
- Don't be explicit about what interface attribute is attaching if
  the device only has one.  (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
  situations, making is visibly easier to see when indirect config is
  in play, and allowing for future change in semantics.  (As of now,
  this is just a wrapper around config_match(), but that is an
  implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance.  This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

config_found_ia() -> config_found() w/ CFARG_IATTR.

Sync with HEAD

Constify lpcib_devices[] so that it lands in .rodata (1584 bytes).

update from HEAD

Sync with netbsd-5

Pull up following revision(s) (requested by msaitoh in ticket #1295):
	sys/arch/x86/pci/ichlpcib.c: revision 1.50
Add Core 5G (mobile) LPC support.

Sync with HEAD

Pull up following revision(s) (requested by maya in ticket #1213):
	sys/arch/x86/pci/ichlpcib.c: revision 1.51
Disable gpio(4) attachment to ichlpcib(4) by default.
The GPIO lines on an ICH are usually connected to opaque platform-
defined functionality, and may be manipulated by the ACPI DSDT or other
mechanisms behind our backs.  In one instance, it was found this
in combiation with gpio_resume() sabotaged repeated suspend/resume cycles.
GPIO functionality can be enabled by setting ichlpcib_gpio_disable to 0,
for instance with `gdb -write`.

Disable gpio(4) attachment to ichlpcib(4) by default.

The GPIO lines on an ICH are usually connected to opaque platform-
defined functionality, and may be manipulated by the ACPI DSDT or other
mechanisms behind our backs.  In one instance, it was found this
in combiation with gpio_resume() sabotaged repeated suspend/resume cycles.

GPIO functionality can be enabled by setting ichlpcib_gpio_disable to 0,
for instance with `gdb -write`.

Sync with HEAD

 Add Core 5G (mobile) LPC support.

Separate the watchdog code from the pcib code, and make the watchdog
a loadable module.

Pull up following revision(s) (requested by msaitoh in ticket #725):
	sys/arch/x86/pci/ichlpcib.c: revisions 1.47, 1.48
	sys/dev/pci/ichsmb.c: revisions 1.39, 1.40, 1.41
	sys/dev/pci/pucdata.c: revision 1.94
Add 9 Series support.
--
Add Intel C61x and X99 devices.
--
attach Mobile 5th Gen. Core SMBus

Sync with HEAD

Add Intel C61x and X99 devices.

Add 9 Series support.

Pull up following revision(s) (requested by msaitoh in ticket #528):
	sys/dev/pci/ichsmb.c: revision 1.38
	sys/dev/pci/pcidevs: revision 1.1206
	sys/dev/pci/pcidevs: revision 1.1207
	sys/arch/x86/pci/ichlpcib.c: revision 1.44
Change Intel 0x0434 entry:
- Rename DH89XX_QA to DH89XXCC_IQIA
- Modify the description to DH89xxCC PCIe Endpoint and QuickAssist
  (include typo fix)
- Rename DH89xxCC's names from DH89XX_ to DH89XXCC_.
- Add some DH89xxCC's devices.
- Add DH89XXCL's devices.
- Rename PCI_PRODUCT_INTEL_DH89XX_SMB to PCI_PRODUCT_INTEL_DH89XXCC_SMB
- Add PCI_PRODUCT_INTEL_DH89XXCL_SMB
Add DH89xxC[CL] LPC devices.

Pull up following revision(s) (requested by msaitoh in ticket #455):
	sys/arch/x86/pci/ichlpcib.c: revision 1.46

The PMBASE and GPIOBASE registers are not compatible with the PCI spec
and the map sizes are fixed to 128bytes. The pci_mapreg_submap()
function has a code to check the range of the BAR. The
PCI_MAPREG_IO_SIZE() macro returns lower than 128bytes on some
machines. This makes it impossible to use pci_mapreg_submap(). Use
pci_conf_read() and bus_space_map() directly.

Pull up following revision(s) (requested by msaitoh in ticket #1239):
	sys/arch/x86/pci/ichlpcib.c: revision 1.46
The PMBASE and GPIOBASE registers are not
compatible with the PCI spec and the map sizes are fixed to 128bytes. The
pci_mapreg_submap() function has a code to check the range of the BAR. The
PCI_MAPREG_IO_SIZE() macro returns lower than 128bytes on some machines.
This makes it impossible to use pci_mapreg_submap(). Use pci_conf_read() and
bus_space_map() directly.

Pull up following revision(s) (requested by msaitoh in ticket #1944):
	sys/arch/x86/pci/ichlpcib.c: revision 1.46

The PMBASE and GPIOBASE registers are not compltible with the PCI spec
and the map sizes are fixed to 128bytes. The pci_mapreg_submap()
function has a code to check the range of the BAR. The
PCI_MAPREG_IO_SIZE() macro returns lower than 128bytes on some
machines. It makes impossible to use pci_mapreg_submap(). Use
pci_conf_read() and bus_space_map() directly.

Pull up the following changes, requested by msaitoh in ticket #1942:

sys/arch/x86/pci/ichlpcib.c		1.40, 1.45 via patch
sys/dev/ic/i82801lpcreg.h		1.12
sys/dev/pci/pci_map.c			1.32 via patch

	- Fix a bug that ichlpcib(4) maps I/O area incorrectly. It might also
	  fixes ACPI related problem described in PR#48960:
	  - The LPCIB_PCI_PMBASE and LPCIB_PCI_GPIO register are alike PCI BAR
	    but not completely compatible with it. It's ok because the
	    registers' addresses are out of BAR0-BAR5(0x10-0x24) and are
	    located in the device-dependent header. The PMBASE and GPIO
	    registers define the base address and the type but not describe
	    the size. The size is fixed to 128bytes. So use
	    pci_mapreg_submap().
	  - Fix the calculation of the map size in pci_mapreg_submap().
	- Use '\n' at the end of aprint_error_dev() format strings.

Pull up following revision(s) (requested by msaitoh in ticket #1229):
	sys/arch/x86/pci/ichlpcib.c: revision 1.40, 1.45
	sys/dev/pci/pcivar.h: revision 1.101
	sys/dev/pci/pci_map.c: revision 1.32
	sys/dev/ic/i82801lpcreg.h: revision 1.12
Use '\n' at the end of all aprint_error_dev() format strings.
--
Fix a bug that ichlpcib(4) maps I/O area incorrectly and then fails to attach
gpio. It might also fixes ACPI related problem described in PR#48960:
 - The LPCIB_PCI_PMBASE and LPCIB_PCI_GPIO register are alike PCI BAR but not
   completely compatible with it. It's ok because the registers' addresses are
   out of BAR0-BAR5(0x10-0x24) and are located in the device-dependent header.
   The PMBASE and GPIO registers define the base address and the type but not
   describe the size. The size is fixed to 128bytes. So use
   pci_mapreg_submap().
 - Make pci_mapreg_submap() extern again.
 - Fix the calculation of the map size in pci_mapreg_submap().

As I wrote in the last commit, The PMBASE and GPIOBASE registers are not
compltible with the PCI spec and the map sizes are fixed to 128bytes. The
pci_mapreg_submap() function has a code to check the range of the BAR. The
PCI_MAPREG_IO_SIZE() macro returns lower than 128bytes on some machines.
It makes impossible to use pci_mapreg_submap(). Use pci_conf_read() and
bus_space_map() directly. Observed and tested with my Thinkpad X61.

Pull up following revision(s) (requested by msaitoh in ticket #394):
	sys/dev/pci/pcivar.h: revision 1.101
	sys/dev/pci/pci_map.c: revision 1.32
	sys/dev/ic/i82801lpcreg.h: revision 1.12
	sys/arch/x86/pci/ichlpcib.c: revision 1.45
Fix a bug that ichlpcib(4) maps I/O area incorrectly and then fails to attach
gpio. It might also fix ACPI related problem described in PR#48960:
  - The LPCIB_PCI_PMBASE and LPCIB_PCI_GPIO register are alike PCI BAR but not
    completely compatible with it. It's ok because the registers' addresses are
    out of BAR0-BAR5(0x10-0x24) and are located in the device-dependent header.
    The PMBASE and GPIO registers define the base address and the type but not
    describe the size. The size is fixed to 128bytes. So use
    pci_mapreg_submap().
  - Make pci_mapreg_submap() extern again.
  - Fix the calculation of the map size in pci_mapreg_submap().

Fix a bug that ichlpcib(4) maps I/O area incorrectly and then fails to attach
gpio. It might also fix ACPI related problem described in PR#48960:
 - The LPCIB_PCI_PMBASE and LPCIB_PCI_GPIO register are alike PCI BAR but not
   completely compatible with it. It's ok because the registers' addresses are
   out of BAR0-BAR5(0x10-0x24) and are located in the device-dependent header.
   The PMBASE and GPIO registers define the base address and the type but not
   describe the size. The size is fixed to 128bytes. So use
   pci_mapreg_submap().
 - Make pci_mapreg_submap() extern again.
 - Fix the calculation of the map size in pci_mapreg_submap().

Add DH89xxC[CL] LPC devices.

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Add Z68 LPC.

Temporary disable C2000 PCU because the behavior of the wdog is little strange.

Add C2000 Platform Controller Unit(PCU).

Use '\n' at the end of all aprint_error_dev() format strings.

resync from head

Add Intel 8 Series / C220 Series LPC devices.

resync with head

sync with head

sync with (a bit old) head

Match the C600's ichlpcib.

Add Intel 7 series' LPC devices.

Add support 3400 series, 5 series, C216, 82801GH, 82801E and 6300ESB.

No functional change:
- Remove trailing white space.
- Sort entries.
- Remove duplicated entries.

sync with head

Also match ICH8, ICH9 and ICH10 devices.  Tested on ICH10.

Sync with HEAD. Most notably: uvm/pmap work done by rmind@, and MP Xen
work of cherry@.

No regression observed on suspend/restore.

Add some LPC entries for Intel 6 series and C20x.

#include <sys/bus.h> instead of <machine/bus.h>.

Catchup with rmind-uvmplock merge.

Factor out hpet(4) from ichlpcib(4).

sync with head

Rename to use PCI_PRODUCT_INTEL_82801DBM_LPC

Sync with HEAD.

Sync with head.

sync with head

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args.  Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
    pci_intr_map() was a leftover from Xen 2.  Probably a bug.  I
    stopped writing it.  I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
    Probably a bug.  I use a temporary variable.  I have not tested this
    change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
    Probably a bug.  Use a local pci_attach_args.  I have not tested
    this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
    caller's pci_attach_args.  Probably a bug.  Make a local copy of the
    caller's pci_attach_args and modify the copy.  I have not tested
    this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
	HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
	KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
	TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
	OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

sync with head

Sync with HEAD

Sync with HEAD (-D20101022).

sync with head

make it compile.

Sync with HEAD.

Match ichlpcib(4) on ICH0 (82801AB_LPC).

sync with head.

Finish cleaning up pchb from recent change.
Use fewer magic numbers in ichlpcib.
Slightly improve style conformance.
Update paths in cpp re-inclusion guards.

Almost entirely rework Intel Firmware Hub random number generator support.

This introduces fwhrng(4) which attaches via ichlpcib(4), replacing
the rnd(4) support in pchb(4).

Sync with HEAD.

sync to netbsd-5

sync with head

A pointer typedef entails trading too much flexibility to declare const
and non-const types, and the kernel uses both const and non-const
PMF qualifiers and device suspensors, so change the pmf_qual_t and
device_suspensor_t typedefs from "pointers to const" to non-pointer,
non-const types.

Expand PMF_FN_* macros.

Move all copies of ifattr_match() to sys/kern/subr_autoconf.c.

Sync with HEAD.

Make this build without gpio(4).

gpio(4) support for Intel ICH southbridges.

Tested on Intel SS4200-E (ICH7), and Acorp 6A815EPD (ICH2) motherboards,
on amd64 and i386 ports respectively.

It should be noted that the majority of boards with ICH chips do not
expose the GPIO pins for off-board use.  For instance, aside from the
three exposed-on-a-header pins on the 6A815EPD, another pin is also
used to control write protect on the FWH.  The SS4200 exposes the GPIO
on a header that connects to the 10 LEDs on the front panel, as well
as a tact switch on the back panel.

sync with head.

Let us detach ichlpcib(4) and its children.

XXX More testing is needed.  I've tested this on a Dell Dimension 3000,
XXX but that system does not attach every possible device that I try to
XXX detach with this code:

ichlpcib0 at pci0 dev 31 function 0
ichlpcib0: vendor 0x8086 product 0x24d0 (rev. 0x02)
timecounter: Timecounter "ichlpcib0" frequency 3579545 Hz quality 1000
ichlpcib0: 24-bit timer
ichlpcib0: TCO (watchdog) timer configured.
isa0 at ichlpcib0

Pull up following revision(s) (requested by bouyer in ticket #912):
	sys/arch/x86/pci/ichlpcib.c: revision 1.18
Fix watchdog code:
- the timer bound constants are in tick, so convert period to tick before
  checking it against the bounds
- for ICH5 or older, fix code that would have always written a 0 period
  to the register.

Pull up following revision(s) (requested by bouyer in ticket #912):
	sys/arch/x86/pci/ichlpcib.c: revision 1.18
Fix watchdog code:
- the timer bound constants are in tick, so convert period to tick before
  checking it against the bounds
- for ICH5 or older, fix code that would have always written a 0 period
  to the register.

Fix watchdog code:
- the timer bound constants are in tick, so convert period to tick before
  checking it against the bounds
- for ICH5 or older, fix code that would have always written a 0 period
  to the register.

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

sync with head.

Attach 82801IEM LPC Interface Bridge too.

Sync with HEAD.

Pull up following revision(s) (requested by joerg in ticket #669):
	sys/arch/x86/pci/ichlpcib.c: revision 1.16
Restore SpeedStep settings on shutdown. Some BIOSes don't like it, if
SpeedStep is enabled and powerdown fails otherwise. Fixes PR kern/40487.

Restore SpeedStep settings on shutdown. Some BIOSes don't like it, if
SpeedStep is enabled and powerdown fails otherwise. Fixes PR kern/40487.

Sync with HEAD.

don't enable speedstep on systems with intel 82855GM host bridges.

Sync with HEAD.

Sync with HEAD.

Intel Tempest can use ichlpcib as well.

Sync with HEAD.

Sync with wrstuden-revivesa-base-2.

revert some parts of the following commit.
(given that it reverted other developers' changes saying
"misc/cosmetic changes", i assume that it was unintentional.)
this makes a watchdog on my box (8086:24d0) work again.
    ----------------------------
    revision 1.1
    date: 2007/08/26 16:49:47;  author: xtraeme;  state: Exp;
    branches:  1.1.2;
    Some changes for the ichlpcib driver:

    - Moved to x86/pci, so that EM64T systems running NetBSD/amd64 can use it.
    - Added support for the TCO on ICH6 or newer chipsets, adapted from
      FreeBSD.
    - Added timecounter support for the power management timer, adapted from
      OpenBSD.
    - Plus some misc/cosmetic changes.

    Thanks to yukonbob on irc@freenode for testing the TCO part on ICH4-M.
    Tested by me with ICH7 too.

Sync with head.

Make struct pcib_softc explicit in our softc.

Sync with HEAD.

sync with head.

sync with head.

Remove clause 3 and 4 from TNF licenses

- use aprint_*_dev and device_xname
- use POSIX integer types

Sync with HEAD.

sync with head.

sync with head.

sync with HEAD

Split device_t/softc for ichlpcib(4) and all hpet consumers, plus
other related cosmetic changes.

sync with head.

Use PMF_FN_ARGS, PMF_FN_PROTO.

Sync with HEAD.

sync with head

Sync with HEAD

fix some unaligned PCI config space accesses in suspend/resume functions

sync with HEAD

Sync with HEAD.

Sync with head.

sync with head.

Merge jmcneill-pm branch.

Sync with HEAD.

Rename pnp(9) -> pmf(9), as requested by many.

sync with head

Sync with HEAD.

Sync with HEAD. amd64 Xen support needs testing.

tcotimer_setmode: convert seconds to ticks after the value has been
checked with the limits. We can use now the max timeout value on ICH6
or newer (i.e 613 seconds and not the half of it as previously).

GC unused softc field.

sync with HEAD

Refactor PNP API:
- Make suspend/resume directly a device functionality. It consists of
  three layers (class logic, device logic, bus logic), all of them being
  optional. This replaces D0/D3 transitions.
- device_is_active returns true if the device was not disabled and was
  not suspended (even partially), device_is_enabled returns true if the
  device was enabled.
- Change pnp_global_transition into pnp_system_suspend and
  pnp_system_resume. Before running any suspend/resume handlers, check
  that all currently attached devices support power management and bail
  out otherwise. The latter is not done for the shutdown/panic case.
- Make the former bus-specific generic network handlers a class handler.
- Make PNP message like volume up/down/toogle PNP events. Each device
  can register what events they are interested in and whether the handler
  should be global or not.
- Introduce device_active API for devices to mark themselve in use from
  either the system or the device. Use this to implement the idle handling
  for audio and input devices. This is intended to replace most ad-hoc
  watchdogs as well.
- Fix somes situations in which audio resume would lose mixer settings.
- Make USB host controllers better deal with suspend in the light of
  shared interrupts.
- Flush filesystem cache on suspend.
- Flush disk caches on suspend. Put ATA disks into standby on suspend as
  well.
- Adopt drivers to use the new PNP API.
- Fix a critical bug in the generic cardbus layer that made D0->D3
  break.
- Fix ral(4) to set if_stop.
- Convert cbb(4) to the new PNP API.
- Apply the PCI Express SCI fix on resume again.

Sync with head.

Extend device API by device_power_private and device_power_set_private.
The latter is a temporary mean until the pnp_register API itself is
overhault. This functions allow a generic power handler to store its
state independent of the driver.

Use this and revamp the PCI power handling. Pretty much all PCI devices
had power handlers that did the same thing, generalize this in
pci_generic_power_register/deregister and the handler. This interface
offers callbacks for the drivers to save and restore state on
transistions. After a long discussion with jmcneill@ it was considered
to be powerful enough until evidence is shown that devices can handle
D1/D2 with less code and higher speed than without the full
save/restore. The generic code is carefully written to handle device
without PCI-PM support and ensure that the correct registers are written
to when D3 loses all state.

Reimplement the generic PCI network device handling on
top of PCI generic power handling.

Introduce pci_disable_retry as used and implemented locally at least by
ath(4) and iwi(4). Use it in this drivers to restore behaviour from
before the introduction of generic PCI network handling.

Convert all PCI drivers that were using pnp_register to the new
framework. The only exception is vga(4) as it is commonly used as
console device. Add a note therein that this should be fixed later.

Finish previous commit.

Avoid any future confusion by renaming the (unused) first argument of
lpci_hpet_match from "self" to "parent".  Sprinkle a few device_t while
there.

Try to map the HPET window in the match function to deal with the
possible ACPI attachmened HPET earlier and cleaner.

Move variables into the branches where they are used. Make status
32bit wide to match the actual register operations.

Correctly attach HPET on ichlpcib. Patch and hints how to do this
from cube@

XXX because of pcibattach, we need to keep our softcs in sync with pcib(4)

Push the mapping of the HPET register window into the attach function.
This should prevent DIAGNOSTIC from complaining when hpet is attached
via ACPI.

Don't use a global variable to decide whether this is a ICH6+,
use a variable in the softc to determine whether the RCBA is supported.
Add generic HPET support for ICH5 and ICH6+.

This is not (yet) enabled by default, until someone adds the code to
not use the direct attachment if hpet was configured via ACPI.

Merge back power management changes from arch/i386/pci/ichlpcib.c.

Explicitly remember pci_attach_args and drop the corresponding argument
processing.

Sync with HEAD.

sync with head.

Sync with HEAD.

file ichlpcib.c was added on branch vmlocking on 2007-10-09 13:38:43 +0000

file ichlpcib.c was added on branch jmcneill-pm on 2007-09-03 16:47:46 +0000

file ichlpcib.c was added on branch yamt-lazymbuf on 2007-09-03 14:31:22 +0000

file ichlpcib.c was added on branch nick-csl-alignment on 2007-09-03 10:19:51 +0000

Improve some comments.

Attach to ICH8M LPC.
Tested watchdog and it works.
ok xtraeme@

Attach to the ICH9 LPC Interface Bridges. The datasheet doesn't mention
any difference in the TCO part (compared to ICH[678]).

Some changes for the ichlpcib driver:

- Moved to x86/pci, so that EM64T systems running NetBSD/amd64 can use it.
- Added support for the TCO on ICH6 or newer chipsets, adapted from
  FreeBSD.
- Added timecounter support for the power management timer, adapted from
  OpenBSD.
- Plus some misc/cosmetic changes.

Thanks to yukonbob on irc@freenode for testing the TCO part on ICH4-M.
Tested by me with ICH7 too.