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Default branch: MAIN
Current tag: MAIN
Revision 1.63 / (download) - annotate - [select for diffs], Wed Mar 6 11:51:40 2013 UTC (3 months, 1 week ago) by yamt
Branch: MAIN
CVS Tags: khorben-n900,
agc-symver-base,
agc-symver,
HEAD
Changes since 1.62: +32 -1
lines
Diff to previous 1.62 (colored)
some more definitions
Revision 1.62 / (download) - annotate - [select for diffs], Sun Jan 6 22:37:36 2013 UTC (5 months, 1 week ago) by dsl
Branch: MAIN
CVS Tags: yamt-pagecache-base8,
tls-maxphys-nbase,
tls-maxphys-base
Changes since 1.61: +30 -2
lines
Diff to previous 1.61 (colored)
Correct the comment about the extended family and model bits. Add some definitions related to the process extended state enumeration.
Revision 1.61 / (download) - annotate - [select for diffs], Thu Jan 3 23:03:57 2013 UTC (5 months, 1 week ago) by dsl
Branch: MAIN
Changes since 1.60: +73 -36
lines
Diff to previous 1.60 (colored)
Add some missing bit definitions to CPUID2 and those for XCR0. Taken from the August 2012 Intel SDM (intel_x86_325462.pdf). Split all the snprintb() format strings to make them (almost) readable. Fix CPUID_AMD_FLAGS4 to not try to print bits \41 and \42.
Revision 1.60 / (download) - annotate - [select for diffs], Wed Oct 17 16:13:01 2012 UTC (8 months ago) by drochner
Branch: MAIN
CVS Tags: yamt-pagecache-base7,
yamt-pagecache-base6
Changes since 1.59: +7 -4
lines
Diff to previous 1.59 (colored)
recognize the P1GB and RDTSCP which were AMD-only on Intel HW too
Revision 1.59 / (download) - annotate - [select for diffs], Sat May 5 15:08:29 2012 UTC (13 months, 1 week ago) by jym
Branch: MAIN
CVS Tags: yamt-pagecache-base5,
jmcneill-usbmp-base10
Branch point for: tls-maxphys
Changes since 1.58: +19 -13
lines
Diff to previous 1.58 (colored)
Add latest CR4 bits:
- CR4_VMXE: VMX operations, used for hardware virtualization.
- CR4_SMXE: SMX operations, used for safer Mode Extensions (ground for
Intel's TXT - Trusted Execution Technology - platform).
- CR4_FSGSBASE: enable *FSBASE and *GSBASE instructions, for R/W access
to FS/GS segment base addresses.
- CR4_PCIDE: enable Process Context IDentifiers (other architectures may call
these "address space identifiers").
- CR4_OSXSAVE: enable xsave and xrestore instructions
- CR4_SMEP: Supervisor Mode Execution Prevention. Allows enforcing --x rights
from cpl 0.
From Intel® 64 and IA-32 Architectures Software DeveloperÑÔ Manual,
March 2012.
Align declarations.
CPUID_* bits for these features follow.
Revision 1.58 / (download) - annotate - [select for diffs], Mon Apr 30 00:04:31 2012 UTC (13 months, 2 weeks ago) by christos
Branch: MAIN
Changes since 1.57: +6 -1
lines
Diff to previous 1.57 (colored)
Add VIA Eden FCR MSR.
Revision 1.57 / (download) - annotate - [select for diffs], Fri Apr 6 17:23:39 2012 UTC (14 months, 1 week ago) by chs
Branch: MAIN
CVS Tags: yamt-pagecache-base4,
jmcneill-usbmp-base9
Changes since 1.56: +4 -1
lines
Diff to previous 1.56 (colored)
bring in this change from openbsd: Implement the AMD suggested workaround for family 10h & 12h errata 721 "Processor May Incorrectly Update Stack Pointer" by setting a bit marked 'reserved' in an MSR that is only "documented" to exist on 12h.
Revision 1.56 / (download) - annotate - [select for diffs], Fri Mar 2 16:41:00 2012 UTC (15 months, 2 weeks ago) by bouyer
Branch: MAIN
CVS Tags: jmcneill-usbmp-base8,
jmcneill-usbmp-base7,
jmcneill-usbmp-base6,
jmcneill-usbmp-base4
Changes since 1.55: +2 -2
lines
Diff to previous 1.55 (colored)
Don't mask out CPUID_FXSR. If not set, the kernel won't handle SSE and SSE2 registers on context switches; leading to data corruption when running binaries using these instructions (like e.g. binaries built with a -mcpu newer than pentium 4, which enables theses instruction in gcc).
Revision 1.55 / (download) - annotate - [select for diffs], Thu Dec 15 09:38:21 2011 UTC (18 months ago) by abs
Branch: MAIN
CVS Tags: netbsd-6-base,
jmcneill-usbmp-base5,
jmcneill-usbmp-base3,
jmcneill-usbmp-base2
Branch point for: netbsd-6
Changes since 1.54: +17 -1
lines
Diff to previous 1.54 (colored)
Increase MTRR_I686_NVAR_MAX from 8 to 16. Avoids "FIXME: more than 8 MTRRs (10)" message on booting Thinkpad W520 and similar. While here replace a magic number with MTRR_I686_NVAR_MAX * 2
Revision 1.54 / (download) - annotate - [select for diffs], Fri Dec 9 10:08:47 2011 UTC (18 months, 1 week ago) by cegger
Branch: MAIN
Changes since 1.53: +3 -1
lines
Diff to previous 1.53 (colored)
add AMD ucode MSRs
Revision 1.53 / (download) - annotate - [select for diffs], Mon Oct 3 17:31:35 2011 UTC (20 months, 2 weeks ago) by njoly
Branch: MAIN
CVS Tags: yamt-pagecache-base3,
yamt-pagecache-base2,
yamt-pagecache-base,
jmcneill-usbmp-pre-base2,
jmcneill-usbmp-base,
jmcneill-audiomp3-base,
jmcneill-audiomp3
Branch point for: yamt-pagecache,
jmcneill-usbmp
Changes since 1.52: +2 -2
lines
Diff to previous 1.52 (colored)
Do not redefine CPUID_LAHF.
Revision 1.52 / (download) - annotate - [select for diffs], Tue Jul 26 12:59:41 2011 UTC (22 months, 3 weeks ago) by yamt
Branch: MAIN
CVS Tags: jym-xensuspend-nbase,
jym-xensuspend-base
Changes since 1.51: +7 -5
lines
Diff to previous 1.51 (colored)
- add PCID - comment
Revision 1.51 / (download) - annotate - [select for diffs], Sun Feb 20 21:09:32 2011 UTC (2 years, 3 months ago) by jruoho
Branch: MAIN
CVS Tags: rmind-uvmplock-nbase,
rmind-uvmplock-base,
cherry-xenmp-base,
cherry-xenmp,
bouyer-quota2-nbase
Changes since 1.50: +2 -1
lines
Diff to previous 1.50 (colored)
Add MSR_TEMPERATURE_TARGET.
Revision 1.50 / (download) - annotate - [select for diffs], Tue Feb 15 10:11:25 2011 UTC (2 years, 4 months ago) by cegger
Branch: MAIN
CVS Tags: uebayasi-xip-base7,
bouyer-quota2-base
Changes since 1.49: +36 -12
lines
Diff to previous 1.49 (colored)
update cpuid bits
Revision 1.49 / (download) - annotate - [select for diffs], Tue Oct 12 00:39:08 2010 UTC (2 years, 8 months ago) by jakllsch
Branch: MAIN
CVS Tags: uebayasi-xip-base6,
uebayasi-xip-base5,
uebayasi-xip-base4,
uebayasi-xip-base3,
matt-mips64-premerge-20101231,
jruoho-x86intr-base
Branch point for: jruoho-x86intr,
bouyer-quota2
Changes since 1.48: +2 -2
lines
Diff to previous 1.48 (colored)
Correct another off-by-one-bit error. This time for Erratum 97.
Revision 1.48 / (download) - annotate - [select for diffs], Sat Sep 18 15:49:25 2010 UTC (2 years, 9 months ago) by jakllsch
Branch: MAIN
CVS Tags: yamt-nfs-mp-base11
Changes since 1.47: +2 -2
lines
Diff to previous 1.47 (colored)
AMD publication 25759 rev 3.69 says that DisIOReqLock in NB_CFG is "bit 3". They probably mean "bit 3" and not "the third bit" (or bit 2). This change should prevent superfluous warnings of errata 89.
Revision 1.47 / (download) - annotate - [select for diffs], Wed Aug 25 05:07:43 2010 UTC (2 years, 9 months ago) by jruoho
Branch: MAIN
Changes since 1.46: +22 -2
lines
Diff to previous 1.46 (colored)
Add definitions for Intel Digital Thermal Sensor and Power Management, at CPUID Fn0000_0006, %eax, %ecx. Use these instead of magic numbers.
Revision 1.46 / (download) - annotate - [select for diffs], Sat Aug 21 02:59:18 2010 UTC (2 years, 9 months ago) by jruoho
Branch: MAIN
Changes since 1.45: +3 -1
lines
Diff to previous 1.45 (colored)
Add IA32_MPERF (E7h) and IA32_APERF (E8h) as MSR_MPERF and MSR_APERF.
Revision 1.45 / (download) - annotate - [select for diffs], Sat Aug 21 02:31:13 2010 UTC (2 years, 9 months ago) by jruoho
Branch: MAIN
Changes since 1.44: +3 -2
lines
Diff to previous 1.44 (colored)
Add CPUID_APM_CPB at Fn8000_0007 %edx, for core performance boost.
Revision 1.44 / (download) - annotate - [select for diffs], Thu Jul 29 08:16:49 2010 UTC (2 years, 10 months ago) by cegger
Branch: MAIN
CVS Tags: yamt-nfs-mp-base10,
uebayasi-xip-base2
Changes since 1.43: +4 -1
lines
Diff to previous 1.43 (colored)
add RDTSCP_AUX MSR
Revision 1.43 / (download) - annotate - [select for diffs], Sat Jul 24 08:02:46 2010 UTC (2 years, 10 months ago) by cegger
Branch: MAIN
Changes since 1.42: +5 -1
lines
Diff to previous 1.42 (colored)
add AMD OSVW MSRs
Revision 1.42 / (download) - annotate - [select for diffs], Tue Jul 6 20:50:35 2010 UTC (2 years, 11 months ago) by cegger
Branch: MAIN
Changes since 1.41: +2 -1
lines
Diff to previous 1.41 (colored)
Turn PMAP_NOCACHE into MI flag. Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR. Update pmap(9) manpage. hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE. x86: Implement new MI flags using Page-Attribute Tables. x86: Implement BUS_SPACE_MAP_PREFETCHABLE. Patch presented on tech-kern@: http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html No comments on this last version.
Revision 1.41 / (download) - annotate - [select for diffs], Tue May 4 23:27:14 2010 UTC (3 years, 1 month ago) by jym
Branch: MAIN
Changes since 1.40: +1 -3
lines
Diff to previous 1.40 (colored)
Enable the NX bit feature for Xen i386pae and amd64 kernels. Tested with Xen 3.1 and Xen 3.3, dom0 and domU, by bouyer@ and jym@. Ok bouyer@.
Revision 1.40 / (download) - annotate - [select for diffs], Sun Apr 18 23:47:51 2010 UTC (3 years, 2 months ago) by jym
Branch: MAIN
CVS Tags: uebayasi-xip-base1
Changes since 1.39: +14 -4
lines
Diff to previous 1.39 (colored)
This patch fixes the NX regression issue observed on amd64 kernels, where per-page execution right was disabled (therefore leading to the inability of the kernel to detect fraudulent use of memory mappings marked as not being executable). - replace cpu_feature and ci_feature_flags variables by cpu_feature and ci_feat_val arrays. This makes it cleaner and brings kernel code closer to the design of cpuctl(8). A warning will be raised for each CPU that does not expose the same features as the Boot Processor (BP). - the blacklist of CPU features is now a macro defined in the specialreg.h header, instead of hardcoding it inside MD initialization code; fix comments. - replace checks against CPUID_TSC with the cpu_hascounter() function. - clean up the code in init_x86_64(), as cpu_feature variables are set inside cpu_probe(). - use cpu_init_msrs() for i386. It will be eventually used later for NX feature under i386 PAE kernels. - remove code that checks for CPUID_NOX in amd64 mptramp.S, this is already performed by cpu_hatch() through cpu_init_msrs(). - remove cpu_signature and feature_flags members from struct mpbios_proc (they were never used). This patch was tested with i386 MONOLITHIC, XEN3PAE_DOM0 and XEN3_DOM0 under a native i386 host, and amd64 GENERIC, XEN3_DOM0 via QEMU virtual machines. XXX Should kernel rev be bumped? XXX A similar patch should be pulled-up for NetBSD-5, hopefully tomorrow.
Revision 1.39 / (download) - annotate - [select for diffs], Sat Apr 3 23:17:05 2010 UTC (3 years, 2 months ago) by jym
Branch: MAIN
Changes since 1.38: +6 -13
lines
Diff to previous 1.38 (colored)
Fix the comments about cpuid flags, according cpuid documentation by Intel and AMD.
Revision 1.38 / (download) - annotate - [select for diffs], Wed Jan 13 12:54:49 2010 UTC (3 years, 5 months ago) by cegger
Branch: MAIN
CVS Tags: yamt-nfs-mp-base9,
uebayasi-xip-base
Branch point for: uebayasi-xip,
rmind-uvmplock
Changes since 1.37: +4 -2
lines
Diff to previous 1.37 (colored)
recognize SVM PauseFilter
Revision 1.37 / (download) - annotate - [select for diffs], Thu Aug 13 11:27:34 2009 UTC (3 years, 10 months ago) by cegger
Branch: MAIN
CVS Tags: yamt-nfs-mp-base8,
yamt-nfs-mp-base7,
matt-premerge-20091211
Changes since 1.36: +4 -3
lines
Diff to previous 1.36 (colored)
recognize virtual cpu feature indicating guest state.
Revision 1.36 / (download) - annotate - [select for diffs], Tue May 26 01:42:02 2009 UTC (4 years ago) by rmind
Branch: MAIN
CVS Tags: yamt-nfs-mp-base6,
yamt-nfs-mp-base5,
jymxensuspend-base
Changes since 1.35: +2 -1
lines
Diff to previous 1.35 (colored)
Add CPU topology detection support for AMD processors. Tested on the following AMD CPUs: - Family 15, model 65 - Family 15, model 67 - Family 15, model 75 - Family 16, model 2 - Family 17, model 3 Reviewed (slightly older version of patch) by <yamt>.
Revision 1.35 / (download) - annotate - [select for diffs], Sat May 16 13:36:44 2009 UTC (4 years, 1 month ago) by pgoyette
Branch: MAIN
Changes since 1.34: +4 -4
lines
Diff to previous 1.34 (colored)
Correctly identify flag bit for SSSE3 (one of the 'S' was missing). Also rename AMD bit from SCALL/RET to SYSCALL/SYSRET to match Intel bit name.
Revision 1.34 / (download) - annotate - [select for diffs], Wed May 13 22:25:51 2009 UTC (4 years, 1 month ago) by pgoyette
Branch: MAIN
CVS Tags: yamt-nfs-mp-base4
Changes since 1.33: +22 -18
lines
Diff to previous 1.33 (colored)
1. Extend CPU probe of Intel processors to handle extended-models. This allows us to properly identify new Intel 45nm processors, Core i7, Atom, and the 45nm Xeon MP. 2. Properly decode several new Intel cache descriptors, as listed in the most recent (March 2009) edition of Intel's Application Note 485. 3. Convert decode of the various features masks to use the newly added snprintb_m(3) routine. Addresses my PR bin/41289 Addresses my PR bin/41290
Revision 1.33 / (download) - annotate - [select for diffs], Thu Mar 12 09:08:40 2009 UTC (4 years, 3 months ago) by yamt
Branch: MAIN
CVS Tags: yamt-nfs-mp-base3,
nick-hppapmap-base4,
nick-hppapmap-base3,
nick-hppapmap-base
Changes since 1.32: +9 -1
lines
Diff to previous 1.32 (colored)
add definitions for SVM features.
Revision 1.32 / (download) - annotate - [select for diffs], Thu Mar 12 09:07:29 2009 UTC (4 years, 3 months ago) by yamt
Branch: MAIN
Changes since 1.31: +3 -1
lines
Diff to previous 1.31 (colored)
comments
Revision 1.31 / (download) - annotate - [select for diffs], Tue Oct 14 15:49:04 2008 UTC (4 years, 8 months ago) by cegger
Branch: MAIN
CVS Tags: nick-hppapmap-base2,
netbsd-5-base,
netbsd-5-0-RELEASE,
netbsd-5-0-RC4,
netbsd-5-0-RC3,
netbsd-5-0-RC2,
netbsd-5-0-RC1,
netbsd-5-0-2-RELEASE,
netbsd-5-0-1-RELEASE,
netbsd-5-0,
mjf-devfs2-base,
matt-nb5-mips64-u2-k2-k4-k7-k8-k9,
matt-nb5-mips64-u1-k1-k5,
matt-nb5-mips64-premerge-20091211,
matt-nb4-mips64-k7-u2a-k9b,
matt-mips64-base2,
haad-nbase2,
haad-dm-base2,
haad-dm-base1,
haad-dm-base,
ad-audiomp2-base,
ad-audiomp2
Branch point for: nick-hppapmap,
netbsd-5,
matt-nb5-mips64,
jym-xensuspend
Changes since 1.30: +2 -2
lines
Diff to previous 1.30 (colored)
do correct octal counting and use CPUID_APM_FLAGS in cpuctl
Revision 1.30 / (download) - annotate - [select for diffs], Tue Oct 14 14:33:51 2008 UTC (4 years, 8 months ago) by cegger
Branch: MAIN
Changes since 1.29: +20 -1
lines
Diff to previous 1.29 (colored)
add cpuid fn 80000007 %edx: AMD Power Management feature flags
Revision 1.29 / (download) - annotate - [select for diffs], Tue Oct 14 12:22:29 2008 UTC (4 years, 8 months ago) by cegger
Branch: MAIN
Changes since 1.28: +2 -2
lines
Diff to previous 1.28 (colored)
fix output of 3DNOWPREFETCH feature flag
Revision 1.28 / (download) - annotate - [select for diffs], Mon Oct 13 19:14:53 2008 UTC (4 years, 8 months ago) by cegger
Branch: MAIN
Changes since 1.27: +35 -4
lines
Diff to previous 1.27 (colored)
Add cpuid 0x80000001 %ecx features flags. Rename CPUID_MASK4 to CPUID_INTEL_MASK4 for consistency with new CPUID_AMD_MASK4
Revision 1.27 / (download) - annotate - [select for diffs], Tue Aug 26 13:43:47 2008 UTC (4 years, 9 months ago) by pgoyette
Branch: MAIN
CVS Tags: wrstuden-revivesa-base-4,
wrstuden-revivesa-base-3,
wrstuden-revivesa-base-2
Changes since 1.26: +5 -4
lines
Diff to previous 1.26 (colored)
Clean up previous: add bit definitions for some new fields, and use "old" style bitmask_printf(9) format string for consistency with the rest of the file. No functional change. OK cegger@
Revision 1.26 / (download) - annotate - [select for diffs], Sun Aug 24 22:04:21 2008 UTC (4 years, 9 months ago) by pgoyette
Branch: MAIN
Changes since 1.25: +2 -2
lines
Diff to previous 1.25 (colored)
Shorten SYSCALL/SYSRET to SCALL/RET bit definition so it fits on one line.
Revision 1.25 / (download) - annotate - [select for diffs], Sun Aug 24 20:27:34 2008 UTC (4 years, 9 months ago) by pgoyette
Branch: MAIN
Changes since 1.24: +4 -5
lines
Diff to previous 1.24 (colored)
1. For non-Intel vendors, don't overload cpuflags with the extended flags from CPUID 80000001_EDX. Instead, keep the extended flags separate, in ci_feature3_flags (Intel processors already kept a separate ci_feature3_flag value). 2. Decode/display ci_feature3_flag in a vendor-specific manner, since the definitions are vendor-specific. OK cegger@
Revision 1.24 / (download) - annotate - [select for diffs], Sun May 25 15:19:22 2008 UTC (5 years ago) by chris
Branch: MAIN
CVS Tags: yamt-pf42-base4,
yamt-pf42-base3,
wrstuden-revivesa-base-1,
wrstuden-revivesa-base,
simonb-wapbl-nbase,
simonb-wapbl-base,
simonb-wapbl
Branch point for: haad-dm
Changes since 1.23: +6 -1
lines
Diff to previous 1.23 (colored)
Add detection of errata for AMD Family 10h steppings A and 2. Covering
errata:
254: Internal Resource Livelock Involving Cached TLB Reload
261: Processor May Stall Entering Stop-Grant Due to Pending Data
Cache Scrub
298: L2 Eviction May Occur During Processor Operation To Set
Accessed or Dirty Bit
309: Processor Core May Execute Incorrect Instructions on
Concurrent L2 and Northbridge Response
Revision 1.23 / (download) - annotate - [select for diffs], Sun Feb 3 06:19:06 2008 UTC (5 years, 4 months ago) by xtraeme
Branch: MAIN
CVS Tags: yamt-pf42-baseX,
yamt-pf42-base2,
yamt-pf42-base,
yamt-nfs-mp-base2,
yamt-nfs-mp-base,
yamt-lazymbuf-base15,
yamt-lazymbuf-base14,
nick-net80211-sync-base,
nick-net80211-sync,
mjf-devfs-base,
matt-armv6-nbase,
keiichi-mipv6-nbase,
keiichi-mipv6-base,
keiichi-mipv6,
hpcarm-cleanup-nbase,
hpcarm-cleanup-base,
ad-socklock-base1
Branch point for: yamt-pf42,
yamt-nfs-mp,
wrstuden-revivesa,
mjf-devfs2
Changes since 1.22: +10 -4
lines
Diff to previous 1.22 (colored)
Add DTES64 and SSE4 related bits to CPUID2_FLAGS, from FreeBSD.
Revision 1.22 / (download) - annotate - [select for diffs], Fri Dec 21 14:57:22 2007 UTC (5 years, 5 months ago) by drochner
Branch: MAIN
CVS Tags: vmlocking2-base3,
matt-armv6-base,
bouyer-xeni386-nbase,
bouyer-xeni386-base
Changes since 1.21: +3 -2
lines
Diff to previous 1.21 (colored)
define the SSSE3 feature flag bit and print out all known bits
Revision 1.21 / (download) - annotate - [select for diffs], Mon Oct 29 00:42:29 2007 UTC (5 years, 7 months ago) by xtraeme
Branch: MAIN
CVS Tags: yamt-kmem-base3,
yamt-kmem-base2,
yamt-kmem-base,
yamt-kmem,
vmlocking2-base2,
vmlocking2-base1,
vmlocking-nbase,
reinoud-bufcleanup-nbase,
reinoud-bufcleanup-base,
jmcneill-pm-base,
jmcneill-base,
cube-autoconf-base,
cube-autoconf,
bouyer-xenamd64-base2,
bouyer-xenamd64-base
Branch point for: vmlocking2,
mjf-devfs,
bouyer-xeni386
Changes since 1.20: +2 -1
lines
Diff to previous 1.20 (colored)
Add coretemp(4). A new driver for Intel Core's on-die thermal sensor, available on Intel Core or newer CPUs. Ported from FreeBSD. Tested by rmind on i386 and joerg on amd64. Enabled with "options INTEL_CORETEMP".
Revision 1.20 / (download) - annotate - [select for diffs], Wed Oct 17 19:58:15 2007 UTC (5 years, 8 months ago) by garbled
Branch: MAIN
CVS Tags: yamt-x86pmap-base4
Changes since 1.19: +1 -1
lines
Diff to previous 1.19 (colored)
Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
Revision 1.19 / (download) - annotate - [select for diffs], Wed Sep 26 19:48:38 2007 UTC (5 years, 8 months ago) by ad
Branch: MAIN
CVS Tags: yamt-x86pmap-base3,
yamt-x86pmap-base2,
vmlocking-base,
ppcoea-renovation-base
Branch point for: bouyer-xenamd64
Changes since 1.18: +1 -7
lines
Diff to previous 1.18 (colored)
x86 changes for pcc and LKMs. - Replace most inline assembly with proper functions. As a side effect this reduces the size of amd64 GENERIC by about 120kB, and i386 by a smaller amount. Nearly all of the inlines did something slow, or something that does not need to be fast. - Make curcpu() and curlwp functions proper, unless __GNUC__ && _KERNEL. In that case make them inlines. Makes curlwp LKM and preemption safe. - Make bus_space and bus_dma more LKM friendly. - Share a few more files between the ports. - Other minor changes.
Revision 1.18 / (download) - annotate - [select for diffs], Wed Jul 11 11:56:36 2007 UTC (5 years, 11 months ago) by njoly
Branch: MAIN
CVS Tags: yamt-x86pmap-base,
nick-csl-alignment-base5,
nick-csl-alignment-base,
nick-csl-alignment,
mjf-ufs-trans-base,
matt-mips64-base,
matt-mips64,
hpcarm-cleanup
Branch point for: yamt-x86pmap,
matt-armv6,
jmcneill-pm
Changes since 1.17: +4 -3
lines
Diff to previous 1.17 (colored)
Display RDTSCP bit on AMD processors (Read Serialized TSC Pair). ok by xtraeme
Revision 1.17 / (download) - annotate - [select for diffs], Tue Jul 3 17:07:55 2007 UTC (5 years, 11 months ago) by christos
Branch: MAIN
Changes since 1.16: +13 -4
lines
Diff to previous 1.16 (colored)
Support for VIA Esther (From FreeBSD)
Revision 1.16 / (download) - annotate - [select for diffs], Mon Jun 4 16:21:29 2007 UTC (6 years ago) by xtraeme
Branch: MAIN
Changes since 1.15: +7 -2
lines
Diff to previous 1.15 (colored)
Add four missing bits for CPUID2_FLAGS, from FreeBSD.
Revision 1.15 / (download) - annotate - [select for diffs], Sat Feb 17 00:28:25 2007 UTC (6 years, 4 months ago) by daniel
Branch: MAIN
CVS Tags: yamt-idlelwp-base8,
thorpej-atomic-base,
thorpej-atomic,
reinoud-bufcleanup,
ad-audiomp-base,
ad-audiomp
Branch point for: yamt-idlelwp,
vmlocking,
ppcoea-renovation,
mjf-ufs-trans
Changes since 1.14: +20 -1
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Diff to previous 1.14 (colored)
Add an opencrypto provider for the AES xcrypt instructions found on VIA C5P and later cores (also known as 'ACE', which is part of the VIA PadLock security engine). Ported from OpenBSD. Reviewed on tech-crypto and port-i386, no objections to commiting this.
Revision 1.14 / (download) - annotate - [select for diffs], Tue Jan 16 15:43:44 2007 UTC (6 years, 5 months ago) by christos
Branch: MAIN
CVS Tags: post-newlock2-merge,
newlock2-nbase,
newlock2-base
Changes since 1.13: +8 -4
lines
Diff to previous 1.13 (colored)
PR/35430: Izumi Tsutsui: Identify amd64 CPU on NetBSD/i386
Revision 1.13 / (download) - annotate - [select for diffs], Thu Jan 11 17:24:30 2007 UTC (6 years, 5 months ago) by ad
Branch: MAIN
Changes since 1.12: +4 -3
lines
Diff to previous 1.12 (colored)
x86_errata: correct the definition of MSR_HWCR and re-enable. Problem noted and debugged by Murray Armfield (murray at river-styx.org).
Revision 1.12 / (download) - annotate - [select for diffs], Mon Jan 1 20:56:59 2007 UTC (6 years, 5 months ago) by ad
Branch: MAIN
Changes since 1.11: +45 -1
lines
Diff to previous 1.11 (colored)
Report on and where possible, try to work around some of the known errata for Athlon 64 and Opteron processors. Tested briefly by cube@ and elad@.
Revision 1.11 / (download) - annotate - [select for diffs], Sun Sep 3 06:49:57 2006 UTC (6 years, 9 months ago) by xtraeme
Branch: MAIN
CVS Tags: yamt-splraiseipl-base5,
yamt-splraiseipl-base4,
yamt-splraiseipl-base3,
yamt-splraiseipl-base2,
yamt-splraiseipl-base,
yamt-splraiseipl,
yamt-pdpolicy-base9,
yamt-pdpolicy-base8,
rpaulo-netinet-merge-pcb-base,
netbsd-4-base
Branch point for: newlock2,
netbsd-4
Changes since 1.10: +3 -1
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Diff to previous 1.10 (colored)
Update the enhanced speedstep driver and sync the code with OpenBSD: est.c: * Use a quintuplet (vendor, MHz_hi, mV_hi, MHz_lo, mV_lo } to match CPUs more correctly than parsing the brand string. * Add support for a bunch of models. * Create a fake table on the fly if the CPU is unknown (there's no table for it) with the current/highest/lowest frequency. specialreg.h: * Add some MSRs needed to get the bus clock value. identcpu.c: * Add functions specific to Pentium III, Pentium M and Pentium 4 to get the bus clock value. Note that the new fake table code from Simon Burge is not included on this commit. Ok'ed by simonb and dogcow.
Revision 1.10 / (download) - annotate - [select for diffs], Thu Aug 24 12:55:46 2006 UTC (6 years, 9 months ago) by cube
Branch: MAIN
Changes since 1.9: +4 -3
lines
Diff to previous 1.9 (colored)
Display XD for Intel processors (Execution Disable bit support).
Revision 1.9 / (download) - annotate - [select for diffs], Fri Dec 2 17:11:19 2005 UTC (7 years, 6 months ago) by christos
Branch: MAIN
CVS Tags: yamt-uio_vmspace-base5,
yamt-uio_vmspace,
yamt-pdpolicy-base7,
yamt-pdpolicy-base6,
yamt-pdpolicy-base5,
yamt-pdpolicy-base4,
yamt-pdpolicy-base3,
yamt-pdpolicy-base2,
yamt-pdpolicy-base,
simonb-timecounters-base,
simonb-timecounters,
simonb-timcounters-final,
peter-altq-base,
peter-altq,
ktrace-lwp-base,
gdamore-uart-base,
gdamore-uart,
elad-kernelauth-base,
elad-kernelauth,
chap-midi-nbase,
chap-midi-base,
chap-midi,
abandoned-netbsd-4-base
Branch point for: yamt-pdpolicy,
rpaulo-netinet-merge-pcb,
abandoned-netbsd-4
Changes since 1.8: +2 -2
lines
Diff to previous 1.8 (colored)
PR/32216: Nicolas Joly: Missing HTT feature display for Opterons dual-core CPUs
Revision 1.8 / (download) - annotate - [select for diffs], Mon Feb 21 15:10:51 2005 UTC (8 years, 3 months ago) by he
Branch: MAIN
CVS Tags: yamt-vop-base3,
yamt-vop-base2,
yamt-vop-base,
yamt-vop,
yamt-readahead-pervnode,
yamt-readahead-perfile,
yamt-readahead-base3,
yamt-readahead-base2,
yamt-readahead-base,
yamt-readahead,
yamt-km-base4,
yamt-km-base3,
thorpej-vnode-attr-base,
thorpej-vnode-attr,
netbsd-3-base,
netbsd-3-1-RELEASE,
netbsd-3-1-RC4,
netbsd-3-1-RC3,
netbsd-3-1-RC2,
netbsd-3-1-RC1,
netbsd-3-1-1-RELEASE,
netbsd-3-1,
netbsd-3-0-RELEASE,
netbsd-3-0-RC6,
netbsd-3-0-RC5,
netbsd-3-0-RC4,
netbsd-3-0-RC3,
netbsd-3-0-RC2,
netbsd-3-0-RC1,
netbsd-3-0-3-RELEASE,
netbsd-3-0-2-RELEASE,
netbsd-3-0-1-RELEASE,
netbsd-3-0,
netbsd-3,
kent-audio2-base
Branch point for: yamt-lazymbuf
Changes since 1.7: +10 -1
lines
Diff to previous 1.7 (colored)
Probe and print the Intel Extended Feature Bits, as documented in the CPUID instruction description in the "Intel Extended Memory 64 Technology Software Developer's Guide, Volume 1 of 2" available at ftp://download.intel.com/technology/64bitextensions/30083402.pdf This presently consists of the SYSCALL/SYSRET and the EM64T features. CPUs with the EM64T feature available should be able to run amd64 code. Reviewed by fvdl
Revision 1.7 / (download) - annotate - [select for diffs], Thu Feb 10 20:52:52 2005 UTC (8 years, 4 months ago) by drochner
Branch: MAIN
CVS Tags: yamt-km-base2,
matt-timespec
Changes since 1.6: +4 -2
lines
Diff to previous 1.6 (colored)
Recognize an obscure cpu feature flag bit "xTPR" which indicates that Task Priority Messages might be disabled. Not relevant for the kernel for now (related to interrupt distribution on the APIC bus afaict), but present on one of my boxes. Being here, also recognise the future "Vanderpool" extension.
Revision 1.6 / (download) - annotate - [select for diffs], Mon May 17 15:38:17 2004 UTC (9 years, 1 month ago) by joda
Branch: MAIN
CVS Tags: yamt-km-base,
kent-audio1-beforemerge,
kent-audio1-base,
kent-audio1
Branch point for: yamt-km,
kent-audio2
Changes since 1.5: +7 -4
lines
Diff to previous 1.5 (colored)
the EST and TM2 flags in the second cpuid register were swapped (according AP-485); while here add a few more flags
Revision 1.5 / (download) - annotate - [select for diffs], Thu Feb 19 17:09:39 2004 UTC (9 years, 4 months ago) by drochner
Branch: MAIN
CVS Tags: netbsd-2-base,
netbsd-2-1-RELEASE,
netbsd-2-1-RC6,
netbsd-2-1-RC5,
netbsd-2-1-RC4,
netbsd-2-1-RC3,
netbsd-2-1-RC2,
netbsd-2-1-RC1,
netbsd-2-1,
netbsd-2-0-base,
netbsd-2-0-RELEASE,
netbsd-2-0-RC5,
netbsd-2-0-RC4,
netbsd-2-0-RC3,
netbsd-2-0-RC2,
netbsd-2-0-RC1,
netbsd-2-0-3-RELEASE,
netbsd-2-0-2-RELEASE,
netbsd-2-0-1-RELEASE,
netbsd-2-0,
netbsd-2
Changes since 1.4: +2 -1
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Diff to previous 1.4 (colored)
define AMD64's CPUID_NOX bit (I'm curious where Intel puts this bit in the ia32 extension just announced) XXX there should be a better separation between generic and vendor specific feature flags
Revision 1.4 / (download) - annotate - [select for diffs], Mon Feb 2 08:28:00 2004 UTC (9 years, 4 months ago) by soren
Branch: MAIN
Changes since 1.3: +19 -2
lines
Diff to previous 1.3 (colored)
Add Pentium M MSR definitions from Michael Eriksson.
Revision 1.3 / (download) - annotate - [select for diffs], Thu Aug 7 16:30:33 2003 UTC (9 years, 10 months ago) by agc
Branch: MAIN
Changes since 1.2: +2 -6
lines
Diff to previous 1.2 (colored)
Move UCB-licensed code from 4-clause to 3-clause licence. Patches provided by Joel Baker in PR 22364, verified by myself.
Revision 1.2 / (download) - annotate - [select for diffs], Fri Apr 25 21:54:30 2003 UTC (10 years, 1 month ago) by fvdl
Branch: MAIN
Branch point for: ktrace-lwp
Changes since 1.1: +8 -3
lines
Diff to previous 1.1 (colored)
Share some common cache info cpuid code between i386 and x86_64.
Revision 1.1 / (download) - annotate - [select for diffs], Wed Feb 26 21:26:11 2003 UTC (10 years, 3 months ago) by fvdl
Branch: MAIN
Move some files out of i386 into x86, so that they can be shared with other ports.