Annotation of src/sys/arch/x86/include/specialreg.h, Revision 1.15.6.2
1.15.6.2! ad 1: /* $NetBSD: specialreg.h,v 1.15.6.1 2007/06/09 23:55:31 ad Exp $ */
1.1 fvdl 2:
3: /*-
4: * Copyright (c) 1991 The Regents of the University of California.
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
1.3 agc 15: * 3. Neither the name of the University nor the names of its contributors
1.1 fvdl 16: * may be used to endorse or promote products derived from this software
17: * without specific prior written permission.
18: *
19: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29: * SUCH DAMAGE.
30: *
31: * @(#)specialreg.h 7.1 (Berkeley) 5/9/91
32: */
33:
34: /*
35: * Bits in 386 special registers:
36: */
37: #define CR0_PE 0x00000001 /* Protected mode Enable */
38: #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
39: #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
40: #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
41: #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
42: #define CR0_PG 0x80000000 /* PaGing enable */
43:
44: /*
45: * Bits in 486 special registers:
46: */
47: #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
48: #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
49: #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
50: #define CR0_NW 0x20000000 /* Not Write-through */
51: #define CR0_CD 0x40000000 /* Cache Disable */
52:
53: /*
54: * Cyrix 486 DLC special registers, accessible as IO ports.
55: */
56: #define CCR0 0xc0 /* configuration control register 0 */
57: #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */
58: #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
59: #define CCR0_A20M 0x04 /* enables A20M# input pin */
60: #define CCR0_KEN 0x08 /* enables KEN# input pin */
61: #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
62: #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */
63: #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
64: #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
65:
66: #define CCR1 0xc1 /* configuration control register 1 */
67: #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
68: /* the remaining 7 bits of this register are reserved */
69:
70: /*
71: * bits in the pentiums %cr4 register:
72: */
73:
74: #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
75: #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
76: #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */
77: #define CR4_DE 0x00000008 /* debugging extension */
78: #define CR4_PSE 0x00000010 /* large (4MB) page size enable */
79: #define CR4_PAE 0x00000020 /* physical address extension enable */
80: #define CR4_MCE 0x00000040 /* machine check enable */
81: #define CR4_PGE 0x00000080 /* page global enable */
82: #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
83: #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */
84: #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
85:
86: /*
1.4 soren 87: * CPUID "features" bits in %edx
1.1 fvdl 88: */
89:
90: #define CPUID_FPU 0x00000001 /* processor has an FPU? */
91: #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
92: #define CPUID_DE 0x00000004 /* has debugging extension */
93: #define CPUID_PSE 0x00000008 /* has page 4MB page size extension */
94: #define CPUID_TSC 0x00000010 /* has time stamp counter */
95: #define CPUID_MSR 0x00000020 /* has mode specific registers */
96: #define CPUID_PAE 0x00000040 /* has phys address extension */
97: #define CPUID_MCE 0x00000080 /* has machine check exception */
98: #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
99: #define CPUID_APIC 0x00000200 /* has enabled APIC */
100: #define CPUID_B10 0x00000400 /* reserved, MTRR */
101: #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
102: #define CPUID_MTRR 0x00001000 /* has memory type range register */
103: #define CPUID_PGE 0x00002000 /* has page global extension */
104: #define CPUID_MCA 0x00004000 /* has machine check architecture */
105: #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
106: #define CPUID_PAT 0x00010000 /* Page Attribute Table */
107: #define CPUID_PSE36 0x00020000 /* 36-bit PSE */
108: #define CPUID_PN 0x00040000 /* processor serial number */
109: #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
110: #define CPUID_B20 0x00100000 /* reserved */
111: #define CPUID_DS 0x00200000 /* Debug Store */
112: #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
113: #define CPUID_MMX 0x00800000 /* MMX supported */
114: #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */
115: #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */
116: #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */
117: #define CPUID_SS 0x08000000 /* self-snoop */
118: #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
119: #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
120: #define CPUID_IA64 0x40000000 /* IA-64 architecture */
121: #define CPUID_SBF 0x80000000 /* signal break on FERR */
122:
123: #define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE" \
124: "\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR"
125: #define CPUID_MASK1 0x00001fff
126: #define CPUID_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN\24CFLUSH" \
127: "\25B20\26DS\27ACPI\30MMX"
128: #define CPUID_MASK2 0x00ffe000
129: #define CPUID_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM\37IA64\40SBF"
130: #define CPUID_MASK3 0xff000000
131:
132: /*
1.8 he 133: * CPUID Intel extended features
134: */
135: #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */
1.10 cube 136: #define CPUID_XD 0x00100000 /* Execute Disable */
1.8 he 137: #define CPUID_EM64T 0x20000000 /* Intel EM64T */
138:
1.10 cube 139: #define CPUID_MASK4 0x20100800
140: #define CPUID_FLAGS4 "\20\14SYSCALL/SYSRET\25XD\36EM64T"
1.8 he 141:
142: /*
1.1 fvdl 143: * AMD/VIA processor specific flags.
144: */
145:
146: #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */
1.5 drochner 147: #define CPUID_NOX 0x00100000 /* No Execute Page Protection */
1.1 fvdl 148: #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */
1.15.6.2! ad 149: #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */
1.1 fvdl 150: #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
151: #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
152:
153: #define CPUID_EXT_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \
1.2 fvdl 154: "\24MPC\25NOX\26B21\27MMXX\30MMX"
1.15.6.2! ad 155: #define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34RDTSCP\35HTT" \
! 156: "\36LONG\0373DNOW2\0403DNOW"
1.1 fvdl 157:
1.4 soren 158: /*
1.15.6.2! ad 159: * Centaur Extended Feature flags
1.15 daniel 160: */
1.15.6.2! ad 161: #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */
! 162: #define CPUID_VIA_DO_RNG 0x00000008
! 163: #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */
! 164: #define CPUID_VIA_DO_ACE 0x00000080
! 165: #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */
! 166: #define CPUID_VIA_DO_ACE2 0x00000200
! 167: #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */
! 168: #define CPUID_VIA_DO_PHE 0x00000800
! 169: #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */
! 170: #define CPUID_VIA_DO_PMM 0x00002000
1.15 daniel 171:
1.15.6.2! ad 172: #define CPUID_FLAGS_PADLOCK "\20\3RNG\7AES\11AES/CTR\13SHA1/SHA256\15RSA"
1.15 daniel 173:
174: /*
1.4 soren 175: * CPUID "features" bits in %ecx
176: */
177:
1.6 joda 178: #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
179: #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
180: #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
1.7 drochner 181: #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */
1.15.6.1 ad 182: #define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */
1.6 joda 183: #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */
184: #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
1.4 soren 185: #define CPUID2_CID 0x00000400 /* Context ID */
1.15.6.1 ad 186: #define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
1.7 drochner 187: #define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
1.15.6.1 ad 188: #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */
189: #define CPUID2_DCA 0x00040000 /* Direct Cache Access */
1.4 soren 190:
1.15.6.1 ad 191: #define CPUID2_FLAGS "\20\1SSE3\4MONITOR\5DS-CPL\6VMX\7SMX\10EST\11TM2" \
192: "\13CID\17xTPR\20PDCM\23DCA"
1.4 soren 193:
1.14 christos 194: #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf)
195: #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf)
196: #define CPUID2STEPPING(cpuid) ((cpuid) & 0xf)
197:
198: /* Extended family and model are defined on amd64 processors */
199: #define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)
200: #define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf)
1.2 fvdl 201:
202: #define CPUID(code, eax, ebx, ecx, edx) \
203: __asm("cpuid" \
204: : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
205: : "a" (code));
1.1 fvdl 206:
207:
208: /*
209: * Model-specific registers for the i386 family
210: */
211: #define MSR_P5_MC_ADDR 0x000 /* P5 only */
212: #define MSR_P5_MC_TYPE 0x001 /* P5 only */
213: #define MSR_TSC 0x010
214: #define MSR_CESR 0x011 /* P5 only (trap on P6) */
215: #define MSR_CTR0 0x012 /* P5 only (trap on P6) */
216: #define MSR_CTR1 0x013 /* P5 only (trap on P6) */
217: #define MSR_APICBASE 0x01b
218: #define MSR_EBL_CR_POWERON 0x02a
1.11 xtraeme 219: #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */
1.1 fvdl 220: #define MSR_TEST_CTL 0x033
221: #define MSR_BIOS_UPDT_TRIG 0x079
222: #define MSR_BBL_CR_D0 0x088 /* PII+ only */
223: #define MSR_BBL_CR_D1 0x089 /* PII+ only */
224: #define MSR_BBL_CR_D2 0x08a /* PII+ only */
225: #define MSR_BIOS_SIGN 0x08b
226: #define MSR_PERFCTR0 0x0c1
227: #define MSR_PERFCTR1 0x0c2
1.11 xtraeme 228: #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */
1.1 fvdl 229: #define MSR_MTRRcap 0x0fe
230: #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
231: #define MSR_BBL_CR_DECC 0x118 /* PII+ only */
232: #define MSR_BBL_CR_CTL 0x119 /* PII+ only */
233: #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */
234: #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */
235: #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */
236: #define MSR_SYSENTER_CS 0x174 /* PII+ only */
237: #define MSR_SYSENTER_ESP 0x175 /* PII+ only */
238: #define MSR_SYSENTER_EIP 0x176 /* PII+ only */
239: #define MSR_MCG_CAP 0x179
240: #define MSR_MCG_STATUS 0x17a
241: #define MSR_MCG_CTL 0x17b
242: #define MSR_EVNTSEL0 0x186
243: #define MSR_EVNTSEL1 0x187
1.4 soren 244: #define MSR_PERF_STATUS 0x198 /* Pentium M */
245: #define MSR_PERF_CTL 0x199 /* Pentium M */
246: #define MSR_THERM_CONTROL 0x19a
247: #define MSR_THERM_INTERRUPT 0x19b
248: #define MSR_THERM_STATUS 0x19c
249: #define MSR_THERM2_CTL 0x19d /* Pentium M */
250: #define MSR_MISC_ENABLE 0x1a0
1.1 fvdl 251: #define MSR_DEBUGCTLMSR 0x1d9
252: #define MSR_LASTBRANCHFROMIP 0x1db
253: #define MSR_LASTBRANCHTOIP 0x1dc
254: #define MSR_LASTINTFROMIP 0x1dd
255: #define MSR_LASTINTTOIP 0x1de
256: #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
257: #define MSR_MTRRphysBase0 0x200
258: #define MSR_MTRRphysMask0 0x201
259: #define MSR_MTRRphysBase1 0x202
260: #define MSR_MTRRphysMask1 0x203
261: #define MSR_MTRRphysBase2 0x204
262: #define MSR_MTRRphysMask2 0x205
263: #define MSR_MTRRphysBase3 0x206
264: #define MSR_MTRRphysMask3 0x207
265: #define MSR_MTRRphysBase4 0x208
266: #define MSR_MTRRphysMask4 0x209
267: #define MSR_MTRRphysBase5 0x20a
268: #define MSR_MTRRphysMask5 0x20b
269: #define MSR_MTRRphysBase6 0x20c
270: #define MSR_MTRRphysMask6 0x20d
271: #define MSR_MTRRphysBase7 0x20e
272: #define MSR_MTRRphysMask7 0x20f
273: #define MSR_MTRRfix64K_00000 0x250
274: #define MSR_MTRRfix16K_80000 0x258
275: #define MSR_MTRRfix16K_A0000 0x259
276: #define MSR_MTRRfix4K_C0000 0x268
277: #define MSR_MTRRfix4K_C8000 0x269
278: #define MSR_MTRRfix4K_D0000 0x26a
279: #define MSR_MTRRfix4K_D8000 0x26b
280: #define MSR_MTRRfix4K_E0000 0x26c
281: #define MSR_MTRRfix4K_E8000 0x26d
282: #define MSR_MTRRfix4K_F0000 0x26e
283: #define MSR_MTRRfix4K_F8000 0x26f
284: #define MSR_MTRRdefType 0x2ff
285: #define MSR_MC0_CTL 0x400
286: #define MSR_MC0_STATUS 0x401
287: #define MSR_MC0_ADDR 0x402
288: #define MSR_MC0_MISC 0x403
289: #define MSR_MC1_CTL 0x404
290: #define MSR_MC1_STATUS 0x405
291: #define MSR_MC1_ADDR 0x406
292: #define MSR_MC1_MISC 0x407
293: #define MSR_MC2_CTL 0x408
294: #define MSR_MC2_STATUS 0x409
295: #define MSR_MC2_ADDR 0x40a
296: #define MSR_MC2_MISC 0x40b
297: #define MSR_MC4_CTL 0x40c
298: #define MSR_MC4_STATUS 0x40d
299: #define MSR_MC4_ADDR 0x40e
300: #define MSR_MC4_MISC 0x40f
301: #define MSR_MC3_CTL 0x410
302: #define MSR_MC3_STATUS 0x411
303: #define MSR_MC3_ADDR 0x412
304: #define MSR_MC3_MISC 0x413
305:
306: /*
1.15 daniel 307: * VIA "Nehemiah" MSRs
308: */
309: #define MSR_VIA_RNG 0x0000110b
310: #define MSR_VIA_RNG_ENABLE 0x00000040
311: #define MSR_VIA_RNG_NOISE_MASK 0x00000300
312: #define MSR_VIA_RNG_NOISE_A 0x00000000
313: #define MSR_VIA_RNG_NOISE_B 0x00000100
314: #define MSR_VIA_RNG_2NOISE 0x00000300
315: #define MSR_VIA_ACE 0x00001107
316: #define MSR_VIA_ACE_ENABLE 0x10000000
317:
318: /*
1.1 fvdl 319: * AMD K6/K7 MSRs.
320: */
321: #define MSR_K6_UWCCR 0xc0000085
322: #define MSR_K7_EVNTSEL0 0xc0010000
323: #define MSR_K7_EVNTSEL1 0xc0010001
324: #define MSR_K7_EVNTSEL2 0xc0010002
325: #define MSR_K7_EVNTSEL3 0xc0010003
326: #define MSR_K7_PERFCTR0 0xc0010004
327: #define MSR_K7_PERFCTR1 0xc0010005
328: #define MSR_K7_PERFCTR2 0xc0010006
329: #define MSR_K7_PERFCTR3 0xc0010007
330:
331: /*
1.12 ad 332: * AMD K8 (Opteron) MSRs.
333: */
334: #define MSR_SYSCFG 0xc0000010
335:
336: #define MSR_EFER 0xc0000080 /* Extended feature enable */
337: #define EFER_SCE 0x00000001 /* SYSCALL extension */
338: #define EFER_LME 0x00000100 /* Long Mode Active */
339: #define EFER_LMA 0x00000400 /* Long Mode Enabled */
340: #define EFER_NXE 0x00000800 /* No-Execute Enabled */
341:
342: #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */
343: #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */
344: #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */
345: #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */
346:
347: #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */
348: #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */
349: #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */
350:
351: /*
352: * These require a 'passcode' for access. See cpufunc.h.
353: */
1.13 ad 354: #define MSR_HWCR 0xc0010015
355: #define HWCR_FFDIS 0x00000040
356:
1.12 ad 357: #define MSR_NB_CFG 0xc001001f
358: #define NB_CFG_DISIOREQLOCK 0x0000000000000004ULL
359: #define NB_CFG_DISDATMSK 0x0000001000000000ULL
360:
361: #define MSR_LS_CFG 0xc0011020
362: #define LS_CFG_DIS_LS2_SQUISH 0x02000000
363:
364: #define MSR_IC_CFG 0xc0011021
365: #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
366:
367: #define MSR_DC_CFG 0xc0011022
368: #define DC_CFG_DIS_CNV_WC_SSO 0x00000004
369: #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400
370:
371: #define MSR_BU_CFG 0xc0011023
372: #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL
373: #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
374: #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
375:
376: /*
1.1 fvdl 377: * Constants related to MTRRs
378: */
379: #define MTRR_N64K 8 /* numbers of fixed-size entries */
380: #define MTRR_N16K 16
381: #define MTRR_N4K 64
382:
383: /*
384: * the following four 3-byte registers control the non-cacheable regions.
385: * These registers must be written as three separate bytes.
386: *
387: * NCRx+0: A31-A24 of starting address
388: * NCRx+1: A23-A16 of starting address
389: * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
390: *
391: * The non-cacheable region's starting address must be aligned to the
392: * size indicated by the NCR_SIZE_xx field.
393: */
394: #define NCR1 0xc4
395: #define NCR2 0xc7
396: #define NCR3 0xca
397: #define NCR4 0xcd
398:
399: #define NCR_SIZE_0K 0
400: #define NCR_SIZE_4K 1
401: #define NCR_SIZE_8K 2
402: #define NCR_SIZE_16K 3
403: #define NCR_SIZE_32K 4
404: #define NCR_SIZE_64K 5
405: #define NCR_SIZE_128K 6
406: #define NCR_SIZE_256K 7
407: #define NCR_SIZE_512K 8
408: #define NCR_SIZE_1M 9
409: #define NCR_SIZE_2M 10
410: #define NCR_SIZE_4M 11
411: #define NCR_SIZE_8M 12
412: #define NCR_SIZE_16M 13
413: #define NCR_SIZE_32M 14
414: #define NCR_SIZE_4G 15
415:
416: /*
417: * Performance monitor events.
418: *
419: * Note that 586-class and 686-class CPUs have different performance
420: * monitors available, and they are accessed differently:
421: *
422: * 686-class: `rdpmc' instruction
423: * 586-class: `rdmsr' instruction, CESR MSR
424: *
425: * The descriptions of these events are too lenghy to include here.
426: * See Appendix A of "Intel Architecture Software Developer's
427: * Manual, Volume 3: System Programming" for more information.
428: */
429:
430: /*
431: * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits
432: * is CTR1.
433: */
434:
435: #define PMC5_CESR_EVENT 0x003f
436: #define PMC5_CESR_OS 0x0040
437: #define PMC5_CESR_USR 0x0080
438: #define PMC5_CESR_E 0x0100
439: #define PMC5_CESR_P 0x0200
440:
441: #define PMC5_DATA_READ 0x00
442: #define PMC5_DATA_WRITE 0x01
443: #define PMC5_DATA_TLB_MISS 0x02
444: #define PMC5_DATA_READ_MISS 0x03
445: #define PMC5_DATA_WRITE_MISS 0x04
446: #define PMC5_WRITE_M_E 0x05
447: #define PMC5_DATA_LINES_WBACK 0x06
448: #define PMC5_DATA_CACHE_SNOOP 0x07
449: #define PMC5_DATA_CACHE_SNOOP_HIT 0x08
450: #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09
451: #define PMC5_BANK_CONFLICTS 0x0a
452: #define PMC5_MISALIGNED_DATA 0x0b
453: #define PMC5_INST_READ 0x0c
454: #define PMC5_INST_TLB_MISS 0x0d
455: #define PMC5_INST_CACHE_MISS 0x0e
456: #define PMC5_SEGMENT_REG_LOAD 0x0f
457: #define PMC5_BRANCHES 0x12
458: #define PMC5_BTB_HITS 0x13
459: #define PMC5_BRANCH_TAKEN 0x14
460: #define PMC5_PIPELINE_FLUSH 0x15
461: #define PMC5_INST_EXECUTED 0x16
462: #define PMC5_INST_EXECUTED_V_PIPE 0x17
463: #define PMC5_BUS_UTILIZATION 0x18
464: #define PMC5_WRITE_BACKUP_STALL 0x19
465: #define PMC5_DATA_READ_STALL 0x1a
466: #define PMC5_WRITE_E_M_STALL 0x1b
467: #define PMC5_LOCKED_BUS 0x1c
468: #define PMC5_IO_CYCLE 0x1d
469: #define PMC5_NONCACHE_MEM_READ 0x1e
470: #define PMC5_AGI_STALL 0x1f
471: #define PMC5_FLOPS 0x22
472: #define PMC5_BP0_MATCH 0x23
473: #define PMC5_BP1_MATCH 0x24
474: #define PMC5_BP2_MATCH 0x25
475: #define PMC5_BP3_MATCH 0x26
476: #define PMC5_HARDWARE_INTR 0x27
477: #define PMC5_DATA_RW 0x28
478: #define PMC5_DATA_RW_MISS 0x29
479:
480: /*
481: * 686-class Event Selector MSR format.
482: */
483:
484: #define PMC6_EVTSEL_EVENT 0x000000ff
485: #define PMC6_EVTSEL_UNIT 0x0000ff00
486: #define PMC6_EVTSEL_UNIT_SHIFT 8
487: #define PMC6_EVTSEL_USR (1 << 16)
488: #define PMC6_EVTSEL_OS (1 << 17)
489: #define PMC6_EVTSEL_E (1 << 18)
490: #define PMC6_EVTSEL_PC (1 << 19)
491: #define PMC6_EVTSEL_INT (1 << 20)
492: #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */
493: #define PMC6_EVTSEL_INV (1 << 23)
494: #define PMC6_EVTSEL_COUNTER_MASK 0xff000000
495: #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24
496:
497: /* Data Cache Unit */
498: #define PMC6_DATA_MEM_REFS 0x43
499: #define PMC6_DCU_LINES_IN 0x45
500: #define PMC6_DCU_M_LINES_IN 0x46
501: #define PMC6_DCU_M_LINES_OUT 0x47
502: #define PMC6_DCU_MISS_OUTSTANDING 0x48
503:
504: /* Instruction Fetch Unit */
505: #define PMC6_IFU_IFETCH 0x80
506: #define PMC6_IFU_IFETCH_MISS 0x81
507: #define PMC6_ITLB_MISS 0x85
508: #define PMC6_IFU_MEM_STALL 0x86
509: #define PMC6_ILD_STALL 0x87
510:
511: /* L2 Cache */
512: #define PMC6_L2_IFETCH 0x28
513: #define PMC6_L2_LD 0x29
514: #define PMC6_L2_ST 0x2a
515: #define PMC6_L2_LINES_IN 0x24
516: #define PMC6_L2_LINES_OUT 0x26
517: #define PMC6_L2_M_LINES_INM 0x25
518: #define PMC6_L2_M_LINES_OUTM 0x27
519: #define PMC6_L2_RQSTS 0x2e
520: #define PMC6_L2_ADS 0x21
521: #define PMC6_L2_DBUS_BUSY 0x22
522: #define PMC6_L2_DBUS_BUSY_RD 0x23
523:
524: /* External Bus Logic */
525: #define PMC6_BUS_DRDY_CLOCKS 0x62
526: #define PMC6_BUS_LOCK_CLOCKS 0x63
527: #define PMC6_BUS_REQ_OUTSTANDING 0x60
528: #define PMC6_BUS_TRAN_BRD 0x65
529: #define PMC6_BUS_TRAN_RFO 0x66
530: #define PMC6_BUS_TRANS_WB 0x67
531: #define PMC6_BUS_TRAN_IFETCH 0x68
532: #define PMC6_BUS_TRAN_INVAL 0x69
533: #define PMC6_BUS_TRAN_PWR 0x6a
534: #define PMC6_BUS_TRANS_P 0x6b
535: #define PMC6_BUS_TRANS_IO 0x6c
536: #define PMC6_BUS_TRAN_DEF 0x6d
537: #define PMC6_BUS_TRAN_BURST 0x6e
538: #define PMC6_BUS_TRAN_ANY 0x70
539: #define PMC6_BUS_TRAN_MEM 0x6f
540: #define PMC6_BUS_DATA_RCV 0x64
541: #define PMC6_BUS_BNR_DRV 0x61
542: #define PMC6_BUS_HIT_DRV 0x7a
543: #define PMC6_BUS_HITM_DRDV 0x7b
544: #define PMC6_BUS_SNOOP_STALL 0x7e
545:
546: /* Floating Point Unit */
547: #define PMC6_FLOPS 0xc1
548: #define PMC6_FP_COMP_OPS_EXE 0x10
549: #define PMC6_FP_ASSIST 0x11
550: #define PMC6_MUL 0x12
551: #define PMC6_DIV 0x12
552: #define PMC6_CYCLES_DIV_BUSY 0x14
553:
554: /* Memory Ordering */
555: #define PMC6_LD_BLOCKS 0x03
556: #define PMC6_SB_DRAINS 0x04
557: #define PMC6_MISALIGN_MEM_REF 0x05
558: #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */
559: #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */
560:
561: /* Instruction Decoding and Retirement */
562: #define PMC6_INST_RETIRED 0xc0
563: #define PMC6_UOPS_RETIRED 0xc2
564: #define PMC6_INST_DECODED 0xd0
565: #define PMC6_EMON_KNI_INST_RETIRED 0xd8
566: #define PMC6_EMON_KNI_COMP_INST_RET 0xd9
567:
568: /* Interrupts */
569: #define PMC6_HW_INT_RX 0xc8
570: #define PMC6_CYCLES_INT_MASKED 0xc6
571: #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
572:
573: /* Branches */
574: #define PMC6_BR_INST_RETIRED 0xc4
575: #define PMC6_BR_MISS_PRED_RETIRED 0xc5
576: #define PMC6_BR_TAKEN_RETIRED 0xc9
577: #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
578: #define PMC6_BR_INST_DECODED 0xe0
579: #define PMC6_BTB_MISSES 0xe2
580: #define PMC6_BR_BOGUS 0xe4
581: #define PMC6_BACLEARS 0xe6
582:
583: /* Stalls */
584: #define PMC6_RESOURCE_STALLS 0xa2
585: #define PMC6_PARTIAL_RAT_STALLS 0xd2
586:
587: /* Segment Register Loads */
588: #define PMC6_SEGMENT_REG_LOADS 0x06
589:
590: /* Clocks */
591: #define PMC6_CPU_CLK_UNHALTED 0x79
592:
593: /* MMX Unit */
594: #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */
595: #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */
596: #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */
597: #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */
598: #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */
599: #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */
600: #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */
601:
602: /* Segment Register Renaming */
603: #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */
604: #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */
605: #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */
606:
607: /*
608: * AMD K7 Event Selector MSR format.
609: */
610:
611: #define K7_EVTSEL_EVENT 0x000000ff
612: #define K7_EVTSEL_UNIT 0x0000ff00
613: #define K7_EVTSEL_UNIT_SHIFT 8
614: #define K7_EVTSEL_USR (1 << 16)
615: #define K7_EVTSEL_OS (1 << 17)
616: #define K7_EVTSEL_E (1 << 18)
617: #define K7_EVTSEL_PC (1 << 19)
618: #define K7_EVTSEL_INT (1 << 20)
619: #define K7_EVTSEL_EN (1 << 22)
620: #define K7_EVTSEL_INV (1 << 23)
621: #define K7_EVTSEL_COUNTER_MASK 0xff000000
622: #define K7_EVTSEL_COUNTER_MASK_SHIFT 24
623:
624: /* Segment Register Loads */
625: #define K7_SEGMENT_REG_LOADS 0x20
626:
627: #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21
628:
629: /* Data Cache Unit */
630: #define K7_DATA_CACHE_ACCESS 0x40
631: #define K7_DATA_CACHE_MISS 0x41
632: #define K7_DATA_CACHE_REFILL 0x42
633: #define K7_DATA_CACHE_REFILL_SYSTEM 0x43
634: #define K7_DATA_CACHE_WBACK 0x44
635: #define K7_L2_DTLB_HIT 0x45
636: #define K7_L2_DTLB_MISS 0x46
637: #define K7_MISALIGNED_DATA_REF 0x47
638: #define K7_SYSTEM_REQUEST 0x64
639: #define K7_SYSTEM_REQUEST_TYPE 0x65
640:
641: #define K7_SNOOP_HIT 0x73
642: #define K7_SINGLE_BIT_ECC_ERROR 0x74
643: #define K7_CACHE_LINE_INVAL 0x75
644: #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76
645: #define K7_L2_REQUEST 0x79
646: #define K7_L2_REQUEST_BUSY 0x7a
647:
648: /* Instruction Fetch Unit */
649: #define K7_IFU_IFETCH 0x80
650: #define K7_IFU_IFETCH_MISS 0x81
651: #define K7_IFU_REFILL_FROM_L2 0x82
652: #define K7_IFU_REFILL_FROM_SYSTEM 0x83
653: #define K7_ITLB_L1_MISS 0x84
654: #define K7_ITLB_L2_MISS 0x85
655: #define K7_SNOOP_RESYNC 0x86
656: #define K7_IFU_STALL 0x87
657:
658: #define K7_RETURN_STACK_HITS 0x88
659: #define K7_RETURN_STACK_OVERFLOW 0x89
660:
661: /* Retired */
662: #define K7_RETIRED_INST 0xc0
663: #define K7_RETIRED_OPS 0xc1
664: #define K7_RETIRED_BRANCHES 0xc2
665: #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3
666: #define K7_RETIRED_TAKEN_BRANCH 0xc4
667: #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5
668: #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6
669: #define K7_RETIRED_RESYNC_BRANCH 0xc7
670: #define K7_RETIRED_NEAR_RETURNS 0xc8
671: #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9
672: #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca
673:
674: /* Interrupts */
675: #define K7_CYCLES_INT_MASKED 0xcd
676: #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce
677: #define K7_HW_INTR_RECV 0xcf
678:
679: #define K7_INSTRUCTION_DECODER_EMPTY 0xd0
680: #define K7_DISPATCH_STALLS 0xd1
681: #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2
682: #define K7_SERIALIZE 0xd3
683: #define K7_SEGMENT_LOAD_STALL 0xd4
684: #define K7_ICU_FULL 0xd5
685: #define K7_RESERVATION_STATIONS_FULL 0xd6
686: #define K7_FPU_FULL 0xd7
687: #define K7_LS_FULL 0xd8
688: #define K7_ALL_QUIET_STALL 0xd9
689: #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda
690:
691: #define K7_BP0_MATCH 0xdc
692: #define K7_BP1_MATCH 0xdd
693: #define K7_BP2_MATCH 0xde
694: #define K7_BP3_MATCH 0xdf
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