src/sys/arch/x86/include/specialreg.h - diff

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Diff for /src/sys/arch/x86/include/specialreg.h between version 1.8.4.3 and 1.8.4.4

version 1.8.4.3, 2007/02/26 09:08:49

version 1.8.4.4, 2007/09/03 14:31:21

Line 146

#define CPUID_MPC 0x00080000 /* Multiprocessing Capable */

#define CPUID_NOX 0x00100000 /* No Execute Page Protection */

#define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */

#define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */

#define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */

#define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */

#define CPUID_EXT_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \

"\24MPC\25NOX\26B21\27MMXX\30MMX"

#define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34B27\35HTT\36LONG" \

#define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34RDTSCP\35HTT" \

"\0373DNOW2\0403DNOW"

"\36LONG\0373DNOW2\0403DNOW"

* "Features" that are copied from elsewhere -- not necessarily tied to

* Centaur Extended Feature flags

* a specific CPUID response

#define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */

#define CPUID_VIA_DO_RNG 0x00000008

#define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */

#define CPUID_VIA_DO_ACE 0x00000080

#define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */

#define CPUID_VIA_DO_ACE2 0x00000200

#define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */

#define CPUID_VIA_DO_PHE 0x00000800

#define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */

#define CPUID_VIA_DO_PMM 0x00002000

#define CPUID_FEAT_VACE 0x00000002 /* VIA C3 AES Crypto Extension */

#define CPUID_FLAGS_PADLOCK "\20\3RNG\7AES\11AES/CTR\13SHA1/SHA256\15RSA"

* CPUID "features" bits in %ecx

Line 169

Line 179

#define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */

#define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */

#define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */

#define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */

#define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */

#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */

#define CPUID2_CID 0x00000400 /* Context ID */

#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */

#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */

#define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */

#define CPUID2_DCA 0x00040000 /* Direct Cache Access */

#define CPUID2_FLAGS "\20\1SSE3\4MONITOR\5DS-CPL\6VMX\10EST\11TM2\13CID\17xTPR"

#define CPUID2_FLAGS "\20\1SSE3\4MONITOR\5DS-CPL\6VMX\7SMX\10EST\11TM2" \

"\13CID\17xTPR\20PDCM\23DCA"

#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf)

#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf)

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