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Diff for /src/sys/arch/x86/include/specialreg.h between version 1.55 and 1.55.2.5

version 1.55, 2011/12/15 09:38:21 version 1.55.2.5, 2015/01/26 13:58:05
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 /* the remaining 7 bits of this register are reserved */  /* the remaining 7 bits of this register are reserved */
   
 /*  /*
  * bits in the pentiums %cr4 register:   * bits in the %cr4 control register:
  */   */
   #define CR4_VME         0x00000001 /* virtual 8086 mode extension enable */
   #define CR4_PVI         0x00000002 /* protected mode virtual interrupt enable */
   #define CR4_TSD         0x00000004 /* restrict RDTSC instruction to cpl 0 */
   #define CR4_DE          0x00000008 /* debugging extension */
   #define CR4_PSE         0x00000010 /* large (4MB) page size enable */
   #define CR4_PAE         0x00000020 /* physical address extension enable */
   #define CR4_MCE         0x00000040 /* machine check enable */
   #define CR4_PGE         0x00000080 /* page global enable */
   #define CR4_PCE         0x00000100 /* enable RDPMC instruction for all cpls */
   #define CR4_OSFXSR      0x00000200 /* enable fxsave/fxrestor and SSE */
   #define CR4_OSXMMEXCPT  0x00000400 /* enable unmasked SSE exceptions */
   #define CR4_VMXE        0x00002000 /* enable VMX operations */
   #define CR4_SMXE        0x00004000 /* enable SMX operations */
   #define CR4_FSGSBASE    0x00010000 /* enable *FSBASE and *GSBASE instructions */
   #define CR4_PCIDE       0x00020000 /* enable Process Context IDentifiers */
   #define CR4_OSXSAVE     0x00040000 /* enable xsave and xrestore */
   #define CR4_SMEP        0x00100000 /* enable SMEP support */
   #define CR4_SMAP        0x00200000 /* enable SMAP support */
   
   /*
    * Extended Control Register XCR0
    */
   #define XCR0_X87        0x00000001      /* x87 FPU/MMX state */
   #define XCR0_SSE        0x00000002      /* SSE state */
   #define XCR0_YMM_Hi128  0x00000004      /* AVX-256 (ymmn registers) */
   #define XCR0_BNDREGS    0x00000008      /* Memory protection ext bounds */
   #define XCR0_BNDCSR     0x00000010      /* Memory protection ext state */
   #define XCR0_Opmask     0x00000020      /* AVX-512 Opmask */
   #define XCR0_ZMM_Hi256  0x00000040      /* AVX-512 upper 256 bits low regs */
   #define XCR0_Hi16_ZMM   0x00000080      /* AVX-512 512 bits upper registers */
   
   /*
    * Known fpu bits - only these get enabled
    * I think the XCR0_BNDREGS and XCR0_BNDCSR would need saving on
    * every context switch.
    * The save are is sized for all the fields below (max 2680 bytes).
    */
   #define XCR0_FPU        (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \
                           XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM)
   
   #define XCR0_BND        (XCR0_BNDREGS | XCR0_BNDCSR)
   
   #define XCR0_FLAGS1     "\20" \
           "\1" "x87"      "\2" "SSE"      "\3" "AVX" \
           "\4" "BNDREGS"  "\5" "BNDCSR" \
           "\6" "Opmask"   "\7" "ZMM_Hi256" "\10" "Hi16_ZMM"
   
 #define CR4_VME 0x00000001      /* virtual 8086 mode extension enable */  
 #define CR4_PVI 0x00000002      /* protected mode virtual interrupt enable */  
 #define CR4_TSD 0x00000004      /* restrict RDTSC instruction to cpl 0 only */  
 #define CR4_DE  0x00000008      /* debugging extension */  
 #define CR4_PSE 0x00000010      /* large (4MB) page size enable */  
 #define CR4_PAE 0x00000020      /* physical address extension enable */  
 #define CR4_MCE 0x00000040      /* machine check enable */  
 #define CR4_PGE 0x00000080      /* page global enable */  
 #define CR4_PCE 0x00000100      /* enable RDPMC instruction for all cpls */  
 #define CR4_OSFXSR      0x00000200      /* enable fxsave/fxrestor and SSE */  
 #define CR4_OSXMMEXCPT  0x00000400      /* enable unmasked SSE exceptions */  
   
 /*  /*
  * CPUID "features" bits   * CPUID "features" bits
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 #define CPUID_FPU       0x00000001      /* processor has an FPU? */  #define CPUID_FPU       0x00000001      /* processor has an FPU? */
 #define CPUID_VME       0x00000002      /* has virtual mode (%cr4's VME/PVI) */  #define CPUID_VME       0x00000002      /* has virtual mode (%cr4's VME/PVI) */
 #define CPUID_DE        0x00000004      /* has debugging extension */  #define CPUID_DE        0x00000004      /* has debugging extension */
 #define CPUID_PSE       0x00000008      /* has page 4MB page size extension */  #define CPUID_PSE       0x00000008      /* has 4MB page size extension */
 #define CPUID_TSC       0x00000010      /* has time stamp counter */  #define CPUID_TSC       0x00000010      /* has time stamp counter */
 #define CPUID_MSR       0x00000020      /* has mode specific registers */  #define CPUID_MSR       0x00000020      /* has mode specific registers */
 #define CPUID_PAE       0x00000040      /* has phys address extension */  #define CPUID_PAE       0x00000040      /* has phys address extension */
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 #define CPUID_IA64      0x40000000      /* IA-64 architecture */  #define CPUID_IA64      0x40000000      /* IA-64 architecture */
 #define CPUID_SBF       0x80000000      /* signal break on FERR */  #define CPUID_SBF       0x80000000      /* signal break on FERR */
   
 #define CPUID_FLAGS1    "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE\10MCE\11CX8" \  #define CPUID_FLAGS1    "\20" \
                             "\12APIC\13B10\14SEP\15MTRR\16PGE\17MCA\20CMOV" \          "\1" "FPU"      "\2" "VME"      "\3" "DE"       "\4" "PSE" \
                             "\21PAT\22PSE36\23PN\24CFLUSH\25B20\26DS\27ACPI" \          "\5" "TSC"      "\6" "MSR"      "\7" "PAE"      "\10" "MCE" \
                             "\30MMX\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM" \          "\11" "CX8"     "\12" "APIC"    "\13" "B10"     "\14" "SEP" \
                             "\37IA64\40SBF"          "\15" "MTRR"    "\16" "PGE"     "\17" "MCA"     "\20" "CMOV" \
           "\21" "PAT"     "\22" "PSE36"   "\23" "PN"      "\24" "CFLUSH" \
           "\25" "B20"     "\26" "DS"      "\27" "ACPI"    "\30" "MMX" \
           "\31" "FXSR"    "\32" "SSE"     "\33" "SSE2"    "\34" "SS" \
           "\35" "HTT"     "\36" "TM"      "\37" "IA64"    "\40" "SBF"
   
   /* Blacklists of CPUID flags - used to mask certain features */
   #ifdef XEN
   /* Not on Xen */
   #define CPUID_FEAT_BLACKLIST     (CPUID_PGE|CPUID_PSE|CPUID_MTRR)
   #else
   #define CPUID_FEAT_BLACKLIST     0
   #endif /* XEN */
   
   /*
    * CPUID "features" bits in Fn00000001 %ecx
    */
   
   #define CPUID2_SSE3     0x00000001      /* Streaming SIMD Extensions 3 */
   #define CPUID2_PCLMUL   0x00000002      /* PCLMULQDQ instructions */
   #define CPUID2_DTES64   0x00000004      /* 64-bit Debug Trace */
   #define CPUID2_MONITOR  0x00000008      /* MONITOR/MWAIT instructions */
   #define CPUID2_DS_CPL   0x00000010      /* CPL Qualified Debug Store */
   #define CPUID2_VMX      0x00000020      /* Virtual Machine Extensions */
   #define CPUID2_SMX      0x00000040      /* Safer Mode Extensions */
   #define CPUID2_EST      0x00000080      /* Enhanced SpeedStep Technology */
   #define CPUID2_TM2      0x00000100      /* Thermal Monitor 2 */
   #define CPUID2_SSSE3    0x00000200      /* Supplemental SSE3 */
   #define CPUID2_CID      0x00000400      /* Context ID */
   /* bit 11 unused        0x00000800 */
   #define CPUID2_FMA      0x00001000      /* has Fused Multiply Add */
   #define CPUID2_CX16     0x00002000      /* has CMPXCHG16B instruction */
   #define CPUID2_xTPR     0x00004000      /* Task Priority Messages disabled? */
   #define CPUID2_PDCM     0x00008000      /* Perf/Debug Capability MSR */
   /* bit 16 unused        0x00010000 */
   #define CPUID2_PCID     0x00020000      /* Process Context ID */
   #define CPUID2_DCA      0x00040000      /* Direct Cache Access */
   #define CPUID2_SSE41    0x00080000      /* Streaming SIMD Extensions 4.1 */
   #define CPUID2_SSE42    0x00100000      /* Streaming SIMD Extensions 4.2 */
   #define CPUID2_X2APIC   0x00200000      /* xAPIC Extensions */
   #define CPUID2_MOVBE    0x00400000      /* MOVBE (move after byteswap) */
   #define CPUID2_POPCNT   0x00800000      /* popcount instruction available */
   #define CPUID2_DEADLINE 0x01000000      /* APIC Timer supports TSC Deadline */
   #define CPUID2_AES      0x02000000      /* AES instructions */
   #define CPUID2_XSAVE    0x04000000      /* XSAVE instructions */
   #define CPUID2_OSXSAVE  0x08000000      /* XGETBV/XSETBV instructions */
   #define CPUID2_AVX      0x10000000      /* AVX instructions */
   #define CPUID2_F16C     0x20000000      /* half precision conversion */
   #define CPUID2_RDRAND   0x40000000      /* RDRAND (hardware random number) */
   #define CPUID2_RAZ      0x80000000      /* RAZ. Indicates guest state. */
   
   #define CPUID2_FLAGS1   "\20" \
           "\1" "SSE3"     "\2" "PCLMULQDQ" "\3" "DTES64"  "\4" "MONITOR" \
           "\5" "DS-CPL"   "\6" "VMX"      "\7" "SMX"      "\10" "EST" \
           "\11" "TM2"     "\12" "SSSE3"   "\13" "CID"     "\14" "B11" \
           "\15" "FMA"     "\16" "CX16"    "\17" "xTPR"    "\20" "PDCM" \
           "\21" "B16"     "\22" "PCID"    "\23" "DCA"     "\24" "SSE41" \
           "\25" "SSE42"   "\26" "X2APIC"  "\27" "MOVBE"   "\30" "POPCNT" \
           "\31" "DEADLINE" "\32" "AES"    "\33" "XSAVE"   "\34" "OSXSAVE" \
           "\35" "AVX"     "\36" "F16C"    "\37" "RDRAND"  "\40" "RAZ"
   
   /* CPUID Fn00000001 %eax */
   
   #define CPUID_TO_BASEFAMILY(cpuid)      (((cpuid) >> 8) & 0xf)
   #define CPUID_TO_BASEMODEL(cpuid)       (((cpuid) >> 4) & 0xf)
   #define CPUID_TO_STEPPING(cpuid)        ((cpuid) & 0xf)
   
   /* Old macros for compatibility */
   #define CPUID2FAMILY(cpuid)     CPUID_TO_BASEFAMILY(cpuid)
   #define CPUID2MODEL(cpuid)      CPUID_TO_BASEMODEL(cpuid)
   #define CPUID2STEPPING(cpuid)   CPUID_TO_STEPPING(cpuid)
   
   /*
    * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY()
    * returns 15. They are use to encode family value 16 to 270 (add 15).
    * The Extended model bits are the high 4 bits of the model.
    * They are only valid for family >= 15 or family 6 (intel, but all amd
    * family 6 are documented to return zero bits for them).
    */
   #define CPUID_TO_EXTFAMILY(cpuid)       (((cpuid) >> 20) & 0xff)
   #define CPUID_TO_EXTMODEL(cpuid)        (((cpuid) >> 16) & 0xf)
   
   /* Old macros for compatibility */
   #define CPUID2EXTFAMILY(cpuid)  CPUID_TO_EXTFAMILY(cpuid)
   #define CPUID2EXTMODEL(cpuid)   CPUID_TO_EXTMODEL(cpuid)
   
   /* The macros for the Display Family and the Display Model */
   #define CPUID_TO_FAMILY(cpuid)  (CPUID_TO_BASEFAMILY(cpuid)     \
               + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f)             \
                   ? 0 : CPUID_TO_EXTFAMILY(cpuid)))
   #define CPUID_TO_MODEL(cpuid)   (CPUID_TO_BASEMODEL(cpuid)      \
               | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f)             \
                   && (CPUID_TO_BASEFAMILY(cpuid) != 0x06)         \
                   ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4)))
   
   /*
    * Intel Deterministic Cache Parameter Leaf
    * Fn0000_0004
    */
   
   /* %eax */
   #define CPUID_DCP_CACHETYPE     __BITS(4, 0)    /* Cache type */
   #define CPUID_DCP_CACHETYPE_N   0               /*   NULL */
   #define CPUID_DCP_CACHETYPE_D   1               /*   Data cache */
   #define CPUID_DCP_CACHETYPE_I   2               /*   Instruction cache */
   #define CPUID_DCP_CACHETYPE_U   3               /*   Unified cache */
   #define CPUID_DCP_CACHELEVEL    __BITS(7, 5)    /* Cache level (start at 1) */
   #define CPUID_DCP_SELFINITCL    __BIT(8)        /* Self initializing cachelvl*/
   #define CPUID_DCP_FULLASSOC     __BIT(9)        /* Full associative */
   #define CPUID_DCP_SHAREING      __BITS(25, 14)  /* shareing */
   #define CPUID_DCP_CORE_P_PKG    __BITS(31, 26)  /* Cores/package */
   
   /* %ebx */
   #define CPUID_DCP_LINESIZE      __BITS(11, 0)   /* System coherency linesize */
   #define CPUID_DCP_PARTITIONS    __BITS(21, 12)  /* Physical line partitions */
   #define CPUID_DCP_WAYS          __BITS(31, 22)  /* Ways of associativity */
   
   /* Number of sets: %ecx */
   
   /* %edx */
   #define CPUID_DCP_INVALIDATE    __BIT(0)        /* WB invalidate/invalidate */
   #define CPUID_DCP_INCLUSIVE     __BIT(1)        /* Cache inclusiveness */
   #define CPUID_DCP_COMPLEX       __BIT(2)        /* Complex cache indexing */
   
 /*  /*
  * Intel Digital Thermal Sensor and   * Intel Digital Thermal Sensor and
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 #define CPUID_DSPM_CME  0x00000020      /* Clock Modulation Extension */  #define CPUID_DSPM_CME  0x00000020      /* Clock Modulation Extension */
 #define CPUID_DSPM_PLTM 0x00000040      /* Package Level Thermal Management */  #define CPUID_DSPM_PLTM 0x00000040      /* Package Level Thermal Management */
   
 #define CPUID_DSPM_FLAGS        "\20\1DTS\2IDA\3ARAT\5PLN\6CME\7PLTM"  #define CPUID_DSPM_FLAGS        "\20" \
           "\1" "DTS"      "\2" "IDA"      "\3" "ARAT" \
           "\5" "PLN"      "\6" "CME"      "\7" "PLTM"
   
 /*  /*
  * Intel Digital Thermal Sensor and   * Intel Digital Thermal Sensor and
  * Power Management, Fn0000_0006 - %ecx.   * Power Management, Fn0000_0006 - %ecx.
  */   */
 #define CPUID_DSPM_HWF  0x00000001      /* MSR_APERF/MSR_MPERF available */  #define CPUID_DSPM_HWF  0x00000001      /* MSR_APERF/MSR_MPERF available */
   #define CPUID_DSPM_EPB  0x00000008      /* Energy Performance Bias */
   
   #define CPUID_DSPM_FLAGS1       "\20" "\1" "HWF" "\4" "EPB"
   
 #define CPUID_DSPM_FLAGS1       "\20\1HWF"  /*
    * Intel Structured Extended Feature leaf
    * Fn0000_0007 main leaf - %ebx.
    */
   #define CPUID_SEF_FSGSBASE      __BIT(0)
   #define CPUID_SEF_TSC_ADJUST    __BIT(1)
   #define CPUID_SEF_BMI1          __BIT(3)
   #define CPUID_SEF_HLE           __BIT(4)
   #define CPUID_SEF_AVX2          __BIT(5)
   #define CPUID_SEF_SMEP          __BIT(7)
   #define CPUID_SEF_BMI2          __BIT(8)
   #define CPUID_SEF_ERMS          __BIT(9)
   #define CPUID_SEF_INVPCID       __BIT(10)
   #define CPUID_SEF_RTM           __BIT(11)
   #define CPUID_SEF_QM            __BIT(12)
   #define CPUID_SEF_FPUCSDS       __BIT(13)
   #define CPUID_SEF_MPX           __BIT(14)
   #define CPUID_SEF_PQE           __BIT(15)
   #define CPUID_SEF_AVX512F       __BIT(16)
   #define CPUID_SEF_RDSEED        __BIT(18)
   #define CPUID_SEF_ADX           __BIT(19)
   #define CPUID_SEF_SMAP          __BIT(20)
   #define CPUID_SEF_PT            __BIT(25)
   #define CPUID_SEF_AVX512PF      __BIT(26)
   #define CPUID_SEF_AVX512ER      __BIT(27)
   #define CPUID_SEF_AVX512CD      __BIT(28)
   #define CPUID_SEF_SHA           __BIT(29)
   
   #define CPUID_SEF_FLAGS "\20" \
           "\1" "FSGSBASE" "\2" "TSCADJUST"                "\4" "BMI1"     \
           "\5" "HLE"      "\6" "AVX2"                     "\10" "SMEP"    \
           "\11" "BMI2"    "\12" "ERMS"    "\13" "INVPCID" "\14" "RTM"     \
           "\15" "QM"      "\16" "FPUCSDS" "\17" "MPX"     "\20" "PQE"     \
           "\21" "AVX512F"                 "\23" "RDSEED"  "\24" "ADX"     \
           "\25" "SMAP"                                                    \
                           "\32" "PT"      "\33" "AVX512PF""\34" "AVX512ER"\
           "\35" "AVX512CD""\36" "SHA"
   
   /*
    * CPUID Processor extended state Enumeration Fn0000000d
    *
    * %ecx == 0: supported features info:
    *      %eax: Valid bits of lower 32bits of XCR0
    *      %ebx Save area size for features enabled in XCR0
    *      %ecx Maximim save area size for all cpu features
    *      %edx: Valid bits of upper 32bits of XCR0
    *
    * %ecx == 1:
    *      %eax: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards)
    *
    * %ecx >= 2: Save area details for XCR0 bit n
    *      %eax: size of save area for this feature
    *      %ebx: offset of save area for this feature
    *      %ecx, %edx: reserved
    *      All of %eax, %ebx, %ecx and %edx are zero for unsupported features.
    */
   
   #define CPUID_PES1_XSAVEOPT     0x00000001      /* xsaveopt instruction */
   #define CPUID_PES1_XSAVEC       0x00000002      /* xsavec & compacted XRSTOR */
   #define CPUID_PES1_XGETBV       0x00000004      /* xgetbv with ECX = 1 */
   #define CPUID_PES1_XSAVES       0x00000008      /* xsaves/xrstors, IA32_XSS */
   
   #define CPUID_PES1_FLAGS        "\20" \
           "\1" "XSAVEOPT" "\2" "XSAVEC"   "\3" "XGETBV"   "\4" "XSAVES"
   
 /* Intel Fn80000001 extended features - %edx */  /* Intel Fn80000001 extended features - %edx */
 #define CPUID_SYSCALL   0x00000800      /* SYSCALL/SYSRET */  #define CPUID_SYSCALL   0x00000800      /* SYSCALL/SYSRET */
 #define CPUID_XD        0x00100000      /* Execute Disable (like CPUID_NOX) */  #define CPUID_XD        0x00100000      /* Execute Disable (like CPUID_NOX) */
   #define CPUID_P1GB      0x04000000      /* 1GB Large Page Support */
   #define CPUID_RDTSCP    0x08000000      /* Read TSC Pair Instruction */
 #define CPUID_EM64T     0x20000000      /* Intel EM64T */  #define CPUID_EM64T     0x20000000      /* Intel EM64T */
   
 #define CPUID_INTEL_EXT_FLAGS   "\20\14SYSCALL/SYSRET\25XD\36EM64T"  #define CPUID_INTEL_EXT_FLAGS   "\20" \
           "\14" "SYSCALL/SYSRET"  "\25" "XD"      "\33" "P1GB" \
           "\34" "RDTSCP"  "\36" "EM64T"
   
 /* Intel Fn80000001 extended features - %ecx */  /* Intel Fn80000001 extended features - %ecx */
 #define CPUID_LAHF      0x00000001      /* LAHF/SAHF in IA-32e mode, 64bit sub*/  #define CPUID_LAHF      0x00000001      /* LAHF/SAHF in IA-32e mode, 64bit sub*/
                   /*      0x00000020 */   /* LZCNT. Same as AMD's CPUID_LZCNT */
   #define CPUID_PREFETCHW 0x00000100      /* PREFETCHW */
   
 #define CPUID_INTEL_FLAGS4      "\20\1LAHF\02B02\03B03"  #define CPUID_INTEL_FLAGS4      "\20"                           \
           "\1" "LAHF"     "\02" "B01"     "\03" "B02"             \
                           "\06" "LZCNT"                           \
           "\11" "PREFETCHW"
   
 /* AMD/VIA Fn80000001 extended features - %edx */  /* AMD/VIA Fn80000001 extended features - %edx */
 /*      CPUID_SYSCALL                      SYSCALL/SYSRET */  /*      CPUID_SYSCALL                      SYSCALL/SYSRET */
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 #define CPUID_NOX       0x00100000      /* No Execute Page Protection */  #define CPUID_NOX       0x00100000      /* No Execute Page Protection */
 #define CPUID_MMXX      0x00400000      /* AMD MMX Extensions */  #define CPUID_MMXX      0x00400000      /* AMD MMX Extensions */
 #define CPUID_FFXSR     0x02000000      /* FXSAVE/FXSTOR Extensions */  #define CPUID_FFXSR     0x02000000      /* FXSAVE/FXSTOR Extensions */
 #define CPUID_P1GB      0x04000000      /* 1GB Large Page Support */  /*      CPUID_P1GB                         1GB Large Page Support */
 #define CPUID_RDTSCP    0x08000000      /* Read TSC Pair Instruction */  /*      CPUID_RDTSCP                       Read TSC Pair Instruction */
 /*      CPUID_EM64T                        Long mode */  /*      CPUID_EM64T                        Long mode */
 #define CPUID_3DNOW2    0x40000000      /* 3DNow! Instruction Extension */  #define CPUID_3DNOW2    0x40000000      /* 3DNow! Instruction Extension */
 #define CPUID_3DNOW     0x80000000      /* 3DNow! Instructions */  #define CPUID_3DNOW     0x80000000      /* 3DNow! Instructions */
   
 #define CPUID_EXT_FLAGS "\20\14SYSCALL/SYSRET\24MPC\25NOX" \  #define CPUID_EXT_FLAGS "\20" \
                             "\27MXX\32FFXSR\33P1GB\34RDTSCP" \          "\14" "SYSCALL/SYSRET"          "\24" "MPC"     "\25" "NOX" \
                             "\36LONG\0373DNOW2\0403DNOW" \          "\27" "MMXX"    "\32" "FFXSR"   "\33" "P1GB"    "\34" "RDTSCP" \
           "\36" "LONG"    "\37" "3DNOW2"  "\40" "3DNOW"
   
 /* AMD Fn80000001 extended features - %ecx */  /* AMD Fn80000001 extended features - %ecx */
 /*      CPUID_LAHF                         LAHF/SAHF instruction */  /*      CPUID_LAHF                         LAHF/SAHF instruction */
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 #define CPUID_NODEID    0x00080000      /* NodeID MSR available*/  #define CPUID_NODEID    0x00080000      /* NodeID MSR available*/
 #define CPUID_TBM       0x00200000      /* TBM instructions */  #define CPUID_TBM       0x00200000      /* TBM instructions */
 #define CPUID_TOPOEXT   0x00400000      /* cpuid Topology Extension */  #define CPUID_TOPOEXT   0x00400000      /* cpuid Topology Extension */
   #define CPUID_PCEC      0x00800000      /* Perf Ctr Ext Core */
 #define CPUID_AMD_FLAGS4        "\20\1LAHF\2CMPLEGACY\3SVM\4EAPIC\5ALTMOVCR0" \  #define CPUID_PCENB     0x01000000      /* Perf Ctr Ext NB */
                                     "\6LZCNT\7SSE4A\10MISALIGNSSE" \  #define CPUID_SPM       0x02000000      /* Stream Perf Mon */
                                     "\0113DNOWPREFETCH\12OSVW\13IBS" \  #define CPUID_DBE       0x04000000      /* Data Breakpoint Extension */
                                     "\14XOP\15SKINIT\16WDT\20LWP" \  #define CPUID_PTSC      0x08000000      /* PerfTsc */
                                     "\21FMA4\22B17\23B18\24NodeID\25B20\26TBM" \  
                                     "\27TopoExt\30B23\31B24" \  #define CPUID_AMD_FLAGS4        "\20" \
                                     "\32B25\33B25\34B26" \          "\1" "LAHF"     "\2" "CMPLEGACY" "\3" "SVM"     "\4" "EAPIC" \
                                     "\35B27\36B28\37B29\40B30\41B31\42B32"          "\5" "ALTMOVCR0" "\6" "LZCNT"   "\7" "SSE4A"    "\10" "MISALIGNSSE" \
           "\11" "3DNOWPREFETCH" \
 /* AMD Fn8000000a %edx features (SVM features) */                          "\12" "OSVW"    "\13" "IBS"     "\14" "XOP" \
 #define CPUID_AMD_SVM_NP                0x00000001          "\15" "SKINIT"  "\16" "WDT"     "\17" "B14"     "\20" "LWP" \
 #define CPUID_AMD_SVM_LbrVirt           0x00000002          "\21" "FMA4"    "\22" "B17"     "\23" "B18"     "\24" "NodeID" \
 #define CPUID_AMD_SVM_SVML              0x00000004          "\25" "B20"     "\26" "TBM"     "\27" "TopoExt" "\30" "PCExtC" \
 #define CPUID_AMD_SVM_NRIPS             0x00000008          "\31" "PCExtNB" "\32" "StrmPM"  "\33" "DBExt"   "\34" "PerfTsc" \
 #define CPUID_AMD_SVM_TSCRateCtrl       0x00000010          "\35" "B28"     "\36" "B29"     "\37" "B30"     "\40" "B31"
 #define CPUID_AMD_SVM_VMCBCleanBits     0x00000020  
 #define CPUID_AMD_SVM_FlushByASID       0x00000040  
 #define CPUID_AMD_SVM_DecodeAssist      0x00000080  
 #define CPUID_AMD_SVM_PauseFilter       0x00000400  
 #define CPUID_AMD_SVM_FLAGS      "\20\1NP\2LbrVirt\3SVML\4NRIPS" \  
                                     "\5TSCRate\6VMCBCleanBits\7FlushByASID" \  
                                     "\10DecodeAssist\11B08" \  
                                     "\12B09\13PauseFilter" \  
                                     "\14B11\15B12" \  
                                     "\16B13\17B17\20B18\21B19"  
   
 /*  /*
  * AMD Advanced Power Management   * AMD Advanced Power Management
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 #define CPUID_APM_CPB   0x00000200      /* Core performance boost */  #define CPUID_APM_CPB   0x00000200      /* Core performance boost */
 #define CPUID_APM_EFF   0x00000400      /* Effective Frequency (read-only) */  #define CPUID_APM_EFF   0x00000400      /* Effective Frequency (read-only) */
   
 #define CPUID_APM_FLAGS         "\20\1TS\2FID\3VID\4TTP\5HTC\6STC\007100" \  #define CPUID_APM_FLAGS         "\20" \
                                     "\10HWP\11TSC\12CPB\13EffFreq\14B11\15B12"          "\1" "TS"       "\2" "FID"      "\3" "VID"      "\4" "TTP" \
           "\5" "HTC"      "\6" "STC"      "\7" "100"      "\10" "HWP" \
           "\11" "TSC"     "\12" "CPB"     "\13" "EffFreq" "\14" "B11" \
           "\15" "B12"
   
   /* AMD Fn8000000a %edx features (SVM features) */
   #define CPUID_AMD_SVM_NP                0x00000001
   #define CPUID_AMD_SVM_LbrVirt           0x00000002
   #define CPUID_AMD_SVM_SVML              0x00000004
   #define CPUID_AMD_SVM_NRIPS             0x00000008
   #define CPUID_AMD_SVM_TSCRateCtrl       0x00000010
   #define CPUID_AMD_SVM_VMCBCleanBits     0x00000020
   #define CPUID_AMD_SVM_FlushByASID       0x00000040
   #define CPUID_AMD_SVM_DecodeAssist      0x00000080
   #define CPUID_AMD_SVM_PauseFilter       0x00000400
   #define CPUID_AMD_SVM_FLAGS      "\20" \
           "\1" "NP"       "\2" "LbrVirt"  "\3" "SVML"     "\4" "NRIPS" \
           "\5" "TSCRate"  "\6" "VMCBCleanBits" \
                   "\7" "FlushByASID"      "\10" "DecodeAssist" \
           "\11" "B08"     "\12" "B09"     "\13" "PauseFilter" "\14" "B11" \
           "\15" "B12"     "\16" "B13"     "\17" "B17"     "\20" "B18" \
           "\21" "B19"
   
 /*  /*
  * Centaur Extended Feature flags   * Centaur Extended Feature flags
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 #define CPUID_VIA_HAS_PMM       0x00001000      /* RSA Instructions */  #define CPUID_VIA_HAS_PMM       0x00001000      /* RSA Instructions */
 #define CPUID_VIA_DO_PMM        0x00002000  #define CPUID_VIA_DO_PMM        0x00002000
   
 #define CPUID_FLAGS_PADLOCK     "\20\3RNG\7AES\11AES/CTR\13SHA1/SHA256\15RSA"  #define CPUID_FLAGS_PADLOCK     "\20" \
           "\3" "RNG"      "\7" "AES"      "\11" "AES/CTR" "\13" "SHA1/SHA256" \
 /*          "\15" "RSA"
  * CPUID "features" bits in Fn00000001 %ecx  
  */  
   
 #define CPUID2_SSE3     0x00000001      /* Streaming SIMD Extensions 3 */  
 #define CPUID2_PCLMUL   0x00000002      /* PCLMULQDQ instructions */  
 #define CPUID2_DTES64   0x00000004      /* 64-bit Debug Trace */  
 #define CPUID2_MONITOR  0x00000008      /* MONITOR/MWAIT instructions */  
 #define CPUID2_DS_CPL   0x00000010      /* CPL Qualified Debug Store */  
 #define CPUID2_VMX      0x00000020      /* Virtual Machine Extensions */  
 #define CPUID2_SMX      0x00000040      /* Safer Mode Extensions */  
 #define CPUID2_EST      0x00000080      /* Enhanced SpeedStep Technology */  
 #define CPUID2_TM2      0x00000100      /* Thermal Monitor 2 */  
 #define CPUID2_SSSE3    0x00000200      /* Supplemental SSE3 */  
 #define CPUID2_CID      0x00000400      /* Context ID */  
 #define CPUID2_CX16     0x00002000      /* has CMPXCHG16B instruction */  
 #define CPUID2_xTPR     0x00004000      /* Task Priority Messages disabled? */  
 #define CPUID2_PDCM     0x00008000      /* Perf/Debug Capability MSR */  
 #define CPUID2_PCID     0x00020000      /* Process Context ID */  
 #define CPUID2_DCA      0x00040000      /* Direct Cache Access */  
 #define CPUID2_SSE41    0x00080000      /* Streaming SIMD Extensions 4.1 */  
 #define CPUID2_SSE42    0x00100000      /* Streaming SIMD Extensions 4.2 */  
 #define CPUID2_X2APIC   0x00200000      /* xAPIC Extensions */  
 #define CPUID2_POPCNT   0x00800000      /* popcount instruction available */  
 #define CPUID2_AES      0x02000000      /* AES instructions */  
 #define CPUID2_XSAVE    0x04000000      /* XSAVE instructions */  
 #define CPUID2_OSXSAVE  0x08000000      /* XGETBV/XSETBV instructions */  
 #define CPUID2_AVX      0x10000000      /* AVX instructions */  
 #define CPUID2_F16C     0x20000000      /* half precision conversion */  
 #define CPUID2_RAZ      0x80000000      /* RAZ. Indicates guest state. */  
   
 #define CPUID2_FLAGS1   "\20\1SSE3\2PCLMULQDQ\3DTES64\4MONITOR\5DS-CPL\6VMX\7SMX" \  
                         "\10EST\11TM2\12SSSE3\13CID\14B11\15B12\16CX16" \  
                         "\17xTPR\20PDCM\21B16\22PCID\23DCA\24SSE41\25SSE42" \  
                         "\26X2APIC\27MOVBE\30POPCNT\31B24\32AES\33XSAVE" \  
                         "\34OSXSAVE\35AVX\36F16C\37B30\40RAZ"  
   
 #define CPUID2FAMILY(cpuid)     (((cpuid) >> 8) & 0xf)  
 #define CPUID2MODEL(cpuid)      (((cpuid) >> 4) & 0xf)  
 #define CPUID2STEPPING(cpuid)   ((cpuid) & 0xf)  
   
 /* Extended family and model are defined on amd64 processors */  
 #define CPUID2EXTFAMILY(cpuid)  (((cpuid) >> 20) & 0xff)  
 #define CPUID2EXTMODEL(cpuid)   (((cpuid) >> 16) & 0xf)  
   
 /* Blacklists of CPUID flags - used to mask certain features */  
 #ifdef XEN  
 /* Not on Xen */  
 #define CPUID_FEAT_BLACKLIST     (CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR)  
 #else  
 #define CPUID_FEAT_BLACKLIST     0  
 #endif /* XEN */  
   
 /*  /*
  * Model-specific registers for the i386 family   * Model-specific registers for the i386 family
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 #define MSR_CESR                0x011   /* P5 only (trap on P6) */  #define MSR_CESR                0x011   /* P5 only (trap on P6) */
 #define MSR_CTR0                0x012   /* P5 only (trap on P6) */  #define MSR_CTR0                0x012   /* P5 only (trap on P6) */
 #define MSR_CTR1                0x013   /* P5 only (trap on P6) */  #define MSR_CTR1                0x013   /* P5 only (trap on P6) */
   #define MSR_IA32_PLATFORM_ID    0x017
 #define MSR_APICBASE            0x01b  #define MSR_APICBASE            0x01b
 #define MSR_EBL_CR_POWERON      0x02a  #define MSR_EBL_CR_POWERON      0x02a
 #define MSR_EBC_FREQUENCY_ID    0x02c   /* PIV only */  #define MSR_EBC_FREQUENCY_ID    0x02c   /* PIV only */
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 #define MSR_VIA_ACE_ENABLE      0x10000000  #define MSR_VIA_ACE_ENABLE      0x10000000
   
 /*  /*
    * VIA "Eden" MSRs
    */
   #define MSR_VIA_FCR             MSR_VIA_ACE
   
   /*
  * AMD K6/K7 MSRs.   * AMD K6/K7 MSRs.
  */   */
 #define MSR_K6_UWCCR            0xc0000085  #define MSR_K6_UWCCR            0xc0000085
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 #define         BU_CFG_WBPFSMCCHKDIS    0x0000200000000000ULL  #define         BU_CFG_WBPFSMCCHKDIS    0x0000200000000000ULL
 #define         BU_CFG_WBENHWSBDIS      0x0001000000000000ULL  #define         BU_CFG_WBENHWSBDIS      0x0001000000000000ULL
   
   #define MSR_DE_CFG      0xc0011029
   #define         DE_CFG_ERRATA_721       0x00000001
   
 /* AMD Family10h MSRs */  /* AMD Family10h MSRs */
 #define MSR_OSVW_ID_LENGTH              0xc0010140  #define MSR_OSVW_ID_LENGTH              0xc0010140
 #define MSR_OSVW_STATUS                 0xc0010141  #define MSR_OSVW_STATUS                 0xc0010141
Legend:
Removed from v.1.55  
changed lines
  Added in v.1.55.2.5
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