src/sys/arch/x86/include/specialreg.h - diff

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version 1.18, 2007/07/11 11:56:36

version 1.18.10.2, 2008/01/09 01:49:49

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#define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */

#define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */

#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */

#define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */

#define CPUID2_CID 0x00000400 /* Context ID */

#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */

#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */

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#define CPUID2_DCA 0x00040000 /* Direct Cache Access */

#define CPUID2_FLAGS "\20\1SSE3\4MONITOR\5DS-CPL\6VMX\7SMX\10EST\11TM2" \

"\13CID\17xTPR\20PDCM\23DCA"

"\12SSSE3\13CID\16CX16\17xTPR\20PDCM\23DCA"

#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf)

#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf)

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#define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)

#define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf)

#define CPUID(code, eax, ebx, ecx, edx) \

__asm("cpuid" \

: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \

: "a" (code));

* Model-specific registers for the i386 family

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#define MSR_PERFCTR0 0x0c1

#define MSR_PERFCTR1 0x0c2

#define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */

#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */

#define MSR_MTRRcap 0x0fe

#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */

#define MSR_BBL_CR_DECC 0x118 /* PII+ only */