The NetBSD Project

CVS log for src/sys/arch/x86/include/specialreg.h

[BACK] Up to [cvs.NetBSD.org] / src / sys / arch / x86 / include

Request diff between arbitrary revisions


Default branch: MAIN


Revision 1.98.2.25 / (download) - annotate - [select for diffs], Mon Jan 23 13:09:54 2023 UTC (2 weeks, 1 day ago) by martin
Branch: netbsd-8
Changes since 1.98.2.24: +258 -92 lines
Diff to previous 1.98.2.24 (colored) to branchpoint 1.98 (colored) next main 1.99 (colored)

Pull up the following revisions, requested by msaitoh in ticket #1791:

	sys/arch/x86/include/specialreg.h		1.193-1.198

- Add CPUID Fn0000_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25
  Hardware Feedback Notification support.
- Add CPUID Fn0000_0007 %ecx bit 29 ENQCMD.
- Add CPUID Fn0000_0007 %edx bit 1 SGX-KEYS.
- Add CPUID Fn0000_0007 %edx bit 5 UINTR(User INTeRrupts).
- Add CPUID Fn0000_0007 %edx bit 11 RTM_ALWAYS_ABORT.
- Add CPUID Fn0000_0007 %edx bit 22 AMX_BF16.
- Add CPUID Fn0000_0007 %edx bit 23 AVX512_FP16.
- Add CPUID Fn0000_0007 %edx bit 24 AMX_TILE.
- Add CPUID Fn0000_0007 %edx bit 25 AMX_INT8.
- Add CPUID Fn0000_0007 sub-leaf 1 %edx bit 18 CET_SSS.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx definitions.
- Add CPUID Fn0000_000d sub-leaf 1 %eax bit 4 XFD.
- Add CPUID Fn0000_001d Tile Information.
- Add CPUID Fn0000_001e TMUL Information.
- Add CPUID Fn8000_0007 %eax RAS capabilities.
- Add CPUID Fn8000_0008 %ebx BTC_NO,
- Add cpuid Fn8000_000a x2AVIC, VNMI, IBSVIRT and ROGPT.
- Add CPUID Fn8000_001b Instruction-Based Sampling.
- Add CPUID Fn8000_001e Processor Topology Information.
- Add CPUID Fn8000_001f %eax RPMQUERY, VmplSSS, TscAuxVirt,
  VmgexitParam, VirtualTomMsr, IbsVirtGuest, SmtProtection,
  vsmCommPageMSR and NestedVirtSnpMsr.
- Add CPUID Fn8000_0021 AMD Extended Features Identification 2.
- Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.
- Rename HW_FEEDBACK to HWI (Hardware Feedback Interface).
- Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT.
- Modify comment. Both Intel and AMD support CPUID Fn0000000b.
- Modify comment. Hybrid Information -> Native Model ID Information.
- Use __BIT(). Add comment. Whitespace fix.

Revision 1.150.2.12 / (download) - annotate - [select for diffs], Mon Jan 23 13:00:53 2023 UTC (2 weeks, 1 day ago) by martin
Branch: netbsd-9
Changes since 1.150.2.11: +258 -92 lines
Diff to previous 1.150.2.11 (colored) to branchpoint 1.150 (colored) next main 1.151 (colored)

Pull up the following revisions, requested by msaitoh in ticket #1574:

	sys/arch/x86/include/specialreg.h		1.193-1.198

- Add CPUID Fn0000_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25
  Hardware Feedback Notification support.
- Add CPUID Fn0000_0007 %ecx bit 29 ENQCMD.
- Add CPUID Fn0000_0007 %edx bit 1 SGX-KEYS.
- Add CPUID Fn0000_0007 %edx bit 5 UINTR(User INTeRrupts).
- Add CPUID Fn0000_0007 %edx bit 11 RTM_ALWAYS_ABORT.
- Add CPUID Fn0000_0007 %edx bit 22 AMX_BF16.
- Add CPUID Fn0000_0007 %edx bit 23 AVX512_FP16.
- Add CPUID Fn0000_0007 %edx bit 24 AMX_TILE.
- Add CPUID Fn0000_0007 %edx bit 25 AMX_INT8.
- Add CPUID Fn0000_0007 sub-leaf 1 %edx bit 18 CET_SSS.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx definitions.
- Add CPUID Fn0000_000d sub-leaf 1 %eax bit 4 XFD.
- Add CPUID Fn0000_001d Tile Information.
- Add CPUID Fn0000_001e TMUL Information.
- Add CPUID Fn8000_0007 %eax RAS capabilities.
- Add CPUID Fn8000_0008 %ebx BTC_NO,
- Add cpuid Fn8000_000a x2AVIC, VNMI, IBSVIRT and ROGPT.
- Add CPUID Fn8000_001b Instruction-Based Sampling.
- Add CPUID Fn8000_001e Processor Topology Information.
- Add CPUID Fn8000_001f %eax RPMQUERY, VmplSSS, TscAuxVirt,
  VmgexitParam, VirtualTomMsr, IbsVirtGuest, SmtProtection,
  vsmCommPageMSR and NestedVirtSnpMsr.
- Add CPUID Fn8000_0021 AMD Extended Features Identification 2.
- Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.
- Rename HW_FEEDBACK to HWI (Hardware Feedback Interface).
- Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT.
- Modify comment. Both Intel and AMD support CPUID Fn0000000b.
- Modify comment. Hybrid Information -> Native Model ID Information.
- Use __BIT(). Add comment. Whitespace fix.

Revision 1.198.2.1 / (download) - annotate - [select for diffs], Mon Jan 23 12:52:17 2023 UTC (2 weeks, 1 day ago) by martin
Branch: netbsd-10
Changes since 1.198: +137 -81 lines
Diff to previous 1.198 (colored) next main 1.199 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #56):

	sys/arch/x86/include/specialreg.h: revision 1.200
	sys/arch/x86/include/specialreg.h: revision 1.201
	sys/arch/x86/include/specialreg.h: revision 1.199

Use __BIT(). Add comment. Whitespace. No functional change.

Update definitions from the latest Intel SDM.
 - Rename HW_FEEDBACK to HWI (Hardware Feedback Interface).
 - Add CPUID Fn0000_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware
   Feedback Notification support.
 - Add CPUID Fn0000_0007 %ecx bit 29 ENQCMD.
 - Add CPUID Fn0000_0007 %edx bit 1 SGX-KEYS.
 - Add CPUID Fn0000_0007 %edx bit 5 UINTR(User INTeRrupts).
 - Add CPUID Fn0000_0007 %edx bit 1 RTM_ALWAYS_ABORT.
 - Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT.
 - Add CPUID Fn0000_0007 %edx bit 22 AMX_BF16.
 - Add CPUID Fn0000_0007 %edx bit 23 AVX512_FP16.
 - Add CPUID Fn0000_0007 %edx bit 24 AMX_TILE.
 - Add CPUID Fn0000_0007 %edx bit 25 AMX_INT8.
 - Add CPUID Fn0000_0007 sub-leaf 1 %edx bit 18 CET_SSS.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 0 PSFD.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 1 IPRED_CTRL.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 2 RRSBA_CTRL.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 3 DDPD_U.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 4 BHI_CTRL.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 5 MCDT_NO.
 - Modify comment. Both Intel and AMD support CPUID Fn0000000b.
 - Add CPUID Fn0000_000d sub-leaf 1 %eax bit 4 XFD.
 - Modify comment. Hybrid Information -> Native Model ID Information.
 - Add CPUID Fn0000_001d Tile Information.
 - Add CPUID Fn0000_001e TMUL Information.

Fix comment.

Revision 1.201 / (download) - annotate - [select for diffs], Fri Dec 30 14:50:52 2022 UTC (5 weeks, 4 days ago) by msaitoh
Branch: MAIN
CVS Tags: HEAD
Changes since 1.200: +5 -5 lines
Diff to previous 1.200 (colored)

Fix comment.

Revision 1.200 / (download) - annotate - [select for diffs], Fri Dec 30 12:12:54 2022 UTC (5 weeks, 4 days ago) by msaitoh
Branch: MAIN
Changes since 1.199: +73 -18 lines
Diff to previous 1.199 (colored)

Update definitions from the latest Intel SDM.

 - Rename HW_FEEDBACK to HWI (Hardware Feedback Interface).
 - Add CPUID Fn0000_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware
   Feedback Notification support.
 - Add CPUID Fn0000_0007 %ecx bit 29 ENQCMD.
 - Add CPUID Fn0000_0007 %edx bit 1 SGX-KEYS.
 - Add CPUID Fn0000_0007 %edx bit 5 UINTR(User INTeRrupts).
 - Add CPUID Fn0000_0007 %edx bit 1 RTM_ALWAYS_ABORT.
 - Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT.
 - Add CPUID Fn0000_0007 %edx bit 22 AMX_BF16.
 - Add CPUID Fn0000_0007 %edx bit 23 AVX512_FP16.
 - Add CPUID Fn0000_0007 %edx bit 24 AMX_TILE.
 - Add CPUID Fn0000_0007 %edx bit 25 AMX_INT8.
 - Add CPUID Fn0000_0007 sub-leaf 1 %edx bit 18 CET_SSS.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 0 PSFD.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 1 IPRED_CTRL.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 2 RRSBA_CTRL.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 3 DDPD_U.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 4 BHI_CTRL.
 - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 5 MCDT_NO.
 - Modify comment. Both Intel and AMD support CPUID Fn0000000b.
 - Add CPUID Fn0000_000d sub-leaf 1 %eax bit 4 XFD.
 - Modify comment. Hybrid Information -> Native Model ID Information.
 - Add CPUID Fn0000_001d Tile Information.
 - Add CPUID Fn0000_001e TMUL Information.

Revision 1.199 / (download) - annotate - [select for diffs], Tue Dec 27 09:36:29 2022 UTC (6 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.198: +65 -64 lines
Diff to previous 1.198 (colored)

Use __BIT(). Add comment. Whitespace. No functional change.

Revision 1.198 / (download) - annotate - [select for diffs], Mon Nov 21 12:21:17 2022 UTC (2 months, 2 weeks ago) by msaitoh
Branch: MAIN
CVS Tags: netbsd-10-base
Branch point for: netbsd-10
Changes since 1.197: +6 -3 lines
Diff to previous 1.197 (colored)

Update AMD CPUID Fn8000_001b

 - Add IbsFetchCtlExtd and IbsOpData4.
 - Fix typo (lbs -> Ibs).

Revision 1.197 / (download) - annotate - [select for diffs], Wed Nov 16 14:55:50 2022 UTC (2 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.196: +19 -1 lines
Diff to previous 1.196 (colored)

Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.

Revision 1.196 / (download) - annotate - [select for diffs], Wed Nov 16 14:01:41 2022 UTC (2 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.195: +24 -1 lines
Diff to previous 1.195 (colored)

Add CPUID Fn8000_0021 AMD Extended Features Identification 2.

Revision 1.195 / (download) - annotate - [select for diffs], Wed Nov 16 13:14:33 2022 UTC (2 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.194: +56 -9 lines
Diff to previous 1.194 (colored)

Add Some definitions from AMD APM:

- Add CPUID Fn8000_0007 %eax RAS capabilities.
- Add CPUID Fn8000_001b Instruction-Based Sampling capabilities.
- Add BTC_NO, ROGPT, RPMQUERY, VmplSSS, TscAuxVirt, VmgexitParam,
  VirtualTomMsr, bsVirtGuest, SmtProtection, vsmCommPageMSR and
  NestedVirtSnpMsr.

Revision 1.194 / (download) - annotate - [select for diffs], Wed Oct 19 15:01:24 2022 UTC (3 months, 2 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.193: +6 -3 lines
Diff to previous 1.193 (colored)

Add AMD cpuid Fn8000_000a x2AVIC, VNMI and IBSVIRT from APM Vol. 3 Rev. 3.34.

Revision 1.98.2.24 / (download) - annotate - [select for diffs], Sat Oct 15 10:16:07 2022 UTC (3 months, 3 weeks ago) by martin
Branch: netbsd-8
Changes since 1.98.2.23: +32 -22 lines
Diff to previous 1.98.2.23 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1775):

	sys/arch/x86/include/specialreg.h: revision 1.189
	usr.sbin/cpuctl/arch/i386.c: revision 1.128
	sys/arch/x86/include/specialreg.h: revision 1.190
	sys/arch/x86/include/specialreg.h: revision 1.191
	sys/arch/x86/include/specialreg.h: revision 1.192

s/shareing/sharing/. No functional change.

Add top-down slots event bit of architectural performance monitoring leaf.

Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.

Modify output of CPUID Fn0000000a.
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>

Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().

Revision 1.150.2.11 / (download) - annotate - [select for diffs], Sat Oct 15 10:08:40 2022 UTC (3 months, 3 weeks ago) by martin
Branch: netbsd-9
Changes since 1.150.2.10: +32 -22 lines
Diff to previous 1.150.2.10 (colored) to branchpoint 1.150 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1542):

	sys/arch/x86/include/specialreg.h: revision 1.189
	sys/dev/nvmm/x86/nvmm_x86.c: revision 1.23
	usr.sbin/cpuctl/arch/i386.c: revision 1.128
	sys/arch/x86/include/specialreg.h: revision 1.190
	sys/arch/x86/include/specialreg.h: revision 1.191
	sys/arch/x86/include/specialreg.h: revision 1.192

s/shareing/sharing/. No functional change.

Add top-down slots event bit of architectural performance monitoring leaf.

Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.

Modify output of CPUID Fn0000000a.
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>

Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().

Revision 1.193 / (download) - annotate - [select for diffs], Wed Oct 12 10:25:41 2022 UTC (3 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.192: +17 -1 lines
Diff to previous 1.192 (colored)

Add CPUID Fn8000_001e Processor Topology Information.

Revision 1.192 / (download) - annotate - [select for diffs], Thu Oct 6 00:22:16 2022 UTC (4 months ago) by msaitoh
Branch: MAIN
Changes since 1.191: +21 -17 lines
Diff to previous 1.191 (colored)

Update some AMD CPUID bits:

- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().

Revision 1.191 / (download) - annotate - [select for diffs], Wed Jun 15 16:25:33 2022 UTC (7 months, 3 weeks ago) by msaitoh
Branch: MAIN
CVS Tags: bouyer-sunxi-drm-base, bouyer-sunxi-drm
Changes since 1.190: +8 -3 lines
Diff to previous 1.190 (colored)

Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.

Revision 1.190 / (download) - annotate - [select for diffs], Mon Jun 13 06:22:31 2022 UTC (7 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.189: +5 -4 lines
Diff to previous 1.189 (colored)

Add top-down slots event bit of architectural performance monitoring leaf.

Revision 1.189 / (download) - annotate - [select for diffs], Tue Feb 1 05:27:40 2022 UTC (12 months, 1 week ago) by msaitoh
Branch: MAIN
Changes since 1.188: +3 -3 lines
Diff to previous 1.188 (colored)

s/shareing/sharing/. No functional change.

Revision 1.98.2.23 / (download) - annotate - [select for diffs], Mon Jan 31 17:46:36 2022 UTC (12 months, 1 week ago) by martin
Branch: netbsd-8
Changes since 1.98.2.22: +346 -287 lines
Diff to previous 1.98.2.22 (colored) to branchpoint 1.98 (colored)

Pull up the following revisions (all via patch), requested by
msaitoh in ticket #1731:

	sys/arch/x86/include/specialreg.h		1.179-1.188

- Add CPUID definitions of Last Branch Record, Thread Director,
  AVX version of VNNI, Fast short REP MOV, HRESET, PPIN, Architectural
  LBR, Linear Address Masking and Hybrid Information from the latest
  Intel SDM.
- Add CPUID definitions of AddrMaskExt, INT_WBINVD, IbrsSameMode,
  EferLmsleUnsupported, PSFD and SecureTSC from AMD APM.
- Print CLFSH instead of CLFLUSH because both Intel and AMD documents
  say so.
- Modify comment. Add comment. Fix typo. Use __BIT(). KNF. Sort lines.
  No functional change.

Revision 1.150.2.10 / (download) - annotate - [select for diffs], Mon Jan 31 17:42:17 2022 UTC (12 months, 1 week ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-3-RELEASE
Changes since 1.150.2.9: +346 -287 lines
Diff to previous 1.150.2.9 (colored) to branchpoint 1.150 (colored)

Pull up the following revisions (all via patch), requested by msaitoh
in ticket #1417:

	sys/arch/x86/include/specialreg.h		1.179-1.188

- Add CPUID definitions of Last Branch Record, Thread Director,
  AVX version of VNNI, Fast short REP MOV, HRESET, PPIN, Architectural
  LBR, Linear Address Masking and Hybrid Information from the latest
  Intel SDM.
- Add CPUID definitions of AddrMaskExt, INT_WBINVD, IbrsSameMode,
  EferLmsleUnsupported, PSFD and SecureTSC from AMD APM.
- Print CLFSH instead of CLFLUSH because both Intel and AMD documents
  say so.
- Modify comment. Add comment. Fix typo. Use __BIT(). KNF. Sort lines.
  No functional change.

Revision 1.188 / (download) - annotate - [select for diffs], Sat Jan 29 08:18:22 2022 UTC (12 months, 1 week ago) by msaitoh
Branch: MAIN
Changes since 1.187: +10 -1 lines
Diff to previous 1.187 (colored)

Add Intel Hybrid Information Enumeration (CPUID Fn0000_001a).

Revision 1.187 / (download) - annotate - [select for diffs], Mon Jan 17 20:56:02 2022 UTC (12 months, 3 weeks ago) by andvar
Branch: MAIN
Changes since 1.186: +2 -2 lines
Diff to previous 1.186 (colored)

fix typos in comments, mainly s/foward/forward/.

Revision 1.186 / (download) - annotate - [select for diffs], Sat Jan 15 10:59:40 2022 UTC (12 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.185: +22 -9 lines
Diff to previous 1.185 (colored)

Add Some definitions from AMD APM:

 - CPUID Fn80000001 %ecx bit 30 AddrMaskExt.
 - CPUID Fn80000008 %ebx bit 13 INT_WBINVD.
 - CPUID Fn80000008 %ebx bit 19 IbrsSameMode.
 - CPUID Fn80000008 %ebx bit 20 EferLmsleUnsupported.
 - CPUID Fn80000008 %ebx bit 28 PSFD.
 - CPUID Fn80000008 %edx bit 30 as "B30". Not documented.
 - CPUID Fn8000001f %eax bit  8 SecureTSC.
 - CPUID Fn8000001f %eax bit 24 VmsaRegProt.
 - Tested by nonaka@.

Revision 1.185 / (download) - annotate - [select for diffs], Sat Jan 15 10:09:15 2022 UTC (12 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.184: +23 -23 lines
Diff to previous 1.184 (colored)

Whitespace. No functional change.

Revision 1.184 / (download) - annotate - [select for diffs], Sat Jan 15 09:58:23 2022 UTC (12 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.183: +6 -6 lines
Diff to previous 1.183 (colored)

Move CPUID_CAPEX_FLAGS next to %eax because it's for %eax.

Revision 1.183 / (download) - annotate - [select for diffs], Sat Jan 15 09:55:13 2022 UTC (12 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.182: +125 -111 lines
Diff to previous 1.182 (colored)

No functional change.

 - Modify comment. Add comment. Fix typo. Mainly taken from dragonfly.
 - Use __BIT().

Revision 1.182 / (download) - annotate - [select for diffs], Fri Jan 14 15:46:41 2022 UTC (12 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.181: +7 -3 lines
Diff to previous 1.181 (colored)

Add Architectural LBR and Linear Address Masking.

Revision 1.181 / (download) - annotate - [select for diffs], Fri Jan 14 15:45:53 2022 UTC (12 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.180: +2 -2 lines
Diff to previous 1.180 (colored)

Both Intel and AMD says the name of CPUID 0x01 %edx bit 19 is "CLFSH".

Revision 1.180 / (download) - annotate - [select for diffs], Thu Jan 13 16:03:38 2022 UTC (12 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.179: +25 -6 lines
Diff to previous 1.179 (colored)

Add some CPUID bits from the latest Intel SDM.

 - Last Branch Record.
 - Thread Director.
 - AVX version of VNNI.
 - Fast short REP MOV.
 - HRESET.
 - PPIN.

Revision 1.179 / (download) - annotate - [select for diffs], Thu Jan 13 00:21:41 2022 UTC (12 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.178: +153 -153 lines
Diff to previous 1.178 (colored)

 Use __BIT(). KNF. No functional change.

Revision 1.98.2.22 / (download) - annotate - [select for diffs], Wed Dec 8 15:56:17 2021 UTC (14 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.21: +96 -68 lines
Diff to previous 1.98.2.21 (colored) to branchpoint 1.98 (colored)

Pull up the following, requested by msaitoh in ticket #1720:

	sys/arch/x86/include/specialreg.h		1.146, 1.171,
							1.173-1.178 via patch
	sys/arch/x86/x86/identcpu.c			1.106, 1.117,
							1.122 via patch
	sys/arch/x86/x86/pmap.c				patch
	sys/external/bsd/drm2/drm/drm_cache.c		1.14
	usr.sbin/cpuctl/arch/i386.c			1.114-1.117


- Add PT, PKRU, HDC, LA57, PKE, PKS, CET, CET_U, CET_S, HWP, KL,
  AVX512_BF16, TME_EN and PCONFIG.
- Rename some macros to match the x86 specification and the other OSes.
- Print CPUID 0x8000008 %ebx on Intel, too.
- Print CPUID leaf 7 subleaf 1.
- Identify Tiger Lake, 3rd gen Xeon Scalable (Ice Lake), Elkhart Lake
  and Jasper Lake.
- Remove a few unused MSRs.
- Add comment.
- KNF. Whitespace fix.

Revision 1.150.2.9 / (download) - annotate - [select for diffs], Wed Dec 8 15:44:16 2021 UTC (14 months ago) by martin
Branch: netbsd-9
Changes since 1.150.2.8: +44 -32 lines
Diff to previous 1.150.2.8 (colored) to branchpoint 1.150 (colored)

Pull up the following revisions, requested by msaitoh in ticket #1391:

	sys/arch/x86/include/specialreg.h		1.171, 1.173-1.178
	sys/arch/x86/x86/identcpu.c			1.106, 1.117,
							1.122 via patch
	sys/dev/nvmm/x86/nvmm_x86.c			1.18
	sys/external/bsd/drm2/drm/drm_cache.c		1.14
	sys/external/bsd/drm2/include/asm/cpufeature.h	1.5
	usr.sbin/cpuctl/arch/i386.c			1.114-1.117


- Add LA57, PKE, PKS, CET, CET_U, CET_S, HWP, KL, AVX512_BF16, TME_EN
  and PCONFIG.
- Rename some macros to match the x86 specification and the other OSes.
- Print CPUID 0x8000008 %ebx on Intel, too.
- Print CPUID leaf 7 subleaf 1.
- Identify Tiger Lake, 3rd gen Xeon Scalable (Ice Lake), Elkhart Lake
  and Jasper Lake.
- Add comment.
- KNF. Whitespace fix.

Revision 1.178 / (download) - annotate - [select for diffs], Thu Sep 30 15:54:55 2021 UTC (16 months, 1 week ago) by msaitoh
Branch: MAIN
Changes since 1.177: +2 -2 lines
Diff to previous 1.177 (colored)

Print CPUID_PBE (Pending Break Enable) with "PBE".

Revision 1.176.4.1 / (download) - annotate - [select for diffs], Sun Aug 1 22:42:19 2021 UTC (18 months, 1 week ago) by thorpej
Branch: thorpej-i2c-spi-conf
Changes since 1.176: +5 -3 lines
Diff to previous 1.176 (colored) next main 1.177 (colored)

Sync with HEAD.

Revision 1.177 / (download) - annotate - [select for diffs], Sat Jul 10 17:08:37 2021 UTC (18 months, 4 weeks ago) by msaitoh
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base, thorpej-i2c-spi-conf2, thorpej-i2c-spi-conf-base, thorpej-futex2-base, thorpej-futex2, thorpej-cfargs2-base, thorpej-cfargs2
Changes since 1.176: +5 -3 lines
Diff to previous 1.176 (colored)

Add some definitions from Intel SDM:

 - CPUID leaf 7:0 %ecx bit 13 TME_EN (Total Memory Encryption)
 - CPUID leaf 7:0 %edx bit 18 PCONFIG (Platform CONFIGuration)

Revision 1.175.2.1 / (download) - annotate - [select for diffs], Mon Dec 14 14:38:03 2020 UTC (2 years, 1 month ago) by thorpej
Branch: thorpej-futex
Changes since 1.175: +13 -6 lines
Diff to previous 1.175 (colored) next main 1.176 (colored)

Sync w/ HEAD.

Revision 1.176 / (download) - annotate - [select for diffs], Tue Nov 24 00:46:28 2020 UTC (2 years, 2 months ago) by msaitoh
Branch: MAIN
CVS Tags: thorpej-futex-base, thorpej-cfargs-base, thorpej-cfargs, cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x
Branch point for: thorpej-i2c-spi-conf
Changes since 1.175: +13 -6 lines
Diff to previous 1.175 (colored)

Add some definitions from the latest Intel SDM:

 - Add CPUID leaf 7 %edx bit 23 "KL" (Key Locker).
 - Add CPUID leaf 7 subleaf 1 %eax bit 5 "AVX512_BF16".

Revision 1.175 / (download) - annotate - [select for diffs], Mon Sep 7 13:19:20 2020 UTC (2 years, 5 months ago) by jakllsch
Branch: MAIN
Branch point for: thorpej-futex
Changes since 1.174: +2 -2 lines
Diff to previous 1.174 (colored)

Fix printb string for LA57

Revision 1.174 / (download) - annotate - [select for diffs], Mon Sep 7 03:03:09 2020 UTC (2 years, 5 months ago) by msaitoh
Branch: MAIN
Changes since 1.173: +3 -1 lines
Diff to previous 1.173 (colored)

 Add CPUID(EAX=07H, ECX=0) ECX bit 16 LA57 from maxv.

Revision 1.173 / (download) - annotate - [select for diffs], Sat Sep 5 07:45:44 2020 UTC (2 years, 5 months ago) by maxv
Branch: MAIN
Changes since 1.172: +12 -15 lines
Diff to previous 1.172 (colored)

x86: fix several CPUID flags

 - Rename: CPUID_PN      -> CPUID_PSN
           CPUID_CFLUSH  -> CPUID_CLFSH
           CPUID_SBF     -> CPUID_PBE
           CPUID_LZCNT   -> CPUID_ABM
           CPUID_P1GB    -> CPUID_PAGE1GB
           CPUID2_PCLMUL -> CPUID2_PCLMULQDQ
           CPUID2_CID    -> CPUID2_CNXTID
           CPUID2_xTPR   -> CPUID2_XTPR
           CPUID2_AES    -> CPUID2_AESNI
   To match the x86 specification and the other OSes.

 - Remove: CPUID_B10, CPUID_B20, CPUID_IA64. They do not exist.

Revision 1.150.2.8 / (download) - annotate - [select for diffs], Fri Sep 4 18:53:43 2020 UTC (2 years, 5 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-2-RELEASE, netbsd-9-1-RELEASE
Changes since 1.150.2.7: +9 -1 lines
Diff to previous 1.150.2.7 (colored) to branchpoint 1.150 (colored)

Pull up following revision(s) (requested by maxv in ticket #1076):

	sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.75
	sys/arch/x86/include/specialreg.h: revision 1.172
	sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.72

nvmm-x86-vmx: fix detection of the BIOS lock

If it's locked, ensure it's locked with VMX enabled. If it's not locked,
then lock it ourselves with VMX enabled.

Should fix NetBSD PR/55596.

 -

Add a few more CPUID flags.

 -

nvmm-x86-svm: check the SVM revision
Only revision 1 exists, but check it, for future-proofness.

Revision 1.172 / (download) - annotate - [select for diffs], Fri Sep 4 17:05:09 2020 UTC (2 years, 5 months ago) by maxv
Branch: MAIN
Changes since 1.171: +9 -1 lines
Diff to previous 1.171 (colored)

Add a few more CPUID flags.

Revision 1.98.2.21 / (download) - annotate - [select for diffs], Wed Aug 5 18:26:17 2020 UTC (2 years, 6 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.20: +12 -1 lines
Diff to previous 1.98.2.20 (colored) to branchpoint 1.98 (colored)

Accidently not commited for ticket #1595:

	sys/arch/x86/include/specialreg.h               1.129 via patch

Add six errata for AMD Family 17h (Ryzen etc).

Revision 1.98.2.20 / (download) - annotate - [select for diffs], Wed Aug 5 16:02:53 2020 UTC (2 years, 6 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.19: +38 -14 lines
Diff to previous 1.98.2.19 (colored) to branchpoint 1.98 (colored)

Pull up the following revisions, requested by msaitoh in ticket #1588:

	sys/arch/x86/include/specialreg.h		1.162-1.168 via patch

- AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL".
- Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory
  features.
- Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC
  intercept bit.
- Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE.
- Add some definitions for Intel:
  - Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and
    IA32_PACKAGE_TERM* MSRs.
  - Add CPUID leaf 7 %ecx bit 31 for Protection Keys.
  - Add definition of Load only TLB and Store only TLB.
  - Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES
  - Fix HWP_IGNIDL.
- Add CPUID 7 %edx bit 9 "SRBDS_CTRL"
- Modify comment. Style and fix typo.

Revision 1.171 / (download) - annotate - [select for diffs], Wed Aug 5 15:40:46 2020 UTC (2 years, 6 months ago) by maxv
Branch: MAIN
Changes since 1.170: +14 -10 lines
Diff to previous 1.170 (colored)

Add new fields here and there.

Revision 1.170 / (download) - annotate - [select for diffs], Mon Jul 20 05:50:55 2020 UTC (2 years, 6 months ago) by maxv
Branch: MAIN
Changes since 1.169: +1 -4 lines
Diff to previous 1.169 (colored)

Revert previous, to unbreak the build (NVMM declares the macro too).

There are hundreds of MSRs, we're not going to list them all, especially
when the majority are unused.

Revision 1.169 / (download) - annotate - [select for diffs], Sun Jul 19 16:17:00 2020 UTC (2 years, 6 months ago) by jdolecek
Branch: MAIN
Changes since 1.168: +4 -1 lines
Diff to previous 1.168 (colored)

add definition for MSR_IA32_FEATURE_CONTROL, just for information

Revision 1.150.2.7 / (download) - annotate - [select for diffs], Mon Jul 13 13:33:29 2020 UTC (2 years, 6 months ago) by martin
Branch: netbsd-9
Changes since 1.150.2.6: +39 -15 lines
Diff to previous 1.150.2.6 (colored) to branchpoint 1.150 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #998):

	sys/arch/x86/include/specialreg.h: revision 1.162
	sys/arch/x86/include/specialreg.h: revision 1.164
	sys/arch/x86/include/specialreg.h: revision 1.165
	sys/arch/x86/include/specialreg.h: revision 1.166
	sys/arch/x86/include/specialreg.h: revision 1.167
	sys/arch/x86/include/specialreg.h: revision 1.168

- AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL".
- Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory
   features.
- Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit.
- Modify comment.
Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE.
This bit makes lfence instruction serializing.
Add some definitions from the latest Intel SDM plus small fix:
  - Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs.
  - Add CPUID leaf 7 %ecx bit 31 for Protection Keys.
  - Add definition of Load only TLB and Store only TLB.
  - Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES
  - Fix HWP_IGNIDL.
  Add SRBDS_CTRL bit.
style and fix typo

Revision 1.168 / (download) - annotate - [select for diffs], Thu Jun 18 16:27:24 2020 UTC (2 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.167: +7 -7 lines
Diff to previous 1.167 (colored)

style and fix typo

Revision 1.167 / (download) - annotate - [select for diffs], Wed Jun 10 03:39:03 2020 UTC (2 years, 7 months ago) by msaitoh
Branch: MAIN
Changes since 1.166: +3 -2 lines
Diff to previous 1.166 (colored)

 Add SRBDS_CTRL bit.

Revision 1.166 / (download) - annotate - [select for diffs], Mon Jun 1 08:32:39 2020 UTC (2 years, 8 months ago) by msaitoh
Branch: MAIN
Changes since 1.165: +9 -4 lines
Diff to previous 1.165 (colored)

Add some definitions from the latest Intel SDM plus small fix:

 - Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs.
 - Add CPUID leaf 7 %ecx bit 31 for Protection Keys.
 - Add definition of Load only TLB and Store only TLB.
 - Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES
 - Fix HWP_IGNIDL.

Revision 1.165 / (download) - annotate - [select for diffs], Thu May 28 07:59:38 2020 UTC (2 years, 8 months ago) by msaitoh
Branch: MAIN
Changes since 1.164: +2 -1 lines
Diff to previous 1.164 (colored)

Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE.
This bit makes lfence instruction serializing.

Revision 1.164 / (download) - annotate - [select for diffs], Fri May 1 04:07:24 2020 UTC (2 years, 9 months ago) by msaitoh
Branch: MAIN
Changes since 1.163: +7 -4 lines
Diff to previous 1.163 (colored)

- Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit.
- Modify comment.

Revision 1.163 / (download) - annotate - [select for diffs], Sat Apr 25 15:26:18 2020 UTC (2 years, 9 months ago) by bouyer
Branch: MAIN
Changes since 1.162: +1 -1 lines
Diff to previous 1.162 (colored)

Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
guests in GENERIC.
Xen support can be disabled at runtime with
boot -c
disable hypervisor

Revision 1.161.2.1 / (download) - annotate - [select for diffs], Sat Apr 25 11:23:57 2020 UTC (2 years, 9 months ago) by bouyer
Branch: bouyer-xenpvh
Changes since 1.161: +17 -3 lines
Diff to previous 1.161 (colored) next main 1.162 (colored)

Sync with bouyer-xenpvh-base2 (HEAD)

Revision 1.162 / (download) - annotate - [select for diffs], Fri Apr 24 09:49:05 2020 UTC (2 years, 9 months ago) by msaitoh
Branch: MAIN
CVS Tags: bouyer-xenpvh-base2
Changes since 1.161: +17 -3 lines
Diff to previous 1.161 (colored)

- AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL".
- Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory
  features.

Revision 1.98.2.19 / (download) - annotate - [select for diffs], Wed Apr 15 14:25:09 2020 UTC (2 years, 9 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.18: +12 -6 lines
Diff to previous 1.98.2.18 (colored) to branchpoint 1.98 (colored)

Pull up the following, requested by msaitoh in ticket #1530:

	sys/arch/x86/x86/procfs_machdep.c		1.33-1.36
	sys/arch/x86/x86/tsc.c				1.40
	sys/arch/x86/x86/specialreg.h			1.159-1.161
	usr.sbin/cpuctl/arch/i386.c			1.109-1.110 via patch

- Print avx512ifma, cqm_mbm_total, cqm_mbm_local, waitpkg, rdpru,
  Fast Short Rep Mov(fsrm), AVX512_VP2INTERSECT, SERIALIZE and
  TSXLDTRK.
- Rename CPUID Fn8000_0007 %edx bit 8 from "TSC" to "ITSC"
  (Invariant TSC) to avoid confusion.
- Print CPUID 0x80000007 %edx on both Intel and AMD.
- Remove ci_max_ext_cpuid from usr.sbin/cpuctl/arch/i386.c because it's
  the same as ci_cpuid_extlevel.
- Use unsigned to avoid undefined behavior in procfs_getonefeatreg().

Revision 1.150.2.6 / (download) - annotate - [select for diffs], Tue Apr 14 17:15:02 2020 UTC (2 years, 9 months ago) by martin
Branch: netbsd-9
Changes since 1.150.2.5: +12 -6 lines
Diff to previous 1.150.2.5 (colored) to branchpoint 1.150 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #833):

	usr.sbin/cpuctl/arch/i386.c: revision 1.109
	sys/arch/x86/include/specialreg.h: revision 1.159
	usr.sbin/cpuctl/arch/i386.c: revision 1.110
	sys/arch/x86/include/specialreg.h: revision 1.160
	sys/arch/x86/include/specialreg.h: revision 1.161
	sys/arch/x86/x86/tsc.c: revision 1.40
	sys/arch/x86/x86/procfs_machdep.c: revision 1.35
	sys/arch/x86/x86/procfs_machdep.c: revision 1.36

  Add Fast Short Rep Mov(fsrm).

Add AVX512_VP2INTERSECT, SERIALIZE and TSXLDTRK(TSX suspend load addr tracking)

  CPUID Fn00000001 %edx bit 8 is printed as "TSC", so rename CPUID Fn8000_0007
%edx bit 8 from "TSC" to "ITSC" (Invariant TSC) to avoid confusion.

  Rename CPUID_APM_TSC to CPUID_APM_ITSC. No functional change.

  Remove ci_max_ext_cpuid because it's the same as ci_cpuid_extlevel.

  Print CPUID 0x80000007 %edx on both Intel and AMD.

Revision 1.126.2.2 / (download) - annotate - [select for diffs], Mon Apr 13 08:04:11 2020 UTC (2 years, 9 months ago) by martin
Branch: phil-wifi
Changes since 1.126.2.1: +118 -16 lines
Diff to previous 1.126.2.1 (colored) to branchpoint 1.126 (colored) next main 1.127 (colored)

Mostly merge changes from HEAD upto 20200411

Revision 1.161 / (download) - annotate - [select for diffs], Mon Apr 6 09:24:49 2020 UTC (2 years, 10 months ago) by msaitoh
Branch: MAIN
CVS Tags: phil-wifi-20200421, phil-wifi-20200411, phil-wifi-20200406, bouyer-xenpvh-base1, bouyer-xenpvh-base
Branch point for: bouyer-xenpvh
Changes since 1.160: +5 -3 lines
Diff to previous 1.160 (colored)

 Rename CPUID_APM_TSC to CPUID_APM_ITSC. No functional change.

Revision 1.160 / (download) - annotate - [select for diffs], Mon Apr 6 02:36:49 2020 UTC (2 years, 10 months ago) by msaitoh
Branch: MAIN
Changes since 1.159: +3 -3 lines
Diff to previous 1.159 (colored)

 CPUID Fn00000001 %edx bit 8 is printed as "TSC", so rename CPUID Fn8000_0007
%edx bit 8 from "TSC" to "ITSC" (Invariant TSC) to avoid confusion.

Revision 1.159 / (download) - annotate - [select for diffs], Wed Apr 1 08:21:38 2020 UTC (2 years, 10 months ago) by msaitoh
Branch: MAIN
Changes since 1.158: +7 -3 lines
Diff to previous 1.158 (colored)

Add AVX512_VP2INTERSECT, SERIALIZE and TSXLDTRK(TSX suspend load addr tracking)

Revision 1.98.2.18 / (download) - annotate - [select for diffs], Fri Jan 31 10:53:29 2020 UTC (3 years ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-2-RELEASE
Changes since 1.98.2.17: +63 -10 lines
Diff to previous 1.98.2.17 (colored) to branchpoint 1.98 (colored)

Pull up the following, requested by msaitoh in ticket #1494:

	sys/arch/x86/include/specialreg.h	1.146, 1.151-1.154, 1.156 via patch
	usr.sbin/cpuctl/arch/i386.c		1.105-1.107 via patch

- Add definitions of AMD's CPUID Fn8000_0008 %ebx.
- Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.
- Call cpu_dcp_cacheinfo() only when the cpuid Topology Extension flag
  is set on AMD processor.
- Fix typos.

Revision 1.150.2.5 / (download) - annotate - [select for diffs], Tue Nov 19 13:15:57 2019 UTC (3 years, 2 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-0-RELEASE, netbsd-9-0-RC2, netbsd-9-0-RC1
Changes since 1.150.2.4: +9 -3 lines
Diff to previous 1.150.2.4 (colored) to branchpoint 1.150 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #452):

	usr.sbin/cpuctl/arch/i386.c: revision 1.108
	sys/arch/x86/include/specialreg.h: revision 1.158

Add the following bit definitions from the latest Intel SDM:
 - CET shadow stack
 - Fast Short REP MOV
 - Hybrid part
 - CET Indirect Branch Tracking
0x7d and 0x7e are for 10th generation Core (Ice Lake).

Revision 1.98.2.17 / (download) - annotate - [select for diffs], Tue Nov 19 10:45:11 2019 UTC (3 years, 2 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.16: +9 -3 lines
Diff to previous 1.98.2.16 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1450):

	usr.sbin/cpuctl/arch/i386.c: revision 1.108
	sys/arch/x86/include/specialreg.h: revision 1.158

Add the following bit definitions from the latest Intel SDM:
 - CET shadow stack
 - Fast Short REP MOV
 - Hybrid part
 - CET Indirect Branch Tracking

0x7d and 0x7e are for 10th generation Core (Ice Lake).

Revision 1.158 / (download) - annotate - [select for diffs], Sun Nov 17 15:31:05 2019 UTC (3 years, 2 months ago) by msaitoh
Branch: MAIN
CVS Tags: phil-wifi-20191119, is-mlppp-base, is-mlppp, ad-namecache-base3, ad-namecache-base2, ad-namecache-base1, ad-namecache-base, ad-namecache
Changes since 1.157: +9 -3 lines
Diff to previous 1.157 (colored)

Add the following bit definitions from the latest Intel SDM:
 - CET shadow stack
 - Fast Short REP MOV
 - Hybrid part
 - CET Indirect Branch Tracking

Revision 1.98.2.16 / (download) - annotate - [select for diffs], Tue Nov 12 18:28:40 2019 UTC (3 years, 2 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.15: +6 -1 lines
Diff to previous 1.98.2.15 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by maxv in ticket #1433):

	sys/arch/x86/include/specialreg.h: revision 1.157
	sys/arch/x86/x86/spectre.c: revision 1.31

Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA).

Two sysctls are added:
	machdep.taa.mitigated = {0/1} user-settable
	machdep.taa.method = {string} constructed by the kernel

There are two cases:

  (1) If the CPU is affected by MDS, then the MDS mitigation will also
mitigate TAA, and we have nothing else to do. We make the 'mitigated' leaf
read-only, and force:

	machdep.taa.mitigated = machdep.mds.mitigated
	machdep.taa.method = [MDS]

The kernel already enables the MDS mitigation by default.

  (2) If the CPU is not affected by MDS but is affected by TAA, then we use
the new TSX_CTRL MSR to disable RTM. This MSR is provided via a microcode
update, now available on the Intel website. The kernel will automatically
enable the TAA mitigation if the updated microcode is present. If the new
microcode is not present, the user can load it via cpuctl, and set
machdep.taa.mitigated=1.

Revision 1.150.2.4 / (download) - annotate - [select for diffs], Tue Nov 12 18:24:37 2019 UTC (3 years, 2 months ago) by martin
Branch: netbsd-9
Changes since 1.150.2.3: +6 -1 lines
Diff to previous 1.150.2.3 (colored) to branchpoint 1.150 (colored)

Pull up following revision(s) (requested by maxv in ticket #419):

	sys/arch/x86/include/specialreg.h: revision 1.157
	sys/arch/x86/x86/spectre.c: revision 1.31

Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA).

Two sysctls are added:
	machdep.taa.mitigated = {0/1} user-settable
	machdep.taa.method = {string} constructed by the kernel

There are two cases:

  (1) If the CPU is affected by MDS, then the MDS mitigation will also
mitigate TAA, and we have nothing else to do. We make the 'mitigated' leaf
read-only, and force:

	machdep.taa.mitigated = machdep.mds.mitigated
	machdep.taa.method = [MDS]

The kernel already enables the MDS mitigation by default.

  (2) If the CPU is not affected by MDS but is affected by TAA, then we use
the new TSX_CTRL MSR to disable RTM. This MSR is provided via a microcode
update, now available on the Intel website. The kernel will automatically
enable the TAA mitigation if the updated microcode is present. If the new
microcode is not present, the user can load it via cpuctl, and set
machdep.taa.mitigated=1.

Revision 1.157 / (download) - annotate - [select for diffs], Tue Nov 12 18:00:13 2019 UTC (3 years, 2 months ago) by maxv
Branch: MAIN
Changes since 1.156: +6 -1 lines
Diff to previous 1.156 (colored)

Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA).

Two sysctls are added:

	machdep.taa.mitigated = {0/1} user-settable
	machdep.taa.method = {string} constructed by the kernel

There are two cases:

 (1) If the CPU is affected by MDS, then the MDS mitigation will also
mitigate TAA, and we have nothing else to do. We make the 'mitigated' leaf
read-only, and force:
	machdep.taa.mitigated = machdep.mds.mitigated
	machdep.taa.method = [MDS]
The kernel already enables the MDS mitigation by default.

 (2) If the CPU is not affected by MDS but is affected by TAA, then we use
the new TSX_CTRL MSR to disable RTM. This MSR is provided via a microcode
update, now available on the Intel website. The kernel will automatically
enable the TAA mitigation if the updated microcode is present. If the new
microcode is not present, the user can load it via cpuctl, and set
machdep.taa.mitigated=1.

Revision 1.150.2.3 / (download) - annotate - [select for diffs], Sun Nov 10 13:06:46 2019 UTC (3 years, 2 months ago) by martin
Branch: netbsd-9
Changes since 1.150.2.2: +5 -4 lines
Diff to previous 1.150.2.2 (colored) to branchpoint 1.150 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #407):

	sys/arch/x86/include/specialreg.h: revision 1.156

- GMET is not bit 11 but 17.
- Add unknown CPUID Fn8000_000a %edx bit 20.

Revision 1.156 / (download) - annotate - [select for diffs], Wed Oct 30 05:35:36 2019 UTC (3 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.155: +5 -4 lines
Diff to previous 1.155 (colored)

- GMET is not bit 11 but 17.
- Add unknown CPUID Fn8000_000a %edx bit 20.

Revision 1.150.2.2 / (download) - annotate - [select for diffs], Thu Oct 17 18:56:24 2019 UTC (3 years, 3 months ago) by martin
Branch: netbsd-9
Changes since 1.150.2.1: +25 -6 lines
Diff to previous 1.150.2.1 (colored) to branchpoint 1.150 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #344):

	sys/arch/x86/include/specialreg.h: revision 1.154
	sys/arch/x86/include/specialreg.h: revision 1.155
	usr.sbin/cpuctl/arch/i386.c: revision 1.107
	sys/arch/x86/x86/procfs_machdep.c: revision 1.34

- Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.

 Fix AMD Fn8000_0001f %eax bit 0's name.

Add rdpru.

Revision 1.155 / (download) - annotate - [select for diffs], Tue Oct 8 03:16:21 2019 UTC (3 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.154: +2 -2 lines
Diff to previous 1.154 (colored)

 Fix AMD Fn8000_0001f %eax bit 0's name.

Revision 1.154 / (download) - annotate - [select for diffs], Thu Oct 3 15:21:44 2019 UTC (3 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.153: +25 -6 lines
Diff to previous 1.153 (colored)

- Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.

Revision 1.150.2.1 / (download) - annotate - [select for diffs], Thu Sep 26 18:47:14 2019 UTC (3 years, 4 months ago) by martin
Branch: netbsd-9
Changes since 1.150: +34 -1 lines
Diff to previous 1.150 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #241):

	sys/arch/x86/include/specialreg.h: revision 1.152
	sys/arch/x86/include/specialreg.h: revision 1.153
	usr.sbin/cpuctl/arch/i386.c: revision 1.105
	sys/arch/x86/x86/spectre.c: revision 1.30
	sys/arch/x86/include/specialreg.h: revision 1.151

Add definitions of AMD's CPUID Fn8000_0008 %ebx.
Decode AMD's CPUID Fn8000_0008 %ebx.
Use macro.
Add MCOMMIT instruction.
Define CPUID_CAPEX_FLAGS's bit 10 correctly.

Revision 1.153 / (download) - annotate - [select for diffs], Thu Sep 26 06:42:52 2019 UTC (3 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.152: +2 -2 lines
Diff to previous 1.152 (colored)

 Define CPUID_CAPEX_FLAGS's bit 10 correctly.

Revision 1.152 / (download) - annotate - [select for diffs], Mon Sep 9 05:28:32 2019 UTC (3 years, 5 months ago) by msaitoh
Branch: MAIN
Changes since 1.151: +3 -2 lines
Diff to previous 1.151 (colored)

 Add MCOMMIT instruction.

Revision 1.151 / (download) - annotate - [select for diffs], Fri Aug 30 13:11:28 2019 UTC (3 years, 5 months ago) by msaitoh
Branch: MAIN
Changes since 1.150: +33 -1 lines
Diff to previous 1.150 (colored)

 Add definitions of AMD's CPUID Fn8000_0008 %ebx.

Revision 1.98.2.15 / (download) - annotate - [select for diffs], Fri Aug 16 15:36:17 2019 UTC (3 years, 5 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.14: +9 -1 lines
Diff to previous 1.98.2.14 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1338):

	usr.sbin/cpuctl/arch/i386.c: revision 1.104
	sys/arch/x86/x86/identcpu.c: revision 1.93
	sys/arch/x86/include/cacheinfo.h: revision 1.28
	sys/arch/x86/include/specialreg.h: revision 1.150

- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
  Intel Deterministic Cache Parameter Leaf(0x04), so make new
  cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
  common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?

Revision 1.150 / (download) - annotate - [select for diffs], Fri Jul 26 10:03:40 2019 UTC (3 years, 6 months ago) by msaitoh
Branch: MAIN
CVS Tags: netbsd-9-base
Branch point for: netbsd-9
Changes since 1.149: +9 -1 lines
Diff to previous 1.149 (colored)

- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
  Intel Deterministic Cache Parameter Leaf(0x04), so make new
  cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
  common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?

Revision 1.98.2.14 / (download) - annotate - [select for diffs], Wed Jul 17 15:37:33 2019 UTC (3 years, 6 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.13: +11 -7 lines
Diff to previous 1.98.2.13 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1293):

	sys/arch/x86/include/specialreg.h: revision 1.149

 Define some new bits of CPUID Fn8000_0007 %edx AMD Advanced Power Management
leaf.

Revision 1.149 / (download) - annotate - [select for diffs], Sat Jul 13 09:28:03 2019 UTC (3 years, 6 months ago) by msaitoh
Branch: MAIN
Changes since 1.148: +11 -7 lines
Diff to previous 1.148 (colored)

 Define some new bits of CPUID Fn8000_0007 %edx AMD Advanced Power Management
leaf.

Revision 1.148 / (download) - annotate - [select for diffs], Wed Jun 26 12:29:00 2019 UTC (3 years, 7 months ago) by mgorny
Branch: MAIN
Changes since 1.147: +21 -1 lines
Diff to previous 1.147 (colored)

Fetch XSAVE area component offsets and sizes when initializing x86 CPU

Introduce two new arrays, x86_xsave_offsets and x86_xsave_sizes,
and initialize them with XSAVE area component offsets and sizes queried
via CPUID.  This will be needed to implement getters and setters for
additional register types.

While at it, add XSAVE_* constants corresponding to specific XSAVE
components.

Revision 1.126.2.1 / (download) - annotate - [select for diffs], Mon Jun 10 22:06:53 2019 UTC (3 years, 8 months ago) by christos
Branch: phil-wifi
Changes since 1.126: +190 -459 lines
Diff to previous 1.126 (colored)

Sync with HEAD

Revision 1.147 / (download) - annotate - [select for diffs], Wed May 29 16:54:41 2019 UTC (3 years, 8 months ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20190609
Changes since 1.146: +8 -1 lines
Diff to previous 1.146 (colored)

Add PCID support in SVS. This avoids TLB flushes during kernel<->user
transitions, which greatly reduces the performance penalty introduced by
SVS.

We use two ASIDs, 0 (kern) and 1 (user), and use invpcid to flush pages
in both ASIDs.

The read-only machdep.svs.pcid={0,1} sysctl is added, and indicates whether
SVS+PCID is in use.

Revision 1.98.2.13 / (download) - annotate - [select for diffs], Wed May 29 15:43:26 2019 UTC (3 years, 8 months ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-1-RELEASE
Changes since 1.98.2.12: +7 -3 lines
Diff to previous 1.98.2.12 (colored) to branchpoint 1.98 (colored)

Pullup the following, requested by msaitoh in ticket #1270:

	sys/arch/x86/include/specialreg.h		1.143, 1.145 via patch
	sys/arch/x86/x86/procfs_machdep.c		1.30

Add TSX_FORCE_ABORT related definitions.
Add cpuid7 edx bit 10 "MD_CLEAR".

Revision 1.146 / (download) - annotate - [select for diffs], Sat May 18 08:17:39 2019 UTC (3 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.145: +50 -45 lines
Diff to previous 1.145 (colored)

Clean up a little, add new XCR0 bits, remove a few unused MSRs, and fix
typos.

Revision 1.145 / (download) - annotate - [select for diffs], Tue May 14 18:11:34 2019 UTC (3 years, 8 months ago) by msaitoh
Branch: MAIN
Changes since 1.144: +2 -1 lines
Diff to previous 1.144 (colored)

 Add snprintb's string for cpuid7 edx bit 10 "MD_CLEAR".

Revision 1.98.2.12 / (download) - annotate - [select for diffs], Tue May 14 17:12:19 2019 UTC (3 years, 8 months ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-1-RC1
Changes since 1.98.2.11: +3 -1 lines
Diff to previous 1.98.2.11 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by maxv in ticket #1269):

	sys/arch/amd64/amd64/locore.S: revision 1.181 (adapted)
	sys/arch/amd64/amd64/amd64_trap.S: revision 1.47 (adapted)
	sys/arch/x86/include/specialreg.h: revision 1.144 (adapted)
	sys/arch/amd64/include/frameasm.h: revision 1.43 (adapted)
	sys/arch/x86/x86/spectre.c: revision 1.27 (adapted)

Mitigation for INTEL-SA-00233: Microarchitectural Data Sampling (MDS).
It requires a microcode update, now available on the Intel website. The
microcode modifies the behavior of the VERW instruction, and makes it flush
internal CPU buffers. We hotpatch the return-to-userland path to add VERW.

Two sysctls are added:

	machdep.mds.mitigated = {0/1} user-settable
	machdep.mds.method = {string} constructed by the kernel

The kernel will automatically enable the mitigation if the updated
microcode is present. If the new microcode is not present, the user can
load it via cpuctl, and set machdep.mds.mitigated=1.

Revision 1.144 / (download) - annotate - [select for diffs], Tue May 14 16:59:26 2019 UTC (3 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.143: +3 -1 lines
Diff to previous 1.143 (colored)

Mitigation for INTEL-SA-00233: Microarchitectural Data Sampling (MDS).

It requires a microcode update, now available on the Intel website. The
microcode modifies the behavior of the VERW instruction, and makes it flush
internal CPU buffers. We hotpatch the return-to-userland path to add VERW.

Two sysctls are added:

	machdep.mds.mitigated = {0/1} user-settable
	machdep.mds.method = {string} constructed by the kernel

The kernel will automatically enable the mitigation if the updated
microcode is present. If the new microcode is not present, the user can
load it via cpuctl, and set machdep.mds.mitigated=1.

Revision 1.143 / (download) - annotate - [select for diffs], Wed Mar 13 05:22:07 2019 UTC (3 years, 10 months ago) by msaitoh
Branch: MAIN
CVS Tags: isaki-audio2-base, isaki-audio2
Changes since 1.142: +6 -3 lines
Diff to previous 1.142 (colored)

Add TSX_FORCE_ABORT related definitions.

Revision 1.142 / (download) - annotate - [select for diffs], Sat Mar 9 08:42:26 2019 UTC (3 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.141: +2 -2 lines
Diff to previous 1.141 (colored)

Start replacing the x86 PTE bits.

Revision 1.141 / (download) - annotate - [select for diffs], Sat Feb 16 12:05:30 2019 UTC (3 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.140: +11 -2 lines
Diff to previous 1.140 (colored)

Handle MSR_MISC_ENABLE on NVMM-Intel (Intel-specific).

Revision 1.98.2.11 / (download) - annotate - [select for diffs], Tue Feb 12 09:27:17 2019 UTC (3 years, 11 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.10: +3 -3 lines
Diff to previous 1.98.2.10 (colored) to branchpoint 1.98 (colored)

Actually pull up rev 1.139 (as claimed, but not done in previous),
requested by msaitoh in ticket #1187:

 Fix bitstring format of Intel CPUID Architectural Performance Monitoring
Fn0000000a %ebx.

Revision 1.140 / (download) - annotate - [select for diffs], Mon Feb 11 14:59:32 2019 UTC (3 years, 11 months ago) by cherry
Branch: MAIN
Changes since 1.139: +3 -3 lines
Diff to previous 1.139 (colored)

We reorganise definitions for XEN source support as follows:

XEN - common sources required for baseline XEN support.
XENPV - sources required for support of XEN in PV mode.
XENPVHVM - sources required for support for XEN in HVM mode.
XENPVH - sources required for support for XEN in PVH mode.

Revision 1.98.2.10 / (download) - annotate - [select for diffs], Mon Feb 11 13:23:03 2019 UTC (3 years, 11 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.9: +10 -4 lines
Diff to previous 1.98.2.9 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1187):

	usr.sbin/cpuctl/arch/i386.c: revision 1.92
	sys/arch/x86/include/specialreg.h: revision 1.138

 Add new CPUID flags WAITPKG, CLDEMOTE, MOVDIRI, MOVDIR64B and
IA32_CORE_CAPABILITIES from the latest Intel SDM.

 Add Ice Lake and Tremont from the latest Intel SDM.

 Fix bitstring format of Intel CPUID Architectural Performance Monitoring
Fn0000000a %ebx.

Revision 1.139 / (download) - annotate - [select for diffs], Fri Feb 8 04:06:00 2019 UTC (4 years ago) by msaitoh
Branch: MAIN
Changes since 1.138: +3 -3 lines
Diff to previous 1.138 (colored)

 Fix bitstring format of Intel CPUID Architectural Performance Monitoring
Fn0000000a %ebx.

Revision 1.138 / (download) - annotate - [select for diffs], Tue Feb 5 08:07:19 2019 UTC (4 years ago) by msaitoh
Branch: MAIN
Changes since 1.137: +10 -4 lines
Diff to previous 1.137 (colored)

 Add new CPUID flags WAITPKG, CLDEMOTE, MOVDIRI, MOVDIR64B and
IA32_CORE_CAPABILITIES from the latest Intel SDM.

Revision 1.112.2.8 / (download) - annotate - [select for diffs], Fri Jan 18 08:50:24 2019 UTC (4 years ago) by pgoyette
Branch: pgoyette-compat
CVS Tags: pgoyette-compat-merge-20190127
Changes since 1.112.2.7: +4 -1 lines
Diff to previous 1.112.2.7 (colored) to branchpoint 1.112 (colored) next main 1.113 (colored)

Synch with HEAD

Revision 1.137 / (download) - annotate - [select for diffs], Sun Jan 13 12:19:09 2019 UTC (4 years ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-20190127, pgoyette-compat-20190118
Changes since 1.136: +4 -1 lines
Diff to previous 1.136 (colored)

Forgot to commit file along with identcpu.c::rev1.86.

Revision 1.98.2.9 / (download) - annotate - [select for diffs], Thu Dec 27 12:17:19 2018 UTC (4 years, 1 month ago) by martin
Branch: netbsd-8
Changes since 1.98.2.8: +4 -2 lines
Diff to previous 1.98.2.8 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by maxv in ticket #1148):

	sys/arch/x86/x86/identcpu.c: revision 1.81
	sys/arch/x86/x86/identcpu.c: revision 1.82
	sys/arch/x86/x86/identcpu.c: revision 1.84
	sys/arch/x86/include/specialreg.h: revision 1.131

Declare the MSR_VIA_ACE values as macros, and use a consistent naming,
similar to the rest of the file.

I'm wondering if I'm not fixing a huge bug here. The ECX8 value we were
using was wrong: ECX8 is bit 1, not bit 0. Bit 0 is ALTINST, an alternate
ISA, which is now known to be backdoored.

So it looks like we were explicitly enabling the backdoor.

Not tested, because I don't have a VIA cpu.

 -

Merge the VIA detection code into cpu_probe_c3.

 -

Explicitly disable ALTINST on VIA, in case it isn't disabled by default
already (the 'VIA cpu backdoor').

Revision 1.112.2.7 / (download) - annotate - [select for diffs], Wed Dec 26 14:01:45 2018 UTC (4 years, 1 month ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.112.2.6: +38 -1 lines
Diff to previous 1.112.2.6 (colored) to branchpoint 1.112 (colored)

Sync with HEAD, resolve a few conflicts

Revision 1.98.2.8 / (download) - annotate - [select for diffs], Tue Dec 4 11:52:57 2018 UTC (4 years, 2 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.7: +87 -12 lines
Diff to previous 1.98.2.7 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1120):

	usr.sbin/cpuctl/arch/i386.c: revision 1.85
	usr.sbin/cpuctl/arch/i386.c: revision 1.86
	usr.sbin/cpuctl/arch/i386.c: revision 1.87
	usr.sbin/cpuctl/arch/i386.c: revision 1.88
	usr.sbin/cpuctl/arch/i386.c: revision 1.89
	usr.sbin/cpuctl/arch/i386.c: revision 1.90
	sys/arch/x86/include/specialreg.h: revision 1.132
	sys/arch/x86/include/specialreg.h: revision 1.133
	sys/arch/x86/include/specialreg.h: revision 1.134
	sys/arch/x86/include/specialreg.h: revision 1.135
	sys/arch/x86/include/specialreg.h: revision 1.136
	sys/arch/x86/x86/cpu_topology.c: revision 1.14

  Add MAWAU (for BND{LD,ST}X instruction) from the latest Intel SDM.

  Whitespace fix. No functional change.

Modify comment. No functional change:
- AMD also has CPUID 0x06 and 0x0d.
- PCOMMIT was obsoleted.
- Use ci_feat_val[7] as CPUID 7 %edx to match x86/cpu.h
- AMD also has CPUID 6.
- Remove unused code for coretemp.
- Consistently use descs[] instead of data[].
- AMD also reports CPUID 7's highest subleaf. Print it.
- Use macro.
  Add Intel CPUID Extended Topology Enumeration Fn0000000b definitions.
  Decode package, core and SMT id if CPUID 0x0b is available on Intel processor.

If the value is different from the kernel value, we should fix the kernel code.

TODO: Use 0x1f if it's available.

  Add Intel/AMD MONITOR/MWAIT leaf.
  Decode Intel/AMD MONITOR/MWAIT leaf.

  Add Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.

  Print Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.

Revision 1.136 / (download) - annotate - [select for diffs], Mon Nov 26 04:43:37 2018 UTC (4 years, 2 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-compat-1226
Changes since 1.135: +38 -1 lines
Diff to previous 1.135 (colored)

 Add Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.

Revision 1.112.2.6 / (download) - annotate - [select for diffs], Mon Nov 26 01:52:28 2018 UTC (4 years, 2 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.112.2.5: +53 -13 lines
Diff to previous 1.112.2.5 (colored) to branchpoint 1.112 (colored)

Sync with HEAD, resolve a couple of conflicts

Revision 1.135 / (download) - annotate - [select for diffs], Thu Nov 22 06:14:35 2018 UTC (4 years, 2 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-compat-1126
Changes since 1.134: +19 -1 lines
Diff to previous 1.134 (colored)

 Add Intel/AMD MONITOR/MWAIT leaf.

Revision 1.134 / (download) - annotate - [select for diffs], Wed Nov 21 12:18:53 2018 UTC (4 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.133: +18 -1 lines
Diff to previous 1.133 (colored)

 Add Intel CPUID Extended Topology Enumeration Fn0000000b definitions.

Revision 1.133 / (download) - annotate - [select for diffs], Wed Nov 21 06:09:49 2018 UTC (4 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.132: +6 -5 lines
Diff to previous 1.132 (colored)

Modify comment. No functional change:
- AMD also has CPUID 0x06 and 0x0d.
- PCOMMIT was obsoleted.

Revision 1.132 / (download) - annotate - [select for diffs], Thu Nov 15 03:50:22 2018 UTC (4 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.131: +10 -8 lines
Diff to previous 1.131 (colored)

 Add MAWAU (for BND{LD,ST}X instruction) from the latest Intel SDM.

Revision 1.131 / (download) - annotate - [select for diffs], Sat Nov 10 10:52:51 2018 UTC (4 years, 2 months ago) by maxv
Branch: MAIN
Changes since 1.130: +4 -2 lines
Diff to previous 1.130 (colored)

Declare the MSR_VIA_ACE values as macros, and use a consistent naming,
similar to the rest of the file.

I'm wondering if I'm not fixing a huge bug here. The ECX8 value we were
using was wrong: ECX8 is bit 1, not bit 0. Bit 0 is ALTINST, an alternate
ISA, which is now known to be backdoored.

So it looks like we were explicitly enabling the backdoor.

Not tested, because I don't have a VIA cpu.

Revision 1.78.4.6 / (download) - annotate - [select for diffs], Tue Oct 9 15:43:38 2018 UTC (4 years, 4 months ago) by snj
Branch: netbsd-7
Changes since 1.78.4.5: +166 -65 lines
Diff to previous 1.78.4.5 (colored) to branchpoint 1.78 (colored) next main 1.79 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1636):
	sys/arch/x86/include/cacheinfo.h: 1.23-1.26
	sys/arch/x86/include/cpu.h: 1.70
	sys/arch/x86/include/specialreg.h: 1.91-1.93,1.98,1.100,1.102-1.124,1.126,1.130 via patch
	sys/arch/x86/x86/cpu_topology.c: 1.10
	sys/arch/x86/x86/identcpu.c: 1.56-1.57,1.70 via patch
	usr.sbin/cpuctl/arch/i386.c: 1.71,1.75-1.79,1.81-1.85 via patch
Add some register definitions for x86:
  - Add CLWB bit.
  - Fix a few (unused) MSR values, and add some bit definitions of
    MSR_EFER from Murray Armfield in PR#42861.
  - CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify
    comments and snprintb() string.
  - Define CPUID Fn00000001 %ebx bits and use them.
    No functional change.
  - Add Structured Extended Flags Enumeration Leaf's bit definitions:
    AVX512_{IFMA,VBMI2,VNNI,BITALG,VPOPCNTDQ,4VNNIW,4FMAPS},GFNI&VAES.
  - Add Turbo Boost Max Technology 3.0 bit.
  - Add AMD SVM features definitions.
  - Add Intel cpuid 7 %edx IBRS and STIBP bit definitions.
  - Fix swapped comments for EFER LME and LMA
  - Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
  - Add MSR_IA32_ARCH_CAPABILITIES definition.
  - Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.
  - Add Intel Deterministic Address Translation Parameter Leaf(0x18)
    definitions.
  - s/CLFUSH/CLFLUSH/
  - Add AMD's Disable Indirect Branch Predictor bit definition.
  - Add the MSR bits definitions for IBRS, STIBP and IBPB.
  - Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
  - Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.
  - Add AMD's CPUID Fn80000001 %edx MMX and FXSR bit definitions.
  - Add RDCL_NO and IBRS_ALL.
  - Add SSBD and RSBA bit definitions.
  - Add AMD's SSB bit definitions for F15H, F16H and F17H.
  - Add cpuid 7 edx L1D_FLUSH bit.
  - Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
  - Add IA32_FLUSH_CMD MSR.
  - Add yet another Shared L2 TLB (2M/4M pages).
  - Add 3way and 6way of L2 cache or TLB on AMD CPU.
  - AMD L3 cache association bitfield is not 8bit but 4bit like others
    association bitfields.
  - Sort entries. No functional change.
  - Modify comment, fix typo in comment and add comment.
cpuctl(8):
  - Add detection for Quark X1000, Xeon E5 v4, E7 v4,
    Core i7-69xx Extreme Edition, Xeon Scalable (Skylake),
    Xeon Phi [357]200 (Knights Landing), Atom (Goldmont),
    Atom (Denverton), Future Core (Cannon Lake), Atom (Goldmont Plus),
    Xeon Phi 7215, 7285 and 7295 (Knights Mill) and
    7th or 8th gen Core (Kaby Lake, Coffee Lake).
  - Print Structured Extended Feature leaf Fn0000_0007 %ebx on AMD,too.
  - Print Fn0000_0007 %ecx on Intel.
  - Print Intel cpuid 7 %edx.
  - Parse the TLB info from `cpuid leaf 18H' on Intel processor.
  - Use aprint_error_dev() for error output.

Revision 1.98.2.7 / (download) - annotate - [select for diffs], Sun Sep 23 17:35:33 2018 UTC (4 years, 4 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.6: +6 -2 lines
Diff to previous 1.98.2.6 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1026):

	sys/arch/x86/x86/procfs_machdep.c: revision 1.24
	sys/arch/x86/include/specialreg.h: revision 1.130

OK'd by maxv:
- Add cpuid 7 edx L1D_FLUSH bit.
- Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
- Add IA32_FLUSH_CMD MSR.

Revision 1.112.2.5 / (download) - annotate - [select for diffs], Thu Sep 6 06:55:44 2018 UTC (4 years, 5 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.112.2.4: +17 -2 lines
Diff to previous 1.112.2.4 (colored) to branchpoint 1.112 (colored)

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Revision 1.130 / (download) - annotate - [select for diffs], Mon Aug 20 08:53:48 2018 UTC (4 years, 5 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-compat-1020, pgoyette-compat-0930, pgoyette-compat-0906
Changes since 1.129: +6 -2 lines
Diff to previous 1.129 (colored)

OK'd by maxv:
- Add cpuid 7 edx L1D_FLUSH bit.
- Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
- Add IA32_FLUSH_CMD MSR.

Revision 1.129 / (download) - annotate - [select for diffs], Tue Aug 7 10:50:12 2018 UTC (4 years, 6 months ago) by maxv
Branch: MAIN
Changes since 1.128: +12 -1 lines
Diff to previous 1.128 (colored)

Add five errata for AMD Family 17h (Ryzen etc), tested by Patrick Welche,
thanks. Also add two errata for Family 16h, not yet tested, so not yet
enabled.

Revision 1.112.2.4 / (download) - annotate - [select for diffs], Sat Jul 28 04:37:42 2018 UTC (4 years, 6 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.112.2.3: +2 -399 lines
Diff to previous 1.112.2.3 (colored) to branchpoint 1.112 (colored)

Sync with HEAD

Revision 1.98.2.6 / (download) - annotate - [select for diffs], Fri Jul 13 15:51:28 2018 UTC (4 years, 6 months ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-0-RELEASE
Changes since 1.98.2.5: +2 -1 lines
Diff to previous 1.98.2.5 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by maya in ticket #912):

	sys/arch/x86/x86/identcpu.c: revision 1.79
	sys/arch/x86/include/specialreg.h: revision 1.127

Disable MWAIT/MONITOR on Apollo Lake CPUs to workaround APL30 errata.

We use MWAIT/MONITOR to hatch secondary CPUs. The errata means that
the wakeup may not happen, so SMP boot fails.
Use wrmsr to disable it in hardware too, for extra paranoia.

PR port-amd64/53420,
also reported on netbsd-users by joern clausen and ssartor.

Revision 1.128 / (download) - annotate - [select for diffs], Fri Jul 13 09:37:32 2018 UTC (4 years, 6 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-0728
Changes since 1.127: +1 -399 lines
Diff to previous 1.127 (colored)

Remove the X86PMC code I had written, replaced by tprof. Many defines
become unused in specialreg.h, so remove them. We don't want to add
defines all the time, there are countless PMCs on many generations, and
it's better to just inline the event/unit values.

Revision 1.127 / (download) - annotate - [select for diffs], Wed Jul 4 07:55:57 2018 UTC (4 years, 7 months ago) by maya
Branch: MAIN
Changes since 1.126: +2 -1 lines
Diff to previous 1.126 (colored)

Disable MWAIT/MONITOR on Apollo Lake CPUs to workaround APL30 errata.

We use MWAIT/MONITOR to hatch secondary CPUs. The errata means that
the wakeup may not happen, so SMP boot fails.
Use wrmsr to disable it in hardware too, for extra paranoia.

PR port-amd64/53420,
also reported on netbsd-users by joern clausen and ssartor.

Revision 1.112.2.3 / (download) - annotate - [select for diffs], Mon Jun 25 07:25:47 2018 UTC (4 years, 7 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.112.2.2: +11 -6 lines
Diff to previous 1.112.2.2 (colored) to branchpoint 1.112 (colored)

Sync with HEAD

Revision 1.98.2.5 / (download) - annotate - [select for diffs], Sat Jun 9 15:12:21 2018 UTC (4 years, 8 months ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-0-RC2
Changes since 1.98.2.4: +11 -6 lines
Diff to previous 1.98.2.4 (colored) to branchpoint 1.98 (colored)

Pullup the following revisions, requested by maxv in ticket #865:

	sys/arch/amd64/amd64/machdep.c		1.303 (patch)
	sys/arch/amd64/conf/GENERIC		1.492 (patch)
	sys/arch/amd64/conf/files.amd64		1.103 (patch)
	sys/arch/i386/i386/machdep.c		1.806 (patch)
	sys/arch/i386/conf/GENERIC		1.1179 (patch)
	sys/arch/i386/conf/files.i386		1.393 (patch)
	sys/arch/x86/include/cpu.h		1.91 (patch)
	sys/arch/x86/include/specialreg.h	upto 1.126 (patch)
	sys/arch/x86/x86/x86_machdep.c		upto 1.115 (patch, adapted)
	sys/arch/x86/x86/spectre.c		upto 1.19 (patch, adapted,
						no IBRS,
						SpectreV2 mitigations not
						enabled	by default)

Backport the hardware SpectreV2 and SpectreV4 mitigations.

Revision 1.126 / (download) - annotate - [select for diffs], Thu May 31 03:29:01 2018 UTC (4 years, 8 months ago) by msaitoh
Branch: MAIN
CVS Tags: phil-wifi-base, pgoyette-compat-0625
Branch point for: phil-wifi
Changes since 1.125: +5 -4 lines
Diff to previous 1.125 (colored)

 Fix the bit location of SSBD in the macro for snprintb.

Revision 1.125 / (download) - annotate - [select for diffs], Wed May 23 07:24:37 2018 UTC (4 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.124: +3 -5 lines
Diff to previous 1.124 (colored)

Clean up the FPU headers.

Revision 1.124 / (download) - annotate - [select for diffs], Tue May 22 17:14:46 2018 UTC (4 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.123: +2 -1 lines
Diff to previous 1.123 (colored)

Extend the AMD NONARCH method to family 17h. The AMD spec states that for
17h care must be taken when handling sibling threads.

The concern is that if we have a protected two-thread process running on
two siblings, and context switch one thread to another unprotected thread,
disabling the SSB protection on one logical core will disable SSB on its
sibling too (which is still running the protected thread).

All of that doesn't matter to us, because the SSB value we set is
system-wide, not per-process.

Revision 1.123 / (download) - annotate - [select for diffs], Tue May 22 10:20:04 2018 UTC (4 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.122: +3 -1 lines
Diff to previous 1.122 (colored)

Implement a mitigation for SpectreV4 on AMD families 15h and 16h. We use
a non-architectural MSR. This MSR is also available on 17h, but there SMT
is involved, and it needs more investigation.

Not tested (I have only 10h).

Revision 1.122 / (download) - annotate - [select for diffs], Tue May 22 07:24:08 2018 UTC (4 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.121: +2 -1 lines
Diff to previous 1.121 (colored)

Add RSBA. When set, it indicates that the CPU is vulnerable to SpectreV2
via the RSB.

Revision 1.121 / (download) - annotate - [select for diffs], Tue May 22 07:11:53 2018 UTC (4 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.120: +7 -5 lines
Diff to previous 1.120 (colored)

Mitigation for SpectreV4, based on SSBD. The following sysctl branches
are added:

	machdep.spectre_v4.mitigated = {0/1} user-settable
	machdep.spectre_v4.affected = {0/1} set by the kernel

The mitigation is not enabled by default yet. It is not tested either,
because no microcode update has been published yet.

On current CPUs a microcode/bios update must be applied for SSBD to be
available. The user can then set mitigated=1. Even with an update applied
the kernel will set affected=1.

On future CPUs, where the problem will presumably be fixed by default,
the CPU will report SSB_NO, and the kernel will set affected=0. In this
case we also have mitigated=0, but the mitigation is not needed.

For now the feature is system-wide. Perhaps we will want a more
fine-grained, per-process approach in the future.

Revision 1.98.2.4 / (download) - annotate - [select for diffs], Wed Apr 18 14:14:17 2018 UTC (4 years, 9 months ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-0-RC1
Changes since 1.98.2.3: +17 -6 lines
Diff to previous 1.98.2.3 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #778):

	sys/arch/x86/include/specialreg.h: revision 1.118,1.119

 From the latest Intel SDM:
- Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
- Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.

Add Some bit definitions of AMD Fn80000001 %edx:
  - MMX
  - FXSR

Revision 1.112.2.2 / (download) - annotate - [select for diffs], Sat Apr 7 04:12:14 2018 UTC (4 years, 10 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.112.2.1: +19 -6 lines
Diff to previous 1.112.2.1 (colored) to branchpoint 1.112 (colored)

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Revision 1.98.2.3 / (download) - annotate - [select for diffs], Sat Mar 31 10:51:05 2018 UTC (4 years, 10 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.2: +7 -1 lines
Diff to previous 1.98.2.2 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by maxv in ticket #678):

	sys/arch/x86/include/specialreg.h: revision 1.115-1.117,1.120

Add IC_CFG.DIS_IND: "Disable Indirect Branch Predictor". Available (at
least) on AMD Families 10h, 12h and 16h.

Add the IBRS and STIBP MSRs.

... and also add IBPB ...

Add RDCL_NO and IBRS_ALL.

Revision 1.120 / (download) - annotate - [select for diffs], Fri Mar 30 19:49:49 2018 UTC (4 years, 10 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-0521, pgoyette-compat-0502, pgoyette-compat-0422, pgoyette-compat-0415, pgoyette-compat-0407
Changes since 1.119: +3 -1 lines
Diff to previous 1.119 (colored)

Add RDCL_NO and IBRS_ALL.

Revision 1.119 / (download) - annotate - [select for diffs], Fri Mar 30 09:30:56 2018 UTC (4 years, 10 months ago) by msaitoh
Branch: MAIN
Changes since 1.118: +8 -4 lines
Diff to previous 1.118 (colored)

Add Some bit definitions of AMD Fn80000001 %edx:
 - MMX
 - FXSR

Revision 1.118 / (download) - annotate - [select for diffs], Fri Mar 30 09:28:37 2018 UTC (4 years, 10 months ago) by msaitoh
Branch: MAIN
Changes since 1.117: +10 -3 lines
Diff to previous 1.117 (colored)

From the latest Intel SDM:
- Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
- Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.

Revision 1.98.2.2 / (download) - annotate - [select for diffs], Fri Mar 16 13:05:31 2018 UTC (4 years, 10 months ago) by martin
Branch: netbsd-8
Changes since 1.98.2.1: +84 -45 lines
Diff to previous 1.98.2.1 (colored) to branchpoint 1.98 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #633):
	sys/arch/x86/include/specialreg.h: revision 1.107
	sys/arch/x86/include/specialreg.h: revision 1.108
	sys/arch/x86/include/specialreg.h: revision 1.109
	sys/arch/x86/include/cacheinfo.h: revision 1.23
	sys/arch/x86/include/specialreg.h: revision 1.110
	sys/arch/x86/include/specialreg.h: revision 1.111
	sys/arch/x86/include/specialreg.h: revision 1.112
	sys/arch/x86/include/specialreg.h: revision 1.113
	sys/arch/x86/include/specialreg.h: revision 1.114
	usr.sbin/cpuctl/arch/i386.c: revision 1.79
	sys/arch/x86/x86/identcpu.c: revision 1.70
	sys/arch/x86/include/specialreg.h: revision 1.106

  Add comment.

  Add Intel cpuid 7 %edx IBRS(IBPB Speculation Control) and
STIBP(STIBP Speculation Control) from OpenBSD.

  Print Intel cpuid 7 %edx.

Example output of cpuctl -v identify 0:
+cpu0: 00000007: 00000000 000027ab 00000000 0c000000
(snip)
+cpu0: SEF edx 0xc000000<IBRS,STIBP>

fix swapped comments for EFER LME and LMA

- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add comment.
  Add MSR_IA32_ARCH_CAPABILITIES definition.

  Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.

Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

  Sort entries. No functional change.

s/CLFUSH/CLFLUSH/
No functional change.

Revision 1.112.2.1 / (download) - annotate - [select for diffs], Thu Mar 15 09:12:04 2018 UTC (4 years, 10 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.112: +28 -24 lines
Diff to previous 1.112 (colored)

Synch with HEAD

Revision 1.117 / (download) - annotate - [select for diffs], Wed Mar 14 15:03:16 2018 UTC (4 years, 10 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-0330, pgoyette-compat-0322, pgoyette-compat-0315
Changes since 1.116: +2 -1 lines
Diff to previous 1.116 (colored)

... and also add IBPB ...

Revision 1.116 / (download) - annotate - [select for diffs], Wed Mar 14 14:44:25 2018 UTC (4 years, 10 months ago) by maxv
Branch: MAIN
Changes since 1.115: +3 -1 lines
Diff to previous 1.115 (colored)

Add the IBRS and STIBP MSRs.

Revision 1.115 / (download) - annotate - [select for diffs], Wed Mar 14 14:15:02 2018 UTC (4 years, 10 months ago) by maxv
Branch: MAIN
Changes since 1.114: +2 -1 lines
Diff to previous 1.114 (colored)

Add IC_CFG.DIS_IND: "Disable Indirect Branch Predictor". Available (at
least) on AMD Families 10h, 12h and 16h.

Revision 1.114 / (download) - annotate - [select for diffs], Mon Mar 12 07:12:54 2018 UTC (4 years, 10 months ago) by msaitoh
Branch: MAIN
Changes since 1.113: +2 -2 lines
Diff to previous 1.113 (colored)

s/CLFUSH/CLFLUSH/
No functional change.

Revision 1.113 / (download) - annotate - [select for diffs], Thu Mar 8 04:15:11 2018 UTC (4 years, 11 months ago) by msaitoh
Branch: MAIN
Changes since 1.112: +23 -23 lines
Diff to previous 1.112 (colored)

 Sort entries. No functional change.

Revision 1.112 / (download) - annotate - [select for diffs], Mon Mar 5 05:44:07 2018 UTC (4 years, 11 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-compat-base
Branch point for: pgoyette-compat
Changes since 1.111: +31 -1 lines
Diff to previous 1.111 (colored)

Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

Revision 1.111 / (download) - annotate - [select for diffs], Mon Jan 15 08:17:20 2018 UTC (5 years ago) by msaitoh
Branch: MAIN
Changes since 1.110: +3 -1 lines
Diff to previous 1.110 (colored)

 Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.

Revision 1.110 / (download) - annotate - [select for diffs], Mon Jan 15 07:19:00 2018 UTC (5 years ago) by msaitoh
Branch: MAIN
Changes since 1.109: +2 -1 lines
Diff to previous 1.109 (colored)

 Add MSR_IA32_ARCH_CAPABILITIES definition.

Revision 1.109 / (download) - annotate - [select for diffs], Mon Jan 15 06:08:40 2018 UTC (5 years ago) by msaitoh
Branch: MAIN
Changes since 1.108: +5 -2 lines
Diff to previous 1.108 (colored)

- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add comment.

Revision 1.108 / (download) - annotate - [select for diffs], Sat Jan 13 17:55:57 2018 UTC (5 years ago) by jdolecek
Branch: MAIN
Changes since 1.107: +3 -3 lines
Diff to previous 1.107 (colored)

fix swapped comments for EFER LME and LMA

Revision 1.107 / (download) - annotate - [select for diffs], Wed Jan 10 07:04:54 2018 UTC (5 years ago) by msaitoh
Branch: MAIN
Changes since 1.106: +5 -2 lines
Diff to previous 1.106 (colored)

 Add Intel cpuid 7 %edx IBRS(IBPB Speculation Control) and
STIBP(STIBP Speculation Control) from OpenBSD.

Revision 1.106 / (download) - annotate - [select for diffs], Wed Jan 10 04:45:24 2018 UTC (5 years ago) by msaitoh
Branch: MAIN
Changes since 1.105: +41 -41 lines
Diff to previous 1.105 (colored)

 Add comment.

Revision 1.59.2.5 / (download) - annotate - [select for diffs], Sun Dec 3 11:36:50 2017 UTC (5 years, 2 months ago) by jdolecek
Branch: tls-maxphys
Changes since 1.59.2.4: +666 -432 lines
Diff to previous 1.59.2.4 (colored) to branchpoint 1.59 (colored) next main 1.60 (colored)

update from HEAD

Revision 1.98.2.1 / (download) - annotate - [select for diffs], Tue Nov 21 15:03:20 2017 UTC (5 years, 2 months ago) by martin
Branch: netbsd-8
Changes since 1.98: +47 -11 lines
Diff to previous 1.98 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #365):
	sys/arch/x86/include/specialreg.h: revision 1.99
	usr.sbin/cpuctl/arch/i386.c: revision 1.75
	usr.sbin/cpuctl/arch/i386.c: revision 1.76
	usr.sbin/cpuctl/arch/i386.c: revision 1.77
	usr.sbin/cpuctl/arch/i386.c: revision 1.78
	sys/arch/x86/x86/identcpu.c: revision 1.56
	sys/arch/x86/x86/identcpu.c: revision 1.57
	sys/arch/x86/x86/cpu_topology.c: revision 1.10
	sys/arch/x86/include/specialreg.h: revision 1.100
	sys/arch/x86/include/specialreg.h: revision 1.101
	sys/arch/x86/include/specialreg.h: revision 1.102
	sys/arch/x86/include/specialreg.h: revision 1.103
	sys/arch/x86/include/specialreg.h: revision 1.104
	sys/arch/x86/include/specialreg.h: revision 1.105
Add EFER_TCE. This would be an interesting feature to have, since it
reduces the indirect cost of invlpg; but I'm not convinced the way we
flush upper-levels is correct for this yet.
Fix typo in comment
Add a comment about APICBASE_PHYSADDR. Has to do with PR/42597.
  Define CPUID Fn00000001 %ebx bits and use them. No functional change.
Set ci->ci_cflush_lsize correctly. This bug was added in the last commit(1.56).
  Add the following instruction bits in Structured Extended Flags Enumeration
Leaf from "Intel Architecture Instruction Set Extensions and Future Features
Programming Reference" (319433-030):
	AVX512_IFMA
	AVX512_VBMI
	AVX512_VBMI2
	GFNI
	VAES
	VPCLMULQDQ
	AVX512_VNNI
	AVX512_BITALG
	AVX512_VPOPCNTDQ
	AVX512_4VNNIW
	AVX512_4FMAPS
- Print ci_feat_val[5] (Structured Extended Feature leaf Fn0000_0007 %ebx) on
   AMD, too.
- Print ci_feat_val[6] (Fn0000_0007 %ecx) on Intel.
Update from the latest Intel SDM:
  0x5c: Atom (Goldmont)
  0x5f: Atom (Goldmont, Denverton)
  0x7a: Atom (Goldmont Plus)
  Add Turbo Boost Max Technology 3.0 bit.
Update from Intel SDM:
  0x55: Xeon Scalable (Skylake)
  0x57: Xeon Phi [357]200 (Knights Landing)
  0x66: Future Core (Cannon Lake)
  0x85: Future Xeon Phi (Knights Mill)
  Add the following bits in AMD Fn8000000a %edx features (SVM features):
	PFThreshold (PAUSE filter threshold)
	AVIC (AMD virtual interrupt controller)
	V_VMSAVE_VMLOAD (virtualized VMSAVE and VMLOAD)
	vGIF (virtualized GIF)

Revision 1.105 / (download) - annotate - [select for diffs], Thu Oct 19 06:29:16 2017 UTC (5 years, 3 months ago) by msaitoh
Branch: MAIN
CVS Tags: tls-maxphys-base-20171202
Changes since 1.104: +11 -6 lines
Diff to previous 1.104 (colored)

 Add the following bits in AMD Fn8000000a %edx features (SVM features):
	PFThreshold (PAUSE filter threshold)
	AVIC (AMD virtual interrupt controller)
	V_VMSAVE_VMLOAD (virtualized VMSAVE and VMLOAD)
	vGIF (virtualized GIF)

Revision 1.104 / (download) - annotate - [select for diffs], Wed Oct 18 03:38:32 2017 UTC (5 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.103: +3 -2 lines
Diff to previous 1.103 (colored)

 Add Turbo Boost Max Technology 3.0 bit.

Revision 1.103 / (download) - annotate - [select for diffs], Fri Oct 13 13:53:54 2017 UTC (5 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.102: +22 -4 lines
Diff to previous 1.102 (colored)

 Add the following instruction bits in Structured Extended Flags Enumeration
Leaf from "Intel Architecture Instruction Set Extensions and Future Features
Programming Reference" (319433-030):
	AVX512_IFMA
	AVX512_VBMI
	AVX512_VBMI2
	GFNI
	VAES
	VPCLMULQDQ
	AVX512_VNNI
	AVX512_BITALG
	AVX512_VPOPCNTDQ
	AVX512_4VNNIW
	AVX512_4FMAPS

Revision 1.102 / (download) - annotate - [select for diffs], Thu Sep 7 06:40:42 2017 UTC (5 years, 5 months ago) by msaitoh
Branch: MAIN
Changes since 1.101: +7 -1 lines
Diff to previous 1.101 (colored)

 Define CPUID Fn00000001 %ebx bits and use them. No functional change.

Revision 1.80.2.8 / (download) - annotate - [select for diffs], Mon Aug 28 17:51:56 2017 UTC (5 years, 5 months ago) by skrll
Branch: nick-nhusb
Changes since 1.80.2.7: +227 -72 lines
Diff to previous 1.80.2.7 (colored) to branchpoint 1.80 (colored) next main 1.81 (colored)

Sync with HEAD

Revision 1.101 / (download) - annotate - [select for diffs], Fri Aug 11 06:27:12 2017 UTC (5 years, 5 months ago) by maxv
Branch: MAIN
CVS Tags: nick-nhusb-base-20170825
Changes since 1.100: +6 -1 lines
Diff to previous 1.100 (colored)

Add a comment about APICBASE_PHYSADDR. Has to do with PR/42597.

Revision 1.100 / (download) - annotate - [select for diffs], Tue Jul 11 14:00:15 2017 UTC (5 years, 6 months ago) by gson
Branch: MAIN
CVS Tags: perseant-stdc-iso10646-base, perseant-stdc-iso10646
Changes since 1.99: +2 -2 lines
Diff to previous 1.99 (colored)

Fix typo in comment

Revision 1.99 / (download) - annotate - [select for diffs], Wed Jun 14 08:45:42 2017 UTC (5 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.98: +2 -1 lines
Diff to previous 1.98 (colored)

Add EFER_TCE. This would be an interesting feature to have, since it
reduces the indirect cost of invlpg; but I'm not convinced the way we
flush upper-levels is correct for this yet.

Revision 1.97.2.1 / (download) - annotate - [select for diffs], Fri May 19 00:22:56 2017 UTC (5 years, 8 months ago) by pgoyette
Branch: prg-localcount2
Changes since 1.97: +3 -3 lines
Diff to previous 1.97 (colored) next main 1.98 (colored)

Resolve conflicts from previous merge (all resulting from $NetBSD
keywork expansion)

Revision 1.98 / (download) - annotate - [select for diffs], Mon May 15 04:02:52 2017 UTC (5 years, 8 months ago) by msaitoh
Branch: MAIN
CVS Tags: prg-localcount2-base3, netbsd-8-base, matt-nb8-mediatek-base, matt-nb8-mediatek
Branch point for: netbsd-8
Changes since 1.97: +3 -3 lines
Diff to previous 1.97 (colored)

 CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify comments
and snprintb() sring.

Revision 1.87.2.4 / (download) - annotate - [select for diffs], Wed Apr 26 02:53:09 2017 UTC (5 years, 9 months ago) by pgoyette
Branch: pgoyette-localcount
Changes since 1.87.2.3: +29 -1 lines
Diff to previous 1.87.2.3 (colored) to branchpoint 1.87 (colored) next main 1.88 (colored)

Sync with HEAD

Revision 1.97 / (download) - annotate - [select for diffs], Sat Apr 22 04:24:25 2017 UTC (5 years, 9 months ago) by nonaka
Branch: MAIN
CVS Tags: prg-localcount2-base2, prg-localcount2-base1, prg-localcount2-base, pgoyette-localcount-20170426
Branch point for: prg-localcount2
Changes since 1.96: +5 -1 lines
Diff to previous 1.96 (colored)

move LAPIC_MSR* to specialreg.h.

Revision 1.96 / (download) - annotate - [select for diffs], Sat Apr 22 04:23:17 2017 UTC (5 years, 9 months ago) by nonaka
Branch: MAIN
Changes since 1.95: +25 -1 lines
Diff to previous 1.95 (colored)

Add x2APIC register definitions.

Revision 1.91.2.1 / (download) - annotate - [select for diffs], Fri Apr 21 16:53:39 2017 UTC (5 years, 9 months ago) by bouyer
Branch: bouyer-socketcan
Changes since 1.91: +191 -70 lines
Diff to previous 1.91 (colored) next main 1.92 (colored)

Sync with HEAD

Revision 1.87.2.3 / (download) - annotate - [select for diffs], Mon Mar 20 06:57:22 2017 UTC (5 years, 10 months ago) by pgoyette
Branch: pgoyette-localcount
Changes since 1.87.2.2: +218 -97 lines
Diff to previous 1.87.2.2 (colored) to branchpoint 1.87 (colored)

Sync with HEAD

Revision 1.95 / (download) - annotate - [select for diffs], Sat Mar 11 10:33:46 2017 UTC (5 years, 11 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-localcount-20170320, jdolecek-ncq-base, jdolecek-ncq, bouyer-socketcan-base1
Changes since 1.94: +30 -73 lines
Diff to previous 1.94 (colored)

Add the AMD 10h family, with additional events that I believe are useful,
the DTLB misses on large pages for example.

While here, remove a few K7 flags that do not actually exist on K7 (there
must have been a confusion between K7 and K8); and make the 'pmc list'
command a little more user-friendly.

Revision 1.94 / (download) - annotate - [select for diffs], Sat Feb 18 16:15:51 2017 UTC (5 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.93: +163 -2 lines
Diff to previous 1.93 (colored)

Add the AMD 10h family PMC values. Some values depend on the CPU revision,
they are commented out. Several other values are common with K7, we could
merge them later.

This family of CPUs has a 12bit event selector, contrary to K7 (8bit). The
thing is, i386's PMC interface takes as argument a uint8_t from userland,
so these counters are not accessible (yet).

Revision 1.93 / (download) - annotate - [select for diffs], Sat Feb 11 15:11:45 2017 UTC (5 years, 11 months ago) by maxv
Branch: MAIN
Changes since 1.92: +17 -14 lines
Diff to previous 1.92 (colored)

Fix a few (unused) MSR values, and add some others that I believe are
relevant.

From Murray Armfield (PR/42861).

Revision 1.80.2.7 / (download) - annotate - [select for diffs], Sun Feb 5 13:40:23 2017 UTC (6 years ago) by skrll
Branch: nick-nhusb
Changes since 1.80.2.6: +6 -5 lines
Diff to previous 1.80.2.6 (colored) to branchpoint 1.80 (colored)

Sync with HEAD

Revision 1.92 / (download) - annotate - [select for diffs], Thu Feb 2 05:43:48 2017 UTC (6 years ago) by msaitoh
Branch: MAIN
CVS Tags: nick-nhusb-base-20170204
Changes since 1.91: +2 -2 lines
Diff to previous 1.91 (colored)

 Modify comment. Use long form.

Revision 1.78.4.4.2.1 / (download) - annotate - [select for diffs], Wed Jan 18 08:46:26 2017 UTC (6 years ago) by skrll
Branch: netbsd-7-nhusb
Changes since 1.78.4.4: +17 -8 lines
Diff to previous 1.78.4.4 (colored) next main 1.78.4.5 (colored)

Sync with netbsd-5

Revision 1.87.2.2 / (download) - annotate - [select for diffs], Sat Jan 7 08:56:28 2017 UTC (6 years, 1 month ago) by pgoyette
Branch: pgoyette-localcount
Changes since 1.87.2.1: +5 -4 lines
Diff to previous 1.87.2.1 (colored) to branchpoint 1.87 (colored)

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

Revision 1.91 / (download) - annotate - [select for diffs], Thu Dec 8 06:11:03 2016 UTC (6 years, 2 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-localcount-20170107, bouyer-socketcan-base
Branch point for: bouyer-socketcan
Changes since 1.90: +3 -2 lines
Diff to previous 1.90 (colored)

Add CLWB bit.

Revision 1.78.4.5 / (download) - annotate - [select for diffs], Thu Dec 8 00:15:25 2016 UTC (6 years, 2 months ago) by snj
Branch: netbsd-7
CVS Tags: netbsd-7-nhusb-base-20170116, netbsd-7-2-RELEASE, netbsd-7-1-RELEASE, netbsd-7-1-RC2, netbsd-7-1-RC1, netbsd-7-1-2-RELEASE, netbsd-7-1-1-RELEASE, netbsd-7-1
Changes since 1.78.4.4: +17 -8 lines
Diff to previous 1.78.4.4 (colored) to branchpoint 1.78 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1285):
	sys/arch/x86/include/cacheinfo.h: revision 1.22
	sys/arch/x86/include/specialreg.h: revisions 1.87 and 1.90
	usr.sbin/cpuctl/arch/i386.c: revisions 1.72-1.74
Changes for x86's cpuctl(8):
- Add Quark X1000, Xeon E[57] v4, Core i7-69xx Extreme, 7th gen Core,
  Denverton, Xeon Phi [357]200, Future Xeon and Future Xeon Phi.
- Add SGX, UMIP, RDPID, SGXLC, AVX512DQ, AVX512BW and AVX512VL bit.
- Fix the bit location of CLFLUSHOPT.
- Add new TLB descriptor 0x64 and 0xc4.

Revision 1.90 / (download) - annotate - [select for diffs], Mon Dec 5 03:59:47 2016 UTC (6 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.89: +3 -3 lines
Diff to previous 1.89 (colored)

Fix CPUID_SEF_FLAGS. Octal value has no 8.

Revision 1.80.2.6 / (download) - annotate - [select for diffs], Wed Oct 5 20:55:36 2016 UTC (6 years, 4 months ago) by skrll
Branch: nick-nhusb
Changes since 1.80.2.5: +386 -384 lines
Diff to previous 1.80.2.5 (colored) to branchpoint 1.80 (colored)

Sync with HEAD

Revision 1.89 / (download) - annotate - [select for diffs], Fri Aug 19 18:53:29 2016 UTC (6 years, 5 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-localcount-20161104, nick-nhusb-base-20161204, nick-nhusb-base-20161004, localcount-20160914
Changes since 1.88: +385 -385 lines
Diff to previous 1.88 (colored)

KNF so NXR likes it, and some typos

Revision 1.87.2.1 / (download) - annotate - [select for diffs], Tue Jul 26 03:24:19 2016 UTC (6 years, 6 months ago) by pgoyette
Branch: pgoyette-localcount
Changes since 1.87: +3 -1 lines
Diff to previous 1.87 (colored)

Sync with HEAD

Revision 1.88 / (download) - annotate - [select for diffs], Sat Jul 16 13:47:01 2016 UTC (6 years, 6 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-localcount-20160806, pgoyette-localcount-20160726
Changes since 1.87: +3 -1 lines
Diff to previous 1.87 (colored)

Add the cr4 flags for PKE and UMIP.

Revision 1.80.2.5 / (download) - annotate - [select for diffs], Sun May 29 08:44:19 2016 UTC (6 years, 8 months ago) by skrll
Branch: nick-nhusb
Changes since 1.80.2.4: +17 -8 lines
Diff to previous 1.80.2.4 (colored) to branchpoint 1.80 (colored)

Sync with HEAD

Revision 1.87 / (download) - annotate - [select for diffs], Wed Apr 27 08:51:32 2016 UTC (6 years, 9 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-localcount-base, nick-nhusb-base-20160907, nick-nhusb-base-20160529
Branch point for: pgoyette-localcount
Changes since 1.86: +17 -8 lines
Diff to previous 1.86 (colored)

Add some bit definitions mainly taken from the latest Intel SDM:
 - Add SGX, UMIP, RDPID and SGXLC.
 - Add avx512dq, avx512bw and avx512vl.
Fix the bit location of CLFLUSHOPT.

Revision 1.80.2.4 / (download) - annotate - [select for diffs], Sat Mar 19 11:30:07 2016 UTC (6 years, 10 months ago) by skrll
Branch: nick-nhusb
Changes since 1.80.2.3: +11 -6 lines
Diff to previous 1.80.2.3 (colored) to branchpoint 1.80 (colored)

Sync with HEAD

Revision 1.78.4.4 / (download) - annotate - [select for diffs], Sun Mar 6 17:49:55 2016 UTC (6 years, 11 months ago) by martin
Branch: netbsd-7
CVS Tags: netbsd-7-nhusb-base
Branch point for: netbsd-7-nhusb
Changes since 1.78.4.3: +27 -14 lines
Diff to previous 1.78.4.3 (colored) to branchpoint 1.78 (colored)

Pull up the following changes, requested by msaitoh in #1117:

	sys/arch/x86/include/cacheinfo.h		1.20-1.21
	sys/arch/x86/include/specialreg.h		1.83-1.86
	usr.sbin/cpuctl/arch/i386.c			1.67-1.70

Changes for x86's cpuctl(8):
- Add some TLB information (index 0x6a-0x6d).
- Add Hardware-Controlled Performance States (HWP) bits, FPU Data
  Pointer Updated Only bit and CLFLUSHOPT bit.
- Add some AMD's bit definitions from "BIOS and Kernel Developer(BKDG)
  for AMD Family 15h Models 60h-6Fh Processors".
- Add Xeon E5-4600 v3,
- Add Xeon E3-1200 v4 and v5.
- Add 6th gen Core, Xeon E3-1500 v5 and Xeon D-1500.
- Change CPU family 0x1c from "Atom Family" to "45nm Atom Family"

Revision 1.86 / (download) - annotate - [select for diffs], Wed Jan 13 07:19:29 2016 UTC (7 years ago) by msaitoh
Branch: MAIN
CVS Tags: nick-nhusb-base-20160422, nick-nhusb-base-20160319
Changes since 1.85: +6 -3 lines
Diff to previous 1.85 (colored)

 Add some AMD's bit definitions from "BIOS and Kernel Developer(BKDG) for AMD
Family 15h Models 60h-6Fh Processors".

Revision 1.85 / (download) - annotate - [select for diffs], Fri Jan 8 03:26:35 2016 UTC (7 years, 1 month ago) by msaitoh
Branch: MAIN
Changes since 1.84: +4 -3 lines
Diff to previous 1.84 (colored)

 Add CLFLUSHOPT bit.

Revision 1.84 / (download) - annotate - [select for diffs], Fri Jan 8 02:27:07 2016 UTC (7 years, 1 month ago) by msaitoh
Branch: MAIN
Changes since 1.83: +3 -2 lines
Diff to previous 1.83 (colored)

 Add x86 FPU Data Pointer Updated Only bit from Intel SDM.

Revision 1.80.2.3 / (download) - annotate - [select for diffs], Tue Sep 22 12:05:54 2015 UTC (7 years, 4 months ago) by skrll
Branch: nick-nhusb
Changes since 1.80.2.2: +17 -9 lines
Diff to previous 1.80.2.2 (colored) to branchpoint 1.80 (colored)

Sync with HEAD

Revision 1.83 / (download) - annotate - [select for diffs], Fri Aug 14 06:54:22 2015 UTC (7 years, 5 months ago) by msaitoh
Branch: MAIN
CVS Tags: nick-nhusb-base-20151226, nick-nhusb-base-20150921
Changes since 1.82: +17 -9 lines
Diff to previous 1.82 (colored)

 - Add Hardware-Controlled Performance States (HWP) bits.
 - Use __BIT()

Revision 1.80.2.2 / (download) - annotate - [select for diffs], Sat Jun 6 14:40:04 2015 UTC (7 years, 8 months ago) by skrll
Branch: nick-nhusb
Changes since 1.80.2.1: +26 -8 lines
Diff to previous 1.80.2.1 (colored) to branchpoint 1.80 (colored)

Sync with HEAD

Revision 1.31.4.1.2.1 / (download) - annotate - [select for diffs], Mon Jun 1 15:49:47 2015 UTC (7 years, 8 months ago) by sborrill
Branch: netbsd-5-1
Changes since 1.31.4.1: +34 -8 lines
Diff to previous 1.31.4.1 (colored) next main 1.31.4.2 (colored)

Pull up the following revisions(s) (requested by msaitoh in ticket #1968):
	sys/arch/x86/include/specialreg.h: revision 1.72 via patch

Backup CPUID_TO_*() macros. Old macros are kept for compatibility.

Revision 1.31.4.2.2.1 / (download) - annotate - [select for diffs], Mon Jun 1 15:49:16 2015 UTC (7 years, 8 months ago) by sborrill
Branch: netbsd-5-2
Changes since 1.31.4.2: +34 -8 lines
Diff to previous 1.31.4.2 (colored) next main 1.31.4.3 (colored)

Pull up the following revisions(s) (requested by msaitoh in ticket #1968):
	sys/arch/x86/include/specialreg.h: revision 1.72 via patch

Backup CPUID_TO_*() macros. Old macros are kept for compatibility.

Revision 1.31.4.4 / (download) - annotate - [select for diffs], Mon Jun 1 15:45:46 2015 UTC (7 years, 8 months ago) by sborrill
Branch: netbsd-5
Changes since 1.31.4.3: +34 -8 lines
Diff to previous 1.31.4.3 (colored) to branchpoint 1.31 (colored) next main 1.32 (colored)

Pull up the following revisions(s) (requested by msaitoh in ticket #1968):
	sys/arch/x86/include/specialreg.h: revision 1.72 via patch

Backport CPUID_TO_*() macros. Old macros are kept for compatibility.

Revision 1.78.4.3 / (download) - annotate - [select for diffs], Sat May 9 08:35:10 2015 UTC (7 years, 9 months ago) by snj
Branch: netbsd-7
CVS Tags: netbsd-7-0-RELEASE, netbsd-7-0-RC3, netbsd-7-0-RC2, netbsd-7-0-RC1, netbsd-7-0-2-RELEASE, netbsd-7-0-1-RELEASE, netbsd-7-0
Changes since 1.78.4.2: +25 -7 lines
Diff to previous 1.78.4.2 (colored) to branchpoint 1.78 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #739):
	sys/arch/x86/include/specialreg.h: revision 1.82
	usr.sbin/cpuctl/arch/i386.c: revision 1.66
From Intel SDM:
- Add the Silicon Debug bit in CPUID Fn00000001 %ecx
- Add CPUID Fn0000_0007 %ecx bits
- Add comments.
--
Update some Intel CPU models (Sky Lake, Broadwell and Atom X[357]).

Revision 1.82 / (download) - annotate - [select for diffs], Fri May 8 07:23:56 2015 UTC (7 years, 9 months ago) by msaitoh
Branch: MAIN
CVS Tags: nick-nhusb-base-20150606
Changes since 1.81: +25 -7 lines
Diff to previous 1.81 (colored)

From Intel SDM:
- Add the Silicon Debug bit in CPUID Fn00000001 %ecx
- Add CPUID Fn0000_0007 %ecx bits
- Add comments.

Revision 1.80.2.1 / (download) - annotate - [select for diffs], Mon Apr 6 15:18:04 2015 UTC (7 years, 10 months ago) by skrll
Branch: nick-nhusb
Changes since 1.80: +2 -1 lines
Diff to previous 1.80 (colored)

Sync with HEAD

Revision 1.55.2.5 / (download) - annotate - [select for diffs], Mon Jan 26 13:58:05 2015 UTC (8 years ago) by martin
Branch: netbsd-6
Changes since 1.55.2.4: +28 -8 lines
Diff to previous 1.55.2.4 (colored) to branchpoint 1.55 (colored) next main 1.56 (colored)

Pull up the following, requested by msaitoh in ticket #1240:

	sys/arch/x86/include/specialreg.h			1.72 via patch

Add CPUID_TO_*() macros to avoid bug. Old macros are kept for compatibility.
See http://mail-index.netbsd.org/port-amd64/2013/11/12/msg001978.html

Revision 1.78.4.2 / (download) - annotate - [select for diffs], Fri Jan 9 10:33:07 2015 UTC (8 years, 1 month ago) by martin
Branch: netbsd-7
Changes since 1.78.4.1: +2 -1 lines
Diff to previous 1.78.4.1 (colored) to branchpoint 1.78 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #396):
	sys/arch/x86/x86/cpu_ucode_intel.c: revision 1.6
	sys/arch/x86/include/specialreg.h: revision 1.81
Use specialreg.h's definitions.

Revision 1.55.2.4 / (download) - annotate - [select for diffs], Mon Dec 29 15:31:06 2014 UTC (8 years, 1 month ago) by martin
Branch: netbsd-6
Changes since 1.55.2.3: +286 -111 lines
Diff to previous 1.55.2.3 (colored) to branchpoint 1.55 (colored)

Pull up the following revisisions, requested by msaitoh in #1220:

sys/arch/x86/include/specialreg.h		1.59-1.71, 1.73-1.81 (patch)

	Update x86 special register definitions:
	- Add latest CR4 bits.
	- Recognize the P1GB and RDTSCP which were AMD-only on Intel HW too.
	- Add some missing bit definitions for CPUID2 and those for XCR0.
	- Fix CPUID_AMD_FLAGS4 to not try to print bits \41 and \42.
	- Correct the comment about the extended family and model bits.
	- Add some definitions related to the process extended state
	  enumeration.
	- Add Intel Structured Extended Feature leaf (Fn0000_0007).
	- Sort CPUID definitions in initial EAX value.
	- Add Intel Deterministic Cache Parameter Leaf (CPUID leaf 4).
	- Add some AMD Fn80000001 extended features %ecx bits definitions.
	- "s/MXX/MMXX/" because this bit is "MMX eXtention".
	- Add some definitions for cpu 'extended state' enumeration
	  (Fn0000000d).
	- Add Energy Performance Bias bit of Fn0000_0006 %ecx.
	- Add MSR_IA32_PLATFORM_ID (0x017)
	- Modify comment.
	- Style fix.

Revision 1.78.4.1 / (download) - annotate - [select for diffs], Fri Dec 12 16:44:35 2014 UTC (8 years, 1 month ago) by martin
Branch: netbsd-7
Changes since 1.78: +8 -3 lines
Diff to previous 1.78 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #310):
	sys/arch/x86/include/specialreg.h: revision 1.79-1.80
	usr.sbin/cpuctl/arch/i386.c: revision 1.59
	sys/arch/x86/include/cacheinfo.h: revision 1.19

Update some cpuid related values:
- Add XSAVECC, XGETBV, XSAVES, SMAP and PQE
- Change XINUSE to XGETBV
- Add new cache descripter value (0xc3)
- Update signatures for the follwing CPUs:
  - Core M-5xxx
  - Core i7 Extreme
  - Future Core (0x4e)
  - Future Xeon (0x56)

Revision 1.81 / (download) - annotate - [select for diffs], Fri Dec 12 02:25:55 2014 UTC (8 years, 1 month ago) by msaitoh
Branch: MAIN
CVS Tags: nick-nhusb-base-20150406
Changes since 1.80: +2 -1 lines
Diff to previous 1.80 (colored)

Use specialreg.h's definitions.

Revision 1.80 / (download) - annotate - [select for diffs], Thu Sep 11 18:11:59 2014 UTC (8 years, 4 months ago) by msaitoh
Branch: MAIN
CVS Tags: nick-nhusb-base
Branch point for: nick-nhusb
Changes since 1.79: +5 -3 lines
Diff to previous 1.79 (colored)

- Add two more bit definitions
- XINUSE -> XGETBV

Revision 1.79 / (download) - annotate - [select for diffs], Tue Sep 9 15:09:16 2014 UTC (8 years, 5 months ago) by msaitoh
Branch: MAIN
Changes since 1.78: +5 -2 lines
Diff to previous 1.78 (colored)

Update CPUID(EAX=0x0d, ECX=1) from Intel SDM:
- XSAVEC(bit1)
- XGETBV(bit2)
- XSAVES(bit3)

Revision 1.59.2.4 / (download) - annotate - [select for diffs], Wed Aug 20 00:03:29 2014 UTC (8 years, 5 months ago) by tls
Branch: tls-maxphys
Changes since 1.59.2.3: +214 -139 lines
Diff to previous 1.59.2.3 (colored) to branchpoint 1.59 (colored)

Rebase to HEAD as of a few days ago.

Revision 1.53.2.5 / (download) - annotate - [select for diffs], Thu May 22 11:40:13 2014 UTC (8 years, 8 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.53.2.4: +234 -128 lines
Diff to previous 1.53.2.4 (colored) to branchpoint 1.53 (colored) next main 1.54 (colored)

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

Revision 1.63.6.2 / (download) - annotate - [select for diffs], Sun May 18 17:45:30 2014 UTC (8 years, 8 months ago) by rmind
Branch: rmind-smpnet
Changes since 1.63.6.1: +197 -128 lines
Diff to previous 1.63.6.1 (colored) to branchpoint 1.63 (colored) next main 1.64 (colored)

sync with head

Revision 1.78 / (download) - annotate - [select for diffs], Tue Feb 25 22:11:11 2014 UTC (8 years, 11 months ago) by dsl
Branch: MAIN
CVS Tags: yamt-pagecache-base9, tls-maxphys-base, tls-earlyentropy-base, tls-earlyentropy, rmind-smpnet-nbase, rmind-smpnet-base, riastradh-xf86-video-intel-2-7-1-pre-2-21-15, riastradh-drm2-base3, netbsd-7-base
Branch point for: netbsd-7
Changes since 1.77: +21 -3 lines
Diff to previous 1.77 (colored)

Add the XCR bits for snazzy upcoming features.
Define a mask for the fpu releated ones - only these wll be enabled.
The memory bound ones will need saving on every context switch.

Revision 1.77 / (download) - annotate - [select for diffs], Sat Jan 4 21:09:39 2014 UTC (9 years, 1 month ago) by msaitoh
Branch: MAIN
Changes since 1.76: +3 -2 lines
Diff to previous 1.76 (colored)

Add Energy Performance Bias bit.

Revision 1.76 / (download) - annotate - [select for diffs], Sat Jan 4 19:08:43 2014 UTC (9 years, 1 month ago) by msaitoh
Branch: MAIN
Changes since 1.75: +6 -39 lines
Diff to previous 1.75 (colored)

Remove duplicated entry. Modify comments a bit.

Revision 1.75 / (download) - annotate - [select for diffs], Wed Dec 25 13:14:36 2013 UTC (9 years, 1 month ago) by msaitoh
Branch: MAIN
Changes since 1.74: +11 -11 lines
Diff to previous 1.74 (colored)

move XCR0 definitions to next to CR0's.

Revision 1.74 / (download) - annotate - [select for diffs], Sun Dec 8 18:00:51 2013 UTC (9 years, 2 months ago) by dsl
Branch: MAIN
Changes since 1.73: +34 -1 lines
Diff to previous 1.73 (colored)

Add some definitions for cpu 'extended state'.
These are needed for support of the AVX SIMD instructions.
Nothing yet uses them.

Revision 1.73 / (download) - annotate - [select for diffs], Wed Nov 20 17:50:39 2013 UTC (9 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.72: +9 -4 lines
Diff to previous 1.72 (colored)

-  Add some AMD Fn80000001 extended features %ecx bits definitions from
  the document (AMD64 Architecture ProgrammerVolume 3: General-Purpose and
  System Instructions. Document revision 3.20)

-  "s/MXX/MMXX/" because this bit is "MMX eXtention".

Revision 1.72 / (download) - annotate - [select for diffs], Fri Nov 15 08:47:55 2013 UTC (9 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.71: +19 -8 lines
Diff to previous 1.71 (colored)

 Modify some macros and add some new macros for CPU family and model
to reduce code duplication and to avoid bug.

CPUID_TO_STEPPING(cpuid)	(not changed)

CPUID_TO_FAMILY(cpuid)		(new)
CPUID_TO_MODEL(cpuid)		(new)

	Return the display family and the display model.
	The macro names are the same as FreeBSD.

CPUID_TO_BASEFAMILY(cpuid)	(The old name was CPUID2FAMILY)
CPUID_TO_BASEMODEL(cpuid)	(The old name was CPUID2MODEL)

	Only for the base field.

CPUID_TO_EXTFAMILY(cpuid)	(The old name was CPUID2EXTFAMILY)
CPUID_TO_EXTMODEL(cpuid)	(The old name was CPUID2EXTMODEL)

	Only for the extended field.

See http://mail-index.netbsd.org/port-amd64/2013/11/12/msg001978.html

Revision 1.71 / (download) - annotate - [select for diffs], Mon Oct 21 06:11:49 2013 UTC (9 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.70: +31 -2 lines
Diff to previous 1.70 (colored)

- Add Intel Deterministic Cache Parameter Leaf (CPUID leaf 4).
  This definitions are required to know cache information of
  newer Intel CPU.
- Fix comment.

Revision 1.70 / (download) - annotate - [select for diffs], Fri Oct 4 17:53:19 2013 UTC (9 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.69: +122 -122 lines
Diff to previous 1.69 (colored)

Sort definitions. No functional change.
- CPUID_FEAT_BLACKLIST is for Fn00000001 %edx, so move it.
- Sort CPUID definitions with initial EAX value.

Revision 1.69 / (download) - annotate - [select for diffs], Fri Oct 4 17:21:43 2013 UTC (9 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.68: +3 -1 lines
Diff to previous 1.68 (colored)

Add comment about CPUID Processor extended state Enumeration Fn0000000d %eax.

Revision 1.68 / (download) - annotate - [select for diffs], Sat Sep 14 17:18:18 2013 UTC (9 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.67: +7 -4 lines
Diff to previous 1.67 (colored)

Add some definitions of Intel's cpuid feature from the latest document.

Revision 1.63.6.1 / (download) - annotate - [select for diffs], Wed Aug 28 23:59:24 2013 UTC (9 years, 5 months ago) by rmind
Branch: rmind-smpnet
Changes since 1.63: +19 -13 lines
Diff to previous 1.63 (colored)

sync with head

Revision 1.67 / (download) - annotate - [select for diffs], Mon Aug 12 18:16:19 2013 UTC (9 years, 5 months ago) by drochner
Branch: MAIN
Changes since 1.66: +13 -4 lines
Diff to previous 1.66 (colored)

add feature flag definitions for the last round of Intel instruction
set extensions (AVX512 et al.)

Revision 1.66 / (download) - annotate - [select for diffs], Fri Jul 26 05:46:19 2013 UTC (9 years, 6 months ago) by msaitoh
Branch: MAIN
Changes since 1.65: +6 -15 lines
Diff to previous 1.65 (colored)

Style change.

Revision 1.65 / (download) - annotate - [select for diffs], Thu Jul 25 16:34:29 2013 UTC (9 years, 6 months ago) by msaitoh
Branch: MAIN
Changes since 1.64: +6 -0 lines
Diff to previous 1.64 (colored)

 Add some new bit definitions of Structured Extended Feature Flags Enumeration
Leaf from the document (Intel 64 and IA-32 Architectures Software Developer's
Manual).

Revision 1.64 / (download) - annotate - [select for diffs], Thu Jul 25 16:31:33 2013 UTC (9 years, 6 months ago) by msaitoh
Branch: MAIN
Changes since 1.63: +12 -12 lines
Diff to previous 1.63 (colored)

 Fix the bit positions in CPUID_SEF_FLAGS macro. On snprintb(), position 1
means LSB(bit0). The bit position from HLE to SMAP was 1 bit right shifted.
The bit position of BMI1 was completely wrong.

Revision 1.59.2.3 / (download) - annotate - [select for diffs], Sun Jun 23 06:20:14 2013 UTC (9 years, 7 months ago) by tls
Branch: tls-maxphys
Changes since 1.59.2.2: +32 -1 lines
Diff to previous 1.59.2.2 (colored) to branchpoint 1.59 (colored)

resync from head

Revision 1.31.4.3 / (download) - annotate - [select for diffs], Wed Jun 19 07:44:42 2013 UTC (9 years, 7 months ago) by bouyer
Branch: netbsd-5
Changes since 1.31.4.2: +17 -1 lines
Diff to previous 1.31.4.2 (colored) to branchpoint 1.31 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1847):
	sys/arch/x86/include/mtrr.h: revision 1.5
	sys/arch/x86/x86/mtrr_i686.c: revision 1.25
	sys/arch/x86/include/specialreg.h: revision 1.55
Increase MTRR_I686_NVAR_MAX from 8 to 16. Avoids
"FIXME: more than 8 MTRRs (10)" message on booting Thinkpad W520 and
similar. While here replace a magic number with MTRR_I686_NVAR_MAX * 2

Revision 1.63 / (download) - annotate - [select for diffs], Wed Mar 6 11:51:40 2013 UTC (9 years, 11 months ago) by yamt
Branch: MAIN
CVS Tags: riastradh-drm2-base2, riastradh-drm2-base1, riastradh-drm2-base, riastradh-drm2, khorben-n900, agc-symver-base, agc-symver
Branch point for: rmind-smpnet
Changes since 1.62: +32 -1 lines
Diff to previous 1.62 (colored)

some more definitions

Revision 1.59.2.2 / (download) - annotate - [select for diffs], Mon Feb 25 00:29:04 2013 UTC (9 years, 11 months ago) by tls
Branch: tls-maxphys
Changes since 1.59.2.1: +102 -37 lines
Diff to previous 1.59.2.1 (colored) to branchpoint 1.59 (colored)

resync with head

Revision 1.53.2.4 / (download) - annotate - [select for diffs], Wed Jan 23 00:06:00 2013 UTC (10 years ago) by yamt
Branch: yamt-pagecache
CVS Tags: yamt-pagecache-tag8
Changes since 1.53.2.3: +102 -37 lines
Diff to previous 1.53.2.3 (colored) to branchpoint 1.53 (colored)

sync with head

Revision 1.62 / (download) - annotate - [select for diffs], Sun Jan 6 22:37:36 2013 UTC (10 years, 1 month ago) by dsl
Branch: MAIN
CVS Tags: yamt-pagecache-base8
Changes since 1.61: +30 -2 lines
Diff to previous 1.61 (colored)

Correct the comment about the extended family and model bits.
Add some definitions related to the process extended state enumeration.

Revision 1.61 / (download) - annotate - [select for diffs], Thu Jan 3 23:03:57 2013 UTC (10 years, 1 month ago) by dsl
Branch: MAIN
Changes since 1.60: +73 -36 lines
Diff to previous 1.60 (colored)

Add some missing bit definitions to CPUID2 and those for XCR0.
Taken from the August 2012 Intel SDM (intel_x86_325462.pdf).
Split all the snprintb() format strings to make them (almost) readable.
Fix CPUID_AMD_FLAGS4 to not try to print bits \41 and \42.

Revision 1.31.4.2 / (download) - annotate - [select for diffs], Wed Nov 28 04:39:03 2012 UTC (10 years, 2 months ago) by riz
Branch: netbsd-5
CVS Tags: netbsd-5-2-RELEASE, netbsd-5-2-3-RELEASE, netbsd-5-2-2-RELEASE, netbsd-5-2-1-RELEASE
Branch point for: netbsd-5-2
Changes since 1.31.4.1: +6 -1 lines
Diff to previous 1.31.4.1 (colored) to branchpoint 1.31 (colored)

Pull up following revision(s) (requested by christos in ticket #1819):
	sys/arch/x86/include/specialreg.h: revision 1.58
Add VIA Eden FCR MSR.

Revision 1.59.2.1 / (download) - annotate - [select for diffs], Tue Nov 20 03:01:51 2012 UTC (10 years, 2 months ago) by tls
Branch: tls-maxphys
Changes since 1.59: +7 -4 lines
Diff to previous 1.59 (colored)

Resync to 2012-11-19 00:00:00 UTC

Revision 1.53.2.3 / (download) - annotate - [select for diffs], Tue Oct 30 17:20:33 2012 UTC (10 years, 3 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.53.2.2: +7 -4 lines
Diff to previous 1.53.2.2 (colored) to branchpoint 1.53 (colored)

sync with head

Revision 1.60 / (download) - annotate - [select for diffs], Wed Oct 17 16:13:01 2012 UTC (10 years, 3 months ago) by drochner
Branch: MAIN
CVS Tags: yamt-pagecache-base7, yamt-pagecache-base6
Changes since 1.59: +7 -4 lines
Diff to previous 1.59 (colored)

recognize the P1GB and RDTSCP which were AMD-only on Intel HW too

Revision 1.53.6.6 / (download) - annotate - [select for diffs], Sat Jun 2 11:09:11 2012 UTC (10 years, 8 months ago) by mrg
Branch: jmcneill-usbmp
Changes since 1.53.6.5: +24 -13 lines
Diff to previous 1.53.6.5 (colored) to branchpoint 1.53 (colored) next main 1.54 (colored)

sync to latest -current.

Revision 1.53.2.2 / (download) - annotate - [select for diffs], Wed May 23 10:07:51 2012 UTC (10 years, 8 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.53.2.1: +24 -13 lines
Diff to previous 1.53.2.1 (colored) to branchpoint 1.53 (colored)

sync with head.

Revision 1.55.2.3 / (download) - annotate - [select for diffs], Mon May 7 16:37:19 2012 UTC (10 years, 9 months ago) by riz
Branch: netbsd-6
CVS Tags: netbsd-6-1-RELEASE, netbsd-6-1-RC4, netbsd-6-1-RC3, netbsd-6-1-RC2, netbsd-6-1-RC1, netbsd-6-1-5-RELEASE, netbsd-6-1-4-RELEASE, netbsd-6-1-3-RELEASE, netbsd-6-1-2-RELEASE, netbsd-6-1-1-RELEASE, netbsd-6-1, netbsd-6-0-RELEASE, netbsd-6-0-RC2, netbsd-6-0-RC1, netbsd-6-0-6-RELEASE, netbsd-6-0-5-RELEASE, netbsd-6-0-4-RELEASE, netbsd-6-0-3-RELEASE, netbsd-6-0-2-RELEASE, netbsd-6-0-1-RELEASE, netbsd-6-0, matt-nb6-plus-nbase, matt-nb6-plus-base, matt-nb6-plus
Changes since 1.55.2.2: +6 -1 lines
Diff to previous 1.55.2.2 (colored) to branchpoint 1.55 (colored)

Pull up following revision(s) (requested by christos in ticket #220):
	sys/arch/x86/x86/identcpu.c: revision 1.31
	sys/arch/x86/include/specialreg.h: revision 1.58
PR/41267: Andrius V: 5.0 RC4 does not detect second CPU in VIA. VIA Eden cpuid
lies about it's ability to do cmpxchg8b. Turn the feature on using the FCR MSR.
Needs pullup to both 5 and 6.
Add VIA Eden FCR MSR.

Revision 1.59 / (download) - annotate - [select for diffs], Sat May 5 15:08:29 2012 UTC (10 years, 9 months ago) by jym
Branch: MAIN
CVS Tags: yamt-pagecache-base5, jmcneill-usbmp-base10
Branch point for: tls-maxphys
Changes since 1.58: +19 -13 lines
Diff to previous 1.58 (colored)

Add latest CR4 bits:
- CR4_VMXE: VMX operations, used for hardware virtualization.
- CR4_SMXE: SMX operations, used for safer Mode Extensions (ground for
            Intel's TXT - Trusted Execution Technology - platform).
- CR4_FSGSBASE: enable *FSBASE and *GSBASE instructions, for R/W access
                to FS/GS segment base addresses.
- CR4_PCIDE: enable Process Context IDentifiers (other architectures may call
             these "address space identifiers").
- CR4_OSXSAVE: enable xsave and xrestore instructions
- CR4_SMEP: Supervisor Mode Execution Prevention. Allows enforcing --x rights
            from cpl 0.

From Intel¬ģ 64 and IA-32 Architectures Software Developer—‘ Manual,
March 2012.

Align declarations.

CPUID_* bits for these features follow.

Revision 1.58 / (download) - annotate - [select for diffs], Mon Apr 30 00:04:31 2012 UTC (10 years, 9 months ago) by christos
Branch: MAIN
Changes since 1.57: +6 -1 lines
Diff to previous 1.57 (colored)

Add VIA Eden FCR MSR.

Revision 1.53.6.5 / (download) - annotate - [select for diffs], Sun Apr 29 23:04:43 2012 UTC (10 years, 9 months ago) by mrg
Branch: jmcneill-usbmp
Changes since 1.53.6.4: +4 -1 lines
Diff to previous 1.53.6.4 (colored) to branchpoint 1.53 (colored)

sync to latest -current.

Revision 1.53.2.1 / (download) - annotate - [select for diffs], Tue Apr 17 00:07:05 2012 UTC (10 years, 9 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.53: +23 -2 lines
Diff to previous 1.53 (colored)

sync with head

Revision 1.55.2.2 / (download) - annotate - [select for diffs], Mon Apr 9 18:02:24 2012 UTC (10 years, 10 months ago) by riz
Branch: netbsd-6
Changes since 1.55.2.1: +4 -1 lines
Diff to previous 1.55.2.1 (colored) to branchpoint 1.55 (colored)

Pull up following revision(s) (requested by chs in ticket #168):
	sys/arch/x86/include/specialreg.h: revision 1.57
	sys/arch/x86/x86/errata.c: revision 1.20
bring in this change from openbsd:
Implement the AMD suggested workaround for family 10h & 12h errata 721
"Processor May Incorrectly Update Stack Pointer" by setting a bit
marked 'reserved' in an MSR that is only "documented" to exist on 12h.

Revision 1.57 / (download) - annotate - [select for diffs], Fri Apr 6 17:23:39 2012 UTC (10 years, 10 months ago) by chs
Branch: MAIN
CVS Tags: yamt-pagecache-base4, jmcneill-usbmp-base9
Changes since 1.56: +4 -1 lines
Diff to previous 1.56 (colored)

bring in this change from openbsd:
Implement the AMD suggested workaround for family 10h & 12h errata 721
"Processor May Incorrectly Update Stack Pointer" by setting a bit
marked 'reserved' in an MSR that is only "documented" to exist on 12h.

Revision 1.53.6.4 / (download) - annotate - [select for diffs], Tue Mar 6 18:26:39 2012 UTC (10 years, 11 months ago) by mrg
Branch: jmcneill-usbmp
Changes since 1.53.6.3: +2 -2 lines
Diff to previous 1.53.6.3 (colored) to branchpoint 1.53 (colored)

sync to -current

Revision 1.53.6.3 / (download) - annotate - [select for diffs], Tue Mar 6 09:56:11 2012 UTC (10 years, 11 months ago) by mrg
Branch: jmcneill-usbmp
Changes since 1.53.6.2: +2 -2 lines
Diff to previous 1.53.6.2 (colored) to branchpoint 1.53 (colored)

sync to -current

Revision 1.55.2.1 / (download) - annotate - [select for diffs], Mon Mar 5 20:18:03 2012 UTC (10 years, 11 months ago) by sborrill
Branch: netbsd-6
Changes since 1.55: +2 -2 lines
Diff to previous 1.55 (colored)

Pull up the following revisions(s) (requested by bouyer in ticket #80):
	sys/arch/xen/x86/x86_xpmap.c:	revision 1.42
	sys/arch/x86/include/specialreg.h:	revision 1.56
	sys/arch/amd64/amd64/machdep.c:	revision 1.179
	sys/arch/i386/i386/locore.S:	revision 1.97
	sys/arch/i386/i386/machdep.c:	revision 1.723 via patch
	sys/arch/x86/include/cpu.h:	revision 1.49

Fix possible FPU registers corruption on context switches.
Fix type of pointers passed to some hypercalls.

Revision 1.53.6.2 / (download) - annotate - [select for diffs], Sun Mar 4 00:46:16 2012 UTC (10 years, 11 months ago) by mrg
Branch: jmcneill-usbmp
Changes since 1.53.6.1: +2 -2 lines
Diff to previous 1.53.6.1 (colored) to branchpoint 1.53 (colored)

sync to latest -current.

Revision 1.56 / (download) - annotate - [select for diffs], Fri Mar 2 16:41:00 2012 UTC (10 years, 11 months ago) by bouyer
Branch: MAIN
CVS Tags: jmcneill-usbmp-base8, jmcneill-usbmp-base7, jmcneill-usbmp-base6, jmcneill-usbmp-base4
Changes since 1.55: +2 -2 lines
Diff to previous 1.55 (colored)

Don't mask out CPUID_FXSR. If not set, the kernel won't handle SSE and SSE2
registers on context switches; leading to data corruption when running
binaries using these instructions (like e.g. binaries built with a
-mcpu newer than pentium 4, which enables theses instruction in gcc).

Revision 1.53.6.1 / (download) - annotate - [select for diffs], Sat Feb 18 07:33:34 2012 UTC (10 years, 11 months ago) by mrg
Branch: jmcneill-usbmp
Changes since 1.53: +19 -1 lines
Diff to previous 1.53 (colored)

merge to -current.

Revision 1.55 / (download) - annotate - [select for diffs], Thu Dec 15 09:38:21 2011 UTC (11 years, 1 month ago) by abs
Branch: MAIN
CVS Tags: netbsd-6-base, jmcneill-usbmp-base5, jmcneill-usbmp-base3, jmcneill-usbmp-base2
Branch point for: netbsd-6
Changes since 1.54: +17 -1 lines
Diff to previous 1.54 (colored)

Increase MTRR_I686_NVAR_MAX from 8 to 16. Avoids
"FIXME: more than 8 MTRRs (10)" message on booting Thinkpad W520 and
similar. While here replace a magic number with MTRR_I686_NVAR_MAX * 2

Revision 1.54 / (download) - annotate - [select for diffs], Fri Dec 9 10:08:47 2011 UTC (11 years, 2 months ago) by cegger
Branch: MAIN
Changes since 1.53: +3 -1 lines
Diff to previous 1.53 (colored)

add AMD ucode MSRs

Revision 1.53 / (download) - annotate - [select for diffs], Mon Oct 3 17:31:35 2011 UTC (11 years, 4 months ago) by njoly
Branch: MAIN
CVS Tags: yamt-pagecache-base3, yamt-pagecache-base2, yamt-pagecache-base, jmcneill-usbmp-pre-base2, jmcneill-usbmp-base, jmcneill-audiomp3-base, jmcneill-audiomp3
Branch point for: yamt-pagecache, jmcneill-usbmp
Changes since 1.52: +2 -2 lines
Diff to previous 1.52 (colored)

Do not redefine CPUID_LAHF.

Revision 1.31.8.6 / (download) - annotate - [select for diffs], Sat Aug 27 15:37:29 2011 UTC (11 years, 5 months ago) by jym
Branch: jym-xensuspend
Changes since 1.31.8.5: +7 -5 lines
Diff to previous 1.31.8.5 (colored) to branchpoint 1.31 (colored) next main 1.32 (colored)

Sync with HEAD. Most notably: uvm/pmap work done by rmind@, and MP Xen
work of cherry@.

No regression observed on suspend/restore.

Revision 1.52 / (download) - annotate - [select for diffs], Tue Jul 26 12:59:41 2011 UTC (11 years, 6 months ago) by yamt
Branch: MAIN
CVS Tags: jym-xensuspend-nbase, jym-xensuspend-base
Changes since 1.51: +7 -5 lines
Diff to previous 1.51 (colored)

- add PCID
- comment

Revision 1.49.2.1 / (download) - annotate - [select for diffs], Mon Jun 6 09:07:06 2011 UTC (11 years, 8 months ago) by jruoho
Branch: jruoho-x86intr
Changes since 1.49: +37 -12 lines
Diff to previous 1.49 (colored) next main 1.50 (colored)

Sync with HEAD.

Revision 1.31.8.5 / (download) - annotate - [select for diffs], Mon Mar 28 23:04:50 2011 UTC (11 years, 10 months ago) by jym
Branch: jym-xensuspend
Changes since 1.31.8.4: +37 -12 lines
Diff to previous 1.31.8.4 (colored) to branchpoint 1.31 (colored)

Sync with HEAD. TODO before merge:
- shortcut for suspend code in sysmon, when powerd(8) is not running.
Borrow ``xs_watch'' thread context?
- bug hunting in xbd + xennet resume. Rings are currently thrashed upon
resume, so current implementation force flush them on suspend. It's not
really needed.

Revision 1.38.4.2 / (download) - annotate - [select for diffs], Sat Mar 5 20:52:28 2011 UTC (11 years, 11 months ago) by rmind
Branch: rmind-uvmplock
Changes since 1.38.4.1: +71 -15 lines
Diff to previous 1.38.4.1 (colored) to branchpoint 1.38 (colored) next main 1.39 (colored)

sync with head

Revision 1.49.4.2 / (download) - annotate - [select for diffs], Sat Mar 5 15:10:10 2011 UTC (11 years, 11 months ago) by bouyer
Branch: bouyer-quota2
Changes since 1.49.4.1: +2 -1 lines
Diff to previous 1.49.4.1 (colored) to branchpoint 1.49 (colored) next main 1.50 (colored)

Sync with HEAD

Revision 1.51 / (download) - annotate - [select for diffs], Sun Feb 20 21:09:32 2011 UTC (11 years, 11 months ago) by jruoho
Branch: MAIN
CVS Tags: rmind-uvmplock-nbase, rmind-uvmplock-base, cherry-xenmp-base, cherry-xenmp, bouyer-quota2-nbase
Changes since 1.50: +2 -1 lines
Diff to previous 1.50 (colored)

Add MSR_TEMPERATURE_TARGET.

Revision 1.49.4.1 / (download) - annotate - [select for diffs], Thu Feb 17 12:00:06 2011 UTC (11 years, 11 months ago) by bouyer
Branch: bouyer-quota2
Changes since 1.49: +36 -12 lines
Diff to previous 1.49 (colored)

Sync with HEAD

Revision 1.50 / (download) - annotate - [select for diffs], Tue Feb 15 10:11:25 2011 UTC (11 years, 11 months ago) by cegger
Branch: MAIN
CVS Tags: uebayasi-xip-base7, bouyer-quota2-base
Changes since 1.49: +36 -12 lines
Diff to previous 1.49 (colored)

update cpuid bits

Revision 1.31.8.4 / (download) - annotate - [select for diffs], Sun Oct 24 22:48:16 2010 UTC (12 years, 3 months ago) by jym
Branch: jym-xensuspend
Changes since 1.31.8.3: +52 -18 lines
Diff to previous 1.31.8.3 (colored) to branchpoint 1.31 (colored)

Sync with HEAD

Revision 1.38.2.3 / (download) - annotate - [select for diffs], Fri Oct 22 07:21:41 2010 UTC (12 years, 3 months ago) by uebayasi
Branch: uebayasi-xip
Changes since 1.38.2.2: +27 -4 lines
Diff to previous 1.38.2.2 (colored) to branchpoint 1.38 (colored) next main 1.39 (colored)

Sync with HEAD (-D20101022).

Revision 1.49 / (download) - annotate - [select for diffs], Tue Oct 12 00:39:08 2010 UTC (12 years, 4 months ago) by jakllsch
Branch: MAIN
CVS Tags: uebayasi-xip-base6, uebayasi-xip-base5, uebayasi-xip-base4, uebayasi-xip-base3, matt-mips64-premerge-20101231, jruoho-x86intr-base
Branch point for: jruoho-x86intr, bouyer-quota2
Changes since 1.48: +2 -2 lines
Diff to previous 1.48 (colored)

Correct another off-by-one-bit error.  This time for Erratum 97.

Revision 1.23.10.7 / (download) - annotate - [select for diffs], Sat Oct 9 03:31:56 2010 UTC (12 years, 4 months ago) by yamt
Branch: yamt-nfs-mp
Changes since 1.23.10.6: +27 -4 lines
Diff to previous 1.23.10.6 (colored) to branchpoint 1.23 (colored) next main 1.24 (colored)

sync with head

Revision 1.48 / (download) - annotate - [select for diffs], Sat Sep 18 15:49:25 2010 UTC (12 years, 4 months ago) by jakllsch
Branch: MAIN
CVS Tags: yamt-nfs-mp-base11
Changes since 1.47: +2 -2 lines
Diff to previous 1.47 (colored)

AMD publication 25759 rev 3.69 says that DisIOReqLock in NB_CFG is "bit 3".
They probably mean "bit 3" and not "the third bit" (or bit 2).
This change should prevent superfluous warnings of errata 89.

Revision 1.47 / (download) - annotate - [select for diffs], Wed Aug 25 05:07:43 2010 UTC (12 years, 5 months ago) by jruoho
Branch: MAIN
Changes since 1.46: +22 -2 lines
Diff to previous 1.46 (colored)

Add definitions for Intel Digital Thermal Sensor and Power Management, at
CPUID Fn0000_0006, %eax, %ecx. Use these instead of magic numbers.

Revision 1.46 / (download) - annotate - [select for diffs], Sat Aug 21 02:59:18 2010 UTC (12 years, 5 months ago) by jruoho
Branch: MAIN
Changes since 1.45: +3 -1 lines
Diff to previous 1.45 (colored)

Add IA32_MPERF (E7h) and IA32_APERF (E8h) as MSR_MPERF and MSR_APERF.

Revision 1.45 / (download) - annotate - [select for diffs], Sat Aug 21 02:31:13 2010 UTC (12 years, 5 months ago) by jruoho
Branch: MAIN
Changes since 1.44: +3 -2 lines
Diff to previous 1.44 (colored)

Add CPUID_APM_CPB at Fn8000_0007 %edx, for core performance boost.

Revision 1.38.2.2 / (download) - annotate - [select for diffs], Tue Aug 17 06:45:31 2010 UTC (12 years, 5 months ago) by uebayasi
Branch: uebayasi-xip
Changes since 1.38.2.1: +8 -2 lines
Diff to previous 1.38.2.1 (colored) to branchpoint 1.38 (colored)

Sync with HEAD.

Revision 1.23.10.6 / (download) - annotate - [select for diffs], Wed Aug 11 22:52:55 2010 UTC (12 years, 6 months ago) by yamt
Branch: yamt-nfs-mp
Changes since 1.23.10.5: +24 -15 lines
Diff to previous 1.23.10.5 (colored) to branchpoint 1.23 (colored)

sync with head.

Revision 1.44 / (download) - annotate - [select for diffs], Thu Jul 29 08:16:49 2010 UTC (12 years, 6 months ago) by cegger
Branch: MAIN
CVS Tags: yamt-nfs-mp-base10, uebayasi-xip-base2
Changes since 1.43: +4 -1 lines
Diff to previous 1.43 (colored)

add RDTSCP_AUX MSR

Revision 1.43 / (download) - annotate - [select for diffs], Sat Jul 24 08:02:46 2010 UTC (12 years, 6 months ago) by cegger
Branch: MAIN
Changes since 1.42: +5 -1 lines
Diff to previous 1.42 (colored)

add AMD OSVW MSRs

Revision 1.42 / (download) - annotate - [select for diffs], Tue Jul 6 20:50:35 2010 UTC (12 years, 7 months ago) by cegger
Branch: MAIN
Changes since 1.41: +2 -1 lines
Diff to previous 1.41 (colored)

Turn PMAP_NOCACHE into MI flag.
Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR.
Update pmap(9) manpage.

hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag
mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE.

x86: Implement new MI flags using Page-Attribute Tables.
x86: Implement BUS_SPACE_MAP_PREFETCHABLE.

Patch presented on tech-kern@:
http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html

No comments on this last version.

Revision 1.38.4.1 / (download) - annotate - [select for diffs], Sun May 30 05:17:12 2010 UTC (12 years, 8 months ago) by rmind
Branch: rmind-uvmplock
Changes since 1.38: +16 -15 lines
Diff to previous 1.38 (colored)

sync with head

Revision 1.41 / (download) - annotate - [select for diffs], Tue May 4 23:27:14 2010 UTC (12 years, 9 months ago) by jym
Branch: MAIN
Changes since 1.40: +1 -3 lines
Diff to previous 1.40 (colored)

Enable the NX bit feature for Xen i386pae and amd64 kernels.

Tested with Xen 3.1 and Xen 3.3, dom0 and domU, by bouyer@ and jym@.

Ok bouyer@.

Revision 1.38.2.1 / (download) - annotate - [select for diffs], Fri Apr 30 14:39:57 2010 UTC (12 years, 9 months ago) by uebayasi
Branch: uebayasi-xip
Changes since 1.38: +18 -15 lines
Diff to previous 1.38 (colored)

Sync with HEAD.

Revision 1.31.12.1 / (download) - annotate - [select for diffs], Wed Apr 21 00:33:45 2010 UTC (12 years, 9 months ago) by matt
Branch: matt-nb5-mips64
CVS Tags: matt-nb5-mips64-premerge-20101231, matt-nb5-mips64-k15
Changes since 1.31: +2 -1 lines
Diff to previous 1.31 (colored) next main 1.32 (colored)

sync to netbsd-5

Revision 1.40 / (download) - annotate - [select for diffs], Sun Apr 18 23:47:51 2010 UTC (12 years, 9 months ago) by jym
Branch: MAIN
CVS Tags: uebayasi-xip-base1
Changes since 1.39: +14 -4 lines
Diff to previous 1.39 (colored)

This patch fixes the NX regression issue observed on amd64 kernels, where
per-page execution right was disabled (therefore leading to the inability
of the kernel to detect fraudulent use of memory mappings marked as not
being executable).

- replace cpu_feature and ci_feature_flags variables by cpu_feature and
ci_feat_val arrays. This makes it cleaner and brings kernel code closer
to the design of cpuctl(8). A warning will be raised for each CPU that
does not expose the same features as the Boot Processor (BP).

- the blacklist of CPU features is now a macro defined in the
specialreg.h header, instead of hardcoding it inside MD initialization
code; fix comments.

- replace checks against CPUID_TSC with the cpu_hascounter() function.

- clean up the code in init_x86_64(), as cpu_feature variables are set
inside cpu_probe().

- use cpu_init_msrs() for i386. It will be eventually used later for NX
feature under i386 PAE kernels.

- remove code that checks for CPUID_NOX in amd64 mptramp.S, this is already
performed by cpu_hatch() through cpu_init_msrs().

- remove cpu_signature and feature_flags members from struct mpbios_proc
(they were never used).

This patch was tested with i386 MONOLITHIC, XEN3PAE_DOM0 and XEN3_DOM0 under
a native i386 host, and amd64 GENERIC, XEN3_DOM0 via QEMU virtual machines.

XXX Should kernel rev be bumped?

XXX A similar patch should be pulled-up for NetBSD-5, hopefully tomorrow.

Revision 1.39 / (download) - annotate - [select for diffs], Sat Apr 3 23:17:05 2010 UTC (12 years, 10 months ago) by jym
Branch: MAIN
Changes since 1.38: +6 -13 lines
Diff to previous 1.38 (colored)

Fix the comments about cpuid flags, according cpuid documentation by
Intel and AMD.

Revision 1.23.10.5 / (download) - annotate - [select for diffs], Thu Mar 11 15:03:08 2010 UTC (12 years, 11 months ago) by yamt
Branch: yamt-nfs-mp
Changes since 1.23.10.4: +4 -2 lines
Diff to previous 1.23.10.4 (colored) to branchpoint 1.23 (colored)

sync with head

Revision 1.38 / (download) - annotate - [select for diffs], Wed Jan 13 12:54:49 2010 UTC (13 years ago) by cegger
Branch: MAIN
CVS Tags: yamt-nfs-mp-base9, uebayasi-xip-base
Branch point for: uebayasi-xip, rmind-uvmplock
Changes since 1.37: +4 -2 lines
Diff to previous 1.37 (colored)

recognize SVM PauseFilter

Revision 1.31.8.3 / (download) - annotate - [select for diffs], Sun Nov 1 13:58:16 2009 UTC (13 years, 3 months ago) by jym
Branch: jym-xensuspend
Changes since 1.31.8.2: +4 -3 lines
Diff to previous 1.31.8.2 (colored) to branchpoint 1.31 (colored)

Sync with HEAD.

Revision 1.23.10.4 / (download) - annotate - [select for diffs], Wed Aug 19 18:46:50 2009 UTC (13 years, 5 months ago) by yamt
Branch: yamt-nfs-mp
Changes since 1.23.10.3: +4 -3 lines
Diff to previous 1.23.10.3 (colored) to branchpoint 1.23 (colored)

sync with head.

Revision 1.37 / (download) - annotate - [select for diffs], Thu Aug 13 11:27:34 2009 UTC (13 years, 5 months ago) by cegger
Branch: MAIN
CVS Tags: yamt-nfs-mp-base8, yamt-nfs-mp-base7, matt-premerge-20091211
Changes since 1.36: +4 -3 lines
Diff to previous 1.36 (colored)

recognize virtual cpu feature indicating guest state.

Revision 1.23.10.3 / (download) - annotate - [select for diffs], Sat Jun 20 07:20:12 2009 UTC (13 years, 7 months ago) by yamt
Branch: yamt-nfs-mp
Changes since 1.23.10.2: +5 -4 lines
Diff to previous 1.23.10.2 (colored) to branchpoint 1.23 (colored)

sync with head

Revision 1.31.4.1 / (download) - annotate - [select for diffs], Tue Jun 16 02:23:31 2009 UTC (13 years, 7 months ago) by snj
Branch: netbsd-5
CVS Tags: netbsd-5-2-RC1, netbsd-5-1-RELEASE, netbsd-5-1-RC4, netbsd-5-1-RC3, netbsd-5-1-RC2, netbsd-5-1-RC1, netbsd-5-1-5-RELEASE, netbsd-5-1-4-RELEASE, netbsd-5-1-3-RELEASE, netbsd-5-1-2-RELEASE, netbsd-5-1-1-RELEASE, matt-nb5-pq3-base, matt-nb5-pq3
Branch point for: netbsd-5-1
Changes since 1.31: +2 -1 lines
Diff to previous 1.31 (colored)

Pull up following revision(s) (requested by rmind in ticket #789):
	sys/arch/x86/include/specialreg.h: revision 1.36
	sys/arch/x86/x86/cpu_topology.c: revision 1.2
Add CPU topology detection support for AMD processors.
Tested on the following AMD CPUs:
- Family 15, model 65
- Family 15, model 67
- Family 15, model 75
- Family 16, model 2
- Family 17, model 3
Reviewed (slightly older version of patch) by <yamt>.

Revision 1.31.8.2 / (download) - annotate - [select for diffs], Sun May 31 14:32:34 2009 UTC (13 years, 8 months ago) by jym
Branch: jym-xensuspend
Changes since 1.31.8.1: +25 -20 lines
Diff to previous 1.31.8.1 (colored) to branchpoint 1.31 (colored)

Sync with HEAD.

Revision 1.36 / (download) - annotate - [select for diffs], Tue May 26 01:42:02 2009 UTC (13 years, 8 months ago) by rmind
Branch: MAIN
CVS Tags: yamt-nfs-mp-base6, yamt-nfs-mp-base5, jymxensuspend-base
Changes since 1.35: +2 -1 lines
Diff to previous 1.35 (colored)

Add CPU topology detection support for AMD processors.
Tested on the following AMD CPUs:
- Family 15, model 65
- Family 15, model 67
- Family 15, model 75
- Family 16, model 2
- Family 17, model 3

Reviewed (slightly older version of patch) by <yamt>.

Revision 1.35 / (download) - annotate - [select for diffs], Sat May 16 13:36:44 2009 UTC (13 years, 8 months ago) by pgoyette
Branch: MAIN
Changes since 1.34: +4 -4 lines
Diff to previous 1.34 (colored)

Correctly identify flag bit for SSSE3 (one of the 'S' was missing).  Also
rename AMD bit from SCALL/RET to SYSCALL/SYSRET to match Intel bit name.

Revision 1.23.10.2 / (download) - annotate - [select for diffs], Sat May 16 10:41:17 2009 UTC (13 years, 8 months ago) by yamt
Branch: yamt-nfs-mp
Changes since 1.23.10.1: +22 -18 lines
Diff to previous 1.23.10.1 (colored) to branchpoint 1.23 (colored)

sync with head

Revision 1.34 / (download) - annotate - [select for diffs], Wed May 13 22:25:51 2009 UTC (13 years, 8 months ago) by pgoyette
Branch: MAIN
CVS Tags: yamt-nfs-mp-base4
Changes since 1.33: +22 -18 lines
Diff to previous 1.33 (colored)

1. Extend CPU probe of Intel processors to handle extended-models.  This
   allows us to properly identify new Intel 45nm processors, Core i7,
   Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
   most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
   snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290

Revision 1.31.8.1 / (download) - annotate - [select for diffs], Wed May 13 17:18:44 2009 UTC (13 years, 8 months ago) by jym
Branch: jym-xensuspend
Changes since 1.31: +11 -1 lines
Diff to previous 1.31 (colored)

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

Revision 1.23.10.1 / (download) - annotate - [select for diffs], Mon May 4 08:12:09 2009 UTC (13 years, 9 months ago) by yamt
Branch: yamt-nfs-mp
Changes since 1.23: +73 -8 lines
Diff to previous 1.23 (colored)

sync with head.

Revision 1.31.2.1 / (download) - annotate - [select for diffs], Tue Apr 28 07:34:56 2009 UTC (13 years, 9 months ago) by skrll
Branch: nick-hppapmap
Changes since 1.31: +11 -1 lines
Diff to previous 1.31 (colored) next main 1.32 (colored)

Sync with HEAD.

Revision 1.33 / (download) - annotate - [select for diffs], Thu Mar 12 09:08:40 2009 UTC (13 years, 11 months ago) by yamt
Branch: MAIN
CVS Tags: yamt-nfs-mp-base3, nick-hppapmap-base4, nick-hppapmap-base3, nick-hppapmap-base
Changes since 1.32: +9 -1 lines
Diff to previous 1.32 (colored)

add definitions for SVM features.

Revision 1.32 / (download) - annotate - [select for diffs], Thu Mar 12 09:07:29 2009 UTC (13 years, 11 months ago) by yamt
Branch: MAIN
Changes since 1.31: +3 -1 lines
Diff to previous 1.31 (colored)

comments

Revision 1.23.6.3 / (download) - annotate - [select for diffs], Sat Jan 17 13:28:38 2009 UTC (14 years ago) by mjf
Branch: mjf-devfs2
Changes since 1.23.6.2: +53 -3 lines
Diff to previous 1.23.6.2 (colored) to branchpoint 1.23 (colored) next main 1.24 (colored)

Sync with HEAD.

Revision 1.24.4.1 / (download) - annotate - [select for diffs], Sun Oct 19 22:16:07 2008 UTC (14 years, 3 months ago) by haad
Branch: haad-dm
Changes since 1.24: +58 -8 lines
Diff to previous 1.24 (colored) next main 1.25 (colored)

Sync with HEAD.

Revision 1.31 / (download) - annotate - [select for diffs], Tue Oct 14 15:49:04 2008 UTC (14 years, 3 months ago) by cegger
Branch: MAIN
CVS Tags: nick-hppapmap-base2, netbsd-5-base, netbsd-5-0-RELEASE, netbsd-5-0-RC4, netbsd-5-0-RC3, netbsd-5-0-RC2, netbsd-5-0-RC1, netbsd-5-0-2-RELEASE, netbsd-5-0-1-RELEASE, netbsd-5-0, mjf-devfs2-base, matt-nb5-mips64-u2-k2-k4-k7-k8-k9, matt-nb5-mips64-u1-k1-k5, matt-nb5-mips64-premerge-20091211, matt-nb4-mips64-k7-u2a-k9b, matt-mips64-base2, haad-nbase2, haad-dm-base2, haad-dm-base1, haad-dm-base, ad-audiomp2-base, ad-audiomp2
Branch point for: nick-hppapmap, netbsd-5, matt-nb5-mips64, jym-xensuspend
Changes since 1.30: +2 -2 lines
Diff to previous 1.30 (colored)

do correct octal counting and use CPUID_APM_FLAGS in cpuctl

Revision 1.30 / (download) - annotate - [select for diffs], Tue Oct 14 14:33:51 2008 UTC (14 years, 3 months ago) by cegger
Branch: MAIN
Changes since 1.29: +20 -1 lines
Diff to previous 1.29 (colored)

add cpuid fn 80000007 %edx: AMD Power Management feature flags

Revision 1.29 / (download) - annotate - [select for diffs], Tue Oct 14 12:22:29 2008 UTC (14 years, 3 months ago) by cegger
Branch: MAIN
Changes since 1.28: +2 -2 lines
Diff to previous 1.28 (colored)

fix output of 3DNOWPREFETCH feature flag

Revision 1.28 / (download) - annotate - [select for diffs], Mon Oct 13 19:14:53 2008 UTC (14 years, 3 months ago) by cegger
Branch: MAIN
Changes since 1.27: +35 -4 lines
Diff to previous 1.27 (colored)

Add cpuid 0x80000001 %ecx features flags. Rename CPUID_MASK4 to CPUID_INTEL_MASK4 for consistency with new CPUID_AMD_MASK4

Revision 1.23.6.2 / (download) - annotate - [select for diffs], Sun Sep 28 10:40:11 2008 UTC (14 years, 4 months ago) by mjf
Branch: mjf-devfs2
Changes since 1.23.6.1: +4 -4 lines
Diff to previous 1.23.6.1 (colored) to branchpoint 1.23 (colored)

Sync with HEAD.

Revision 1.23.12.2 / (download) - annotate - [select for diffs], Thu Sep 18 04:33:37 2008 UTC (14 years, 4 months ago) by wrstuden
Branch: wrstuden-revivesa
Changes since 1.23.12.1: +5 -5 lines
Diff to previous 1.23.12.1 (colored) to branchpoint 1.23 (colored) next main 1.24 (colored)

Sync with wrstuden-revivesa-base-2.

Revision 1.27 / (download) - annotate - [select for diffs], Tue Aug 26 13:43:47 2008 UTC (14 years, 5 months ago) by pgoyette
Branch: MAIN
CVS Tags: wrstuden-revivesa-base-4, wrstuden-revivesa-base-3, wrstuden-revivesa-base-2
Changes since 1.26: +5 -4 lines
Diff to previous 1.26 (colored)

Clean up previous:  add bit definitions for some new fields, and use "old"
style bitmask_printf(9) format string for consistency with the rest of the
file.  No functional change.

OK cegger@

Revision 1.26 / (download) - annotate - [select for diffs], Sun Aug 24 22:04:21 2008 UTC (14 years, 5 months ago) by pgoyette
Branch: MAIN
Changes since 1.25: +2 -2 lines
Diff to previous 1.25 (colored)

Shorten SYSCALL/SYSRET to SCALL/RET bit definition so it fits on one line.

Revision 1.25 / (download) - annotate - [select for diffs], Sun Aug 24 20:27:34 2008 UTC (14 years, 5 months ago) by pgoyette
Branch: MAIN
Changes since 1.24: +4 -5 lines
Diff to previous 1.24 (colored)

1. For non-Intel vendors, don't overload cpuflags with the extended
   flags from CPUID 80000001_EDX.  Instead, keep the extended flags
   separate, in ci_feature3_flags (Intel processors already kept a
   separate ci_feature3_flag value).

2. Decode/display ci_feature3_flag in a vendor-specific manner, since
   the definitions are vendor-specific.

OK cegger@

Revision 1.23.12.1 / (download) - annotate - [select for diffs], Mon Jun 23 04:30:50 2008 UTC (14 years, 7 months ago) by wrstuden
Branch: wrstuden-revivesa
Changes since 1.23: +6 -1 lines
Diff to previous 1.23 (colored)

Sync w/ -current. 34 merge conflicts to follow.

Revision 1.23.8.1 / (download) - annotate - [select for diffs], Wed Jun 4 02:04:58 2008 UTC (14 years, 8 months ago) by yamt
Branch: yamt-pf42
Changes since 1.23: +6 -1 lines
Diff to previous 1.23 (colored) next main 1.24 (colored)

sync with head

Revision 1.23.6.1 / (download) - annotate - [select for diffs], Mon Jun 2 13:22:50 2008 UTC (14 years, 8 months ago) by mjf
Branch: mjf-devfs2
Changes since 1.23: +6 -1 lines
Diff to previous 1.23 (colored)

Sync with HEAD.

Revision 1.24 / (download) - annotate - [select for diffs], Sun May 25 15:19:22 2008 UTC (14 years, 8 months ago) by chris
Branch: MAIN
CVS Tags: yamt-pf42-base4, yamt-pf42-base3, wrstuden-revivesa-base-1, wrstuden-revivesa-base, simonb-wapbl-nbase, simonb-wapbl-base, simonb-wapbl
Branch point for: haad-dm
Changes since 1.23: +6 -1 lines
Diff to previous 1.23 (colored)

Add detection of errata for AMD Family 10h steppings A and 2.  Covering
errata:
254: Internal Resource Livelock Involving Cached TLB Reload
261: Processor May Stall Entering Stop-Grant Due to Pending Data
     Cache Scrub
298: L2 Eviction May Occur During Processor Operation To Set
     Accessed or Dirty Bit
309: Processor Core May Execute Incorrect Instructions on
     Concurrent L2 and Northbridge Response

Revision 1.18.10.3 / (download) - annotate - [select for diffs], Sun Mar 23 02:04:28 2008 UTC (14 years, 10 months ago) by matt
Branch: matt-armv6
Changes since 1.18.10.2: +10 -4 lines
Diff to previous 1.18.10.2 (colored) to branchpoint 1.18 (colored) next main 1.19 (colored)

sync with HEAD

Revision 1.21.2.1 / (download) - annotate - [select for diffs], Mon Feb 18 21:05:17 2008 UTC (14 years, 11 months ago) by mjf
Branch: mjf-devfs
Changes since 1.21: +10 -4 lines
Diff to previous 1.21 (colored) next main 1.22 (colored)

Sync with HEAD.

Revision 1.8.4.8 / (download) - annotate - [select for diffs], Mon Feb 4 09:22:50 2008 UTC (15 years ago) by yamt
Branch: yamt-lazymbuf
Changes since 1.8.4.7: +10 -4 lines
Diff to previous 1.8.4.7 (colored) to branchpoint 1.8 (colored) next main 1.9 (colored)

sync with head.

Revision 1.23 / (download) - annotate - [select for diffs], Sun Feb 3 06:19:06 2008 UTC (15 years ago) by xtraeme
Branch: MAIN
CVS Tags: yamt-pf42-baseX, yamt-pf42-base2, yamt-pf42-base, yamt-nfs-mp-base2, yamt-nfs-mp-base, yamt-lazymbuf-base15, yamt-lazymbuf-base14, nick-net80211-sync-base, nick-net80211-sync, mjf-devfs-base, matt-armv6-nbase, keiichi-mipv6-nbase, keiichi-mipv6-base, keiichi-mipv6, hpcarm-cleanup-nbase, hpcarm-cleanup-base, ad-socklock-base1
Branch point for: yamt-pf42, yamt-nfs-mp, wrstuden-revivesa, mjf-devfs2
Changes since 1.22: +10 -4 lines
Diff to previous 1.22 (colored)

Add DTES64 and SSE4 related bits to CPUID2_FLAGS, from FreeBSD.

Revision 1.8.4.7 / (download) - annotate - [select for diffs], Mon Jan 21 09:40:09 2008 UTC (15 years ago) by yamt
Branch: yamt-lazymbuf
Changes since 1.8.4.6: +3 -2 lines
Diff to previous 1.8.4.6 (colored) to branchpoint 1.8 (colored)

sync with head

Revision 1.18.10.2 / (download) - annotate - [select for diffs], Wed Jan 9 01:49:49 2008 UTC (15 years, 1 month ago) by matt
Branch: matt-armv6
Changes since 1.18.10.1: +3 -2 lines
Diff to previous 1.18.10.1 (colored) to branchpoint 1.18 (colored)

sync with HEAD

Revision 1.21.8.1 / (download) - annotate - [select for diffs], Wed Jan 2 21:51:20 2008 UTC (15 years, 1 month ago) by bouyer
Branch: bouyer-xeni386
CVS Tags: bouyer-xeni386-merge1
Changes since 1.21: +3 -2 lines
Diff to previous 1.21 (colored) next main 1.22 (colored)

Sync with HEAD

Revision 1.21.4.1 / (download) - annotate - [select for diffs], Wed Dec 26 19:42:56 2007 UTC (15 years, 1 month ago) by ad
Branch: vmlocking2
Changes since 1.21: +3 -2 lines
Diff to previous 1.21 (colored) next main 1.22 (colored)

Sync with head.

Revision 1.22 / (download) - annotate - [select for diffs], Fri Dec 21 14:57:22 2007 UTC (15 years, 1 month ago) by drochner
Branch: MAIN
CVS Tags: vmlocking2-base3, matt-armv6-base, bouyer-xeni386-nbase, bouyer-xeni386-base
Changes since 1.21: +3 -2 lines
Diff to previous 1.21 (colored)

define the SSSE3 feature flag bit and print out all known bits

Revision 1.15.6.4 / (download) - annotate - [select for diffs], Mon Dec 3 18:40:09 2007 UTC (15 years, 2 months ago) by ad
Branch: vmlocking
Changes since 1.15.6.3: +2 -1 lines
Diff to previous 1.15.6.3 (colored) to branchpoint 1.15 (colored) next main 1.16 (colored)

Sync with HEAD.

Revision 1.8.4.6 / (download) - annotate - [select for diffs], Thu Nov 15 11:43:39 2007 UTC (15 years, 2 months ago) by yamt
Branch: yamt-lazymbuf
Changes since 1.8.4.5: +2 -1 lines
Diff to previous 1.8.4.5 (colored) to branchpoint 1.8 (colored)

sync with head.

Revision 1.19.2.1 / (download) - annotate - [select for diffs], Tue Nov 13 16:00:17 2007 UTC (15 years, 2 months ago) by bouyer
Branch: bouyer-xenamd64
Changes since 1.19: +2 -1 lines
Diff to previous 1.19 (colored) next main 1.20 (colored)

Sync with HEAD

Revision 1.18.10.1 / (download) - annotate - [select for diffs], Tue Nov 6 23:23:38 2007 UTC (15 years, 3 months ago) by matt
Branch: matt-armv6
CVS Tags: matt-armv6-prevmlocking
Changes since 1.18: +2 -7 lines
Diff to previous 1.18 (colored)

sync with HEAD

Revision 1.18.8.2 / (download) - annotate - [select for diffs], Mon Oct 29 02:57:23 2007 UTC (15 years, 3 months ago) by joerg
Branch: jmcneill-pm
Changes since 1.18.8.1: +2 -1 lines
Diff to previous 1.18.8.1 (colored) to branchpoint 1.18 (colored) next main 1.19 (colored)

Sync with HEAD.

Revision 1.21 / (download) - annotate - [select for diffs], Mon Oct 29 00:42:29 2007 UTC (15 years, 3 months ago) by xtraeme
Branch: MAIN
CVS Tags: yamt-kmem-base3, yamt-kmem-base2, yamt-kmem-base, yamt-kmem, vmlocking2-base2, vmlocking2-base1, vmlocking-nbase, reinoud-bufcleanup-nbase, reinoud-bufcleanup-base, jmcneill-pm-base, jmcneill-base, cube-autoconf-base, cube-autoconf, bouyer-xenamd64-base2, bouyer-xenamd64-base
Branch point for: vmlocking2, mjf-devfs, bouyer-xeni386
Changes since 1.20: +2 -1 lines
Diff to previous 1.20 (colored)

Add coretemp(4). A new driver for Intel Core's on-die thermal sensor,
available on Intel Core or newer CPUs.

Ported from FreeBSD. Tested by rmind on i386 and joerg on amd64.

Enabled with "options INTEL_CORETEMP".

Revision 1.8.4.5 / (download) - annotate - [select for diffs], Sat Oct 27 11:28:56 2007 UTC (15 years, 3 months ago) by yamt
Branch: yamt-lazymbuf
Changes since 1.8.4.4: +1 -7 lines
Diff to previous 1.8.4.4 (colored) to branchpoint 1.8 (colored)

sync with head.

Revision 1.20 / (download) - annotate - [select for diffs], Wed Oct 17 19:58:15 2007 UTC (15 years, 3 months ago) by garbled
Branch: MAIN
CVS Tags: yamt-x86pmap-base4
Changes since 1.19: +1 -1 lines
Diff to previous 1.19 (colored)

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Revision 1.15.6.3 / (download) - annotate - [select for diffs], Tue Oct 9 13:38:42 2007 UTC (15 years, 4 months ago) by ad
Branch: vmlocking
Changes since 1.15.6.2: +1 -7 lines
Diff to previous 1.15.6.2 (colored) to branchpoint 1.15 (colored)

Sync with head.

Revision 1.18.12.1 / (download) - annotate - [select for diffs], Sat Oct 6 15:33:33 2007 UTC (15 years, 4 months ago) by yamt
Branch: yamt-x86pmap
Changes since 1.18: +1 -7 lines
Diff to previous 1.18 (colored) next main 1.19 (colored)

sync with head.

Revision 1.15.14.2 / (download) - annotate - [select for diffs], Wed Oct 3 19:25:50 2007 UTC (15 years, 4 months ago) by garbled
Branch: ppcoea-renovation
Changes since 1.15.14.1: +16 -12 lines
Diff to previous 1.15.14.1 (colored) to branchpoint 1.15 (colored) next main 1.16 (colored)

Sync with HEAD

Revision 1.18.8.1 / (download) - annotate - [select for diffs], Tue Oct 2 18:27:50 2007 UTC (15 years, 4 months ago) by joerg
Branch: jmcneill-pm
Changes since 1.18: +1 -7 lines
Diff to previous 1.18 (colored)

Sync with HEAD.

Revision 1.19 / (download) - annotate - [select for diffs], Wed Sep 26 19:48:38 2007 UTC (15 years, 4 months ago) by ad
Branch: MAIN
CVS Tags: yamt-x86pmap-base3, yamt-x86pmap-base2, vmlocking-base, ppcoea-renovation-base
Branch point for: bouyer-xenamd64
Changes since 1.18: +1 -7 lines
Diff to previous 1.18 (colored)

x86 changes for pcc and LKMs.

- Replace most inline assembly with proper functions. As a side effect
  this reduces the size of amd64 GENERIC by about 120kB, and i386 by a
  smaller amount. Nearly all of the inlines did something slow, or something
  that does not need to be fast.
- Make curcpu() and curlwp functions proper, unless __GNUC__ && _KERNEL.
  In that case make them inlines. Makes curlwp LKM and preemption safe.
- Make bus_space and bus_dma more LKM friendly.
- Share a few more files between the ports.
- Other minor changes.

Revision 1.8.4.4 / (download) - annotate - [select for diffs], Mon Sep 3 14:31:21 2007 UTC (15 years, 5 months ago) by yamt
Branch: yamt-lazymbuf
Changes since 1.8.4.3: +22 -7 lines
Diff to previous 1.8.4.3 (colored) to branchpoint 1.8 (colored)

sync with head.

Revision 1.15.6.2 / (download) - annotate - [select for diffs], Sun Jul 15 13:17:15 2007 UTC (15 years, 6 months ago) by ad
Branch: vmlocking
Changes since 1.15.6.1: +16 -6 lines
Diff to previous 1.15.6.1 (colored) to branchpoint 1.15 (colored)

Sync with head.

Revision 1.15.8.1 / (download) - annotate - [select for diffs], Wed Jul 11 20:03:15 2007 UTC (15 years, 7 months ago) by mjf
Branch: mjf-ufs-trans
Changes since 1.15: +22 -7 lines
Diff to previous 1.15 (colored) next main 1.16 (colored)

Sync with head.

Revision 1.18 / (download) - annotate - [select for diffs], Wed Jul 11 11:56:36 2007 UTC (15 years, 7 months ago) by njoly
Branch: MAIN
CVS Tags: yamt-x86pmap-base, nick-csl-alignment-base5, nick-csl-alignment-base, nick-csl-alignment, mjf-ufs-trans-base, matt-mips64-base, matt-mips64, hpcarm-cleanup
Branch point for: yamt-x86pmap, matt-armv6, jmcneill-pm
Changes since 1.17: +4 -3 lines
Diff to previous 1.17 (colored)

Display RDTSCP bit on AMD processors (Read Serialized TSC Pair).

ok by xtraeme

Revision 1.17 / (download) - annotate - [select for diffs], Tue Jul 3 17:07:55 2007 UTC (15 years, 7 months ago) by christos
Branch: MAIN
Changes since 1.16: +13 -4 lines
Diff to previous 1.16 (colored)

Support for VIA Esther (From FreeBSD)

Revision 1.15.14.1 / (download) - annotate - [select for diffs], Tue Jun 26 18:13:53 2007 UTC (15 years, 7 months ago) by garbled
Branch: ppcoea-renovation
Changes since 1.15: +7 -2 lines
Diff to previous 1.15 (colored)

Sync with HEAD.

Revision 1.15.6.1 / (download) - annotate - [select for diffs], Sat Jun 9 23:55:31 2007 UTC (15 years, 8 months ago) by ad
Branch: vmlocking
Changes since 1.15: +7 -2 lines
Diff to previous 1.15 (colored)

Sync with head.

Revision 1.16 / (download) - annotate - [select for diffs], Mon Jun 4 16:21:29 2007 UTC (15 years, 8 months ago) by xtraeme
Branch: MAIN
Changes since 1.15: +7 -2 lines
Diff to previous 1.15 (colored)

Add four missing bits for CPUID2_FLAGS, from FreeBSD.

Revision 1.8.4.3 / (download) - annotate - [select for diffs], Mon Feb 26 09:08:49 2007 UTC (15 years, 11 months ago) by yamt
Branch: yamt-lazymbuf
Changes since 1.8.4.2: +72 -4 lines
Diff to previous 1.8.4.2 (colored) to branchpoint 1.8 (colored)

sync with head.

Revision 1.15.2.2 / (download) - annotate - [select for diffs], Sat Feb 17 00:28:26 2007 UTC (15 years, 11 months ago) by daniel
Branch: yamt-idlelwp
Changes since 1.15.2.1: +679 -0 lines
Diff to previous 1.15.2.1 (colored) to branchpoint 1.15 (colored) next main 1.16 (colored)

Add an opencrypto provider for the AES xcrypt instructions found on VIA
C5P and later cores (also known as 'ACE', which is part of the VIA PadLock
security engine). Ported from OpenBSD.

Reviewed on tech-crypto and port-i386, no objections to commiting this.

Revision 1.15.2.1, Sat Feb 17 00:28:25 2007 UTC (15 years, 11 months ago) by daniel
Branch: yamt-idlelwp
Changes since 1.15: +0 -679 lines
FILE REMOVED

file specialreg.h was added on branch yamt-idlelwp on 2007-02-17 00:28:26 +0000

Revision 1.15 / (download) - annotate - [select for diffs], Sat Feb 17 00:28:25 2007 UTC (15 years, 11 months ago) by daniel
Branch: MAIN
CVS Tags: yamt-idlelwp-base8, thorpej-atomic-base, thorpej-atomic, reinoud-bufcleanup, ad-audiomp-base, ad-audiomp
Branch point for: yamt-idlelwp, vmlocking, ppcoea-renovation, mjf-ufs-trans
Changes since 1.14: +20 -1 lines
Diff to previous 1.14 (colored)

Add an opencrypto provider for the AES xcrypt instructions found on VIA
C5P and later cores (also known as 'ACE', which is part of the VIA PadLock
security engine). Ported from OpenBSD.

Reviewed on tech-crypto and port-i386, no objections to commiting this.

Revision 1.11.6.1 / (download) - annotate - [select for diffs], Sat Feb 10 14:47:45 2007 UTC (16 years ago) by tron
Branch: netbsd-4
CVS Tags: wrstuden-fixsa-newbase, wrstuden-fixsa-base-1, wrstuden-fixsa-base, wrstuden-fixsa, netbsd-4-0-RELEASE, netbsd-4-0-RC5, netbsd-4-0-RC4, netbsd-4-0-RC3, netbsd-4-0-RC2, netbsd-4-0-RC1, netbsd-4-0-1-RELEASE, netbsd-4-0, matt-nb4-arm-base, matt-nb4-arm
Changes since 1.11: +8 -4 lines
Diff to previous 1.11 (colored) next main 1.12 (colored)

Pull up following revision(s) (requested by chs in ticket #411):
	sys/arch/x86/include/specialreg.h: revision 1.14
	sys/arch/i386/i386/identcpu.c: revision 1.53
PR/35430: Izumi Tsutsui: Identify amd64 CPU on NetBSD/i386

Revision 1.11.2.2 / (download) - annotate - [select for diffs], Thu Feb 1 08:48:12 2007 UTC (16 years ago) by ad
Branch: newlock2
Changes since 1.11.2.1: +8 -4 lines
Diff to previous 1.11.2.1 (colored) to branchpoint 1.11 (colored) next main 1.12 (colored)

Sync with head.

Revision 1.14 / (download) - annotate - [select for diffs], Tue Jan 16 15:43:44 2007 UTC (16 years ago) by christos
Branch: MAIN
CVS Tags: post-newlock2-merge, newlock2-nbase, newlock2-base
Changes since 1.13: +8 -4 lines
Diff to previous 1.13 (colored)

PR/35430: Izumi Tsutsui: Identify amd64 CPU on NetBSD/i386

Revision 1.11.2.1 / (download) - annotate - [select for diffs], Fri Jan 12 01:01:01 2007 UTC (16 years, 1 month ago) by ad
Branch: newlock2
Changes since 1.11: +46 -1 lines
Diff to previous 1.11 (colored)

Sync with head.

Revision 1.13 / (download) - annotate - [select for diffs], Thu Jan 11 17:24:30 2007 UTC (16 years, 1 month ago) by ad
Branch: MAIN
Changes since 1.12: +4 -3 lines
Diff to previous 1.12 (colored)

x86_errata: correct the definition of MSR_HWCR and re-enable. Problem
noted and debugged by Murray Armfield (murray at river-styx.org).

Revision 1.12 / (download) - annotate - [select for diffs], Mon Jan 1 20:56:59 2007 UTC (16 years, 1 month ago) by ad
Branch: MAIN
Changes since 1.11: +45 -1 lines
Diff to previous 1.11 (colored)

Report on and where possible, try to work around some of the known errata
for Athlon 64 and Opteron processors. Tested briefly by cube@ and elad@.

Revision 1.8.4.2 / (download) - annotate - [select for diffs], Sat Dec 30 20:47:22 2006 UTC (16 years, 1 month ago) by yamt
Branch: yamt-lazymbuf
Changes since 1.8.4.1: +6 -3 lines
Diff to previous 1.8.4.1 (colored) to branchpoint 1.8 (colored)

sync with head.

Revision 1.9.4.1 / (download) - annotate - [select for diffs], Sat Sep 9 02:44:36 2006 UTC (16 years, 5 months ago) by rpaulo
Branch: rpaulo-netinet-merge-pcb
Changes since 1.9: +6 -3 lines
Diff to previous 1.9 (colored) next main 1.10 (colored)

sync with head

Revision 1.9.18.1 / (download) - annotate - [select for diffs], Wed Sep 6 21:39:04 2006 UTC (16 years, 5 months ago) by riz
Branch: abandoned-netbsd-4
Changes since 1.9: +3 -1 lines
Diff to previous 1.9 (colored) next main 1.10 (colored)

Pull up following revision(s) (requested by xtraeme in ticket #111):
	sys/arch/x86/include/specialreg.h: revision 1.11
	sys/arch/i386/i386/identcpu.c: revision 1.39
	sys/arch/i386/include/cpu.h: revision 1.128
	sys/arch/i386/i386/est.c: revision 1.26
Update the enhanced speedstep driver and sync the code with OpenBSD:
est.c:
* Use a quintuplet (vendor, MHz_hi, mV_hi, MHz_lo, mV_lo } to match
  CPUs more correctly than parsing the brand string.
* Add support for a bunch of models.
* Create a fake table on the fly if the CPU is unknown (there's no
  table for it) with the current/highest/lowest frequency.
specialreg.h:
* Add some MSRs needed to get the bus clock value.
identcpu.c:
* Add functions specific to Pentium III, Pentium M and Pentium 4 to
  get the bus clock value.
Note that the new fake table code from Simon Burge is not included on
this commit.
Ok'ed by simonb and dogcow.

Revision 1.9.8.1 / (download) - annotate - [select for diffs], Sun Sep 3 15:23:37 2006 UTC (16 years, 5 months ago) by yamt
Branch: yamt-pdpolicy
Changes since 1.9: +6 -3 lines
Diff to previous 1.9 (colored) next main 1.10 (colored)

sync with head.

Revision 1.11 / (download) - annotate - [select for diffs], Sun Sep 3 06:49:57 2006 UTC (16 years, 5 months ago) by xtraeme
Branch: MAIN
CVS Tags: yamt-splraiseipl-base5, yamt-splraiseipl-base4, yamt-splraiseipl-base3, yamt-splraiseipl-base2, yamt-splraiseipl-base, yamt-splraiseipl, yamt-pdpolicy-base9, yamt-pdpolicy-base8, rpaulo-netinet-merge-pcb-base, netbsd-4-base
Branch point for: newlock2, netbsd-4
Changes since 1.10: +3 -1 lines
Diff to previous 1.10 (colored)

Update the enhanced speedstep driver and sync the code with OpenBSD:

est.c:

* Use a quintuplet (vendor, MHz_hi, mV_hi, MHz_lo, mV_lo } to match
  CPUs more correctly than parsing the brand string.
* Add support for a bunch of models.
* Create a fake table on the fly if the CPU is unknown (there's no
  table for it) with the current/highest/lowest frequency.

specialreg.h:

* Add some MSRs needed to get the bus clock value.

identcpu.c:

* Add functions specific to Pentium III, Pentium M and Pentium 4 to
  get the bus clock value.

Note that the new fake table code from Simon Burge is not included on
this commit.

Ok'ed by simonb and dogcow.

Revision 1.10 / (download) - annotate - [select for diffs], Thu Aug 24 12:55:46 2006 UTC (16 years, 5 months ago) by cube
Branch: MAIN
Changes since 1.9: +4 -3 lines
Diff to previous 1.9 (colored)

Display XD for Intel processors (Execution Disable bit support).

Revision 1.8.4.1 / (download) - annotate - [select for diffs], Wed Jun 21 14:57:56 2006 UTC (16 years, 7 months ago) by yamt
Branch: yamt-lazymbuf
Changes since 1.8: +2 -2 lines
Diff to previous 1.8 (colored)

sync with head.

Revision 1.2.2.6 / (download) - annotate - [select for diffs], Sun Dec 11 10:28:38 2005 UTC (17 years, 2 months ago) by christos
Branch: ktrace-lwp
Changes since 1.2.2.5: +2 -2 lines
Diff to previous 1.2.2.5 (colored) next main 1.3 (colored)

Sync with head.

Revision 1.9 / (download) - annotate - [select for diffs], Fri Dec 2 17:11:19 2005 UTC (17 years, 2 months ago) by christos
Branch: MAIN
CVS Tags: yamt-uio_vmspace-base5, yamt-uio_vmspace, yamt-pdpolicy-base7, yamt-pdpolicy-base6, yamt-pdpolicy-base5, yamt-pdpolicy-base4, yamt-pdpolicy-base3, yamt-pdpolicy-base2, yamt-pdpolicy-base, simonb-timecounters-base, simonb-timecounters, simonb-timcounters-final, peter-altq-base, peter-altq, ktrace-lwp-base, gdamore-uart-base, gdamore-uart, elad-kernelauth-base, elad-kernelauth, chap-midi-nbase, chap-midi-base, chap-midi, abandoned-netbsd-4-base
Branch point for: yamt-pdpolicy, rpaulo-netinet-merge-pcb, abandoned-netbsd-4
Changes since 1.8: +2 -2 lines
Diff to previous 1.8 (colored)

PR/32216: Nicolas Joly: Missing HTT feature display for Opterons dual-core CPUs

Revision 1.6.4.1 / (download) - annotate - [select for diffs], Fri Apr 29 11:28:29 2005 UTC (17 years, 9 months ago) by kent
Branch: kent-audio2
Changes since 1.6: +13 -2 lines
Diff to previous 1.6 (colored) next main 1.7 (colored)

sync with -current

Revision 1.6.6.2 / (download) - annotate - [select for diffs], Sat Mar 19 08:33:21 2005 UTC (17 years, 10 months ago) by yamt
Branch: yamt-km
Changes since 1.6.6.1: +10 -1 lines
Diff to previous 1.6.6.1 (colored) to branchpoint 1.6 (colored) next main 1.7 (colored)

sync with head.  xen and whitespace.  xen part is not finished.

Revision 1.2.2.5 / (download) - annotate - [select for diffs], Fri Mar 4 16:39:14 2005 UTC (17 years, 11 months ago) by skrll
Branch: ktrace-lwp
Changes since 1.2.2.4: +10 -1 lines
Diff to previous 1.2.2.4 (colored)

Sync with HEAD.

Hi Perry!

Revision 1.8 / (download) - annotate - [select for diffs], Mon Feb 21 15:10:51 2005 UTC (17 years, 11 months ago) by he
Branch: MAIN
CVS Tags: yamt-vop-base3, yamt-vop-base2, yamt-vop-base, yamt-vop, yamt-readahead-pervnode, yamt-readahead-perfile, yamt-readahead-base3, yamt-readahead-base2, yamt-readahead-base, yamt-readahead, yamt-km-base4, yamt-km-base3, thorpej-vnode-attr-base, thorpej-vnode-attr, netbsd-3-base, netbsd-3-1-RELEASE, netbsd-3-1-RC4, netbsd-3-1-RC3, netbsd-3-1-RC2, netbsd-3-1-RC1, netbsd-3-1-1-RELEASE, netbsd-3-1, netbsd-3-0-RELEASE, netbsd-3-0-RC6, netbsd-3-0-RC5, netbsd-3-0-RC4, netbsd-3-0-RC3, netbsd-3-0-RC2, netbsd-3-0-RC1, netbsd-3-0-3-RELEASE, netbsd-3-0-2-RELEASE, netbsd-3-0-1-RELEASE, netbsd-3-0, netbsd-3, kent-audio2-base
Branch point for: yamt-lazymbuf
Changes since 1.7: +10 -1 lines
Diff to previous 1.7 (colored)

Probe and print the Intel Extended Feature Bits, as documented
in the CPUID instruction description in the "Intel Extended Memory 64
Technology Software Developer's Guide, Volume 1 of 2" available at
ftp://download.intel.com/technology/64bitextensions/30083402.pdf

This presently consists of the SYSCALL/SYSRET and the EM64T features.
CPUs with the EM64T feature available should be able to run amd64 code.

Reviewed by fvdl

Revision 1.2.2.4 / (download) - annotate - [select for diffs], Tue Feb 15 21:33:12 2005 UTC (17 years, 11 months ago) by skrll
Branch: ktrace-lwp
Changes since 1.2.2.3: +4 -2 lines
Diff to previous 1.2.2.3 (colored)

Sync with HEAD.

Revision 1.6.6.1 / (download) - annotate - [select for diffs], Sat Feb 12 18:17:41 2005 UTC (17 years, 11 months ago) by yamt
Branch: yamt-km
Changes since 1.6: +4 -2 lines
Diff to previous 1.6 (colored)

sync with head.

Revision 1.7 / (download) - annotate - [select for diffs], Thu Feb 10 20:52:52 2005 UTC (18 years ago) by drochner
Branch: MAIN
CVS Tags: yamt-km-base2
Changes since 1.6: +4 -2 lines
Diff to previous 1.6 (colored)

Recognize an obscure cpu feature flag bit "xTPR"
which indicates that Task Priority Messages might
be disabled. Not relevant for the kernel for now
(related to interrupt distribution on the APIC bus
afaict), but present on one of my boxes.
Being here, also recognise the future "Vanderpool"
extension.

Revision 1.2.2.3 / (download) - annotate - [select for diffs], Tue Sep 21 13:24:30 2004 UTC (18 years, 4 months ago) by skrll
Branch: ktrace-lwp
Changes since 1.2.2.2: +1 -1 lines
Diff to previous 1.2.2.2 (colored)

Fix the sync with head I botched.

Revision 1.2.2.2 / (download) - annotate - [select for diffs], Sat Sep 18 14:42:37 2004 UTC (18 years, 4 months ago) by skrll
Branch: ktrace-lwp
Changes since 1.2.2.1: +0 -0 lines
Diff to previous 1.2.2.1 (colored)

Sync with HEAD.

Revision 1.2.2.1 / (download) - annotate - [select for diffs], Tue Aug 3 10:43:04 2004 UTC (18 years, 6 months ago) by skrll
Branch: ktrace-lwp
Changes since 1.2: +24 -7 lines
Diff to previous 1.2 (colored)

Sync with HEAD

Revision 1.6 / (download) - annotate - [select for diffs], Mon May 17 15:38:17 2004 UTC (18 years, 8 months ago) by joda
Branch: MAIN
CVS Tags: yamt-km-base, kent-audio1-beforemerge, kent-audio1-base, kent-audio1
Branch point for: yamt-km, kent-audio2
Changes since 1.5: +7 -4 lines
Diff to previous 1.5 (colored)

the EST and TM2 flags in the second cpuid register were swapped
(according AP-485); while here add a few more flags

Revision 1.5 / (download) - annotate - [select for diffs], Thu Feb 19 17:09:39 2004 UTC (18 years, 11 months ago) by drochner
Branch: MAIN
CVS Tags: netbsd-2-base, netbsd-2-1-RELEASE, netbsd-2-1-RC6, netbsd-2-1-RC5, netbsd-2-1-RC4, netbsd-2-1-RC3, netbsd-2-1-RC2, netbsd-2-1-RC1, netbsd-2-1, netbsd-2-0-base, netbsd-2-0-RELEASE, netbsd-2-0-RC5, netbsd-2-0-RC4, netbsd-2-0-RC3, netbsd-2-0-RC2, netbsd-2-0-RC1, netbsd-2-0-3-RELEASE, netbsd-2-0-2-RELEASE, netbsd-2-0-1-RELEASE, netbsd-2-0, netbsd-2
Changes since 1.4: +2 -1 lines
Diff to previous 1.4 (colored)

define AMD64's CPUID_NOX bit (I'm curious where Intel puts this bit in the
ia32 extension just announced)
XXX there should be a better separation between generic and vendor
specific feature flags

Revision 1.4 / (download) - annotate - [select for diffs], Mon Feb 2 08:28:00 2004 UTC (19 years ago) by soren
Branch: MAIN
Changes since 1.3: +19 -2 lines
Diff to previous 1.3 (colored)

Add Pentium M MSR definitions from Michael Eriksson.

Revision 1.3 / (download) - annotate - [select for diffs], Thu Aug 7 16:30:33 2003 UTC (19 years, 6 months ago) by agc
Branch: MAIN
Changes since 1.2: +2 -6 lines
Diff to previous 1.2 (colored)

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

Revision 1.2 / (download) - annotate - [select for diffs], Fri Apr 25 21:54:30 2003 UTC (19 years, 9 months ago) by fvdl
Branch: MAIN
Branch point for: ktrace-lwp
Changes since 1.1: +8 -3 lines
Diff to previous 1.1 (colored)

Share some common cache info cpuid code between i386 and x86_64.

Revision 1.1 / (download) - annotate - [select for diffs], Wed Feb 26 21:26:11 2003 UTC (19 years, 11 months ago) by fvdl
Branch: MAIN

Move some files out of i386 into x86, so that they can be shared with
other ports.

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