Annotation of src/sys/arch/x86/include/intr.h, Revision 1.15.14.1
1.15.14.1! yamt 1: /* $NetBSD: intr.h,v 1.15 2004/10/31 10:39:34 yamt Exp $ */
1.1 fvdl 2:
3: /*-
4: * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
5: * All rights reserved.
6: *
7: * This code is derived from software contributed to The NetBSD Foundation
8: * by Charles M. Hannum, and by Jason R. Thorpe.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed by the NetBSD
21: * Foundation, Inc. and its contributors.
22: * 4. Neither the name of The NetBSD Foundation nor the names of its
23: * contributors may be used to endorse or promote products derived
24: * from this software without specific prior written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36: * POSSIBILITY OF SUCH DAMAGE.
37: */
38:
39: #ifndef _X86_INTR_H_
40: #define _X86_INTR_H_
41:
1.5 martin 42: #ifdef _KERNEL_OPT
1.4 martin 43: #include "opt_multiprocessor.h"
1.5 martin 44: #endif
45:
1.1 fvdl 46: #include <machine/intrdefs.h>
47:
48: #ifndef _LOCORE
49: #include <machine/cpu.h>
50: #include <machine/pic.h>
51:
52: /*
53: * Struct describing an interrupt source for a CPU. struct cpu_info
54: * has an array of MAX_INTR_SOURCES of these. The index in the array
55: * is equal to the stub number of the stubcode as present in vector.s
56: *
57: * The primary CPU's array of interrupt sources has its first 16
58: * entries reserved for legacy ISA irq handlers. This means that
59: * they have a 1:1 mapping for arrayindex:irq_num. This is not
60: * true for interrupts that come in through IO APICs, to find
61: * their source, go through ci->ci_isources[index].is_pic
62: *
63: * It's possible to always maintain a 1:1 mapping, but that means
64: * limiting the total number of interrupt sources to MAX_INTR_SOURCES
65: * (32), instead of 32 per CPU. It also would mean that having multiple
66: * IO APICs which deliver interrupts from an equal pin number would
67: * overlap if they were to be sent to the same CPU.
68: */
69:
70: struct intrstub {
71: void *ist_entry;
72: void *ist_recurse;
73: void *ist_resume;
74: };
75:
76: struct intrsource {
77: int is_maxlevel; /* max. IPL for this source */
78: int is_pin; /* IRQ for legacy; pin for IO APIC */
79: struct intrhand *is_handlers; /* handler chain */
80: struct pic *is_pic; /* originating PIC */
81: void *is_recurse; /* entry for spllower */
82: void *is_resume; /* entry for doreti */
83: struct evcnt is_evcnt; /* interrupt counter */
84: char is_evname[32]; /* event counter name */
85: int is_flags; /* see below */
86: int is_type; /* level, edge */
87: int is_idtvec;
88: int is_minlevel;
89: };
90:
91: #define IS_LEGACY 0x0001 /* legacy ISA irq source */
92: #define IS_IPI 0x0002
93: #define IS_LOG 0x0004
94:
95:
96: /*
97: * Interrupt handler chains. *_intr_establish() insert a handler into
98: * the list. The handler is called with its (single) argument.
99: */
100:
101: struct intrhand {
102: int (*ih_fun)(void *);
103: void *ih_arg;
104: int ih_level;
1.14 yamt 105: int (*ih_realfun)(void *);
106: void *ih_realarg;
1.1 fvdl 107: struct intrhand *ih_next;
108: int ih_pin;
109: int ih_slot;
110: struct cpu_info *ih_cpu;
111: };
112:
113: #define IMASK(ci,level) (ci)->ci_imask[(level)]
114: #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)]
115:
1.9 junyoung 116: extern void Xspllower(int);
1.1 fvdl 117:
1.9 junyoung 118: static __inline int splraise(int);
119: static __inline void spllower(int);
120: static __inline void softintr(int);
1.1 fvdl 121:
122: /*
123: * Convert spl level to local APIC level
124: */
125: #define APIC_LEVEL(l) ((l) << 4)
126:
127: /*
128: * Add a mask to cpl, and return the old value of cpl.
129: */
130: static __inline int
131: splraise(int nlevel)
132: {
133: int olevel;
134: struct cpu_info *ci = curcpu();
135:
136: olevel = ci->ci_ilevel;
137: if (nlevel > olevel)
138: ci->ci_ilevel = nlevel;
1.15 yamt 139: __insn_barrier();
1.1 fvdl 140: return (olevel);
141: }
142:
143: /*
144: * Restore a value to cpl (unmasking interrupts). If any unmasked
145: * interrupts are pending, call Xspllower() to process them.
146: */
147: static __inline void
148: spllower(int nlevel)
149: {
150: struct cpu_info *ci = curcpu();
1.13 fvdl 151: u_int32_t imask;
152: u_long psl;
1.1 fvdl 153:
1.15 yamt 154: __insn_barrier();
1.13 fvdl 155:
156: imask = IUNMASK(ci, nlevel);
157: psl = read_psl();
158: disable_intr();
159: if (ci->ci_ipending & imask) {
1.1 fvdl 160: Xspllower(nlevel);
1.13 fvdl 161: /* Xspllower does enable_intr() */
162: } else {
163: ci->ci_ilevel = nlevel;
164: write_psl(psl);
165: }
1.1 fvdl 166: }
167:
168: /*
169: * Hardware interrupt masks
170: */
171: #define splbio() splraise(IPL_BIO)
172: #define splnet() splraise(IPL_NET)
173: #define spltty() splraise(IPL_TTY)
1.15.14.1! yamt 174: #define spllpt() spltty()
1.1 fvdl 175: #define splaudio() splraise(IPL_AUDIO)
176: #define splclock() splraise(IPL_CLOCK)
177: #define splstatclock() splclock()
178: #define splserial() splraise(IPL_SERIAL)
179: #define splipi() splraise(IPL_IPI)
1.15.14.1! yamt 180: #define splraiseipl(x) splraise(x)
1.1 fvdl 181:
182: #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x))
183:
184: /*
185: * Software interrupt masks
186: *
1.12 dbj 187: * NOTE: spllowersoftclock() is used by hardclock() to lower the priority from
1.1 fvdl 188: * clock to softclock before it calls softclock().
189: */
190: #define spllowersoftclock() spllower(IPL_SOFTCLOCK)
191:
192: #define splsoftclock() splraise(IPL_SOFTCLOCK)
193: #define splsoftnet() splraise(IPL_SOFTNET)
194: #define splsoftserial() splraise(IPL_SOFTSERIAL)
195:
196: /*
197: * Miscellaneous
198: */
1.3 thorpej 199: #define splvm() splraise(IPL_VM)
1.1 fvdl 200: #define splhigh() splraise(IPL_HIGH)
201: #define spl0() spllower(IPL_NONE)
202: #define splsched() splraise(IPL_SCHED)
203: #define spllock() splhigh()
204: #define splx(x) spllower(x)
205:
206: /*
207: * Software interrupt registration
208: *
209: * We hand-code this to ensure that it's atomic.
210: *
211: * XXX always scheduled on the current CPU.
212: */
213: static __inline void
214: softintr(int sir)
215: {
216: struct cpu_info *ci = curcpu();
217:
218: __asm __volatile("lock ; orl %1, %0" :
219: "=m"(ci->ci_ipending) : "ir" (1 << sir));
220: }
221:
222: /*
223: * XXX
224: */
225: #define setsoftnet() softintr(SIR_NET)
226:
227: /*
228: * Stub declarations.
229: */
230:
231: extern void Xsoftclock(void);
232: extern void Xsoftnet(void);
233: extern void Xsoftserial(void);
234:
235: extern struct intrstub i8259_stubs[];
1.2 fvdl 236: extern struct intrstub ioapic_edge_stubs[];
237: extern struct intrstub ioapic_level_stubs[];
1.1 fvdl 238:
239: struct cpu_info;
240:
241: extern char idt_allocmap[];
242:
1.10 fvdl 243: struct pcibus_attach_args;
244:
1.1 fvdl 245: void intr_default_setup(void);
246: int x86_nmi(void);
247: void intr_calculatemasks(struct cpu_info *);
248: int intr_allocate_slot_cpu(struct cpu_info *, struct pic *, int, int *);
249: int intr_allocate_slot(struct pic *, int, int, int, struct cpu_info **, int *,
250: int *);
251: void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *);
252: void intr_disestablish(struct intrhand *);
1.10 fvdl 253: void intr_add_pcibus(struct pcibus_attach_args *);
1.7 fvdl 254: const char *intr_string(int);
1.1 fvdl 255: void cpu_intr_init(struct cpu_info *);
1.10 fvdl 256: int intr_find_mpmapping(int, int, int *);
1.1 fvdl 257: #ifdef INTRDEBUG
258: void intr_printconfig(void);
259: #endif
260:
261: #ifdef MULTIPROCESSOR
262: int x86_send_ipi(struct cpu_info *, int);
263: void x86_broadcast_ipi(int);
264: void x86_multicast_ipi(int, int);
265: void x86_ipi_handler(void);
1.6 fvdl 266: void x86_intlock(struct intrframe *);
267: void x86_intunlock(struct intrframe *);
1.1 fvdl 268: void x86_softintlock(void);
269: void x86_softintunlock(void);
270:
271: extern void (*ipifunc[X86_NIPI])(struct cpu_info *);
272: #endif
273:
274: #endif /* !_LOCORE */
275:
276: /*
277: * Generic software interrupt support.
278: */
279:
280: #define X86_SOFTINTR_SOFTCLOCK 0
281: #define X86_SOFTINTR_SOFTNET 1
282: #define X86_SOFTINTR_SOFTSERIAL 2
283: #define X86_NSOFTINTR 3
284:
285: #ifndef _LOCORE
286: #include <sys/queue.h>
287:
288: struct x86_soft_intrhand {
289: TAILQ_ENTRY(x86_soft_intrhand)
290: sih_q;
291: struct x86_soft_intr *sih_intrhead;
292: void (*sih_fn)(void *);
293: void *sih_arg;
294: int sih_pending;
295: };
296:
297: struct x86_soft_intr {
298: TAILQ_HEAD(, x86_soft_intrhand)
299: softintr_q;
300: int softintr_ssir;
301: struct simplelock softintr_slock;
302: };
303:
304: #define x86_softintr_lock(si, s) \
305: do { \
306: (s) = splhigh(); \
307: simple_lock(&si->softintr_slock); \
308: } while (/*CONSTCOND*/ 0)
309:
310: #define x86_softintr_unlock(si, s) \
311: do { \
312: simple_unlock(&si->softintr_slock); \
313: splx((s)); \
314: } while (/*CONSTCOND*/ 0)
315:
316: void *softintr_establish(int, void (*)(void *), void *);
317: void softintr_disestablish(void *);
318: void softintr_init(void);
319: void softintr_dispatch(int);
320:
321: #define softintr_schedule(arg) \
322: do { \
323: struct x86_soft_intrhand *__sih = (arg); \
324: struct x86_soft_intr *__si = __sih->sih_intrhead; \
325: int __s; \
326: \
327: x86_softintr_lock(__si, __s); \
328: if (__sih->sih_pending == 0) { \
329: TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \
330: __sih->sih_pending = 1; \
331: softintr(__si->softintr_ssir); \
332: } \
333: x86_softintr_unlock(__si, __s); \
334: } while (/*CONSTCOND*/ 0)
335: #endif /* _LOCORE */
336:
337: #endif /* !_X86_INTR_H_ */
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