CVS log for src/sys/arch/x86/include/cpu.h

Up to [cvs.NetBSD.org] / src / sys / arch / x86 / include

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Introduce vm_guest_is_pvh() and use it in place of
	(vm_guest == VM_GUEST_XENPVH || vm_guest == VM_GUEST_GENPVH)

Add support for non-Xen PVH guests to amd64. Patch from
Emile 'iMil' Heitor in PR kern/57813, with some cosmetic tweaks by me.
Tested on bare metal, Xen PV and Xen PVH by me.

Pull up following revision(s) (requested by maya in ticket #316):

	sys/arch/m68k/include/mutex.h: revision 1.13
	sys/arch/arm/include/cpu.h: revision 1.125
	sys/arch/sun68k/include/intr.h: revision 1.21
	sys/arch/arm/include/mutex.h: revision 1.28
	sys/sys/rwlock.h: revision 1.18
	sys/arch/powerpc/include/mutex.h: revision 1.7
	sys/arch/arm/include/mutex.h: revision 1.29
	sys/arch/powerpc/include/mutex.h: revision 1.8
	sys/uvm/uvm_param.h: revision 1.42
	sys/sys/ksem.h: revision 1.16
	sys/arch/x86/include/mutex.h: revision 1.10
	sys/sys/proc.h: revision 1.372
	sys/sys/ksem.h: revision 1.17
	sys/arch/ia64/include/mutex.h: revision 1.8
	sys/arch/evbarm/include/intr.h: revision 1.29
	sys/sys/lua.h: revision 1.9
	sys/arch/next68k/include/intr.h: revision 1.23
	sys/arch/ia64/include/mutex.h: revision 1.9
	sys/arch/hp300/include/intr.h: revision 1.35
	sys/arch/hp300/include/intr.h: revision 1.36
	sys/arch/sparc/include/cpu.h: revision 1.111
	sys/arch/hppa/include/mutex.h: revision 1.16
	sys/arch/vax/include/intr.h: revision 1.31
	sys/arch/hppa/include/mutex.h: revision 1.17
	sys/arch/news68k/include/intr.h: revision 1.28
	sys/arch/hppa/include/mutex.h: revision 1.18
	sys/arch/hppa/include/intr.h: revision 1.3
	sys/arch/hppa/include/mutex.h: revision 1.19
	sys/arch/hppa/include/intr.h: revision 1.4
	sys/sys/sched.h: revision 1.92
	sys/opencrypto/cryptodev.h: revision 1.51
	sys/arch/vax/include/mutex.h: revision 1.20
	sys/arch/sparc64/include/mutex.h: revision 1.10
	sys/arch/ia64/include/sapicvar.h: revision 1.2
	sys/arch/riscv/include/mutex.h: revision 1.5
	sys/arch/amiga/dev/grfabs_cc.c: revision 1.39
	sys/external/bsd/drm2/include/linux/idr.h: revision 1.11
	sys/arch/riscv/include/mutex.h: revision 1.6
	sys/ddb/files.ddb: revision 1.16
	sys/arch/mac68k/include/intr.h: revision 1.32
	share/man/man4/ddb.4: revision 1.203
	sys/ddb/db_command.c: revision 1.183
	sys/arch/mips/include/mutex.h: revision 1.10
	sys/ddb/db_command.c: revision 1.184
	sys/arch/x68k/include/intr.h: revision 1.22
	sys/arch/sparc/include/psl.h: revision 1.51
	sys/arch/or1k/include/mutex.h: revision 1.4
	sys/arch/mips/include/mutex.h: revision 1.11
	sys/arch/arm/xscale/pxa2x0_intr.h: revision 1.16
	sys/arch/sparc64/include/cpu.h: revision 1.134
	sys/arch/sparc/include/psl.h: revision 1.52
	sys/arch/or1k/include/mutex.h: revision 1.5
	sys/arch/mvme68k/include/intr.h: revision 1.22
	sys/arch/luna68k/include/intr.h: revision 1.16
	external/cddl/osnet/sys/sys/kcondvar.h: revision 1.6
	sys/arch/sparc/include/mutex.h: revision 1.12
	sys/arch/sparc/include/mutex.h: revision 1.13
	sys/arch/usermode/include/mutex.h: revision 1.5
	sys/arch/usermode/include/mutex.h: revision 1.6
	sys/kern/kern_core.c: revision 1.38
	usr.sbin/crash/Makefile: revision 1.49
	sys/arch/amiga/include/intr.h: revision 1.23
	sys/arch/alpha/include/mutex.h: revision 1.12
	sys/arch/alpha/include/mutex.h: revision 1.13
	sys/arch/evbarm/lubbock/sacc_obio.c: revision 1.16
	sys/ddb/ddb.h: revision 1.6
	sys/arch/sparc64/include/mutex.h: revision 1.8
	sys/arch/sh3/include/mutex.h: revision 1.12
	sys/arch/evbarm/lubbock/sacc_obio.c: revision 1.17
	sys/ddb/db_syncobj.c: revision 1.1
	sys/arch/vax/include/mutex.h: revision 1.18
	sys/arch/sparc64/include/psl.h: revision 1.63
	sys/arch/sparc64/include/mutex.h: revision 1.9
	sys/arch/sh3/include/mutex.h: revision 1.13
	sys/arch/evbarm/lubbock/obio.c: revision 1.13
	sys/arch/atari/include/intr.h: revision 1.23
	sys/ddb/db_syncobj.c: revision 1.2
	sys/arch/vax/include/mutex.h: revision 1.19
	sys/arch/evbarm/g42xxeb/obio.c: revision 1.14
	sys/arch/evbarm/g42xxeb/obio.c: revision 1.15
	sys/arch/cesfic/include/intr.h: revision 1.14
	sys/ddb/db_syncobj.h: revision 1.1
	sys/arch/x86/include/cpu.h: revision 1.134
	sys/arch/evbarm/g42xxeb/obio.c: revision 1.16
	sys/arch/cesfic/include/intr.h: revision 1.15
	sys/arch/arm/xscale/pxa2x0_intr.c: revision 1.26
	sys/sys/cpu_data.h: revision 1.54
	sys/arch/m68k/include/mutex.h: revision 1.12
	sys/arch/ia64/acpi/madt.c: revision 1.6

sys/rwlock.h: Make this more self-contained for bool.

machine/mutex.h: Sprinkle includes so this can be used by crash(8).

ddb: New `show all tstiles' command.
Shows who's waiting for which locks and what the owner is up to.

Include psl.h for ipl_cookie_t if __MUTEX_PRIVATE

sys: Rip <sys/resourcevar.h> out of <uvm/uvm_param.h>.

And thus out of <sys/param.h>, which is exceedingly overused and
fragile and delenda est.

Should fix (some) issues with the recent inclusion of machine/lock.h
in various machine/mutex.h files.

arm/mutex.h: Need machine/intr.h, machine/lock.h.

For ipl_cookie_t and __cpu_simple_lock_t.
evbarm/intr.h: Define ipl_cookie_t before including ARM_INTR_IMPL.

Otherwise arm/mutex.h doesn't work, due to a cyclic dependency which
should really be fixed.
opencrypto/cryptodev.h: Fix includes.
- Move sys/condvar.h under #ifdef _KERNEL.
- Add some other necessary includes and forward declarations.
- Sort.

hp300/intr.h: Fix missing includes.
linux/idr.h: Need <sys/mutex.h> for kmutex_t.
amiga/intr.h: Don't define spl*() functions if !_KERNEL.

This is used by crash(8) now, and what's important is ipl_cookie_t.
cesfic/intr.h: Expose ipl_cookie_t to userland for crash(8).
cesfic/intr.h: Expose ipl_cookie_t to userland only with _KMEMUSER.

Probably not necessary but let's be a little more cautious about
this.

atari/intr.h: Expose ipl_cookie_t with _KMEMUSER for crash(8).

arm/cpu.h: Need sys/param.h for COHERENCY_UNIT.

Nix machine/param.h -- not meant to be used directly, pulled in by
sys/param.h.

Move the definition of ipl_cookie_t out of the kernel-only sections,
some _KMEMUSER applications need it.

ddb: Cast pointer to uintptr_t first before db_expr_t.

hppa/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

luna68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

mvme68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

news68k/intr.h: Fix includes.  Put some definitions under _KERNEL.

next68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

sys/ksem.h: Hack around fstat(8) abuse of _KERNEL.

sun68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

vax/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

x68k/intr.h: Put functions under _KERNEL so crash(8) can use this.

Make ipl_cookie_t visible for _KMEMUSER userland applications.

fix editor mishap in previous

Explicitly include <sys/mutex.h> for kmutex_t.

Replace kmutex_t * (which may be undefined here) with struct kmutex *,
suggested by Taylor.

hp300/intr.h: Put most of this under #ifdef _KERNEL.
Only ipl_cookie_t really needs to be exposed now, for crash(8).

mac68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).
Make inclusion of sys/intr.h explicit for spl*.

fix hppa and vax builds.

machine/lock.h isn't necessary for __cpu_simple_lock_t, it's in
sys/types.h.  avoids cpu_data.h vs sched.h include order issues.

move the hppa ipl_t typedef with the moved usage of it.
machine/mutex.h: Sprinkle sys/types.h, omit machine/lock.h.

Turns out machine/lock.h is not needed for __cpu_simple_lock_t, which
always comes from sys/types.h.  And, really, sys/types.h (or at least
sys/stdint.h) is needed for uintN_t and uintptr_t.

ddb: Cast pointer to uintptr_t, then to db_expr_t.
Avoids warnings about conversion between pointer and integer of
different size on some architectures.

re-fix hppa builds.

this file uses __cpu_simple_lock(), not just the underlying type,
so it does need machine/lock.h.

Break cycle by using `struct kmutex *' instead of `kmutex_t *'.
sys/sched.h included sys/mutex.h
which includes sys/intr.h
which includes machine/intr.h
which on cats includes arm/footbridge/footbridge_intr.h
which includes arm/cpu.h
which includes sys/cpu_data.h
which includes sys/sched.h

But there was never any real need for sys/mutex.h in sys/sched.h,
because it only uses pointers to the opaque struct kmutex.  Cycle
broken by using `struct kmutex *' instead of pulling in sys/mutex.h
for the definition of kmutex_t.

Side effect: This revealed that sys/cpu_data.h needed sys/intr.h
(which was pulled in accidentally by sys/mutex.h via sys/sched.h) for
SOFTINT_COUNT.  Also revealed some other machine/cpu.h header files
were missing includes of sys/mutex.h for kmutex_t.

ia64: Need sys/types.h for u_int, vaddr_t; sys/mutex.h for kmutex_t.

explicitly include no longer implicitly included sys/mutex.h.

arm/xscale: Use sys/bitops.h fls32 - 1 instead of 31 - __builtin_clz.
Sidesteps namespace collision with `#define bits ...' in net/zlib.c.

complete the previous - there were two calls to find_first_bit() to fix.

arm/xscale: Missed a spot with previous find_first_bit commit.

evbarm/g42xxeb: Fix off-by-one in previous.

The original find_first_bit(x) was 31 - __builtin_clz((uint32_t)x),
which is equivalent to fls32(x) - 1, not to fls32(x).

Note that fls32 is 1-based and returns 0 for x=0.

xen: Report when hardclock jump exceeds timecounter(9) limit.

xen: Record event when local view of timecounter is behind global.

Break cycle by using `struct kmutex *' instead of `kmutex_t *'.

sys/sched.h included sys/mutex.h
which includes sys/intr.h
which includes machine/intr.h
which on cats includes arm/footbridge/footbridge_intr.h
which includes arm/cpu.h
which includes sys/cpu_data.h
which includes sys/sched.h

But there was never any real need for sys/mutex.h in sys/sched.h,
because it only uses pointers to the opaque struct kmutex.  Cycle
broken by using `struct kmutex *' instead of pulling in sys/mutex.h
for the definition of kmutex_t.

Side effect: This revealed that sys/cpu_data.h needed sys/intr.h
(which was pulled in accidentally by sys/mutex.h via sys/sched.h) for
SOFTINT_COUNT.  Also revealed some other machine/cpu.h header files
were missing includes of sys/mutex.h for kmutex_t.

NetBSD/x86: Raise the number of interrupt sources per CPU from 32 to 56.

There has been no objection for three years.
    https://mail-index.netbsd.org/port-amd64/2019/09/22/msg003012.html
Implemented by nonaka@n.o, updated by me.

Pull up the following (all via patch), requested by msaitoh in ticket #1721:

	usr.sbin/cpuctl/arch/i386.c			1.118-1.119, 1.121-1.122
	usr.sbin/cpuctl/arch/cpuctl_i386.h		1.6
	sys/arch/x86/x86/identcpu_subr.c		1.8-1.9
	sys/arch/x86/x86/identcpu.c			1.123
	sys/arch/x86/include/cacheinfo.h		1.30
	sys/arch/x86/include/cpu.h			1.132

- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.

Pull up the following (all via patch), requested by msaitoh in ticket #1396:

	usr.sbin/cpuctl/arch/i386.c			1.118-1.119, 1.121-1.122
	usr.sbin/cpuctl/arch/cpuctl_i386.h		1.6
	sys/arch/x86/x86/identcpu_subr.c		1.8-1.9
	sys/arch/x86/x86/identcpu.c			1.123
	sys/arch/x86/include/cacheinfo.h		1.30
	sys/arch/x86/include/cpu.h			1.132

- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.

Move some common functions into x86/identcpu_subr.c. No functional change.

Improved the performance of kernel profiling on MULTIPROCESSOR, and possible to get profiling data for each CPU.

In the current implementation, locks are acquired at the entrance of the mcount
internal function, so the higher the number of cores, the more lock conflict
occurs, making profiling performance in a MULTIPROCESSOR environment unusable
and slow. Profiling buffers has been changed to be reserved for each CPU,
improving profiling performance in MP by several to several dozen times.

- Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers.
- Add ci_gmon member to struct cpu_info of each MP arch.
- Add kern.profiling.percpu node in sysctl tree.
- Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd.
  For compatibility, if the -c option is not specified, the entire system can be
  operated as before, and the -p option will get the total profiling data for
  all CPUs.

Sync with HEAD.

Identify VirtualBox as a separate guest type.

PR/55547: Dan Plassche: Fix BSD/OS binary emulation.
Centralize lcall sniffer and recognize the BSD/OS flavor.

Pull up the following revisions, requested by msaitoh in ticket #1593:

	sys/arch/x86/conf/files.x86			1.108
	sys/arch/x86/include/apicvar.h			1.7 via patch
	sys/arch/x86/include/cpu.h			1.121
	sys/arch/x86/x86/cpu.c				1.185 via patch
	sys/arch/x86/x86/hyperv.c			1.7
	sys/arch/x86/x86/tsc.c				1.41
	sys/arch/xen/conf/files.xen			1.181

Get TSC frequency from CPUID 0x15 and/or x16 if it's available.
This change fixes a problem that newer Intel processors' timer
counts very slowly.

don't include opt_user_ldt.h when it is not needed

Pull up the following, requested by msaitoh in ticket #1015

	sys/arch/x86/conf/files.x86			1.108 (via patch)
	sys/arch/x86/include/apicvar.h			1.7 (via patch)
	sys/arch/x86/include/cpu.h			1.121 (via patch)
	sys/arch/x86/x86/cpu.c				1.185 (via patch)
	sys/arch/x86/x86/hyperv.c			1.7 (via patch)
	sys/arch/x86/x86/tsc.c				1.41 (via patch)
	sys/arch/xen/conf/files.xen			1.181 (via patch)

Get TSC frequency from CPUID 0x15 and/or x16 if it's available.
This change fixes a problem that newer Intel processors' timer
counts very slowly.

Introduce per-cpu IDTs

This is realized by following modifications:
- Add IDT pages and its allocation maps for each cpu in "struct cpu_info"
- Load per-cpu IDTs at cpu_init_idt(struct cpu_info*)
- Copy the IDT entries for cpu0 to other CPUs at attach
   - These are, for example, exceptions, db, system calls, etc.

And, added a kernel option named PCPU_IDT to enable the feature.

localify

Introduce Xen PVH support in GENERIC.
This is compiled in with
options XENPVHVM
x86 changes:
- add Xen section and xen pvh entry points to locore.S. Set vm_guest
  to VM_GUEST_XENPVH in this entry point.
  Most of the boot procedure (especially page table setup and switch to
  paged mode) is shared with native.
- change some x86_delay() to delay_func(), which points to x86_delay() for
  native/HVM, and xen_delay() for PVH

Xen changes:
- remove Xen bits from init_x86_64_ksyms() and init386_ksyms()
  and move to xen_init_ksyms(), used for both PV and PVH
- set ISA no-legacy-devices property for PVH
- factor out code from Xen's cpu_bootconf() to xen_bootconf()
  in xen_machdep.c
- set up a specific pvh_consinit() which starts with printk()
  (which uses a simple hypercall that is available early) and switch to
  xencons when we can use pmap_kenter_pa().

Don't #include xen/intrdefs.h is !XEN.
Should fix third-party module builds (e.g. virtualbox)

Move ci_vcpu under the #ifdef XEN section at the end of the struct cpu_info.
Hopefully will fix the nvmm module.

Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
guests in GENERIC.
Xen support can be disabled at runtime with
boot -c
disable hypervisor

Sync with bouyer-xenpvh-base2 (HEAD)

Sync with HEAD

Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.

 - If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
   can take TSC/core crystal clock ratio but core crystal clock frequency
   can't be taken. Intel SDM give us the values for some processors.
 - It also required to change lapic_per_second to make LAPIC timer correctly.
 - Add new file x86/x86/identcpu_subr.c to share common subroutines between
   kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
   will be moved to this file in future.
 - Add comment to clarify.

Add PVHVM multiprocessor support:
We need the hypervisor to be set up before cpus attaches.
Move hypervisor setup to a new function xen_hvm_init(), called at the
beggining of mainbus_attach(). This function searches the cfdata[] array
to see if the hypervisor device is enabled (so you can disable PV
support with
disable hypervisor
from userconf).
For HVM, ci_cpuid doens't match the virtual CPU index needed by Xen.
Introduce ci_vcpuid to cpu_info. Introduce xen_hvm_init_cpu(), to be
called for each CPU in in its context, which initialize ci_vcpuid and
ci_vcpu, and setup the event callback.
Change Xen code to use ci_vcpuid.

Do not call lapic_calibrate_timer() for VM_GUEST_XENPVHVM, we will use
Xen timers.

Don't call lapic_initclocks() from cpu_hatch(); instead set
x86_cpu_initclock_func to lapic_initclocks() in lapic_calibrate_timer(),
and call *(x86_cpu_initclock_func)() from cpu_hatch().
Also call x86_cpu_initclock_func from cpu_attach() for the boot CPU.
As x86_cpu_initclock_func is called for all CPUs, x86_initclock_func can
be a NOP for lapic timer.

Reorganize Xen code for x86_initclock_func/x86_cpu_initclock_func.
Move x86_cpu_idle_xen() to hypervisor_machdep.c

Avoid overflow of ci_ipi_events[] in the PVHVM case (it's size is
XEN_NIPIS but we use x86 IPIs): size XEN_NIPIS only for PV, and
CTASSERT that XEN_NIPIS <= X86_NIPI if we ever use Xen IPIs for
PVHVM.

By default, events are bound to CPU 0 (exept for IPIs and VTIMERs which
are bound to a different CPU at creation time).
Recent MI changes caused the scheduler to choose a different CPU when
probing and attaching xennet devices (I guess it's the xenbus thread which
runs on a different CPU). This cause the callback to be called on a different
CPU than the one expected by the kernel, and the event is ignored.
It is handled when the clock causes the callback to be called on the right
CPU, which is why xennet still run, but slowly.

Change event_set_handler() to do a EVTCHNOP_bind_vcpu if requested to,
and make sure we don't do it for IPIs and VIRQs (for theses, the op fails).

Mostly merge changes from HEAD upto 20200411

Get rid of xen-specific ci_x* interrupt handling:
- use the general SIR mechanism, reserving 3 more slots for IPL_VM, IPL_SCHED
  and IPL_HIGH
- remove specific handling from C sources, or change to ipending
- convert IPL number to SIR number in various places
- Remove XUNMASK/XPENDING in assembly or change to IUNMASK/IPENDING
- remove Xen-specific ci_xsources, ci_xmask, ci_xunmask, ci_xpending from
  struct cpu_info
- for now remove a KASSERT that there are no pending interrupts in
  idle_block(). We can get there with some software interrupts pending
  in autoconf XXX needs to be looked at.

Include ci_isources[] for XenPV too.
Adjust spllower() to XenPV needs, and switch XenPV to the native spllower().
Remove xen_spllower().

Skip cx8_spllower patch if we're running on any form of Xen PV,
we can't handle PV interrupts with a single atomic op here.
Enable x86_patch() for Xen too.

Revert, wrong branch

Skip cx8_spllower patch if we're running on any form of Xen PV,
we can't handle PV interrupts with a single atomic op here.
Enable x86_patch() for Xen too.

Remove VM_GUEST_XEN and define only Xen subtypes:
VM_GUEST_XENPV
VM_GUEST_XENPVH
VM_GUEST_XENHVM
VM_GUEST_XENPVHVM

Set vm_guest in the start routine, if it is hypervisor-specific (e.g Xen PV).
If vm_guest was not set early and we detect Xen in identify_hypervisor(),
assume it is VM_GUEST_XENHVM. Refine to VM_GUEST_PVXENHVM in
hypervisor_match().

Sync with head.

Push the INVLPG limit for shootdowns up to 16 (for UBC).

Fix a problem with intr_unmask() that can cause a forever-loop:
- When handling the source-is-masked case in the interrupt vector, set the
  interrupt bit in a new ci_imasked field and ensure the bit is cleared
  from ci_ipending.
- In intr_unmask(), transfer the bit from ci_imasked to ci_ipending for
  non-level-sensitive interrupts (the PIC does the work for us in the
  level-sensitive case), and only force pending interrupts to be processed
  in this case.  (In all cases, make sure the now-unmasked bit is cleared
  from ci_imasked.)

Before, the bit was left in ci_ipending so as not to use edge-triggered
interrupts while the source is masked, but Xspllower() relies on the
pending bits getting cleared.

Tested by forcing all wm(4) interrupts on my test system though an
intr_mask() / softint / intr_unmask() cycle and exercising the network
heavily.

Fix false sharing problems with cpu_info.  Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
  the IPI bitmask and ci_want_resched.

Add a small API for in-kernel FPU operations.

	fpu_kern_enter();
	/* do FPU stuff */
	fpu_kern_leave();

cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

x86 TLB shootdown IPI changes:

- Shave some time off processing.
- Reduce cacheline/bus traffic on systems with many CPUs.
- Reduce time spent at IPL_VM.

mi_userret(): take care of calling preempt(), set spc_curpriority directly,
and remove MD code that does the same.

Rewrite the FPU code on x86. This greatly simplifies the logic and removes
the dependency on IPL_HIGH. NVMM is updated accordingly. Posted on
port-amd64 a week ago.

Bump the kernel version to 9.99.16.

Remove the LazyFPU code, as posted 5 months ago on port-amd64@.

Add support for USER_LDT in SVS. This allows us to have both enabled at
the same time.

We allocate an LDT for each CPU in the GDT and map an area for it, in
addition to the default LDT already present. In context switches between
different processes, we choose between the default or the per-cpu LDT
selector: if the user set specific LDT entries, we memcpy them to the
per-cpu LDT and load the per-cpu selector.

Tested by Naveen Narayanan (with Wine on amd64).

Fetch XSAVE area component offsets and sizes when initializing x86 CPU

Introduce two new arrays, x86_xsave_offsets and x86_xsave_sizes,
and initialize them with XSAVE area component offsets and sizes queried
via CPUID.  This will be needed to implement getters and setters for
additional register types.

While at it, add XSAVE_* constants corresponding to specific XSAVE
components.

Sync with HEAD

Remove 'ci_svs_kpdirpa', unused. While here fix a few comments here and
there, reduces a future diff.

Pull up following revision(s) via patch (requested by nonaka in ticket #1210):

	sys/dev/hyperv/vmbusvar.h: revision 1.1
	sys/dev/hyperv/hvs.c: revision 1.1
	sys/dev/hyperv/if_hvn.c: revision 1.1
	sys/dev/hyperv/vmbusic.c: revision 1.1
	sys/arch/x86/x86/lapic.c: revision 1.69
	sys/arch/x86/isa/clock.c: revision 1.34
	sys/arch/x86/include/intrdefs.h: revision 1.22
	sys/arch/i386/conf/GENERIC: revision 1.1201
	sys/arch/x86/x86/hyperv.c: revision 1.1
	sys/arch/x86/include/cpu.h: revision 1.105
	sys/arch/x86/x86/x86_machdep.c: revision 1.124
	sys/arch/i386/conf/GENERIC: revision 1.1203
	sys/arch/amd64/amd64/genassym.cf: revision 1.74
	sys/arch/i386/conf/GENERIC: revision 1.1204
	sys/arch/amd64/conf/GENERIC: revision 1.520
	sys/arch/x86/x86/hypervreg.h: revision 1.1
	sys/arch/amd64/amd64/vector.S: revision 1.69
	sys/dev/hyperv/hvshutdown.c: revision 1.1
	sys/dev/hyperv/hvshutdown.c: revision 1.2
	sys/dev/usb/if_urndisreg.h: file removal
	sys/arch/x86/x86/cpu.c: revision 1.167
	sys/arch/x86/conf/files.x86: revision 1.107
	sys/dev/usb/if_urndis.c: revision 1.20
	sys/dev/hyperv/vmbusicreg.h: revision 1.1
	sys/dev/hyperv/hvheartbeat.c: revision 1.1
	sys/dev/hyperv/vmbusicreg.h: revision 1.2
	sys/dev/hyperv/hvheartbeat.c: revision 1.2
	sys/dev/hyperv/files.hyperv: revision 1.1
	sys/dev/ic/rndisreg.h: revision 1.1
	sys/arch/i386/i386/genassym.cf: revision 1.111
	sys/dev/ic/rndisreg.h: revision 1.2
	sys/dev/hyperv/hyperv_common.c: revision 1.1
	sys/dev/hyperv/hvtimesync.c: revision 1.1
	sys/dev/hyperv/hypervreg.h: revision 1.1
	sys/dev/hyperv/hvtimesync.c: revision 1.2
	sys/dev/hyperv/vmbusicvar.h: revision 1.1
	sys/dev/hyperv/if_hvnreg.h: revision 1.1
	sys/arch/x86/x86/lapic.c: revision 1.70
	sys/arch/amd64/amd64/vector.S: revision 1.70
	sys/dev/ic/ndisreg.h: revision 1.1
	sys/arch/amd64/conf/GENERIC: revision 1.516
	sys/dev/hyperv/hypervvar.h: revision 1.1
	sys/arch/amd64/conf/GENERIC: revision 1.518
	sys/arch/amd64/conf/GENERIC: revision 1.519
	sys/arch/i386/conf/files.i386: revision 1.400
	sys/dev/acpi/vmbus_acpi.c: revision 1.1
	sys/dev/hyperv/vmbus.c: revision 1.1
	sys/dev/hyperv/vmbus.c: revision 1.2
	sys/arch/x86/x86/intr.c: revision 1.144
	sys/arch/i386/i386/vector.S: revision 1.83
	sys/arch/amd64/conf/files.amd64: revision 1.112

separate RNDIS definitions from urndis(4) for use with Hyper-V NetVSC.

 -

Added Microsoft Hyper-V support.  It ported from OpenBSD and FreeBSD.
graphical console is not work on Gen.2 VM yet. To use the serial console,
enter "consdev com,0x3f8,115200" on efiboot.

 -

Add __diagused.

 -

PR/53984: Partial revert of modify lapic_calibrate_timer() in lapic.c r1.69.

 -

Update Hyper-V related drivers description.

 -

Remove unused definition.

 -

Rename the MODULE_*_HOOK() macros to MODULE_HOOK_*() as briefly
discussed on irc.
NFCI intended.

 -

commented out hvkvp entry.

 -

fix typo. pointed out by pgoyette@n.o.

 -

Use IDTVEC instead of NENTRY for handle_hyperv_hypercall.

 -

Rename the MODULE_*_HOOK() macros to MODULE_HOOK_*() as briefly
discussed on irc.

Added Microsoft Hyper-V support.  It ported from OpenBSD and FreeBSD.

graphical console is not work on Gen.2 VM yet. To use the serial console,
enter "consdev com,0x3f8,115200" on efiboot.

Welcome XENPVHVM mode.

It is UP only, has xbd(4) and xennet(4) as PV drivers.

The console is com0 at isa and the native portion is very
rudimentary AT architecture, so is probably suboptimal to
run without PV support.

We reorganise definitions for XEN source support as follows:

XEN - common sources required for baseline XEN support.
XENPV - sources required for support of XEN in PV mode.
XENPVHVM - sources required for support for XEN in HVM mode.
XENPVH - sources required for support for XEN in PVH mode.

Switch NetBSD/xen to use XEN api tag RELEASE-4.11.1

The headers for this api are in sys/external/mit/xen-include-public/dist/

Sync with HEAD, resolve a few conflicts

Excise XEN specific code out of x86/x86/intr.c into xen/x86/xen_intr.c

While at it, separate the source function tracking so that the interrupt
paths are truly independant.

Use weak symbol exporting to provision for future PVHVM co-existence
of both files, but with independant paths. Introduce assembler code
such that in a unified scenario, native interrupts get first priority
in spllower(), followed by XEN event callbacks. IPL management and
semantics are unchanged - native handlers and xen callbacks are
expected to maintain their ipl related semantics.

In summary, after this commit, native and XEN now have completely
unrelated interrupt handling mechanisms, including
intr_establish_xname() and assembler stubs and intr handler
management.

Happy Christmas!

Sync with HEAD, resolve a couple of conflicts

On Xen, copy just the bits we need from the trapframe for hardclock(9)
and statclock(9).

Current, the macros that use the trapframe are:
CLKF_USERMODE()
CLKF_PC()
CLKF_INTR()

Of these, CLKF_INTR() already ignores the frame and uses the ci_idepth
variable to do its job.

Convert the two remaining ones to do this, but only for XEN.

Save the interrupt trap/clockframe to a per-cpu copy.

We can use this copy to pass on the trapframe to hardclock(9) from
within the xen timer handler. This delinks the current dependency
between MD code and the handler, which is specially prototyped to take
the clockframe unlike any other handler.

This change has performance implications, as each interrupt entry will
copy the entire trapframe over to the per-cpu cached copy. This can be
mitigated by selectively copying just the parts of the clockframe that
are used by hardclock() et. al.

Tested on amd64 XEN domU

Sync with head

Pull up following revision(s) (requested by msaitoh in ticket #1636):
	sys/arch/x86/include/cacheinfo.h: 1.23-1.26
	sys/arch/x86/include/cpu.h: 1.70
	sys/arch/x86/include/specialreg.h: 1.91-1.93,1.98,1.100,1.102-1.124,1.126,1.130 via patch
	sys/arch/x86/x86/cpu_topology.c: 1.10
	sys/arch/x86/x86/identcpu.c: 1.56-1.57,1.70 via patch
	usr.sbin/cpuctl/arch/i386.c: 1.71,1.75-1.79,1.81-1.85 via patch
Add some register definitions for x86:
  - Add CLWB bit.
  - Fix a few (unused) MSR values, and add some bit definitions of
    MSR_EFER from Murray Armfield in PR#42861.
  - CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify
    comments and snprintb() string.
  - Define CPUID Fn00000001 %ebx bits and use them.
    No functional change.
  - Add Structured Extended Flags Enumeration Leaf's bit definitions:
    AVX512_{IFMA,VBMI2,VNNI,BITALG,VPOPCNTDQ,4VNNIW,4FMAPS},GFNI&VAES.
  - Add Turbo Boost Max Technology 3.0 bit.
  - Add AMD SVM features definitions.
  - Add Intel cpuid 7 %edx IBRS and STIBP bit definitions.
  - Fix swapped comments for EFER LME and LMA
  - Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
  - Add MSR_IA32_ARCH_CAPABILITIES definition.
  - Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.
  - Add Intel Deterministic Address Translation Parameter Leaf(0x18)
    definitions.
  - s/CLFUSH/CLFLUSH/
  - Add AMD's Disable Indirect Branch Predictor bit definition.
  - Add the MSR bits definitions for IBRS, STIBP and IBPB.
  - Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
  - Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.
  - Add AMD's CPUID Fn80000001 %edx MMX and FXSR bit definitions.
  - Add RDCL_NO and IBRS_ALL.
  - Add SSBD and RSBA bit definitions.
  - Add AMD's SSB bit definitions for F15H, F16H and F17H.
  - Add cpuid 7 edx L1D_FLUSH bit.
  - Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
  - Add IA32_FLUSH_CMD MSR.
  - Add yet another Shared L2 TLB (2M/4M pages).
  - Add 3way and 6way of L2 cache or TLB on AMD CPU.
  - AMD L3 cache association bitfield is not 8bit but 4bit like others
    association bitfields.
  - Sort entries. No functional change.
  - Modify comment, fix typo in comment and add comment.
cpuctl(8):
  - Add detection for Quark X1000, Xeon E5 v4, E7 v4,
    Core i7-69xx Extreme Edition, Xeon Scalable (Skylake),
    Xeon Phi [357]200 (Knights Landing), Atom (Goldmont),
    Atom (Denverton), Future Core (Cannon Lake), Atom (Goldmont Plus),
    Xeon Phi 7215, 7285 and 7295 (Knights Mill) and
    7th or 8th gen Core (Kaby Lake, Coffee Lake).
  - Print Structured Extended Feature leaf Fn0000_0007 %ebx on AMD,too.
  - Print Fn0000_0007 %ecx on Intel.
  - Print Intel cpuid 7 %edx.
  - Parse the TLB info from `cpuid leaf 18H' on Intel processor.
  - Use aprint_error_dev() for error output.

export x86_fpu_mxcsr_mask, fpu_area_save and fpu_area_restore

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

- Cleanup for dynamic sysctl:
  - Remove unused *_NAMES macros for sysctl.
  - Remove unused *_MAXID for sysctls.
- Move CTL_MACHDEP sysctl definitions for m68k into m68k/include/cpu.h and
  use them on all m68k machines.

Sync with HEAD

More rearrangement of struct cpu_info to keep all the un-conditional
members at fixed locations.

Should address my PR kern/52919

OK maxv@

XXX kernel version bump coming momentarily.

Hum. Move the __HAVE_DIRECT_MAP block a little below, otherwise dynamically
loaded kernel modules use a wrong offset for some ci_* fields. Found when
modloading tprof_amd on an AMD 10h, the read of ci_signature was at a
wrong address, and the cpu family was not detected correctly.

Just use struct cpu_info members for the Xen clock state.

Silly to use percpu(9) for some things and struct cpu_info for
others.

Rewrite Xen timecounter and hardclock timer.

With this change, the Xen timecounter should now be globally
monotonic, as every timecounter is supposed to be.  Should also fix a
litany of races in the timecounter logic.

Proposed last year; see mailing list for further details:
https://mail-index.netbsd.org/port-xen/2017/10/31/msg009112.html

ok cherry

Sync with HEAD

Pull up the following, via patch, requested by maxv in ticket #897:

	sys/arch/amd64/amd64/locore.S           1.166 (patch)
	sys/arch/i386/i386/locore.S             1.157 (patch)
	sys/arch/x86/include/cpu.h              1.92 (patch)
	sys/arch/x86/include/fpu.h              1.9 (patch)
	sys/arch/x86/x86/fpu.c                  1.33-1.39 (patch)
	sys/arch/x86/x86/identcpu.c             1.72 (patch)
	sys/arch/x86/x86/vm_machdep.c           1.34 (patch)
	sys/arch/x86/x86/x86_machdep.c          1.116,1.117 (patch)

Support eager fpu switch, to work around INTEL-SA-00145.
Provide a sysctl machdep.fpu_eager, which gets automatically
initialized to 1 on affected CPUs.

Add some code to support eager fpu switch, INTEL-SA-00145. We restore the
FPU state of the lwp right away during context switches. This guarantees
that when the CPU executes in userland, the FPU doesn't contain secrets.

Maybe we also need to clear the FPU in setregs(), not sure about this one.

Can be enabled/disabled via:

	machdep.fpu_eager = {0/1}

Not yet turned on automatically on affected CPUs (Intel Family 6).

More generally it would be good to turn it on automatically when XSAVEOPT
is supported, because in this case there is probably a non-negligible
performance gain; but we need to fix PR/52966.

Pullup the following revisions, requested by maxv in ticket #865:

	sys/arch/amd64/amd64/machdep.c		1.303 (patch)
	sys/arch/amd64/conf/GENERIC		1.492 (patch)
	sys/arch/amd64/conf/files.amd64		1.103 (patch)
	sys/arch/i386/i386/machdep.c		1.806 (patch)
	sys/arch/i386/conf/GENERIC		1.1179 (patch)
	sys/arch/i386/conf/files.i386		1.393 (patch)
	sys/arch/x86/include/cpu.h		1.91 (patch)
	sys/arch/x86/include/specialreg.h	upto 1.126 (patch)
	sys/arch/x86/x86/x86_machdep.c		upto 1.115 (patch, adapted)
	sys/arch/x86/x86/spectre.c		upto 1.19 (patch, adapted,
						no IBRS,
						SpectreV2 mitigations not
						enabled	by default)

Backport the hardware SpectreV2 and SpectreV4 mitigations.

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Enable the SpectreV2 mitigation by default at boot time.

Pull up following revision(s) (requested by maxv in ticket #681):
	sys/arch/x86/include/cpu.h: revision 1.90
	sys/arch/x86/x86/identcpu.c: revision 1.71
Retrieve cpuid.7:%edx.

Retrieve cpuid.7:%edx.

Pull up the following revisions, requested by maxv in ticket #652:

	sys/arch/amd64/amd64/amd64_trap.S	upto 1.39 (partial, patch)
	sys/arch/amd64/amd64/db_machdep.c	1.6 (patch)
	sys/arch/amd64/amd64/genassym.cf	1.65,1.66,1.67 (patch)
	sys/arch/amd64/amd64/locore.S		upto 1.159 (partial, patch)
	sys/arch/amd64/amd64/machdep.c		1.299-1.302 (patch)
	sys/arch/amd64/amd64/trap.c		upto 1.113 (partial, patch)
	sys/arch/amd64/amd64/amd64/vector.S	upto 1.61 (partial, patch)
	sys/arch/amd64/conf/GENERIC		1.477,1.478 (patch)
	sys/arch/amd64/conf/kern.ldscript	1.26 (patch)
	sys/arch/amd64/include/frameasm.h	upto 1.37 (partial, patch)
	sys/arch/amd64/include/param.h		1.25 (patch)
	sys/arch/amd64/include/pmap.h		1.41,1.43,1.44 (patch)
	sys/arch/x86/conf/files.x86		1.91,1.93 (patch)
	sys/arch/x86/include/cpu.h		1.88,1.89 (patch)
	sys/arch/x86/include/pmap.h		1.75 (patch)
	sys/arch/x86/x86/cpu.c			1.144,1.146,1.148,1.149 (patch)
	sys/arch/x86/x86/pmap.c			upto 1.289 (partial, patch)
	sys/arch/x86/x86/vm_machdep.c		1.31,1.32 (patch)
	sys/arch/x86/x86/x86_machdep.c		1.104,1.106,1.108 (patch)
	sys/arch/x86/x86/svs.c			1.1-1.14
	sys/arch/xen/conf/files.compat		1.30 (patch)

Backport SVS. Not enabled yet.

Pull up following revision(s) (requested by msaitoh in ticket #1118):
	sys/arch/x86/include/cpuvar.h: revision 1.47
	sys/arch/x86/x86/cpu.c: revision 1.117
	sys/arch/x86/x86/identcpu.c: revision 1.49
	sys/arch/x86/include/cpu.h: revision 1.67

Retrieve cpuid7 (Structured Extended Features) into ci_feat_val.

Pull up the following revisions (via patch), requested by maxv in #635:

	sys/arch/amd64/amd64/gdt.c		1.39-1.45 (patch)
	sys/arch/amd64/amd64/amd64/machdep.c	1.284,1.287,1.288 (patch)
	sys/arch/amd64/amd64/include/param.h	1.23 (patch)
	sys/arch/amd64/include/types.h		1.53 (patch)
	sys/arch/x86/include/cpu.h		1.87 (patch)
	sys/arch/x86/include/pmap.h		1.73,1.74 (patch)
	sys/arch/x86/x86/cpu.c			1.142 (patch)
	sys/arch/x86/x86/intr.c			1.117 (partial),1.120 (patch)
	sys/arch/x86/x86/pmap.c			1.276 (patch)

Initialize ist0 in cpu_init_tss.
Backport __HAVE_PCPU_AREA.

Pullup the following revisions via patch, requested by maxv in ticket #629:

	sys/arch/amd64/amd64/genassym.cf		1.63,1.64
	sys/arch/amd64/amd64/locore.S			1.144
	sys/arch/amd64/amd64/machdep.c			1.281-1.283
	sys/arch/i386/i386/genassym.cf			1.105-1.106
	sys/arch/i386/i386/locore.S			1.155
	sys/arch/i386/i386/machdep.c			1.802 (adapted),1.803
	sys/arch/x86/include/cpu.h			1.85
	sys/arch/x86/x86/intr.c				1.115-1.116
	sys/arch/x86/x86/pmap.c				1.275
	sys/arch/x86/x86/sys_machdep.c			1.45
	sys/arch/xen/x86/cpu.c				1.117

Stop sharing the double-fault stack.
Merge the TSS structures into one single cpu_tss structure, and
allocate it dynamically.

Pull up following revision(s) (requested by maxv in ticket #611):
	sys/arch/x86/x86/cpu.c: revision 1.134 (patch)
	sys/arch/x86/include/cpu.h: revision 1.78 (patch)
	sys/arch/i386/i386/machdep.c: revision 1.792 (patch)

style, and move some i386-specific code into i386/

Unmap the kernel heap from the user page tables (SVS).

This implementation is optimized and organized in such a way that we
don't need to copy the kernel stack to a safe place during user<->kernel
transitions. We create two VAs that point to the same physical page; one
will be mapped in userland and is offset in order to contain only the
trapframe, the other is mapped in the kernel and maps the entire stack.

Sent on tech-kern@ a week ago.

Add a new option, SVS (for Separate Virtual Space), that unmaps kernel
pages when running in userland. For now, only the PTE area is unmapped.

Sent on tech-kern@.

Add a __HAVE_PCPU_AREA option, enabled by default on native amd64 but not
Xen.

With this option, the CPU structures that must always be present in the
CPU's page tables are moved on L4 slot 384, which means address
0xffffc00000000000.

A new pcpu_area structure is defined. It contains shared structures (IDT,
LDT), and then an array of pcpu_entry structures, indexed by cpu_index(ci).
Theoretically the LDT should be in the array, but this will be done later.

During the boot procedure, cpu0 calls pmap_init_pcpu, which creates a
page tree that is able to map the pcpu_area structure entirely. cpu0 then
immediately maps the shared structures. Later, every CPU goes through
cpu_pcpuarea_init, which allocates physical pages and kenters the relevant
pcpu_entry to them. Finally, each pointer is replaced to point to pcpuarea.

The point of this change is to make sure that the structures that must
always be present in the page tables have their own L4 slot. Until now
their L4 slot was that of pmap_kernel, and making a distinction between
what must be mapped and what does not need to be was complicated.

Even in the non-speculative-bug case this change makes some sense: there
are several x86 instructions that leak the addresses of the CPU structures,
and putting these structures inside pmap_kernel actually offered a way to
compute the address of the kernel heap - which would have made ASLR on it
plainly useless, had we implemented that.

Note that, for now, pcpuarea does not contain rsp0.

Unfortunately this change adds many #ifdefs, and makes the code harder to
understand. There is also some duplication, but that will be solved later.

Allocate the TSS area dynamically. This way cpu_info and cpu_tss can be
put in separate pages.

Group the different TSSes into a cpu_tss structure. And pack this
structure to make sure there is no padding between 'tss' and 'iomap'.

typos

update from HEAD

Add padding to make the 32/64 bit structs the same.

Remove unused fields, there is no alignment we need to enforce.

Restore removed sysctl(2) x86 entry: fpu_present

Hardcode it to 1 for now on i386 and amd64.

This unbreaks software that used it (e.g. LLDB).

Removal noted by <christos>

PR lib/52756 by myself

GC i386_fpu_present. no FPU x86 is not supported.

Also delete newly unused send_sigill

Move xpq_idx into cpu_info, to prevent false sharing between CPUs. Saves
10s when doing a './build.sh -j 3 kernel=GENERIC' on xen-amd64-domU.

Sync with HEAD

style, and move some i386-specific code into i386/

Localify. By the way, we should use a different stack for NMIs.

Remove vm86.

Pass 3.

Call _proc0_tss_ldt_init only once, and rename them.

2302677

file cpu.h was added on branch perseant-stdc-iso10646 on 2017-07-16 14:02:49 +0000

Unify the xen and native x86/ interrupt setup functions and
spl traversal data structures.

This is towards PVHVM.

dumpconf(void) long doesn't exist, remove the prototype

PR kern/39714 by Henning Petersen

if __HIDE_DELAY is defined, do not define delay() or DELAY().
needed by dtrace and ZFS.

x86: hypervisor detection from FreeBSD for x2APIC support.

Resolve conflicts from previous merge (all resulting from $NetBSD
keywork expansion)

 CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify comments
and snprintb() sring.

Sync with HEAD

Sync with HEAD

x86: Export fpu_save, fpu_save_size, xsave_features to dedicated sysctl nodes

Add new defines:
 - CPU_FPU_SAVE (15)
   int: FPU Instructions layout
   * to use this, CPU_OSFXSR must be true
   * 0: FSAVE
   * 1: FXSAVE
   * 2: XSAVE
   * 3: XSAVEOPT
 - CPU_FPU_SAVE_SIZE (16)
   int: FPU Instruction layout size
 - CPU_XSAVE_FEATURES (17)
   quad: FPU XSAVE features

Bump CPU_MAXID from 15 to 18.

These values were prepared originally to be exported without ASCIIZ name to
be used as handler. These values are useful to get FPU accessors in a
debugger easier to implement on x86 (PT_SETFPREG, PT_GETFPREG).

This interface handles all supported x86 targets. In the older (i386) and
less featured CPUs check first osfxsr (OS uses FXSAVE/FXRSTOR).

According to sys/arch/x86/include/cpu.h r.1.65 this was prepared to be
exported beyond simple CTL_CREATE node.

Sponsored by <The NetBSD Foundation>

Sync with HEAD

Instead of using a global array with per-cpu indexes, embed the tmp VAs
into cpu_info directly. This concerns only {i386, Xen-i386, Xen-amd64},
because amd64 already has a direct map that is way faster than that.

There are two major issues with the global array: maxcpus entries are
allocated while it is unlikely that common i386 machines have so many
cpus, and the base VA of these entries is not cache-line-aligned, which
mostly guarantees cache-line-thrashing each time the VAs are entered.

Now the number of tmp VAs allocated is proportionate to the number of CPUs
attached (which therefore reduces memory consumption), and the base is
properly aligned.

On my 3-core AMD, the number of DC_refills_L2 events triggered when
performing 5x10^6 calls to pmap_zero_page on two dedicated cores is on
average divided by two with this patch.

Discussed on tech-kern a little.

Pull up following revision(s) (requested by msaitoh in ticket #1118):
	sys/arch/x86/include/cpuvar.h: revision 1.47
	sys/arch/x86/x86/cpu.c: revision 1.117
	sys/arch/x86/x86/identcpu.c: revision 1.49
	sys/arch/x86/include/cpu.h: revision 1.67
Retrieve cpuid7 (Structured Extended Features) into ci_feat_val.

Sync with HEAD (as of 26th Dec)

Retrieve cpuid7 (Structured Extended Features) into ci_feat_val.

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Rename (the recently added) 'x86_xsave_size' to 'x86_fpu_save_size'
  and default to 512 (the size of the fxsave structure).

Determine whether the cpu supports xsave (and hence AVX).
The result is only written to sysctl nodes at the moment.
I see:
machdep.fpu_save = 3 (implies xsaveopt)
machdep.xsave_size = 832
machdep.xsave_features = 7
Completely common up the i386 and amd64 machdep sysctl creation.

Re-use the unused ci_cpu_serial[3] to save the highest cpuid values
  for the normal and extended leafs.
(The 'normal' one might be luring in the global cpulevel.)
Read the 'extended feature' from cpuid.80000001.%ecx/edx into
    ci_feat_val[3/2] just after saving cpuid.1.%ecx/dx in ci_feat_val[1/0]
    instead of doing it separately for amd k678 and via c3 processors
    in their probe functions and repeating it for all cpus a few instructions
    later when x86_cpu_topology() is called.
x86_cpu_topology() is only called from cpu_probe() and really doesn't
  deserve its own source file. Chasing the setup code is bad enough anyway.

This needs stdint.h in userspace (for uint64_t)

Remove all references to MDL_USEDFPU and deferred fpu initialisation.
The cost of zeroing the save area on exec is minimal.
This stops the FP registers of a random process being used the first
  time an lwp uses the fpu.
sendsig_siginfo() and get_mcontext() now unconditionally copy the FP
registers.
I'll remove the double-copy for signal handlers soon.
get_mcontext() might have been leaking kernel memory to userspace - and
  may still do so if i386_use_fxsave is false (short copies).

Change i386 to use x86/fpu.c instead of i386/isa/npx.c
This changes the trap10 and trap13 code to call directly into fpu.c,
  removing all the code for T_ARITHTRAP, T_XMM and T_FPUNDA from i386/trap.c
Not all of the code thate appeared to handle fpu traps was ever called!
Most of the changes just replace the include of machine/npx.h with x86/fpu.h
  (or remove it entirely).

There is no need to check for recursive calls into fpudna().
Rename the associated ci_fpsaving field to 'unused'.
I'm not sure they could ever happen, you could get unwanted calls into
  the fpu trap code while saving state when using INT13 - but these are
  different.
The return value from the i386 fpudna() was always 1 - possibly a historic
  relic of the kernel fp emulation. Remove and don't check in trap.S.
The amd64 and i386 fpudna() code is now almost identical.

Remove support for 'external' floating point units and the MS-DOS
  compatible method of handling floating point exceptions.
Make kernel support for teh fpu non-optional (486SX should still work).
Only 386 cpus support external fpu, and i386 support was removed years ago.
This means that the npx code no longer uses port 0xf0 or interupt 13.
All the "npx at isa" lines go from the configs, arch/i386/isa/npx.c
  is now mandatory for all i386 kernels.
I've renamed npxinit() to fpuinit() and npxinit_cpu() to fpuinit_cpu()
  to match the very similar amd64 functions.
The fpu of the boot cpu is now initialised by a direct call from
  cpu_configure(), this enables FP emulation for a 486SX.
  (for amd64 the cr0 values are set in locore.S and similar).
This fixes a long-standing bug in linux_setregs() - which did not
  save the fpu regsiters if they were active.
I've test booted a single cpu i386 kernel (using anita).
amd64 builds - none of teh changes should affect it.
The i386 XEN kernels build, but I'm not sure where they set cr0, and
  it might have got lost!

revert fpu/pcu changes until we figure out what's wrong; they cause random
freezes

use __unused instead of __USE and void cast to mark iterator variable unused
where needed (from phone)

initialize cii before using it.

Use the MI "pcu" framework for bookkeeping of npx/fpu states on x86.
This reduces the amount of MD code enormously, and makes it easier
to implement support for newer CPU features which require more fpu
state, or for fpu usage by the kernel.
For access to FPU state across CPUs, an xcall kthread is used now
rather than a dedicated IPI.
No user visible changes intended.

__USE() unused variables

Resync to 2012-11-19 00:00:00 UTC

sync with head

split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

Rename MDP_IRET to MDL_IRET since it is an lwp flag, not a proc one.
Add an MDL_COMPAT32 flag to the lwp's md_flags, set it for 32bit lwps
  and use it to force 'return to user' with iret (as is done when
  MDL_IRET is set).
Split the iret/sysret code paths much later.
Remove all the replicated code for 32bit system calls - which was only
  needed so that iret was always used.
frameasm.h for XEN contains '#define swapgs', while XEN probable never
  needs swapgs, this is likely to be confusing.
Add a SWAPGS which is a nop on XEN and swapgs otherwise.
(I've not yet checked all the swapgs in files that include frameasm.h)
Simple x86 programs still work.
Hijack 6.99.9 kernel bump (needed for compat32 modules)

rename the global variable "cpu" to "cputype" to avoid conflicting with
dtrace, which wants to use "cpu" as a local variable.

sync with head.

Pull up following revision(s) (requested by rmind in ticket #202):
	sys/arch/x86/include/cpuvar.h: revision 1.46
	sys/arch/xen/include/xenpmap.h: revision 1.34
	sys/arch/i386/include/param.h: revision 1.77
	sys/arch/x86/x86/pmap_tlb.c: revision 1.5
	sys/arch/x86/x86/pmap_tlb.c: revision 1.6
	sys/arch/i386/i386/genassym.cf: revision 1.92
	sys/arch/xen/x86/cpu.c: revision 1.91
	sys/arch/x86/x86/pmap.c: revision 1.177
	sys/arch/xen/x86/xen_pmap.c: revision 1.21
	sys/arch/x86/acpi/acpi_wakeup.c: revision 1.31
	sys/kern/subr_kcpuset.c: revision 1.5
	sys/arch/amd64/include/param.h: revision 1.18
	sys/sys/kcpuset.h: revision 1.5
	sys/arch/x86/x86/mtrr_i686.c: revision 1.26
	sys/arch/x86/x86/mtrr_i686.c: revision 1.27
	sys/arch/xen/x86/x86_xpmap.c: revision 1.43
	sys/arch/x86/x86/cpu.c: revision 1.98
	sys/arch/amd64/amd64/mptramp.S: revision 1.14
	sys/kern/sys_sched.c: revision 1.42
	sys/arch/amd64/amd64/genassym.cf: revision 1.50
	sys/arch/i386/i386/mptramp.S: revision 1.24
	sys/arch/x86/include/pmap.h: revision 1.52
	sys/arch/x86/include/cpu.h: revision 1.50
- Convert x86 MD code, mainly pmap(9) e.g. TLB shootdown code, to use
  kcpuset(9) and thus replace hardcoded CPU bitmasks.  This removes the
  limitation of maximum CPUs.
- Support up to 256 CPUs on amd64 architecture by default.
Bug fixes, improvements, completion of Xen part and testing on 64-core
AMD Opteron(tm) Processor 6282 SE (also, as Xen HVM domU with 128 CPUs)
by Manuel Bouyer.
- pmap_tlb_shootdown: do not overwrite tp_cpumask with pm_cpus, but merge
  like pm_kernel_cpus.  Remove unecessary intersection with kcpuset_running.
  Do not reset tp_userpmap if pmap_kernel().
- Remove pmap_tlb_mailbox_t wrapping, which is pointless after recent changes.
- pmap_tlb_invalidate, pmap_tlb_intr: constify for packet structure.
i686_mtrr_init_first: handle the case when there are no variable-size MTRR
registers available (i686_mtrr_vcnt == 0).

sync to latest -current.

- Convert x86 MD code, mainly pmap(9) e.g. TLB shootdown code, to use
  kcpuset(9) and thus replace hardcoded CPU bitmasks.  This removes the
  limitation of maximum CPUs.

- Support up to 256 CPUs on amd64 architecture by default.

Bug fixes, improvements, completion of Xen part and testing on 64-core
AMD Opteron(tm) Processor 6282 SE (also, as Xen HVM domU with 128 CPUs)
by Manuel Bouyer.

sync with head

sync to -current

sync to -current

Pull up the following revisions(s) (requested by bouyer in ticket #80):
	sys/arch/xen/x86/x86_xpmap.c:	revision 1.42
	sys/arch/x86/include/specialreg.h:	revision 1.56
	sys/arch/amd64/amd64/machdep.c:	revision 1.179
	sys/arch/i386/i386/locore.S:	revision 1.97
	sys/arch/i386/i386/machdep.c:	revision 1.723 via patch
	sys/arch/x86/include/cpu.h:	revision 1.49

Fix possible FPU registers corruption on context switches.
Fix type of pointers passed to some hypercalls.

sync to latest -current.

Follow locore.S and move FPU handling from x86_64_switch_context() to
x86_64_tls_switch(); raise IPL to IPL_HIGH in x86_64_switch_context()
and test ci_fpcurlwp to decide to disable FPU or not.
Change the Xen i386 context switch code to be like the amd64 one.

Pull up following revision(s) (requested by bouyer in ticket #29):
	sys/arch/xen/x86/x86_xpmap.c: revision 1.39
	sys/arch/xen/include/hypervisor.h: revision 1.37
	sys/arch/xen/include/intr.h: revision 1.34
	sys/arch/xen/x86/xen_ipi.c: revision 1.10
	sys/arch/x86/x86/cpu.c: revision 1.97
	sys/arch/x86/include/cpu.h: revision 1.48
	sys/uvm/uvm_map.c: revision 1.315
	sys/arch/x86/x86/pmap.c: revision 1.165
	sys/arch/xen/x86/cpu.c: revision 1.81
	sys/arch/x86/x86/pmap.c: revision 1.167
	sys/arch/xen/x86/cpu.c: revision 1.82
	sys/arch/x86/x86/pmap.c: revision 1.168
	sys/arch/xen/x86/xen_pmap.c: revision 1.17
	sys/uvm/uvm_km.c: revision 1.122
	sys/uvm/uvm_kmguard.c: revision 1.10
	sys/arch/x86/include/pmap.h: revision 1.50
Apply patch proposed in PR port-xen/45975 (this does not solve the exact
problem reported here but is part of the solution):
xen_kpm_sync() is not working as expected,
leading to races between CPUs.
1 the check (xpq_cpu != &x86_curcpu) is always false because we
  have different x86_curcpu symbols with different addresses in the kernel.
  Fortunably, all addresses dissaemble to the same code.
  Because of this we always use the code intended for bootstrap, which doesn't
  use cross-calls or lock.
2 once 1 above is fixed, xen_kpm_sync() will use xcalls to sync other CPUs,
  which cause it to sleep and pmap.c doesn't like that. It triggers this
  KASSERT() in pmap_unmap_ptes():
  KASSERT(pmap->pm_ncsw == curlwp->l_ncsw);
3 pmap->pm_cpus is not safe for the purpose of xen_kpm_sync(), which
  needs to know on which CPU a pmap is loaded *now*:
  pmap->pm_cpus is cleared before cpu_load_pmap() is called to switch
  to a new pmap, leaving a window where a pmap is still in a CPU's
  ci_kpm_pdir but not in pm_cpus. As a virtual CPU may be preempted
  by the hypervisor at any time, it can be large enough to let another
  CPU free the PTP and reuse it as a normal page.
To fix 2), avoid cross-calls and IPIs completely, and instead
use a mutex to update all CPU's ci_kpm_pdir from the local CPU.
It's safe because we just need to update the table page, a tlbflush IPI will
happen later. As a side effect, we don't need a different code for bootstrap,
fixing 1). The mutex added to struct cpu needs a small headers reorganisation.
to fix 3), introduce a pm_xen_ptp_cpus which is updated from
cpu_pmap_load(), whith the ci_kpm_mtx mutex held. Checking it with
ci_kpm_mtx held will avoid overwriting the wrong pmap's ci_kpm_pdir.
While there I removed the unused pmap_is_active() function;
and added some more details to DIAGNOSTIC panics.
When using uvm_km_pgremove_intrsafe() make sure mappings are removed
before returning the pages to the free pool. Otherwise, under Xen,
a page which still has a writable mapping could be allocated for
a PDP by another CPU and the hypervisor would refuse it (this is
PR port-xen/45975).
For this, move the pmap_kremove() calls inside uvm_km_pgremove_intrsafe(),
and do pmap_kremove()/uvm_pagefree() in batch of (at most) 16 entries
(as suggested by Chuck Silvers on tech-kern@, see also
http://mail-index.netbsd.org/tech-kern/2012/02/17/msg012727.html and
followups).
Avoid early use of xen_kpm_sync(); locks are not available at this time.
Don't call cpu_init() twice.
Makes LOCKDEBUG kernels boot again
Revert pmap_pte_flush() -> xpq_flush_queue() in previous.

merge to -current.

Apply patch proposed in PR port-xen/45975 (this does not solve the exact
problem reported here but is part of the solution):
xen_kpm_sync() is not working as expected,
leading to races between CPUs.
1 the check (xpq_cpu != &x86_curcpu) is always false because we
  have different x86_curcpu symbols with different addresses in the kernel.
  Fortunably, all addresses dissaemble to the same code.
  Because of this we always use the code intended for bootstrap, which doesn't
  use cross-calls or lock.

2 once 1 above is fixed, xen_kpm_sync() will use xcalls to sync other CPUs,
  which cause it to sleep and pmap.c doesn't like that. It triggers this
  KASSERT() in pmap_unmap_ptes():
  KASSERT(pmap->pm_ncsw == curlwp->l_ncsw);
3 pmap->pm_cpus is not safe for the purpose of xen_kpm_sync(), which
  needs to know on which CPU a pmap is loaded *now*:
  pmap->pm_cpus is cleared before cpu_load_pmap() is called to switch
  to a new pmap, leaving a window where a pmap is still in a CPU's
  ci_kpm_pdir but not in pm_cpus. As a virtual CPU may be preempted
  by the hypervisor at any time, it can be large enough to let another
  CPU free the PTP and reuse it as a normal page.

To fix 2), avoid cross-calls and IPIs completely, and instead
use a mutex to update all CPU's ci_kpm_pdir from the local CPU.
It's safe because we just need to update the table page, a tlbflush IPI will
happen later. As a side effect, we don't need a different code for bootstrap,
fixing 1). The mutex added to struct cpu needs a small headers reorganisation.

to fix 3), introduce a pm_xen_ptp_cpus which is updated from
cpu_pmap_load(), whith the ci_kpm_mtx mutex held. Checking it with
ci_kpm_mtx held will avoid overwriting the wrong pmap's ci_kpm_pdir.

While there I removed the unused pmap_is_active() function;
and added some more details to DIAGNOSTIC panics.

Xen clock management routines keep track of CPU (following MP merge).
Reflect this change in the suspend/resume routines so they can cope with
domU CPU suspend, instead of setting their cpu_info pointer to NULL.

Avoid copy/pasting by using the resume routines during attachement.

ok releng@.

No regression observed, and allows domU to suspend successfully again.
Restore is a different beast as PD/PT flags are marked "invalid" by Xen-4
hypervisor, and blocks resuming. Looking into it.

stop using alternate pde mapping in xen pmap

Move the per-cpu l3 page allocation code to a separate MD function. Avoids code duplication for xen PAE

switch from xen3-public to xen-public.

[merging from cherry-xenmp] bring in bouyer@'s changes via:
http://mail-index.netbsd.org/source-changes/2011/10/22/msg028271.html
From the Log:
Log Message:
Various interrupt fixes, mainly:
keep a per-cpu mask of enabled events, and use it to get pending events.
A cpu-specific event (all of them at this time) should not be ever masked
by another CPU, because it may prevent the target CPU from seeing it
(the clock events all fires at once for example).

sync with head

Turn the 'i386_use_pae' variable into simply 'use_pae'. Technically
speaking we are also running with PAE enabled in long mode under amd64,
so this variable will be used in various places across x86 machdep to
branch at runtime to functions that require extra handling for PAE mode.

[merging from cherry-xenmp] make pmap_kernel() shadow PMD per-cpu and MP aware.

Reduce exposure of kernel internals for __KMEMUSER

Various interrupt fixes, mainly:
keep a per-cpu mask of enabled events, and use it to get pending events.
A cpu-specific event (all of them at this time) should not be ever masked
by another CPU, because it may prevent the target CPU from seeing it
(the clock events all fires at once for example).

add a "vm" device class for cpufeaturebus

Merge jym-xensuspend branch in -current. ok bouyer@.

Goal: save/restore support in NetBSD domUs, for i386, i386 PAE and amd64.

Executive summary:
- split all Xen drivers (xenbus(4), grant tables, xbd(4), xennet(4))
in two parts: suspend and resume, and hook them to pmf(9).
- modify pmap so that Xen hypervisor does not cry out loud in case
it finds "unexpected" recursive memory mappings
- provide a sysctl(7), machdep.xen.suspend, to command suspend from
userland via powerd(8). Note: a suspend can only be handled correctly
when dom0 requested it, so provide a mechanism that will prevent
kernel to blindly validate user's commands

The code is still in experimental state, use at your own risk: restore
can corrupt backend communications rings; this can completely thrash
dom0 as it will loop at a high interrupt level trying to honor
all domU requests.

XXX PAE suspend does not work in amd64 currently, due to (yet again!)
page validation issues with hypervisor. Will fix.

XXX secondary CPUs are not suspended, I will write the handlers
in sync with cherry's Xen MP work.

Tested under i386 and amd64, bear in mind ring corruption though.

No build break expected, GENERICs and XEN* kernels should be fine.
./build.sh distribution still running. In any case: sorry if it does
break for you, contact me directly for reports.

fix %cr3 init. from mhitch@, tested by riz@ & mhitch@

Sync with HEAD. Most notably: uvm/pmap work done by rmind@, and MP Xen
work of cherry@.

No regression observed on suspend/restore.

PAE MP support (preliminary), amd64 per-cpu L4 model redesigned, i386 pmap_pa_start/end fixup

Pullup relevant changes from -current

Hide the MD details of specific IPIs behind semantically pleasing functions. This cleans up a couple of #ifdef XEN/#endif pairs

Add Xen specific members to struct cpu_info, Add proper per-cpu curcpu() functionality

Introduce a per-cpu "shadow" for pmap_kernel()'s L4 page

Catchup with rmind-uvmplock merge.

Welcome to 5.99.53!  Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
  New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
  the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
  Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
  kernel-lock on some ports).  Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

sync with head

Sync with HEAD.

Initial import of xen MP sources, with kernel and userspace tests.
 - this is a source priview.
 - boots to single user.
 - spurious interrupt and pmap related panics are normal

Don't use the C preprocessor to configure USERCONF.  Instead, either do
or do not link in subr_userconf.c and x86_userconf.c.

Provide no-op stubs for userconf_bootinfo(), userconf_init(), and
userconf_prompt().

Delete all occurrences of #include "opt_userconf.h" as well as USERCONF
and __HAVE_USERCONF_BOOTINFO #ifdef'age.

sync with head

Support userconf(4) command in boot(8)/boot.cfg(5) on i386/amd64.

From jmmv@, no objections seen in the proposed thread:

	http://mail-index.netbsd.org/tech-kern/2009/01/22/msg004081.html

bring matt-nb5-mips64 up to date with netbsd-5-1-RELEASE (except compat).

Sync with head.

sync with head

move the include sys/types.h xor stdbool.h to the top of the file,
so that "bool" will be present when used later in the file.

Sync with HEAD. TODO before merge:
- shortcut for suspend code in sysmon, when powerd(8) is not running.
Borrow ``xs_watch'' thread context?
- bug hunting in xbd + xennet resume. Rings are currently thrashed upon
resume, so current implementation force flush them on suspend. It's not
really needed.

sync with head

Sync with HEAD

Fix autoconf(9) of cpufeaturebus.

Move ENHANCED_SPEEDSTEP, or henceforth est(4), to the cpufeaturebus.

Modularize coretemp(4). Ok jmcneill@.

cpu.h no longer needs via_padlock.h

modularize VIA PadLock support
 - retire options VIA_PADLOCK, replace with 'padlock0 at cpu0'
 - driver supports attach & detach
 - support building as a module

Sync with HEAD

Make __HAVE_CPU_DATA_FIRST true

Sync with HEAD

Sync with HEAD (-D20101022).

sync with head

Sync with HEAD.

Add machdep.pae sysctl(7) for i386. Thanks to Paul and Joerg for their
reviews.

In kernel, it matches the 'i386_use_pae' variable (0: kernel does not use
PAE, 1: kernel uses PAE). Will be used by i386 kvm(3) to know the functions
that should get called for VA => PA translations.

sync with head.

Store the MADT-derived CPU ID to <x86/cpu.h>. This is required to properly
match the ACPI processor object ID with the ID available in the APIC table.

Welcome PAE inside i386 current.

This patch is inspired by work previously done by Jeremy Morse, ported by me
to -current, merged with the work previously done for port-xen, together with
additionals fixes and improvements.

PAE option is disabled by default in GENERIC (but will be enabled in ALL in
the next few days).

In quick, PAE switches the CPU to a mode where physical addresses become
36 bits (64 GiB). Virtual address space remains at 32 bits (4 GiB). To cope
with the increased size of the physical address, they are manipulated as
64 bits variables by kernel and MMU.

When supported by the CPU, it also allows the use of the NX/XD bit that
provides no-execution right enforcement on a per physical page basis.

Notes:

- reworked locore.S

- introduce cpu_load_pmap(), used to switch pmap for the curcpu. Due to the
different handling of pmap mappings with PAE vs !PAE, Xen vs native, details
are hidden within this function. This helps calling it from assembly,
as some features, like BIOS calls, switch to pmap_kernel before mapping
trampoline code in low memory.

- some changes in bioscall and kvm86_call, to reflect the above.

- the L3 is "pinned" per-CPU, and is only manipulated by a
reduced set of functions within pmap. To track the L3, I added two
elements to struct cpu_info, namely ci_l3_pdirpa (PA of the L3), and
ci_l3_pdir (the L3 VA). Rest of the code considers that it runs "just
like" a normal i386, except that the L2 is 4 pages long (PTP_LEVELS is
still 2).

- similar to the ci_pae_l3_pdir{,pa} variables, amd64's xen_current_user_pgd
becomes an element of cpu_info (slowly paving the way for MP world).

- bootinfo_source struct declaration is modified, to cope with paddr_t size
change with PAE (it is not correct to assume that bs_addr is a paddr_t when
compiled with PAE - it should remain 32 bits). bs_addrs is now a
void * array (in bootloader's code under i386/stand/, the bs_addrs
is a physaddr_t, which is an unsigned long).

- fixes in multiboot code (same reason as bootinfo): paddr_t size
change. I used Elf32_* types, use RELOC() where necessary, and move the
memcpy() functions out of the if/else if (I do not expect sym and str tables
to overlap with ELF).

- 64 bits atomic functions for pmap

- all pmap_pdirpa access are now done through the pmap_pdirpa macro. It
hides the L3/L2 stuff from PAE, as well as the pm_pdirpa change in
struct pmap (it now becomes a PDP_SIZE array, with or without PAE).

- manipulation of recursive mappings ( PDIR_SLOT_{,A}PTEs ) is done via
loops on PDP_SIZE.

See also http://mail-index.netbsd.org/port-i386/2010/07/17/msg002062.html

No objection raised on port-i386@ and port-xen@R for about a week.

XXX kvm(3) will be fixed in another patch to properly handle both PAE and !PAE
kernel dumps (VA => PA macros are slightly different, and need proper 64 bits
PA support in kvm_i386).

XXX Mixing PAE and !PAE modules may lead to unwanted/unexpected results. This
cannot be solved easily, and needs lots of thinking before being declared
safe (paddr_t/bus_addr_t size handling, PD/PT macros abstractions).

sync with head

Drop x86 MD package/core/smt IDs and use MI.

Sync with HEAD.

Apply renovated patch to significantly reduce TLB shootdowns in x86 pmap,
also provide TLBSTATS option to measure and track TLB shootdowns.  Details:

http://mail-index.netbsd.org/port-i386/2009/01/11/msg001018.html

Patch from Andrew Doran, proposed on tech-x86 [sic], in January 2009.

XXX: amd64 and xen are not yet; work in progress.

Apply patch (requested by jym in ticket #1380):
Fix the NX regression issue observed on amd64 kernels, where per-page
execution right was disabled (therefore leading to the inability
of the kernel to detect fraudulent use of memory mappings marked as not
being executable).

Apply patch (requested by jym in ticket #1380):
Fix the NX regression issue observed on amd64 kernels, where per-page
execution right was disabled (therefore leading to the inability
of the kernel to detect fraudulent use of memory mappings marked as not
being executable).

sync to netbsd-5

This patch fixes the NX regression issue observed on amd64 kernels, where
per-page execution right was disabled (therefore leading to the inability
of the kernel to detect fraudulent use of memory mappings marked as not
being executable).

- replace cpu_feature and ci_feature_flags variables by cpu_feature and
ci_feat_val arrays. This makes it cleaner and brings kernel code closer
to the design of cpuctl(8). A warning will be raised for each CPU that
does not expose the same features as the Boot Processor (BP).

- the blacklist of CPU features is now a macro defined in the
specialreg.h header, instead of hardcoding it inside MD initialization
code; fix comments.

- replace checks against CPUID_TSC with the cpu_hascounter() function.

- clean up the code in init_x86_64(), as cpu_feature variables are set
inside cpu_probe().

- use cpu_init_msrs() for i386. It will be eventually used later for NX
feature under i386 PAE kernels.

- remove code that checks for CPUID_NOX in amd64 mptramp.S, this is already
performed by cpu_hatch() through cpu_init_msrs().

- remove cpu_signature and feature_flags members from struct mpbios_proc
(they were never used).

This patch was tested with i386 MONOLITHIC, XEN3PAE_DOM0 and XEN3_DOM0 under
a native i386 host, and amd64 GENERIC, XEN3_DOM0 via QEMU virtual machines.

XXX Should kernel rev be bumped?

XXX A similar patch should be pulled-up for NetBSD-5, hopefully tomorrow.

sync with head

x86_cpu_topology, not toplogy.

add x2apic support.
patch presented on current-users@, port-i386@ and port-amd64@ on 2009-12-22

No comments.

Use lwp_getpcb() on x86 MD code, clean from struct user usage.

- Upgrade suspend/resume code to comply with Xen2 removal.
- Add support for PAE domUs suspend/resume.
- Fix an issue regarding initialization of the xbd ring I/O that could end
badly during resume, with invalid block operations submitted to dom0 backend.

NetBSD supports PAE under x86_32 by considering the L2 page as being
4 pages long instead of 1.

Xen validates the page types during resume. Sadly, the hypervisor handles
alternative recursive mappings (== PG/PD entries pointing to pages other
than self) inadequately, which could lead to incorrect page pinning.

As a result, the important change with this patch is to clear these alternative
mappings during suspend, and reset them back to their former self upon
resume. For PAE, approx. all 4 PDIR_SLOT_PTEs could be considered as
alternative recursive mappings.

See comments in pmap.c for further details.

Now, let the testing and bug hunting begin.

Sync with HEAD.

Pull up following revision(s) (requested by rmind in ticket #782):
	sys/arch/x86/conf/files.x86: revision 1.52 via patch
	sys/arch/x86/include/cpu.h: revision 1.17
	sys/arch/x86/x86/cpu_topology.c: revision 1.1
	sys/arch/x86/x86/identcpu.c: revision 1.16 via patch
Move x86 CPU topology detection code into the separate file (as it was
originally).
OK by <yamt>.

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

sync with head.

Move x86 CPU topology detection code into the separate file (as it was originally).
OK by <yamt>.

Sync with HEAD.

cpuctl:

- Add interrupt shielding (direct hardware interrupts away from the
  specified CPUs). Not documented just yet but will be soon.

- Redo /dev/cpu time_t compat so no kernel changes are needed.

x86:

- Make intr_establish, intr_disestablish safe to use when !cold.

- Distribute hardware interrupts among the CPUs, instead of directing
  everything to the boot CPU.

- Add MD code for interrupt sheilding. This works in most cases but there is
  a bug where delivery is not accepted by an LAPIC after redistribution. It
  also needs re-balancing to make things fair after interrupts are turned
  back on for a CPU.

- Add macros to handle (some) trapframe registers for common x86 code.
- Merge i386 and amd64 syscall.c into x86.  No functional changes intended.

Proposed on (port-i386 & port-amd64).  Unfortunately, I cannot merge these
lists into the single port-x86. :(

#include <sys/types.h>, not <stdbool.h> for userland
in defined(_STANDALONE) case too.

kvtop: change return type to paddr_t.

If defined(_KERNEL), #include <sys/types.h>, otherwise #include
<stdbool.h>, for the bool definition that we need. cpu.h only got the
definition by chance, before.

Expose more stuff if _KMEMUSER is defined.

Initial code for xen save/restore/migrate facilities.

- split the attach code of frontends in two half: one that is only needed
during autoconf(9) attach/detach phases, and one used at each save/restore
of device state (between suspend and resume).

Applies to hypervisor, xencons, xenbus, xbd, and xennet.

- add a rwlock(9) ("ptom_lock") to protect the different parts in the kernel
 that manipulate MFNs (which could change between a suspend and a resume,
without the kernel noticing it). Parts that require MFNs acquire a reader lock,
while suspend code will acquire a writer lock to ensure that no-other parts
in kernel still use MFNs.

- integrate the suspend code with sysmon.

- various things in pmap(9), and clock.

TODO:
- factorize code a bit more inside frontends drivers.
- remove all alternative recursive (APDP_PDE) mappings found in PD/PT during
suspend, as Xen does not support them.
- abstract the ptom_lock locking, it is only required when kernel preemption
is enabled, or on MP systems.

Current code works mostly. You may experience difficulties in some corner
cases (dom0 warnings about xennet interface errors, and Xen tools failing to
 validate NetBSD's alternative pmaps).

Sync with HEAD.

Sync with HEAD.

_LKM -> _MODULE

Update haad-dm branch to haad-dm-base2.

this uses an evcnt so, include <sys/evcnt.h>

Sync with HEAD.

print features4: cpuid fn80000001 %ecx on AMD CPUs.

Add files to branch that were added on -current.

After this, all that's left of update is to merge some changes
that had conflicts.

sync with head

Sync with HEAD.

file cpu.h was added on branch wrstuden-revivesa on 2008-06-23 05:02:12 +0000

file cpu.h was added on branch mjf-devfs2 on 2008-06-02 13:22:50 +0000

fillw is dead.

Remove X86_MAXPROCS. There is still a 32-cpu limit, but it's now using
the MI constants.

Mark x86_curlwp() with __attribute__ ((const)), so gcc can CSE it and know
that it does not clobber global data.

sync with head.

sync with head.

file cpu.h was added on branch yamt-pf42 on 2008-05-18 12:33:01 +0000

file cpu.h was added on branch yamt-nfs-mp on 2008-05-16 02:23:27 +0000

- Make cpu_number() return MI index, otherwise the pmap cannot work on
  systems with lapic IDs > X86_MAXPROCS.
- Kill cpu_info[] array and use MI cpu_lookup_byindex().

Don't reload LDTR unless a new value, which only happens for USER_LDT.

Stop using APIC IDs to identify CPUs for software purposes. Allows for
APIC IDs beyond 31, which has been possible for some time now.

Share cpu.h between the x86 ports.