CVS log for src/sys/arch/x86/conf/files.x86

Up to [cvs.NetBSD.org] / src / sys / arch / x86 / conf

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Keyword substitution: kv
Default branch: MAIN

Make PCI_ADDR_FIXUP depended on PCI_BUS_FIXUP.
It is no-op if PCI_BUS_FIXUP is missing.

MI PMAP EFI_RUNTIME support

x86: Support EFI runtime services.

This creates a special pmap, efi_runtime_pmap, which avoids setting
PTE_U but allows mappings to lie in what would normally be user VM --
this way we don't fall afoul of SMAP/SMEP when executing EFI runtime
services from CPL 0.  SVS does not apply to the EFI runtime pmap.

The mechanism is intended to work with either physical addressing or
virtual addressing; currently the bootloader does physical addressing
but in principle it could be modified to do virtual addressing
instead, if it allocated virtual pages, assigned them in the memory
map, and issued RT->SetVirtualAddressMap.

Not sure pmap_activate_sync and pmap_deactivate_sync are correct,
need more review from an x86 wizard.

If this causes fallout, it can be disabled temporarily without
reverting anything by just making efi_runtime_init return immediately
without doing anything, or by removing options EFI_RUNTIME.

amd64-only for now pending type fixes and testing on i386.

x86: Rename x86/efi.c -> x86/efi_machdep.c.

Avoid collision with dev/efi.c.

Sync with HEAD.

x86's platform.c no longer has any x86 specific code in it, so move it to
dev/smbios_platform.c to let other ports use it

Separate MI smbios interface from MD specific code.

move vmt(4) from MD to MI, and add support vmt on aarch64. tested on ESXi-Arm Fling

- move from sys/arch/x86/x86/{vmt.c,vmtreg.h,vmtvar.h} to sys/dev/vmt/{vmt_subr.c,vmtreg.h,vmtvar.h},
  and split the attach part of the cpufeaturebus and fdt
- add aarch64 vmware backdoor op
- add include guard to vmt{reg,var}.h
- Yet there is still some little-endian dependency. it needs to be fixed in order to work properly on aarch64eb

Pull up the following revisions, requested by msaitoh in ticket #1593:

	sys/arch/x86/conf/files.x86			1.108
	sys/arch/x86/include/apicvar.h			1.7 via patch
	sys/arch/x86/include/cpu.h			1.121
	sys/arch/x86/x86/cpu.c				1.185 via patch
	sys/arch/x86/x86/hyperv.c			1.7
	sys/arch/x86/x86/tsc.c				1.41
	sys/arch/xen/conf/files.xen			1.181

Get TSC frequency from CPUID 0x15 and/or x16 if it's available.
This change fixes a problem that newer Intel processors' timer
counts very slowly.

defflag NO_PCI_MSI_MSIX

Implement ChaCha with SSE2 on x86 machines.

Slightly disappointed that it only doubles, rather than quadruples,
throughput on my Ivy Bridge laptop.  Worth investigating.

Pull up the following, requested by msaitoh in ticket #1015

	sys/arch/x86/conf/files.x86			1.108 (via patch)
	sys/arch/x86/include/apicvar.h			1.7 (via patch)
	sys/arch/x86/include/cpu.h			1.121 (via patch)
	sys/arch/x86/x86/cpu.c				1.185 (via patch)
	sys/arch/x86/x86/hyperv.c			1.7 (via patch)
	sys/arch/x86/x86/tsc.c				1.41 (via patch)
	sys/arch/xen/conf/files.xen			1.181 (via patch)

Get TSC frequency from CPUID 0x15 and/or x16 if it's available.
This change fixes a problem that newer Intel processors' timer
counts very slowly.

Introduce per-cpu IDTs

This is realized by following modifications:
- Add IDT pages and its allocation maps for each cpu in "struct cpu_info"
- Load per-cpu IDTs at cpu_init_idt(struct cpu_info*)
- Copy the IDT entries for cpu0 to other CPUs at attach
   - These are, for example, exceptions, db, system calls, etc.

And, added a kernel option named PCPU_IDT to enable the feature.

New permutation-based AES implementation using SSSE3.

This covers a lot of CPUs -- particularly lower-end CPUs over the
past decade which lack AES-NI.

Derived from Mike Hamburg's public domain vpaes software; see
<https://crypto.stanford.edu/vpaes/> for details.

New SSE2-based bitsliced AES implementation.

This should work on essentially all x86 CPUs of the last two decades,
and may improve throughput over the portable C aes_ct implementation
from BearSSL by

(a) reducing the number of vector operations in sequence, and
(b) batching four rather than two blocks in parallel.

Derived from BearSSL'S aes_ct64 implementation adjusted so that where
aes_ct64 uses 64-bit q[0],...,q[7], aes_sse2 uses (q[0], q[4]), ...,
(q[3], q[7]), each tuple representing a pair of 64-bit quantities
stacked in a single 128-bit register.  This translation was done very
naively, and mostly reduces the cost of ShiftRows and data movement
without doing anything to address the S-box or (Inv)MixColumns, which
spread all 64-bit quantities across separate registers and ignore the
upper halves.

Unfortunately, SSE2 -- which is all that is guaranteed on all amd64
CPUs -- doesn't have PSHUFB, which would help out a lot more.  For
example, vpaes relies on that.  Perhaps there are enough CPUs out
there with PSHUFB but not AES-NI to make it worthwhile to import or
adapt vpaes too.

Note: This includes local definitions of various Intel compiler
intrinsics for gcc and clang in terms of their __builtin_* &c.,
because the necessary header files are not available during the
kernel build.  This is a kludge -- we should fix it properly; the
present approach is expedient but not ideal.

Add AES implementation with VIA ACE.

padlock(4): Remove legacy rijndael API use.

This doesn't actually need to compute AES -- it just needs the
standard AES key schedule, so use the BearSSL constant-time key
schedule implementation.

XXX Compile-tested only.
XXX The byte-order business here seems highly questionable.

Add x86 AES-NI support.

Limited to amd64 for now.  In principle, AES-NI should work in 32-bit
mode, and there may even be some 32-bit-only CPUs that support
AES-NI, but that requires work to adapt the assembly.

x86/x86/ipi.c should not be built for XENPV, even if dom0ops is defined.

Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
guests in GENERIC.
Xen support can be disabled at runtime with
boot -c
disable hypervisor

sync with bouyer-xenpvh-base2 (HEAD)

Make crypto/rijindael optional again as cprng_strong does no longer
depend on it. Dependency is explicitly declared in files.foo if a
component requires it.

Sync with HEAD

Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.

 - If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
   can take TSC/core crystal clock ratio but core crystal clock frequency
   can't be taken. Intel SDM give us the values for some processors.
 - It also required to change lapic_per_second to make LAPIC timer correctly.
 - Add new file x86/x86/identcpu_subr.c to share common subroutines between
   kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
   will be moved to this file in future.
 - Add comment to clarify.

Reorganise sources to make it possible to include Xen PVHVM support in
native kernels. Among others:
- move xen/include/amd64/hypercall.h to amd64/include/xen and
  xen/include/i386/hypercall.h to i386/include/xen
- exclude some native files from the build for xenpv
- add xen to "machine" config statement for amd64 and i386
- split arch/xen/conf/files.xen to arch/xen/conf/files.xen (for pv drivers)
  and arch/xen/conf/files.xen.pv (for full pv support)
- add GENERIC_XENHVM kernel config which includes GENERIC and add Xen PV
  drivers.

Move softint and preemtion-related functions out of x86/x86/intr.c to
  its own file, x86/x86/x86_softintr.c
Add x86/x86/x86_softintr.c for native and XenPV
Make sure XenPV also check ci_ioending, which is used for softints.
Switch XenPV to fast softints and allow kernel preemption.
kpreempt_disable() before calling pmap_changeprot_local()
run  xen_wallclock_time() and xen_global_systime_ns() at splshed() to
  avoid being interrupted.

XXX amd64 lock stubs are racy for XPENDING

Sync with HEAD

Pull up following revision(s) via patch (requested by nonaka in ticket #1210):

	sys/dev/hyperv/vmbusvar.h: revision 1.1
	sys/dev/hyperv/hvs.c: revision 1.1
	sys/dev/hyperv/if_hvn.c: revision 1.1
	sys/dev/hyperv/vmbusic.c: revision 1.1
	sys/arch/x86/x86/lapic.c: revision 1.69
	sys/arch/x86/isa/clock.c: revision 1.34
	sys/arch/x86/include/intrdefs.h: revision 1.22
	sys/arch/i386/conf/GENERIC: revision 1.1201
	sys/arch/x86/x86/hyperv.c: revision 1.1
	sys/arch/x86/include/cpu.h: revision 1.105
	sys/arch/x86/x86/x86_machdep.c: revision 1.124
	sys/arch/i386/conf/GENERIC: revision 1.1203
	sys/arch/amd64/amd64/genassym.cf: revision 1.74
	sys/arch/i386/conf/GENERIC: revision 1.1204
	sys/arch/amd64/conf/GENERIC: revision 1.520
	sys/arch/x86/x86/hypervreg.h: revision 1.1
	sys/arch/amd64/amd64/vector.S: revision 1.69
	sys/dev/hyperv/hvshutdown.c: revision 1.1
	sys/dev/hyperv/hvshutdown.c: revision 1.2
	sys/dev/usb/if_urndisreg.h: file removal
	sys/arch/x86/x86/cpu.c: revision 1.167
	sys/arch/x86/conf/files.x86: revision 1.107
	sys/dev/usb/if_urndis.c: revision 1.20
	sys/dev/hyperv/vmbusicreg.h: revision 1.1
	sys/dev/hyperv/hvheartbeat.c: revision 1.1
	sys/dev/hyperv/vmbusicreg.h: revision 1.2
	sys/dev/hyperv/hvheartbeat.c: revision 1.2
	sys/dev/hyperv/files.hyperv: revision 1.1
	sys/dev/ic/rndisreg.h: revision 1.1
	sys/arch/i386/i386/genassym.cf: revision 1.111
	sys/dev/ic/rndisreg.h: revision 1.2
	sys/dev/hyperv/hyperv_common.c: revision 1.1
	sys/dev/hyperv/hvtimesync.c: revision 1.1
	sys/dev/hyperv/hypervreg.h: revision 1.1
	sys/dev/hyperv/hvtimesync.c: revision 1.2
	sys/dev/hyperv/vmbusicvar.h: revision 1.1
	sys/dev/hyperv/if_hvnreg.h: revision 1.1
	sys/arch/x86/x86/lapic.c: revision 1.70
	sys/arch/amd64/amd64/vector.S: revision 1.70
	sys/dev/ic/ndisreg.h: revision 1.1
	sys/arch/amd64/conf/GENERIC: revision 1.516
	sys/dev/hyperv/hypervvar.h: revision 1.1
	sys/arch/amd64/conf/GENERIC: revision 1.518
	sys/arch/amd64/conf/GENERIC: revision 1.519
	sys/arch/i386/conf/files.i386: revision 1.400
	sys/dev/acpi/vmbus_acpi.c: revision 1.1
	sys/dev/hyperv/vmbus.c: revision 1.1
	sys/dev/hyperv/vmbus.c: revision 1.2
	sys/arch/x86/x86/intr.c: revision 1.144
	sys/arch/i386/i386/vector.S: revision 1.83
	sys/arch/amd64/conf/files.amd64: revision 1.112

separate RNDIS definitions from urndis(4) for use with Hyper-V NetVSC.

 -

Added Microsoft Hyper-V support.  It ported from OpenBSD and FreeBSD.
graphical console is not work on Gen.2 VM yet. To use the serial console,
enter "consdev com,0x3f8,115200" on efiboot.

 -

Add __diagused.

 -

PR/53984: Partial revert of modify lapic_calibrate_timer() in lapic.c r1.69.

 -

Update Hyper-V related drivers description.

 -

Remove unused definition.

 -

Rename the MODULE_*_HOOK() macros to MODULE_HOOK_*() as briefly
discussed on irc.
NFCI intended.

 -

commented out hvkvp entry.

 -

fix typo. pointed out by pgoyette@n.o.

 -

Use IDTVEC instead of NENTRY for handle_hyperv_hypercall.

 -

Rename the MODULE_*_HOOK() macros to MODULE_HOOK_*() as briefly
discussed on irc.

Added Microsoft Hyper-V support.  It ported from OpenBSD and FreeBSD.

graphical console is not work on Gen.2 VM yet. To use the serial console,
enter "consdev com,0x3f8,115200" on efiboot.

Sync with HEAD, resolve a few conflicts

Make ipmi driver available to other platforms.
Add ACPI attachment.

Enable 'options NO_PCI_MSI_MSIX' to DTRT in x86 builds.

Document 'options NO_PCI_MSI_MSIX' in options(4).

Add an option to have a static kernel memory layout. This option is
disabled by default - that is to say, KASLR remains enabled by default.

Sync with HEAD

Move
	arch/x86/x86/tprof_pmi.c
	arch/x86/x86/tprof_amdpmi.c
into
	dev/tprof/tprof_x86_intel.c
	dev/tprof/tprof_x86_amd.c

Remove the X86PMC code I had written, replaced by tprof. Many defines
become unused in specialreg.h, so remove them. We don't want to add
defines all the time, there are countless PMCs on many generations, and
it's better to just inline the event/unit values.

Sync with HEAD

Mmh, don't compile spectre.c on Xen.

Synch with HEAD

Make MPVERBOSE a defparam rather than defflag.  It has multiple
non-zero usages within mpacpi.c

Resolve conflicts between branch and HEAD

Move the SpectreV2 mitigation code into a dedicated spectre.c file. The
content of the file is taken from the end of cpu.c, and is copied as-is.

Pull up the following revisions, requested by maxv in ticket #652:

	sys/arch/amd64/amd64/amd64_trap.S	upto 1.39 (partial, patch)
	sys/arch/amd64/amd64/db_machdep.c	1.6 (patch)
	sys/arch/amd64/amd64/genassym.cf	1.65,1.66,1.67 (patch)
	sys/arch/amd64/amd64/locore.S		upto 1.159 (partial, patch)
	sys/arch/amd64/amd64/machdep.c		1.299-1.302 (patch)
	sys/arch/amd64/amd64/trap.c		upto 1.113 (partial, patch)
	sys/arch/amd64/amd64/amd64/vector.S	upto 1.61 (partial, patch)
	sys/arch/amd64/conf/GENERIC		1.477,1.478 (patch)
	sys/arch/amd64/conf/kern.ldscript	1.26 (patch)
	sys/arch/amd64/include/frameasm.h	upto 1.37 (partial, patch)
	sys/arch/amd64/include/param.h		1.25 (patch)
	sys/arch/amd64/include/pmap.h		1.41,1.43,1.44 (patch)
	sys/arch/x86/conf/files.x86		1.91,1.93 (patch)
	sys/arch/x86/include/cpu.h		1.88,1.89 (patch)
	sys/arch/x86/include/pmap.h		1.75 (patch)
	sys/arch/x86/x86/cpu.c			1.144,1.146,1.148,1.149 (patch)
	sys/arch/x86/x86/pmap.c			upto 1.289 (partial, patch)
	sys/arch/x86/x86/vm_machdep.c		1.31,1.32 (patch)
	sys/arch/x86/x86/x86_machdep.c		1.104,1.106,1.108 (patch)
	sys/arch/x86/x86/svs.c			1.1-1.14
	sys/arch/xen/conf/files.compat		1.30 (patch)

Backport SVS. Not enabled yet.

Synch with HEAD, resolve conflicts

Import more christos@ changes from -current

Separate the compat code in its own file to facilitate module building.

move the imc code into x86/pci/files.pci so that pci is defined in time.

Move the imc(4) and imcsmb(4) sources into architecture-specific
directory (for previous CVS history see the sys/dev/pci/imcsmb/
Attic)

Replace spaces with tabs (xterm copy-&-pasto)

Move the imc and imcsmb stuff out of general files.pci and into the
architecture-specific files.x86

Should unbreak the sgimips build.

Move SVS into x86/svs.c

rename sys/arch/x86/x86/pmap_tlb.c to sys/arch/x86/x86/x86_tlb.c, so that
x86 can eventually use uvm/pmap/pmap_tlb.c; step to future PCID support

Make things compile again.

update from HEAD

Sync with HEAD

Merge into x86/.

Merge into x86/.

Sync with HEAD

Sync with HEAD

Move pmc.c into x86/, it can be shared with amd64.

Sync with HEAD

Add cpu_rng, a framework for simple on-CPU random number generators.

Add support for grub to find the ACPI root table pointer via a bootinfo entry
from grub.
    From: https://mail-index.netbsd.org/tech-kern/2014/05/22/msg017119.html

Sync with HEAD (as of 26th Dec)

Split out the pmap_pv_track stuff for use by others.

Discussed with riastradh@

Sync with HEAD

add x86 MD MSI/MSI-X support code.

Normalize: acpicpu depends on acpi.

Define "machdep" attribute and mark files (in amd64 and x86).

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

Merge riastradh-drm2 to HEAD.

sync with head

sync with HEAD

A few "isa" files are so tightly integrated into the x86 platform code
as to not really be part of the optional isa bus autoconf machinery.

Allows configuring a kernel like so:

include "arch/amd64/conf/GENERIC"
no isa

sync with head

Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).

sync to latest -current.

sync with head.

Merge i386 and amd64 version of db_memrw.c.

Use this opportunity to skip calculating the VA of the page. Let the CPU
deal with the invalidation itself through invlpg + destination address to
avoid converting between canonical/non canonical forms.

sync with head

merge to -current.

Make option CPU_UCODE global

Support CPU microcode loading via cpuctl(8).
Implemented and enabled via CPU_UCODE kernel config option
for x86 and Xen Dom0.
Tested on different AMD machines with different
CPU families.

ok wiz@ for the manpages
ok releng@
ok core@ via releng@

Don't link pci_ranges.c with x86 kernels for now, it's using a
pcibus_attach_args member that I haven't added, yet.

vmt needs sysmon_taskq

add a port of the VMware Tools driver vmt(4) from OpenBSD

Add pci_ranges.c to the set of files compiled when 'pci' is configured.

Sync with HEAD. Most notably: uvm/pmap work done by rmind@, and MP Xen
work of cherry@.

No regression observed on suspend/restore.

Catchup with rmind-uvmplock merge.

Follow IA-64 with the x86-specific ACPI MD functions and move these where
they belong to. Remove an unused function. Minor KNF. No functional change.

Move the evaluation of the _PDC control method out from the acpicpu(4)
driver to the main acpi(4) stack. Follow Linux and evaluate it early.
Should fix PR port-amd64/42895, possibly also PR kern/42583, and many
other comparable bugs.

A common sense explanation is that Intel supplies additional CPU tables to
OEMs. BIOS writers do not bother to modify their DSDTs, but instead load
these extra tables dynamically as secondary SSDT tables. The actual Load()
happens when the _PDC method is invoked, and thus namespace errors occur
when the CPU-specific ACPI methods are not yet present but referenced in the
AML by various drivers, including, but not limited to, acpitz(4).

Welcome to 5.99.53!  Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
  New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
  the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
  Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
  kernel-lock on some ports).  Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

sync with head

Sync with HEAD.

Don't use the C preprocessor to configure USERCONF.  Instead, either do
or do not link in subr_userconf.c and x86_userconf.c.

Provide no-op stubs for userconf_bootinfo(), userconf_init(), and
userconf_prompt().

Delete all occurrences of #include "opt_userconf.h" as well as USERCONF
and __HAVE_USERCONF_BOOTINFO #ifdef'age.

Sync with head.

sync with head

Merge db_trace for x86. From: Vladimir Kirillov proger at wilab dot org dot ua

As pointed out by Manuel Bouyer and Taylor R Campbell, I forgot to
commit the change to files.x86 that adds x86_stub.c, so do that.

More sync fixes. And add the mbr_gpt files.

Sync with HEAD. TODO before merge:
- shortcut for suspend code in sysmon, when powerd(8) is not running.
Borrow ``xs_watch'' thread context?
- bug hunting in xbd + xennet resume. Rings are currently thrashed upon
resume, so current implementation force flush them on suspend. It's not
really needed.

sys/arch/x86/x86/iclockmod.c has been removed.

sync with head

Sync with HEAD

Move INTEL_ONDEMAND_CLOCKMOD -- or odcm(4) -- to the cpufeaturebus.

Move acpicpu(4) from "acpinodebus" to "cpufeaturebus".

Move VIA_C7TEMP to the cpufeaturebus.

Move PowerNow! to the cpufeaturebus.

Move ENHANCED_SPEEDSTEP, or henceforth est(4), to the cpufeaturebus.

Modularize coretemp(4). Ok jmcneill@.

modularize VIA PadLock support
 - retire options VIA_PADLOCK, replace with 'padlock0 at cpu0'
 - driver supports attach & detach
 - support building as a module

Sync with HEAD

decouple tprof and its backends.

Pull up following revision(s) (requested by hubertf in ticket #1403):
	sys/arch/x86/conf/files.x86: revision 1.49
	sys/arch/i386/i386/autoconf.c: revision 1.94
	sys/arch/x86/x86/intr.c: revision 1.60
Add opt_intrdebug.h for the INTRDEBUG option, and #include it here and
there.  Fixes GENERIC/i386 compilation with 'options INTRDEBUG'.

xmd_machdep.c is gone.

xmd(4) glue for i386.  XIP mount panics now.

Sync with HEAD.

sync with head.

Merge a driver for ACPI CPUs with basic support for processor power states,
also known as C-states. The code is modular and provides an easy way to add
the remaining functionality later (namely throttling and P-states).

Remarks:

  1.	Commented out in the GENERICs; more testing exposure is needed.

  2.	The C3-state is disabled for the time being because it turns off
	timers, among them the local APIC timer. This may not be universally
	true on all x86 processors; define ACPICPU_ENABLE_C3 to test.

  3.	The algorithm used to choose a power state may need tuning. When
	evaluating the appropriate state, the implementation uses the
	previous sleep time as an indicator. Additional hints would include
	for example the system load.

	Also bus master activity is evaluated when choosing a state. The
	usb(4) stack is notorious for such activity even when unused.
	Typically it must be disabled in order to reach the C3-state,
	but it may also prevent the use of C2.

  4.	While no extensive empirical measurements have been carried out, the
	power savings are somewhere between 1-2 W with C1 and C2, depending
	on the processor, firmware, and load. With C3 even up to 4 W can be
	saved.  The less something ticks, the more power is saved.

ok jmcneill@, joerg@, and discussed with various people.

Unify i386 and amd64 procfs MD code into x86.

Split x86 TLB shootdown code into a separate file.
Code part is under TNF license, as per pmap.c 1.105.2.4 revision.

sync to netbsd-5

sync with head

Sync with HEAD.

Remove X86_IPI_WRITE_MSR (and msr_ipifuncs.c), replace all uses in drivers
with xc_broadcast().  AMD K8 PowerNow driver tested by <jakllsch>, thanks!

Closes PR/37665.

Pull up the following revisions(s) (requested by jmcneill in ticket #1061):
	sys/arch/x86/conf/files.x86:	revision 1.53
	sys/arch/x86/include/cpuvar.h:	revision 1.31
	sys/arch/x86/x86/identcpu.c:	revision 1.17
	sys/arch/x86/x86/viac7temp.c:	revision 1.1
	sys/arch/i386/conf/ALL:	revision 1.218
	sys/arch/i386/conf/GENERIC:	revision 1.949
Add support for VIA C7 temperature sensors (options VIA_C7TEMP) and enable
in i386 GENERIC kernel.

Add support for VIA C7 temperature sensors (options VIA_C7TEMP)

Pull up following revision(s) (requested by rmind in ticket #782):
	sys/arch/x86/conf/files.x86: revision 1.52 via patch
	sys/arch/x86/include/cpu.h: revision 1.17
	sys/arch/x86/x86/cpu_topology.c: revision 1.1
	sys/arch/x86/x86/identcpu.c: revision 1.16 via patch
Move x86 CPU topology detection code into the separate file (as it was
originally).
OK by <yamt>.

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

sync with head.

Move x86 CPU topology detection code into the separate file (as it was originally).
OK by <yamt>.

Sync with HEAD.

Introduce sys/arch/x86/x86/mp.c for common x86 MP configuration code.
mpacpi_scan_pci() and mpbios_scan_pci() are identical code, so replace
them with mp_pci_scan().

Introduce mp_pci_childdetached(), which helps us to detach root PCI
buses that were enumerated either by MP BIOS or by ACPI.

Let us detach and re-attach PCI buses from mainbus0 on i386.  This is
necessarily a work-in-progress, because testing detach and re-attach
is very difficult: to detach and re-attach the entire PCI tree on most
x86 computers that I own is not possible because some essential device
attaches under the PCI subtree: the console, com0, NIC, or storage
controller always attaches in the PCI tree.

- Add macros to handle (some) trapframe registers for common x86 code.
- Merge i386 and amd64 syscall.c into x86.  No functional changes intended.

Proposed on (port-i386 & port-amd64).  Unfortunately, I cannot merge these
lists into the single port-x86. :(

Add opt_intrdebug.h for the INTRDEBUG option, and #include it here and
there.  Fixes GENERIC/i386 compilation with 'options INTRDEBUG'.

Merge i386 and amd64 vm_machdep.c into x86.  No functional changes intended.
Note: some #ifdefs will be removed with macros.

Merge/move core_machdep.c into x86, no difference between i386 and amd64.

Sync with HEAD.

- rewrite x86 nmi dispatcher so that establish and disesablish are safe
  on a running system.
- adapt existing users of the api.  (elan)
- adapt tprof_pmi driver to use the api.

PR# port-i386/37026: userconf(4) doesn't work with vesafb(4)

Add early console support for x86 genfb.

Sync with HEAD.

Sync with HEAD.

Sync with wrstuden-revivesa-base-2.

Move some MD declarations from x86/pci/files.pci to x86/conf/files.x86,
so that Xen can use the former.

Drop Xen's pcib.c in favor of the x86 code and thereby unbreak ichlpcib.

Sync w/ -current. 34 merge conflicts to follow.

Sync with HEAD.

sync with head.

sync with head.

Simplify x86 identcpu code, and share between i386/amd64.

Make cpu_idle a macro calling a function pointer on x86.
Select the Xen idle routine for Xen, mwait if supported by the CPU and
it is not AMD and halt otherwise. As reported by Christoph Egger,
AMD Barcelona keeps the CPU in C0 state with MWAIT, contrary to HLT,
which uses C1 and therefore much less power.

Include null IPI functions if !MULTIPROCESSOR.

Sync with HEAD.

sync with head

sync with HEAD

Sync with HEAD

try to detect processor resource sharing topologies.  ie. package/core/smt IDs.

Sync with HEAD.

Sync with head.

- share idt entry allocation code among x86.
- introduce a function to reserve an idt entry and use it instead of
  manipulating idt_allocmap directly.
- rename idt to xen_idt for amd64 xen.  add missing #ifdef XEN.

Add initial version of calling VGA POST from vga_resume. This is the
equivalent to "vbetool post" using x86emu in the kernel.

Add new IPI for saving CPU state explicitly, share high-level part of
ACPI wakeup code and teach it how to start the APs again. As a side
effect the CPU_START interface allows choosing between different
bootstrap codes more easily now.

sync with head.

Merge jmcneill-pm branch.

Sync with HEAD.

Sync with HEAD.

sync with head

Sync with HEAD.

Sync with HEAD.

Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

Sync with HEAD.

sync with head.

Sync with HEAD

Sync with HEAD.

sync with -HEAD

__cpu_simple_locks really should be simple, otherwise they can cause
problems for e.g. profiling.

sync with HEAD

Sync with HEAD.

Add coretemp(4). A new driver for Intel Core's on-die thermal sensor,
available on Intel Core or newer CPUs.

Ported from FreeBSD. Tested by rmind on i386 and joerg on amd64.

Enabled with "options INTEL_CORETEMP".

Sync with HEAD.

sync with head.

- Share pchb(4) between i386 and amd64; one copy is enough for both.
- Move some of the x86 PCI devices into x86/pci/files.pci.
- Add more x86 stuff into x86/conf/files.x86.

ok joerg.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Sync with somewhat-recent netbsd-4.

Pull up following patches (requested by xtraeme in ticket #809)

	share/man/man4/options.4		patch
	sys/arch/i386/conf/files.i386		patch
	sys/arch/i386/i386/est.c		delete
	sys/arch/i386/i386/identcpu.c		patch
	sys/arch/i386/include/cpu.h		patch
	sys/arch/x86/conf/files.x86		patch
	sys/arch/x86/include/cpuvar.h		patch
	sys/arch/x86/x86/est.c			new file
	sys/arch/x86/x86/intel_busclock.c	new file
	sys/arch/amd64/amd64/identcpu.c		patch
	sys/arch/amd64/conf/GENERIC		patch

 Add support for the VIA C7-M and Eden processors in the Enhanced
 Speedstep driver.
 amd64: The Enhanced Speedstep driver is now able to work on EM64T
 CPUs running in 64bit mode.

Move common PCI devices on i386 and amd64 into a arch/x86/pci/fils.pci.

sync with head.

Pull in power management changes from private branch.

Sync with head.

Sync with HEAD.

- Increase the number of thread priorities from 128 to 256. How the space
  is set up is to be revisited.
- Implement soft interrupts as kernel threads. A generic implementation
  is provided, with hooks for fast-path MD code that can run the interrupt
  threads over the top of other threads executing in the kernel.
- Split vnode::v_flag into three fields, depending on how the flag is
  locked (by the interlock, by the vnode lock, by the file system).
- Miscellaneous locking fixes and improvements.

Sync with head.

Make the Enhanced Speedstep driver available for i386 and amd64.
To use it on EM64T CPUs supporting the EST CPUID feature. Note that
some CPUs still don't work with this driver, like Xeon or Pentium 4.

Move the p[34]_get_bus_clock functions into its own file,
intel_busclock.c and remove this code from i386/identcpu.c.

Tested on i386 by myself and amd64 by Tonerre.

Sync with head.

sync with head.

Pull up following revision(s) (requested by mlelstv in ticket #575):
	sys/arch/i386/i386/est.c		sync with 1.37
	sys/arch/i386/i386/ipifuncs.c		sync with 1.16
	sys/arch/x86/include/cpu_msr.h		sync with 1.4
	sys/arch/x86/include/intrdefs.h		sync with 1.8
	sys/arch/x86/include/powernow.h		sync with 1.9
	sys/arch/x86/x86/powernow_k8.c		sync with 1.20
	sys/arch/x86/x86/msr_ipifuncs.c		sync with 1.8
	sys/arch/amd64/amd64/ipifuncs.c		sync with 1.9
	sys/arch/i386/i386/identcpu.c		patch
	sys/arch/i386/i386/machdep.c		patch
	sys/arch/i386/include/cpu.h		patch
	sys/arch/x86/conf/files.x86		patch
	sys/arch/x86/x86/x86_machdep.c		patch
	sys/arch/amd64/amd64/machdep.c		patch
Add MSR write IPI handler for x86. Use it and the RUN_ONCE framework
to make est and powernow drivers work properly with SMP.

Share the sysarch stuff between the x86 ports. PR kern/36046.

Sync with head.

Pullup to -current

sync with head.

Driver for Intel Thermal Monitor (feature TM) On-Demand Clock
Modulation.

This works by changing the duty cycle of the clock modulation,
and saves power and helps to not increase the temperature by
software.

Adapted from OpenBSD/FreeBSD's p4tcc.

To enable it one must use "options INTEL_ONDEMAND_CLOCKMOD".

Tested by me in UP and SMP, ok'ed by Matthew R. Green.

MSR read and write IPI handlers for x86. A MSR will be read or written
in all CPUs available in the system. This adds another member
to struct cpu_info, ci_msr_rvalue; it will contain the value of the MSR
in a previous operation.

Tested with clockmod in UP and SMP by me, tested with est in SMP
by Daniel Carosone and Michael Van Elst.

Ok'ed by Andrew Doran and Matthew R. Green.

Ok... there were people really angry with this, backing it out.

Add a driver for the Pentium 4 and later models with feature TM
(Thermal Monitor).

This driver will throttle the CPU clock modulation, saving some
power, also known as ODMC (On Demand Modulation Clock).

The processor can change from 12.5% to 100% (there are two erratas,
so two levels might be skipped in the worst case).

If supported, you'll see the following sysctl sub-tree:

machdep.p4tcc.throttling.target: CPU Clock throttling state (0 = lowest, 7 highest)
machdep.p4tcc.throttling.current: current CPU throttling state
machdep.p4tcc.throttling.available: list of CPU Clock throttling states

machdep.p4tcc.throttling.target = 2
machdep.p4tcc.throttling.current = 2
machdep.p4tcc.throttling.available = 7 6 5 4 3 2

Adapted from OpenBSD/FreeBSD.

Sync with HEAD.

clean up how cpus and ioapics are attached at the mainbus:
Seperate "cpubus" and "ioapicbus" -- while they share a common "address
space" (the apic id), the kernel doesn't use this fact. There are different
data passed to cpus and apics, which caused some ugly polymorphism. This
also saves the special "submatch" functions needed to distingush cpus
and ioapics for autoconf. (And it makes that "apid" locators wired
in the kernel configuration are honored now; this allows one to dumb down
an mp box to singleprocessor by userconfig.)
Print "apid" locators in the buses "print" function "as everyone does",
so the per-port cpu drivers don't need to do it.
Being here, constify "struct cpu_functions" and g/c the unused MP_PICMODE
flag.

sync with head.

file files.x86 was added on branch yamt-idlelwp on 2007-03-12 05:51:45 +0000

Add an opencrypto provider for the AES xcrypt instructions found on VIA
C5P and later cores (also known as 'ACE', which is part of the VIA PadLock
security engine). Ported from OpenBSD.

Reviewed on tech-crypto and port-i386, no objections to commiting this.

Merge newlock2 to head.

If running on a PPro or later, at boot patch in versions of spllower() and
similar that use cmpxchg8b instead of cli/sti. Cuts the clock cycles for
splx() by a factor of ~6 on the P4, and ~3 on the PIII when bracketed by
serializing instructions (and hopefully more when not).

Sync with head.

Pull up following revision(s) (requested by bouyer in ticket #1621):
	sys/arch/i386/conf/GENERIC: revision 1.787 via patch
	share/man/man4/Makefile: revision 1.407 via patch
	distrib/sets/lists/man/mi: revision 1.936 via patch
	share/man/man4/ipmi.4: revision 1.1 via patch
	sys/arch/i386/i386/bios32.c: revision 1.11 via patch
	sys/dev/DEVNAMES: revision 1.221 via patch
	sys/arch/x86/x86/ipmi.c: revision 1.1 via patch
	sys/arch/i386/i386/mainbus.c: revision 1.65 via patch
	sys/arch/x86/include/smbiosvar.h: revision 1.1 via patch
	sys/arch/x86/include/ipmivar.h: revision 1.1 via patch
	sys/arch/x86/conf/files.x86: revision 1.20 via patch
	sys/arch/i386/conf/files.i386: revision 1.293 via patch
Add ipmi(4) driver, from OpenBSD. This requires SMBios support, so add
SMBios detection and mapping to bios32.c, also from OpenBSD (for now this
is only compiled in if ipmi(4) is configured). The sensors and watchdog are
accessible though envsys(4).
Works on i386; some work is needed on amd64 to access the BIOS. It would
eventually work on Xen if the SMBios is accessible (to be tested).
Add manpage for new ipmi driver.
Claim ipmi.

Report on and where possible, try to work around some of the known errata
for Athlon 64 and Opteron processors. Tested briefly by cube@ and elad@.

sync with head.

Sync with head.

sync with head

Add ipmi(4) driver, from OpenBSD. This requires SMBios support, so add
SMBios detection and mapping to bios32.c, also from OpenBSD (for now this
is only compiled in if ipmi(4) is configured). The sensors and watchdog are
accessible though envsys(4).
Works on i386; some work is needed on amd64 to access the BIOS. It would
eventually work on Xen if the SMBios is accessible (to be tested).

sync with head

sync with head

* Do not change struct powernow_pst_s (I added another member in my
  previous patch) and this MUST be of that size, otherwise the tables
  won't be found.

* powernow_k8.c moved into x86/x86, it should work both i386 and amd64.

* Added more DPRINTFs needed to found the first problem.

* Create "machdep.powernow.frequency" again, I can't remember why I
  removed frequency... it should work with estd now.

* Do not try to call k[78]_powernow_init() if cpu is not AMD (thanks
  to christos).

And more things I can't remember, but this time it will work in
Athlon 64 cpus and it won't crash in EM64T cpus.

AMD PowerNow!/Cool`n'Quiet driver for NetBSD/amd64,
adapted from OpenBSD.

Tested on a few machines:

http://bigbird.dohd.org:3021/NetBSD/dmesg
http://www.bsd.org.il/netbsd/acpi/dmesg

Thanks to cube, elad and others for testing and fixes.

Enabled by default on GENERIC.

Merge from HEAD.

Apply fvdl's acpi pci interrupt configuration code.
- MPACPI is no more.
- MPACPI_SCANPCI -> ACPI_SCANPCI

sync with head.

sync with head.

Split move interrupt-related PCI functions from pci_machdep.c to
pci_intr_machdep.c. In Xen-3 registers access is done the normal way but
interrupts need custom setup. Proposed on port-amd64, port-i386 and
port-xen a week ago.

Add a 'struct bootinfo' to represent the bootinfo structure used in the
kernel by x86 platforms (instead of a simple char *).  This way, the code
in, e.g., lookup_bootinfo, is a bit easier to understand.

While here, move the lookup_bootinfo function used in x86 platforms (amd64,
i386 and xen) to a common file (x86/x86_machdep.c), as it was exactly the
same in all of them.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

Move definitions for PCI_*_FIXUP to files.x86 so that ACPI compiles for
amd64...

Sync with HEAD.

Move boot device detection code from i386 and amd64 ports to x86_autoconf.c.
Rename i386_alldisks and x86_64_alldisks to x86_alldisks, adjust other
references to compensate.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

Sync with HEAD

pciide_machdep.c depends on pciide_common, not pciide.
Pointed out and fix tested by Marc Recht.

Move the bulk of pci_intr_string into a seperate intr_string function. Use
that new function to print the pciide compat interrupt in pciide_machdep.c.
Share pciide_machdep.c between amd64 and i386.

Add the options MPBIOS_SCANPCI and MPACPI_SCANPCI to configure PCI roots
with the MPBIOS/ACPI bus information, by walking through the buses, and
descending down every bus that hasn't been marked configured yet.

Update for acpi file move to sys/arch/x86/x86.

Share some common cache info cpuid code between i386 and x86_64.

Split bus_space and bus_dma into separate files.

lock_machdep.c moved here from arch/i386/i386.

Add consinit.c

Catch up with isa_machdep.c and pci_machdep.c move.

Move some files out of i386 into x86, so that they can be shared with
other ports.