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Default branch: MAIN
Current tag: MAIN
Revision 1.84 / (download) - annotate - [select for diffs], Sun Oct 25 16:39:00 2020 UTC (3 years, 4 months ago) by nia
Branch: MAIN
CVS Tags: triaxx-drm,
thorpej-ifq-base,
thorpej-ifq,
thorpej-i2c-spi-conf2-base,
thorpej-i2c-spi-conf2,
thorpej-i2c-spi-conf-base,
thorpej-i2c-spi-conf,
thorpej-futex2-base,
thorpej-futex2,
thorpej-futex-base,
thorpej-futex,
thorpej-cfargs2-base,
thorpej-cfargs2,
thorpej-cfargs-base,
thorpej-cfargs,
thorpej-altq-separation-base,
thorpej-altq-separation,
netbsd-10-base,
netbsd-10-0-RC6,
netbsd-10-0-RC5,
netbsd-10-0-RC4,
netbsd-10-0-RC3,
netbsd-10-0-RC2,
netbsd-10-0-RC1,
netbsd-10,
cjep_sun2x-base1,
cjep_sun2x-base,
cjep_sun2x,
cjep_staticlib_x-base1,
cjep_staticlib_x-base,
cjep_staticlib_x,
bouyer-sunxi-drm-base,
bouyer-sunxi-drm,
HEAD
Changes since 1.83: +3 -20
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Diff to previous 1.83 (colored)
Normalize some machine dependent CPU frequenct sysctl variables. This moves machdep.*.frequency.* to machdep.cpu.frequency.*. This was proposed on tech-kern some time ago. The intention is to allow third-party tools such as estd and conky to more easily and reliably fetch or modify the current CPU frequency without iterating through various machine-dependent variables to check their presence.
Revision 1.83 / (download) - annotate - [select for diffs], Thu Mar 19 19:55:34 2020 UTC (4 years ago) by ad
Branch: MAIN
CVS Tags: phil-wifi-20200421,
phil-wifi-20200411,
phil-wifi-20200406,
bouyer-xenpvh-base2,
bouyer-xenpvh-base1,
bouyer-xenpvh-base,
bouyer-xenpvh
Changes since 1.82: +2 -18
lines
Diff to previous 1.82 (colored)
PR kern/55080: current does not boot Back out previous. To be addressed differently.
Revision 1.82 / (download) - annotate - [select for diffs], Sat Mar 14 13:50:46 2020 UTC (4 years ago) by ad
Branch: MAIN
Changes since 1.81: +18 -2
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Diff to previous 1.81 (colored)
Put ACPI idle under ACPICPU_ENABLE_C3 until the wrinkles are ironed out. This seems well written and basically all good, but currently doesn't enter a low power state, and imposes a big performance penalty. Proposed on port-i386 & port-amd64.
Revision 1.81 / (download) - annotate - [select for diffs], Tue Nov 5 20:21:34 2019 UTC (4 years, 4 months ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20191119,
is-mlppp-base,
is-mlppp,
ad-namecache-base3,
ad-namecache-base2,
ad-namecache-base1,
ad-namecache-base,
ad-namecache
Changes since 1.80: +3 -3
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Diff to previous 1.80 (colored)
Add the __nocsan attribute on this function. Races on ci_want_resched are accepted (part of the design).
Revision 1.80 / (download) - annotate - [select for diffs], Sun Oct 6 15:11:17 2019 UTC (4 years, 5 months ago) by uwe
Branch: MAIN
Changes since 1.79: +3 -5
lines
Diff to previous 1.79 (colored)
xc_barrier - convenience function to xc_broadcast() a nop. Make the intent more clear and also avoid a bunch of (xcfunc_t)nullop casts that gcc 8 -Wcast-function-type is not happy about.
Revision 1.79 / (download) - annotate - [select for diffs], Sat Nov 10 09:42:42 2018 UTC (5 years, 4 months ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20190609,
pgoyette-compat-20190127,
pgoyette-compat-20190118,
pgoyette-compat-1226,
pgoyette-compat-1126,
netbsd-9-base,
netbsd-9-3-RELEASE,
netbsd-9-2-RELEASE,
netbsd-9-1-RELEASE,
netbsd-9-0-RELEASE,
netbsd-9-0-RC2,
netbsd-9-0-RC1,
netbsd-9,
isaki-audio2-base,
isaki-audio2
Changes since 1.78: +2 -3
lines
Diff to previous 1.78 (colored)
Remove unused cpu_msr.h includes.
Revision 1.78 / (download) - annotate - [select for diffs], Thu Dec 8 11:31:12 2016 UTC (7 years, 3 months ago) by nat
Branch: MAIN
CVS Tags: tls-maxphys-base-20171202,
prg-localcount2-base3,
prg-localcount2-base2,
prg-localcount2-base1,
prg-localcount2-base,
prg-localcount2,
phil-wifi-base,
pgoyette-localcount-20170426,
pgoyette-localcount-20170320,
pgoyette-localcount-20170107,
pgoyette-compat-base,
pgoyette-compat-1020,
pgoyette-compat-0930,
pgoyette-compat-0906,
pgoyette-compat-0728,
pgoyette-compat-0625,
pgoyette-compat-0521,
pgoyette-compat-0502,
pgoyette-compat-0422,
pgoyette-compat-0415,
pgoyette-compat-0407,
pgoyette-compat-0330,
pgoyette-compat-0322,
pgoyette-compat-0315,
perseant-stdc-iso10646-base,
perseant-stdc-iso10646,
nick-nhusb-base-20170825,
nick-nhusb-base-20170204,
netbsd-8-base,
netbsd-8-2-RELEASE,
netbsd-8-1-RELEASE,
netbsd-8-1-RC1,
netbsd-8-0-RELEASE,
netbsd-8-0-RC2,
netbsd-8-0-RC1,
netbsd-8,
matt-nb8-mediatek-base,
matt-nb8-mediatek,
jdolecek-ncq-base,
jdolecek-ncq,
bouyer-socketcan-base1,
bouyer-socketcan-base,
bouyer-socketcan
Branch point for: phil-wifi,
pgoyette-compat
Changes since 1.77: +3 -2
lines
Diff to previous 1.77 (colored)
Add a synthesized pc beeper and keyboard bell for platforms with an audio device.
Revision 1.77 / (download) - annotate - [select for diffs], Thu Apr 17 16:01:24 2014 UTC (9 years, 11 months ago) by christos
Branch: MAIN
CVS Tags: yamt-pagecache-base9,
tls-maxphys-base,
tls-earlyentropy-base,
rmind-smpnet-nbase,
rmind-smpnet-base,
pgoyette-localcount-base,
pgoyette-localcount-20161104,
pgoyette-localcount-20160806,
pgoyette-localcount-20160726,
nick-nhusb-base-20161204,
nick-nhusb-base-20161004,
nick-nhusb-base-20160907,
nick-nhusb-base-20160529,
nick-nhusb-base-20160422,
nick-nhusb-base-20160319,
nick-nhusb-base-20151226,
nick-nhusb-base-20150921,
nick-nhusb-base-20150606,
nick-nhusb-base-20150406,
nick-nhusb-base,
netbsd-7-nhusb-base-20170116,
netbsd-7-nhusb-base,
netbsd-7-nhusb,
netbsd-7-base,
netbsd-7-2-RELEASE,
netbsd-7-1-RELEASE,
netbsd-7-1-RC2,
netbsd-7-1-RC1,
netbsd-7-1-2-RELEASE,
netbsd-7-1-1-RELEASE,
netbsd-7-1,
netbsd-7-0-RELEASE,
netbsd-7-0-RC3,
netbsd-7-0-RC2,
netbsd-7-0-RC1,
netbsd-7-0-2-RELEASE,
netbsd-7-0-1-RELEASE,
netbsd-7-0,
netbsd-7,
localcount-20160914
Branch point for: pgoyette-localcount,
nick-nhusb
Changes since 1.76: +4 -4
lines
Diff to previous 1.76 (colored)
CID/1203191: Out of bounds read
Revision 1.76 / (download) - annotate - [select for diffs], Thu Mar 27 18:22:56 2014 UTC (9 years, 11 months ago) by christos
Branch: MAIN
CVS Tags: riastradh-xf86-video-intel-2-7-1-pre-2-21-15
Branch point for: tls-earlyentropy
Changes since 1.75: +4 -2
lines
Diff to previous 1.75 (colored)
correct/add protection against snprintf overflow.
Revision 1.75 / (download) - annotate - [select for diffs], Wed Dec 11 02:14:08 2013 UTC (10 years, 3 months ago) by msaitoh
Branch: MAIN
CVS Tags: riastradh-drm2-base3
Changes since 1.74: +16 -26
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Diff to previous 1.74 (colored)
Make new function named tsc_is_invariant() to avoid code duplication. The behavior of acpicpu_md_flags() will change on some CPUs because the detecting code of invariant TSC is replaced with newer code.
Revision 1.74 / (download) - annotate - [select for diffs], Wed Nov 20 13:52:30 2013 UTC (10 years, 4 months ago) by jruoho
Branch: MAIN
Changes since 1.73: +3 -3
lines
Diff to previous 1.73 (colored)
Allow 4-bit range for MSR_THERM_CONTROL.
Revision 1.73 / (download) - annotate - [select for diffs], Fri Nov 15 08:47:55 2013 UTC (10 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.72: +4 -10
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Diff to previous 1.72 (colored)
Modify some macros and add some new macros for CPU family and model to reduce code duplication and to avoid bug. CPUID_TO_STEPPING(cpuid) (not changed) CPUID_TO_FAMILY(cpuid) (new) CPUID_TO_MODEL(cpuid) (new) Return the display family and the display model. The macro names are the same as FreeBSD. CPUID_TO_BASEFAMILY(cpuid) (The old name was CPUID2FAMILY) CPUID_TO_BASEMODEL(cpuid) (The old name was CPUID2MODEL) Only for the base field. CPUID_TO_EXTFAMILY(cpuid) (The old name was CPUID2EXTFAMILY) CPUID_TO_EXTMODEL(cpuid) (The old name was CPUID2EXTMODEL) Only for the extended field. See http://mail-index.netbsd.org/port-amd64/2013/11/12/msg001978.html
Revision 1.72 / (download) - annotate - [select for diffs], Thu Dec 6 04:43:29 2012 UTC (11 years, 3 months ago) by jruoho
Branch: MAIN
CVS Tags: yamt-pagecache-base8,
yamt-pagecache-base7,
riastradh-drm2-base2,
riastradh-drm2-base1,
riastradh-drm2-base,
riastradh-drm2,
khorben-n900,
agc-symver-base,
agc-symver
Branch point for: rmind-smpnet
Changes since 1.71: +11 -2
lines
Diff to previous 1.71 (colored)
Disable C1E also on K8, if present. From Imre Vadasz <imre@vdsz.com> in PR install/47224.
Revision 1.71 / (download) - annotate - [select for diffs], Sat Feb 11 22:09:47 2012 UTC (12 years, 1 month ago) by jruoho
Branch: MAIN
CVS Tags: yamt-pagecache-base6,
yamt-pagecache-base5,
yamt-pagecache-base4,
netbsd-6-base,
netbsd-6-0-RELEASE,
netbsd-6-0-RC2,
netbsd-6-0-RC1,
matt-nb6-plus-nbase,
matt-nb6-plus-base,
matt-nb6-plus,
jmcneill-usbmp-base9,
jmcneill-usbmp-base8,
jmcneill-usbmp-base7,
jmcneill-usbmp-base6,
jmcneill-usbmp-base5,
jmcneill-usbmp-base4,
jmcneill-usbmp-base3,
jmcneill-usbmp-base2,
jmcneill-usbmp-base10
Branch point for: tls-maxphys,
netbsd-6-0,
netbsd-6
Changes since 1.70: +4 -3
lines
Diff to previous 1.70 (colored)
Fix missing case for AMD 0x15.
Revision 1.70 / (download) - annotate - [select for diffs], Sat Feb 11 22:07:53 2012 UTC (12 years, 1 month ago) by jruoho
Branch: MAIN
Changes since 1.69: +4 -3
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Diff to previous 1.69 (colored)
Add non-XPSS support for AMD family 15h a.k.a. "Bulldozer". Ok releng@.
Revision 1.69 / (download) - annotate - [select for diffs], Tue Nov 15 07:20:30 2011 UTC (12 years, 4 months ago) by jruoho
Branch: MAIN
CVS Tags: jmcneill-usbmp-pre-base2,
jmcneill-usbmp-base,
jmcneill-audiomp3-base,
jmcneill-audiomp3
Branch point for: jmcneill-usbmp
Changes since 1.68: +5 -60
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Diff to previous 1.68 (colored)
Add support for AMD family 12h. Also revert revision 1.67, as it implies maintenance burden for limited value. XXX: Need to add family 15h too.
Revision 1.68 / (download) - annotate - [select for diffs], Tue Oct 18 05:08:24 2011 UTC (12 years, 5 months ago) by jruoho
Branch: MAIN
CVS Tags: yamt-pagecache-base3,
yamt-pagecache-base2,
yamt-pagecache-base
Branch point for: yamt-pagecache
Changes since 1.67: +14 -12
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Diff to previous 1.67 (colored)
Convert to use cpufreq(9).
Revision 1.67 / (download) - annotate - [select for diffs], Sat Sep 24 19:41:40 2011 UTC (12 years, 5 months ago) by jruoho
Branch: MAIN
Changes since 1.66: +59 -2
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Diff to previous 1.66 (colored)
Try to obtain reliable MHz values for AMD familiesi 10h and 11h.
Revision 1.66 / (download) - annotate - [select for diffs], Sat Sep 24 11:17:25 2011 UTC (12 years, 5 months ago) by jruoho
Branch: MAIN
Changes since 1.65: +8 -5
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Diff to previous 1.65 (colored)
Be more intelligent; read the MSR_CMPHALT with rdmsr_safe() and set the C1E-flag based on this. Pointed out by jmcneill@.
Revision 1.65 / (download) - annotate - [select for diffs], Sat Sep 24 10:59:02 2011 UTC (12 years, 5 months ago) by jruoho
Branch: MAIN
Changes since 1.64: +4 -3
lines
Diff to previous 1.64 (colored)
As the detection of C1E is not entirely clear-cut, use rdmsr_safe() when reading the AMD "interrupt pending and CMP-halt register".
Revision 1.64 / (download) - annotate - [select for diffs], Wed Jul 13 07:34:55 2011 UTC (12 years, 8 months ago) by jruoho
Branch: MAIN
CVS Tags: jym-xensuspend-nbase,
jym-xensuspend-base
Changes since 1.63: +10 -6
lines
Diff to previous 1.63 (colored)
Do not disable interrupts at machine-level in the MI idle-loop entry.
Revision 1.63 / (download) - annotate - [select for diffs], Thu Jun 23 08:10:35 2011 UTC (12 years, 8 months ago) by jruoho
Branch: MAIN
Changes since 1.62: +18 -12
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Diff to previous 1.62 (colored)
Fix bug pointed out by njoly@.
Revision 1.62 / (download) - annotate - [select for diffs], Wed Jun 22 08:49:54 2011 UTC (12 years, 9 months ago) by jruoho
Branch: MAIN
Changes since 1.61: +34 -24
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Diff to previous 1.61 (colored)
Get rid of RUN_ONCE(9). Should fix PR # kern/44043.
Revision 1.61 / (download) - annotate - [select for diffs], Sun Jun 12 10:11:52 2011 UTC (12 years, 9 months ago) by jruoho
Branch: MAIN
Changes since 1.60: +2 -53
lines
Diff to previous 1.60 (colored)
Move the evaluation of the _PDC control method out from the acpicpu(4) driver to the main acpi(4) stack. Follow Linux and evaluate it early. Should fix PR port-amd64/42895, possibly also PR kern/42583, and many other comparable bugs. A common sense explanation is that Intel supplies additional CPU tables to OEMs. BIOS writers do not bother to modify their DSDTs, but instead load these extra tables dynamically as secondary SSDT tables. The actual Load() happens when the _PDC method is invoked, and thus namespace errors occur when the CPU-specific ACPI methods are not yet present but referenced in the AML by various drivers, including, but not limited to, acpitz(4).
Revision 1.60 / (download) - annotate - [select for diffs], Mon Jun 6 07:42:32 2011 UTC (12 years, 9 months ago) by jruoho
Branch: MAIN
CVS Tags: rmind-uvmplock-nbase,
rmind-uvmplock-base
Changes since 1.59: +14 -2
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Diff to previous 1.59 (colored)
When getting the frequency, use APERF/MPERF as a fallback method.
Revision 1.59 / (download) - annotate - [select for diffs], Tue May 31 14:45:36 2011 UTC (12 years, 9 months ago) by jruoho
Branch: MAIN
CVS Tags: cherry-xenmp-base
Branch point for: cherry-xenmp
Changes since 1.58: +2 -5
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Diff to previous 1.58 (colored)
Remove the sanity check that tested the internal consistency of the "FID/VID algorithm" used by K8. Tested by cegger@. The check is still included in the original powernow(4) (where possible failures have probably gone unnoticed because the driver is less noisy).
Revision 1.58 / (download) - annotate - [select for diffs], Mon Apr 4 20:37:55 2011 UTC (12 years, 11 months ago) by dyoung
Branch: MAIN
Changes since 1.57: +4 -4
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Diff to previous 1.57 (colored)
Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9), pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match predicate passed to pciide_compat_intr_establish() should ever modify their pci_attach_args argument, so make their pci_attach_args arguments const and deal with the fallout throughout the kernel. For the most part, these changes add a 'const' where there was no 'const' before, however, some drivers and MD code used to modify pci_attach_args. Now those drivers either copy their pci_attach_args and modify the copy, or refrain from modifying pci_attach_args: Xen: according to Manuel Bouyer, writing to pci_attach_args in pci_intr_map() was a leftover from Xen 2. Probably a bug. I stopped writing it. I have not tested this change. siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args. Probably a bug. I use a temporary variable. I have not tested this change. slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args. Probably a bug. Use a local pci_attach_args. I have not tested this change. viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the caller's pci_attach_args. Probably a bug. Make a local copy of the caller's pci_attach_args and modify the copy. I have not tested this change. While I'm here, make pci_mapreg_submap() static. With these changes in place, I have tested the compilation of these kernels: alpha GENERIC amd64 GENERIC XEN3_DOM0 arc GENERIC atari HADES MILAN-PCIIDE bebox GENERIC cats GENERIC cobalt GENERIC evbarm-eb NSLU2 evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200 KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425 evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3 evbmips64-el XLSATX evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266 OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT hp700 GENERIC i386 ALL XEN3_DOM0 XEN3_DOMU ibmnws GENERIC macppc GENERIC mvmeppc GENERIC netwinder GENERIC ofppc GENERIC prep GENERIC sandpoint GENERIC sgimips GENERIC32_IP2x sparc GENERIC_SUN4U KRUPS sparc64 GENERIC As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels with or without my patches in place: ### evbmips-el GDIUM nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop ### evbarm-el MPCSA_GENERIC src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc' ### ia64 GENERIC /tmp/genassym.28085/assym.c: In function 'f111': /tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb' /tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type ### sgimips GENERIC32_IP3x crmfb.o: In function `crmfb_attach': crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid' crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid' crmfb.c:(.text+0x234c): undefined reference to `edid_parse' crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse' crmfb.c:(.text+0x2354): undefined reference to `edid_print' crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'
Revision 1.57 / (download) - annotate - [select for diffs], Thu Mar 24 11:52:53 2011 UTC (12 years, 11 months ago) by jruoho
Branch: MAIN
Changes since 1.56: +13 -11
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Diff to previous 1.56 (colored)
Reset APERF and MPERF only after interrupts have been enabled.
Revision 1.56 / (download) - annotate - [select for diffs], Thu Mar 24 05:10:05 2011 UTC (12 years, 11 months ago) by jruoho
Branch: MAIN
Changes since 1.55: +19 -41
lines
Diff to previous 1.55 (colored)
Remove the "simple CPU lock" that was unnecessary. Thanks to rmind@ for clarifications.
Revision 1.55 / (download) - annotate - [select for diffs], Sat Mar 5 09:47:19 2011 UTC (13 years ago) by jruoho
Branch: MAIN
CVS Tags: bouyer-quota2-nbase
Branch point for: rmind-uvmplock
Changes since 1.54: +105 -85
lines
Diff to previous 1.54 (colored)
Add __cpu_simple_lock_t. Use it, x86_read_psl(), and x86_disable_intr() to disable interrupts locally and protect the access to APERF and MPERF. Also rationalize the MD initialization sequence.
Revision 1.54 / (download) - annotate - [select for diffs], Sat Mar 5 06:39:55 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.53: +11 -6
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Diff to previous 1.53 (colored)
If the P-state control mask is set, do a proper read-modify-write.
Revision 1.53 / (download) - annotate - [select for diffs], Fri Mar 4 12:10:49 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.52: +8 -8
lines
Diff to previous 1.52 (colored)
Rename a badly named constant. Make it correspond with <x86/specialreg.h>.
Revision 1.52 / (download) - annotate - [select for diffs], Wed Mar 2 06:23:17 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.51: +4 -3
lines
Diff to previous 1.51 (colored)
Adjust the detection of Turbo Boost to prevent a theoretical array OOB access.
Revision 1.51 / (download) - annotate - [select for diffs], Wed Mar 2 06:17:09 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.50: +10 -4
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Diff to previous 1.50 (colored)
Append Intel's Turbo Boost to the debug printfs if we detect it.
Revision 1.50 / (download) - annotate - [select for diffs], Tue Mar 1 05:02:16 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.49: +16 -28
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Diff to previous 1.49 (colored)
Remove the cross-call from the APERF/MPERF -function.
Revision 1.49 / (download) - annotate - [select for diffs], Tue Mar 1 04:35:48 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.48: +31 -108
lines
Diff to previous 1.48 (colored)
Move the xcall(9) that does the P- and T-state transformations from the MD layer to the main code. Makes the caches coherent and provides consistent vmstat(1) output. This is still not quite right, given that most of the cross-calls are typically unnecessary with the dependency coordination.
Revision 1.48 / (download) - annotate - [select for diffs], Sun Feb 27 18:32:54 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.47: +22 -2
lines
Diff to previous 1.47 (colored)
Provide MD wrappers for match and attach.
Revision 1.47 / (download) - annotate - [select for diffs], Sun Feb 27 17:27:28 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.46: +8 -3
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Diff to previous 1.46 (colored)
Claim to support the dependency coordination during the _PDC/_OSC query. (Although we do not actually support it.) Only after these bits are set, many Intel-based BIOSes are willing to relinquish the necessary information.
Revision 1.46 / (download) - annotate - [select for diffs], Fri Feb 25 17:23:34 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.45: +17 -4
lines
Diff to previous 1.45 (colored)
Fix an oversight; the APERF and MPERF counters are per-CPU, so also reset these by broadcasting to all CPUs with x86_msr_xcall(9).
Revision 1.45 / (download) - annotate - [select for diffs], Fri Feb 25 17:07:30 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.44: +9 -2
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Diff to previous 1.44 (colored)
Add couple of comments.
Revision 1.44 / (download) - annotate - [select for diffs], Fri Feb 25 16:54:36 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.43: +16 -4
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Diff to previous 1.43 (colored)
Also declare support for APERF/MPERF during the BIOS _PDC/_OSC query.
Revision 1.43 / (download) - annotate - [select for diffs], Fri Feb 25 12:08:35 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.42: +10 -10
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Diff to previous 1.42 (colored)
Rename couple of badly named functions for consistency. No functional change.
Revision 1.42 / (download) - annotate - [select for diffs], Fri Feb 25 10:59:32 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.41: +29 -8
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Diff to previous 1.41 (colored)
Add support for APERF and MPERF on AMD processors.
Revision 1.41 / (download) - annotate - [select for diffs], Fri Feb 25 09:16:00 2011 UTC (13 years ago) by jruoho
Branch: MAIN
Changes since 1.40: +92 -4
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Diff to previous 1.40 (colored)
Add preliminary support for the IA32_APERF and IA32_MPERF frequency counters. These are not yet used for anything and only Intel is supported at the moment.
Revision 1.40 / (download) - annotate - [select for diffs], Thu Feb 24 13:19:36 2011 UTC (13 years ago) by jmcneill
Branch: MAIN
Changes since 1.39: +8 -4
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Diff to previous 1.39 (colored)
add support for Family 14h (AMD Fusion)
Revision 1.39 / (download) - annotate - [select for diffs], Tue Feb 15 17:50:46 2011 UTC (13 years, 1 month ago) by jruoho
Branch: MAIN
CVS Tags: uebayasi-xip-base7,
bouyer-quota2-base
Changes since 1.38: +18 -3
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Diff to previous 1.38 (colored)
Fix and add comments.
Revision 1.38 / (download) - annotate - [select for diffs], Thu Jan 13 03:40:50 2011 UTC (13 years, 2 months ago) by jruoho
Branch: MAIN
CVS Tags: jruoho-x86intr-base
Branch point for: jruoho-x86intr,
bouyer-quota2
Changes since 1.37: +5 -11
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Diff to previous 1.37 (colored)
Move the function that counts the CPUs from acpicpu(4) to the MD layer.
Revision 1.37 / (download) - annotate - [select for diffs], Thu Dec 30 17:06:17 2010 UTC (13 years, 2 months ago) by jruoho
Branch: MAIN
CVS Tags: matt-mips64-premerge-20101231
Changes since 1.36: +5 -2
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Diff to previous 1.36 (colored)
Add an additional assertion for the control MSR address.
Revision 1.36 / (download) - annotate - [select for diffs], Tue Nov 30 18:44:07 2010 UTC (13 years, 3 months ago) by jruoho
Branch: MAIN
Changes since 1.35: +7 -3
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Diff to previous 1.35 (colored)
Fix boolean brain freeze.
Revision 1.35 / (download) - annotate - [select for diffs], Tue Nov 30 04:31:00 2010 UTC (13 years, 3 months ago) by jruoho
Branch: MAIN
Changes since 1.34: +27 -4
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Diff to previous 1.34 (colored)
Add AMD C1E quirk. Tested by cegger@. (a) This should be removed once C-states are supported. (b) As there seems to be no reliable way to detect whether C1E is present, the quirk blindly assumes that C1E is used on families 10h and 11h.
Revision 1.34 / (download) - annotate - [select for diffs], Wed Aug 25 05:07:43 2010 UTC (13 years, 6 months ago) by jruoho
Branch: MAIN
CVS Tags: yamt-nfs-mp-base11,
uebayasi-xip-base6,
uebayasi-xip-base5,
uebayasi-xip-base4,
uebayasi-xip-base3
Branch point for: jym-xensuspend
Changes since 1.33: +5 -5
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Diff to previous 1.33 (colored)
Add definitions for Intel Digital Thermal Sensor and Power Management, at CPUID Fn0000_0006, %eax, %ecx. Use these instead of magic numbers.
Revision 1.33 / (download) - annotate - [select for diffs], Tue Aug 24 10:29:53 2010 UTC (13 years, 6 months ago) by jruoho
Branch: MAIN
Changes since 1.32: +25 -38
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Diff to previous 1.32 (colored)
As all reported P-state failures so far have centered around the status- check (today it was christos@' laptop), follow Linux and disable this rather expensive sanity-check for the time being. A hypothesis about the cause of the failures relates to the absence of cross-CPU coordination in the current implementation.
Revision 1.32 / (download) - annotate - [select for diffs], Tue Aug 24 07:28:00 2010 UTC (13 years, 6 months ago) by jruoho
Branch: MAIN
Changes since 1.31: +261 -14
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Diff to previous 1.31 (colored)
Add native support for AMD family 0Fh processors. This is the furthest we will go backwards; K7 will not be supported already due doubts about availability and reliability of ACPI during that era. Some unfortunate code duplication is present (but not overly much). Thanks to cegger@ and jakllsch@ for patiently testing this.
Revision 1.31 / (download) - annotate - [select for diffs], Mon Aug 23 16:20:44 2010 UTC (13 years, 6 months ago) by jruoho
Branch: MAIN
Changes since 1.30: +25 -14
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Diff to previous 1.30 (colored)
Other entry points beyond x86_cpu_idle_halt() may use HLT as the idle-mechanism. Send an IPI also for these in cpu_need_resched().
Revision 1.30 / (download) - annotate - [select for diffs], Sun Aug 22 04:42:57 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.29: +13 -6
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Diff to previous 1.29 (colored)
Still DELAY(9) a little even when we do not do the status-check.
Revision 1.29 / (download) - annotate - [select for diffs], Sat Aug 21 18:25:45 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.28: +9 -6
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Diff to previous 1.28 (colored)
After discussion with jakllsch@ and jmcneill@, revert the previous and only do the status-check when the comparison value reported by BIOS is not zero. The uncertainty noted in the previous commit still applies. But if we ever see a timeout again, it will likely be either a firmware bug or a special case like the Intel Turbo Boost.
Revision 1.28 / (download) - annotate - [select for diffs], Sat Aug 21 15:37:35 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.27: +8 -8
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Diff to previous 1.27 (colored)
When we do the sanity check that a P- or T-state transition was successful, compare also against the control-field. There appears to be many BIOSes in the field that report a zero value in the status-field. It is unclear whether this should be taken as a hint that the status-check is not necessary also during P-state transitions. If we still see timeouts (EAGAIN), this should be reverted and the status-check should be bypassed if ps->ps_status is 0.
Revision 1.27 / (download) - annotate - [select for diffs], Sat Aug 21 09:16:28 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.26: +9 -9
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Diff to previous 1.26 (colored)
Use an inverse logic when filling the (X)PSS structures -- if we know the addresses, we trust ourselves more than a random BIOS in the field.
Revision 1.26 / (download) - annotate - [select for diffs], Sat Aug 21 07:18:34 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.25: +8 -2
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Diff to previous 1.25 (colored)
Add a comment.
Revision 1.25 / (download) - annotate - [select for diffs], Sat Aug 21 06:45:50 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.24: +13 -13
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Diff to previous 1.24 (colored)
Check from CPUID 0x06 %eax (on Intel) whether we might actually have an invariant APIC timer or an "ARAT" ("always running APIC timer"). This means that the APIC timer may keep ticking at the same rate also in deep C-states with some new or forthcoming Intel CPUs.
Revision 1.24 / (download) - annotate - [select for diffs], Sat Aug 21 05:10:43 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.23: +35 -8
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Diff to previous 1.23 (colored)
Add a quirk for Turbo Boost. It was observed that at least Sverre Froyen's ThinkPad T500 reports values that do not match readings from the IA32_PERF_STATUS register. This only applied to the P0-state. Thus, for now, skip the status check if Turbo Boost has been detected and the requested state is P0. This needs to be revisited once Turbo Boost actually works in NetBSD. It is unclear whether this is a BIOS flaw or not; these values may well be what we get from IA32_PERF_STATUS once the CPU actually uses the +133.33 MHz boost.
Revision 1.23 / (download) - annotate - [select for diffs], Sat Aug 21 04:36:29 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.22: +17 -2
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Diff to previous 1.22 (colored)
Detect Intel's Turbo Boost and presence of IA32_APERF/IA32_MPERF. The former is required for a quirk, and the latter is needed for hardware P-state coordination (once acpicpu(4) will support fine-grained coordination).
Revision 1.22 / (download) - annotate - [select for diffs], Sat Aug 21 03:55:24 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.21: +39 -3
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Diff to previous 1.21 (colored)
Detect whether TSC is invariant, which may be the case on both new AMD and Intel processors. The invariance means that TSC runs at a constant rate during all ACPI state changes. If it is variant, skew may occur and TSC is generally unsuitable for wall clock services. This is especially relevant with C-states; with variant TSC, the whole counter may be stopped with states larger than C1. All x86 CPUs before circa mid-2000s can be assumed to have a variant time stamp counter.
Revision 1.21 / (download) - annotate - [select for diffs], Sat Aug 21 02:47:37 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.20: +9 -3
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Diff to previous 1.20 (colored)
Properly detect AMD hardware P-state support. Also detect "core boost" (only present in some models of family 10h).
Revision 1.20 / (download) - annotate - [select for diffs], Fri Aug 20 07:00:17 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.19: +23 -2
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Diff to previous 1.19 (colored)
Check if SpeedStep is enabled. If it is disabled, try to enable it.
Revision 1.19 / (download) - annotate - [select for diffs], Fri Aug 20 06:34:32 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.18: +197 -202
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Diff to previous 1.18 (colored)
Revert all previous changes that were made naively believing that the existing CPU power management implementations could peacefully coexist with the acpicpu(4) driver. The following options can not be used with acpicpu(4): ENHANCED_SPEEDSTEP, INTEL_ONDEMAND_CLOCKMOD, POWERNOW_K7, and POWERNOW_K8.
Revision 1.18 / (download) - annotate - [select for diffs], Thu Aug 19 21:40:45 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.17: +16 -6
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Diff to previous 1.17 (colored)
Properly calculate the AMD CPU family.
Revision 1.17 / (download) - annotate - [select for diffs], Thu Aug 19 18:30:24 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.16: +42 -38
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Diff to previous 1.16 (colored)
Add native P-state support for AMD family 10h and 11h processors. Both are supported irrespective of XPSS. Family 10h tested by jakllsch@.
Revision 1.16 / (download) - annotate - [select for diffs], Thu Aug 19 11:08:33 2010 UTC (13 years, 7 months ago) by jmcneill
Branch: MAIN
Changes since 1.15: +19 -8
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Diff to previous 1.15 (colored)
VIA CPUs can have EST as well, so treat them the same as Intel
Revision 1.15 / (download) - annotate - [select for diffs], Wed Aug 18 18:32:20 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.14: +52 -40
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Diff to previous 1.14 (colored)
Use the idea from cegger@ and fill the (X)PSS structure during initialization.
Revision 1.14 / (download) - annotate - [select for diffs], Wed Aug 18 16:08:50 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.13: +48 -34
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Diff to previous 1.13 (colored)
Check the status of P- and T-state transformations on all CPUs. This is still not ideal, as ACPI gives us information about "cross logical processor dependencies". For instance, a single MSR call on one CPU may cause all other CPUs in the same domain to follow the state shift. Thus, rather than using xc_broadcast(9), we should xc_unicast(9) on per-domain or per-CPU-set basis.
Revision 1.13 / (download) - annotate - [select for diffs], Wed Aug 18 04:12:29 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.12: +91 -51
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Diff to previous 1.12 (colored)
Add MD support for the vendor-independent extended PSS. Some conforming AMD systems are known to work. Alas, not all of them. We still need to deal with the variety of different PowerNow! revisions.
Revision 1.12 / (download) - annotate - [select for diffs], Sat Aug 14 05:13:20 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
CVS Tags: uebayasi-xip-base2
Branch point for: uebayasi-xip
Changes since 1.11: +34 -4
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Diff to previous 1.11 (colored)
Move the PIIX4-quirk to the MD file and disable T-states for PIIX4.
Revision 1.11 / (download) - annotate - [select for diffs], Fri Aug 13 18:44:24 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.10: +2 -12
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Diff to previous 1.10 (colored)
Remove some unnecessary locking. Mainly a leftover from previous revisions where the dynamic maximum/minimum was used also when retrieving the current state. The state-array itself changes only in C-states.
Revision 1.10 / (download) - annotate - [select for diffs], Fri Aug 13 16:21:50 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.9: +101 -11
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Diff to previous 1.9 (colored)
Merge T-state a.k.a. throttling support for acpicpu(4). Remarks: 1. Native instructions are supported only on Intel. Native support for other x86 vendors will be investigated. By assumption, AMD and others use the I/O based approach. 2. The existing code, INTEL_ONDEMAND_CLOCKMOD, must be disabled in order to use acpicpu(4). Otherwise fatal MSR races may occur. Unlike with P-states, no attempt is done to disable the existing implementation. 3. There is no rationale to export controls to user land. 4. Throttling is an artefact from the past. T-states will not be used for power management per se. For CPU frequency management, P-states are preferred in all circumstances. No noticeable additional power savings were observed in various experiments. When the system has been scaled to the highest (i.e. lowest power) P-state, it is preferable to move from C0 to deeper C-states than it is to actively throttle the CPU. 5. But T-states need to be implemented for passive cooling via acpitz(4). As specified by ACPI and Intel documents, these can be used as the last line of defence against critical thermal conditions. Support for this will be added later.
Revision 1.9 / (download) - annotate - [select for diffs], Mon Aug 9 15:46:17 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
CVS Tags: yamt-nfs-mp-base10
Branch point for: yamt-nfs-mp
Changes since 1.8: +86 -9
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Diff to previous 1.8 (colored)
Revert the previous changes to EST. The used hack had an obvious flaw: the acpicpu(4) driver should attach even if the existing frequency management code fails to attach, mainly because ACPI is the only proper way to deal with EST on new Intel system. Use a more drastic hack to deal with this: when acpicpu(4) attachs, it tears down any existing sysctl(8) controls and installs identical ones in place. Upon detachment, the initialization function of the existing EST is called.
Revision 1.8 / (download) - annotate - [select for diffs], Mon Aug 9 13:41:39 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.7: +3 -13
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Diff to previous 1.7 (colored)
Remove a redundant function.
Revision 1.7 / (download) - annotate - [select for diffs], Mon Aug 9 04:27:07 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.6: +3 -3
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Diff to previous 1.6 (colored)
When retrieving the current frequency, scan all available P-states. Only use the dynamic maximum when setting a frequency.
Revision 1.6 / (download) - annotate - [select for diffs], Mon Aug 9 04:18:48 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.5: +8 -24
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Diff to previous 1.5 (colored)
Move the sysctl function pointers used by acpicpu(4) to x86/cpu.c. Rename these so that the same pointers may be used in other parts.
Revision 1.5 / (download) - annotate - [select for diffs], Sun Aug 8 16:58:41 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.4: +254 -13
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Diff to previous 1.4 (colored)
Merge P-state support for acpicpu(4). Remarks: 1. All processors (x86 or not) for which the vendor has implemented ACPI I/O access routines are supported. Native instructions are currently supported only for Intel's "Enhanced Speedstep". Code for "PowerNow!" (AMD) will be merged later. Native support for VIA's "PowerSaver" will be investigated. 2. Backwards compatibility with existing userland code is maintained. Comparable to the case with cpu_idle(9), the ACPI CPU driver installs alternative functions for the existing sysctl(8) controls. The "native" behavior (if any) is restored upon detachment. 3. The dynamic nature of ACPI-provided P-states needs more investigation. The maximum frequency induced (but not forced) by the firmware may change dynamically. Currently, the sysctl(8) controls error out with a value larger than the dynamic maximum. The code itself does not however yet react to the notifications from the firmware by changing the frequencies in-place. Presumably the system administrator should be able to choose whether to use dynamic or static frequencies.
Revision 1.4 / (download) - annotate - [select for diffs], Wed Aug 4 16:16:55 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.3: +10 -5
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Diff to previous 1.3 (colored)
Run a xcall(9) to ensure that all CPUs are out from the ACPI idle-loop before detachment.
Revision 1.3 / (download) - annotate - [select for diffs], Fri Jul 23 13:54:21 2010 UTC (13 years, 7 months ago) by jruoho
Branch: MAIN
Changes since 1.2: +19 -8
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Diff to previous 1.2 (colored)
Make sure we use MWAIT with MONITOR. Also clarify when we have interrupts disabled.
Revision 1.2 / (download) - annotate - [select for diffs], Sun Jul 18 09:39:45 2010 UTC (13 years, 8 months ago) by jruoho
Branch: MAIN
Changes since 1.1: +2 -2
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Diff to previous 1.1 (colored)
Add missing CVS identifiers.
Revision 1.1 / (download) - annotate - [select for diffs], Sun Jul 18 09:29:13 2010 UTC (13 years, 8 months ago) by jruoho
Branch: MAIN
Merge a driver for ACPI CPUs with basic support for processor power states, also known as C-states. The code is modular and provides an easy way to add the remaining functionality later (namely throttling and P-states). Remarks: 1. Commented out in the GENERICs; more testing exposure is needed. 2. The C3-state is disabled for the time being because it turns off timers, among them the local APIC timer. This may not be universally true on all x86 processors; define ACPICPU_ENABLE_C3 to test. 3. The algorithm used to choose a power state may need tuning. When evaluating the appropriate state, the implementation uses the previous sleep time as an indicator. Additional hints would include for example the system load. Also bus master activity is evaluated when choosing a state. The usb(4) stack is notorious for such activity even when unused. Typically it must be disabled in order to reach the C3-state, but it may also prevent the use of C2. 4. While no extensive empirical measurements have been carried out, the power savings are somewhere between 1-2 W with C1 and C2, depending on the processor, firmware, and load. With C3 even up to 4 W can be saved. The less something ticks, the more power is saved. ok jmcneill@, joerg@, and discussed with various people.