version 1.1, 1996/07/20 17:58:28 |
version 1.2, 1998/05/22 09:49:08 |
Line 76 struct confargs { |
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Line 76 struct confargs { |
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#define ca_leflags ca_aux2 |
#define ca_leflags ca_aux2 |
}; |
}; |
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int vsbus_intr_register __P((struct confargs *, int(*)(void*), void*)); |
struct vsbus_attach_args { |
int vsbus_intr_enable __P((struct confargs *)); |
int va_type; |
int vsbus_intr_disable __P((struct confargs *)); |
}; |
int vsbus_intr_unregister __P((struct confargs *)); |
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/* |
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* Some chip addresses and constants, same on all VAXstations. |
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*/ |
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#define NI_ADDR 0x20090000 /* Ethernet address */ |
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#define DZ_CSR 0x200a0000 /* DZ11-compatible chip csr */ |
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#define VS_CLOCK 0x200b0000 /* clock chip address */ |
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#define NI_BASE 0x200e0000 /* LANCE CSRs */ |
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#define NI_IOSIZE (128 * NBPG) /* IO address size */ |
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#define VS_REGS 0x20080000 /* Misc cpu internal regs */ |
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/* |
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* interrupt vector numbers |
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*/ |
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#define IVEC_BASE 0x20040020 |
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#define IVEC_SR 0x000002C0 |
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#define INR_SR 7 |
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#define IVEC_ST 0x000002C4 |
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#define INR_ST 6 |
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#define IVEC_NP 0x00000250 |
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#define INR_NP 5 |
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#define IVEC_NS 0x00000254 |
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#define INR_NS 4 |
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#define IVEC_VF 0x00000244 |
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#define INR_VF 3 |
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#define IVEC_VS 0x00000248 |
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#define INR_VS 2 |
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#define IVEC_SC 0x000003F8 |
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#define INR_SC 1 |
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#define IVEC_DC 0x000003FC |
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#define INR_DC 0 |
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caddr_t dz_regs; /* On-board serial line */ |
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caddr_t le_iomem; /* base addr of RAM -- CPU's view */ |
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short *lance_csr; /* LANCE CSR virtual address */ |
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int *lance_addr; /* Ethernet address */ |
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struct vs_cpu *vs_cpu; /* Common CPU registers */ |
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void vsbus_intr_enable __P((int)); |
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void vsbus_intr_disable __P((int)); |
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void vsbus_intr_attach __P((int, void(*)(int), int)); |
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int vsbus_lockDMA __P((struct confargs *)); |
int vsbus_lockDMA __P((struct confargs *)); |
int vsbus_unlockDMA __P((struct confargs *)); |
int vsbus_unlockDMA __P((struct confargs *)); |