CVS log for src/sys/arch/sparc64/include/intr.h

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Pull up following revision(s) (requested by jdc in ticket #360):

	sys/arch/sparc64/dev/fdc.c: revision 1.52
	sys/arch/sparc64/include/intr.h: revision 1.32
	sys/arch/sparc64/sparc64/autoconf.c: revision 1.239
	sys/arch/sparc64/include/psl.h: revision 1.64

sparc64: fix interrupt level mapping for disk and and parallel devices
on SBUS-based machines

Change the mapping from PIL_SCSI to PIL_BIO, so that they interrupt above
the highest soft interrupt (softserial)

Remove unused PIL_SCSI, PIL_FDSOFT, PIL_AUSOFT and fix the printf in fdc.c

Add "socal" and "SUNW,bpp" to the interrupt map.

sparc64: fix interrupt level mapping for disk and and parallel devices
on SBUS-based machines
Change the mapping from PIL_SCSI to PIL_BIO, so that they interrupt above
the highest soft interrupt (softserial)
Remove unused PIL_SCSI, PIL_FDSOFT, PIL_AUSOFT and fix the printf in fdc.c
Add "socal" and "SUNW,bpp" to the interrupt map.

sync with head

Remove safepri and use IPL_SAFEPRI instead.  This may be defined in a MD
header file (if not, a value of 0 is assmued).

Sync with HEAD.

sync with head

install <machine/intr.h> for crash(8).

(we could avoid this, but it would require a lot of contortions that
make the header files ugly.  maybe someone else can figure out a less
ugly way of doing this later.)

Sync with HEAD.

sync with head.

sync with head

Make C declarations match assembler reality: ipi functions get two arguments
(which most of them (partly) ignore, but anyway).

Sync with HEAD.

sync with head

clean up a bunch of MULTIPROCESSOR:

- always include ci_ipi_evcnt[] in cpuinfo
- #define sparc_ncpus 1 for !MULTIPROCESSOR
- make struct pmap::pm_list an pm_ctx always be an array, and simplify
  several functions and lookups to always be the same

tested on U60 and SB2500 before and after with one and two cpus in an
MP kernel, and UP kernels, and i can't find anything besides noise for
benchmark issues.  (infact, i can't really tell the difference between
GENERIC and GENERIC.MP on these systems...)

- add a PDB_CTX_FLUSHALL debug type to pmap.c, and also log the cpu_number()
  in a bunch more cases

- make sparc64_ipi_halt_thiscpu() and sparc64_ipi_pause_thiscpu() return void,
  their callers never checked anyway.

- remove prototypes for sparc64_ipi_flush_ctx() and sparc64_ipi_flush_all(),
  there are no such functions

sparc64_ipi_flush_ctx and sparc64_ipi_flush_all have been removed,
so remove its event counters as well.

Sync with HEAD.

sync with head.

sync with head.

Remove clause 3 and 4 from TNF licenses

#include "opt_multiprocessor.h"
#include <machine/psl.h>

Make sparc64 kernel build again.

Remove sparc64_ipi_sync_tick.

Since we can use counter-timer as timecounter instead of %tick on SMP kernel,
it is not necessary to sync all CPUs %tick registers.

Sync with HEAD.

sync with head.

sync with HEAD

sync with head.

Improve IPI handling:
- make IPI takes two arguments.
- add IPI event counters per-CPU.
- implement IPI functions which were missing or broken.
- insert DELAY while halting primary CPU in IPI handler.

Make ddb's "mach cpu" command do the right thing: run ddb on the requested
cpu. There is a tiny bit of cheating involved, but I assume we won't run
parallel + recursive ddb scripts to play towers of hanoi.

This fixes the wrong prompt, and (more importantly) makes things like
"mach dtlb" display the registers of the right MMU.

Sync with HEAD.

sync with head

Sync with HEAD

Rename cpuset_t for now to sparc64_cpuset_t, to avoid a name clash with
<sys/pset.h>. Mid-term we should probably convert to the MI cpuset_t.

sync with HEAD

Sync with HEAD.

Sync with HEAD.

sync with head

Sync with HEAD.

Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

sync with head.

Sync with head.

Sync with head.

Update to HEAD.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

Add missing prototype for MP kernels

sync with head.

Sync with head.

sync with head

Initial support for floppy drives on sparc64.  This has been tested
on an Ultra 2 and works fine, apart from formatting which is known
to be broken.  It failed to work on an ebus machine.  The ebus
support compiles fine, but I don't have hardware for testing.  This
code is based on the sparc driver with hints from OpenBSD on how
to do the sbus and ebus attachments, along with help from martin@
and mrg@.

Initial commit approved by martin@

TODO:
- fix ebus support
- fix XXX issues
- check resource deallocation
- fix formatting
- merge remaining differences from sparc driver
- split out back end chip support
- have sparc driver use new common back end chip support
- adapt to newlock when branch is ready
- adapt to "disk-info" property dictionary

file intr.h was added on branch yamt-splraiseipl on 2006-10-22 06:05:11 +0000

Lazy FPU handling for the MULTIPROCESSOR case

sync with head.

SMP cleanup.  provide support for multiple CPUs in DDB.  (SMP itself
is still not working.)

cpu.h:
- add a pointer for DDB regs in SMP environment to struct cpu_info
- remove the #defines for mp_pause_cpus() and mp_resume_cpus()
cpuset.h:
- remove CPUSET_ALL() and rename CPUSET_ALL_BUT() to CPUSET_EXCEPT()
  from petrov.
db_machdep.h:
- rename the members of db_regs_t to be the same as sparc
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
  all references to suit
- redo DDB_REGS to no longer be a pointer to a fixed data structure
  but to one allocated per-cpu when ddb is entered
- move a bunch of prototypes in here
intr.h:
- remove SPARC64_IPI_* macros, no longer used
db_interface.c:
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
  all references to suit
- make "nil" a 64 bit entity
- change the ddb register access methods to work in multiprocessor
  environment, it is now very much like sparc does it
- in kdb_trap() avoid accessing ddb_regp when it is NULL
- update several messages to include the cpu number
- unpause other cpus much later when resuming from ddb
- rename db_lock() to db_lock_cmd(), as the sparc-like code has
  db_lock as a simple lock
- remove "mach cpus" command, and replace it with "mach cpu" (which
  does the same) and also implement "mach cpu N" to switch to
  another cpus saved trapframe
db_trace.c:
- update for the ddb_regs -> ddb_regp change
genassym.cf:
- add TF_KSTACK as offsetof(struct trapframe64, tf_kstack)
ipifuncs.c:
- overhaul extensively
- remove all normal interrupt handlers as IPI's, we now handle
  them all specially in locore.s:interrupt_vector
- add a simplelock around all ipi functions - it's not safe for
  multiple cpus to be sending IPI's to each other right now
- rename sparc64_ipi_pause() to sparc64_ipi_pause_thiscpu() and,
  if DDB is configured, enable it to save the passed-in trapframe
  to a db_regs_t for this cpu's saved DDB registers.
- remove the "ipimask" system (SPARC64_IPI_* macros) and instead
  pass functions directly
- in sparc64_send_ipi() always set the interrupt arguments to 0,
  the address and argument of the to be called function.  (the
  argument right now is the address of ipi_tlb_args variable, and
  part of the reason why only one CPU can send IPI's at a time.)
  don't wait forever for an IPI to complete.  some of this is
  from petrov.
- rename sparc64_ipi_{halt,pause,resume}_cpus() to
  mp_{halt,pause,resume}_cpus()
- new function mp_cpu_is_paused() used to avoid access missing
  saved DDB registers
- actually broadcast the flush in smp_tlb_flush_pte(),
  smp_tlb_flush_ctx() and smp_tlb_flush_all().  the other end may
  not do anything yet in the pte/ctx cases yet...
kgdb_machdep.c:
- rework for changed member names in db_regs_t.
locore.s:
- shave an instruction from syscall_setup() (set + ld -> sethi + ld)
- remove some old dead debug code
- add new sparc64_ipi_halt IPI entry point, it just calls the C
  vector to shutdown.
- add new sparc64_ipi_pause IPI entry point, which just traps into
  the debugger using the normal breakpoint trap.  these cpus usually
  lose the race in db_interface.c:db_suspend_others() and end up
  calling the C vector sparc64_ipi_pause_thiscpu().
- add #if 0'ed code to sparc64_ipi_flush_{pte,ctx}() IPI entry
  points to call the sp_ version of these functions.
- in rft_kernel (return from trap, kernel), check to see if the
  %tpc is at the sparc64_ipi_pause_trap_point and if so, call
  "done" not "retry"
- rework cpu_switch slightly:  save the passed-in lwp instead of
  using the one in curlwp
- in cpu_loadproc(), save the new lwp not the old lwp, to curlwp
- in cpu_initialize(), set %tl to zero as well.  from petrov.
- in cpu_exit(), fix a load register confusion.  from petrov.
- change some "set" in delay branch to "mov".
machdep.c:
- deal with function renames
pmap.c:
- remove a spurious space
trap.c:
- remove unused "trapstats" variable
- add cpu number to a couple of messages

sync with head

sync with head.

Sync with head.

Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.

sync with head.

sync with head

pull splraiseipl() for sparc64 from newlock branch.
reviewed by Martin Husemann.

merge ktrace-lwp.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

De-_P()fy, remove not MULTIPROCESSOR defines for sparc64_ipi_xxx.

checkpoint of MP work from dennis and myself.  includes cross-processor
interrupt framework, a sledgehammer TLB invalidation and misc MP fixes.
doesn't work at all yet.

Rename IPL_IMP -> IPL_VM.

IPL_IMP -> IPL_VM

Sync with head (for UBC+NFS fixes, mostly).

Rename __GENERIC_SOFT_INTERRUPTS to __HAVE_GENERIC_SOFT_INTERRUPTS,
and place the definition in <machine/types.h>.  This can now be used
as a flag to indicate whether or not <machine/intr.h> can be included
to get the generic soft interrupt API.

Sync with HEAD.

Make softintr_establish prototype match other ports, avoiding compile
warnings.

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Update the scheduler to the new locking scheme.

pullup the contents of -current arch/sparc64.  this gives us significant
ultrasparc PCI support (ultra5, ultra10, AXi, and E250 tested so far),
plus many other small fixes.  netbooting is now supported.

Advertise we have __GENERIC_SOFT_INTERRUPTS.

Make these interrupt levels reflect reality a bit better.

Sync w/ netbsd-1-5-base.

New softintr interface.

Revamp interrupts again:

	Fix a bug causing interrmittent panics in interrupt dispatch.
	Use interrupt vectors for softints.
	Add a new send_softint interface.
	Improved D$ flushing.
	Improve traptrace and other debugging enhancements.

Sync w/ -current.

clone intr.h from the SPARC.