version 1.91.2.5, 1997/09/29 07:20:44 |
version 1.91.2.6, 1997/10/14 10:18:49 |
Line 319 char *ctxbusyvector; /* [4m] tells what |
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Line 319 char *ctxbusyvector; /* [4m] tells what |
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#endif |
#endif |
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caddr_t vpage[2]; /* two reserved MD virtual pages */ |
caddr_t vpage[2]; /* two reserved MD virtual pages */ |
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#if defined(SUN4M) |
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int *vpage_pte[2]; /* pte location of vpage[] */ |
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#endif |
caddr_t vmmap; /* one reserved MI vpage for /dev/mem */ |
caddr_t vmmap; /* one reserved MI vpage for /dev/mem */ |
caddr_t vdumppages; /* 32KB worth of reserved dump pages */ |
caddr_t vdumppages; /* 32KB worth of reserved dump pages */ |
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Line 3284 pmap_bootstrap4m(void) |
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Line 3287 pmap_bootstrap4m(void) |
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vmmap = p, p += NBPG; |
vmmap = p, p += NBPG; |
p = reserve_dumppages(p); |
p = reserve_dumppages(p); |
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/* Find PTE locations of vpage[] to optimize zero_fill() et.al. */ |
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for (i = 0; i < 2; i++) { |
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struct regmap *rp; |
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struct segmap *sp; |
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rp = &pmap_kernel()->pm_regmap[VA_VREG(vpage[i])]; |
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sp = &rp->rg_segmap[VA_VSEG(vpage[i])]; |
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vpage_pte[i] = &sp->sg_pte[VA_SUN4M_VPG(vpage[i])]; |
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} |
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/* |
/* |
* Allocate virtual memory for pv_table[], which will be mapped |
* Allocate virtual memory for pv_table[], which will be mapped |
* sparsely in pmap_init(). |
* sparsely in pmap_init(). |
Line 3723 pmap_release(pm) |
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Line 3735 pmap_release(pm) |
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ctx_free(pm); |
ctx_free(pm); |
} |
} |
} |
} |
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#if defined(SUN4M) |
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if (CPU_ISSUN4M) { |
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if ((c = pm->pm_ctx) != NULL) { |
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if (pm->pm_ctxnum == 0) |
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panic("pmap_release: releasing kernel"); |
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ctx_free(pm); |
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} |
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pgtfree(pm->pm_reg_ptps, SRMMU_L1SIZE * sizeof(int)); |
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pm->pm_reg_ptps = NULL; |
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pm->pm_reg_ptps_pa = 0; |
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} |
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#endif |
splx(s); |
splx(s); |
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#ifdef DEBUG |
#ifdef DEBUG |
Line 3751 if (pmapdebug) { |
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Line 3776 if (pmapdebug) { |
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} |
} |
} |
} |
#endif |
#endif |
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if (pm->pm_regstore) |
if (pm->pm_regstore) |
free(pm->pm_regstore, M_VMPMAP); |
free(pm->pm_regstore, M_VMPMAP); |
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if (CPU_ISSUN4M) { |
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if ((c = pm->pm_ctx) != NULL) { |
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if (pm->pm_ctxnum == 0) |
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panic("pmap_release: releasing kernel"); |
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ctx_free(pm); |
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} |
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pgtfree(pm->pm_reg_ptps, SRMMU_L1SIZE * sizeof(int)); |
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pm->pm_reg_ptps = NULL; |
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pm->pm_reg_ptps_pa = 0; |
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} |
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} |
} |
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/* |
/* |
Line 6215 pmap_zero_page4m(pa) |
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Line 6230 pmap_zero_page4m(pa) |
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{ |
{ |
register caddr_t va; |
register caddr_t va; |
register int pte; |
register int pte; |
int ctx; |
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if (((pa & (PMAP_TNC_SRMMU & ~PMAP_NC)) == 0) && managed(pa)) { |
if (((pa & (PMAP_TNC_SRMMU & ~PMAP_NC)) == 0) && managed(pa)) { |
/* |
/* |
Line 6233 pmap_zero_page4m(pa) |
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Line 6247 pmap_zero_page4m(pa) |
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else |
else |
pte &= ~SRMMU_PG_C; |
pte &= ~SRMMU_PG_C; |
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/* XXX - must use context 0 or else setpte4m() will fail */ |
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ctx = getcontext4m(); |
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setcontext4m(0); |
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va = vpage[0]; |
va = vpage[0]; |
setpte4m((vm_offset_t) va, pte); |
*vpage_pte[0] = pte; |
qzero(va, NBPG); |
qzero(va, NBPG); |
setpte4m((vm_offset_t) va, SRMMU_TEINVALID); |
/* Remove temporary mapping */ |
setcontext4m(ctx); |
tlb_flush_page((int)va); |
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*vpage_pte[0] = SRMMU_TEINVALID; |
} |
} |
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/* |
/* |
Line 6258 pmap_copy_page4m(src, dst) |
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Line 6270 pmap_copy_page4m(src, dst) |
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{ |
{ |
register caddr_t sva, dva; |
register caddr_t sva, dva; |
register int spte, dpte; |
register int spte, dpte; |
int ctx; |
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if (managed(src)) { |
if (managed(src)) { |
if (CACHEINFO.c_vactype == VAC_WRITEBACK) |
if (CACHEINFO.c_vactype == VAC_WRITEBACK) |
Line 6279 pmap_copy_page4m(src, dst) |
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Line 6290 pmap_copy_page4m(src, dst) |
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else |
else |
dpte &= ~SRMMU_PG_C; |
dpte &= ~SRMMU_PG_C; |
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/* XXX - must use context 0 or else setpte4m() will fail */ |
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ctx = getcontext4m(); |
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setcontext4m(0); |
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sva = vpage[0]; |
sva = vpage[0]; |
dva = vpage[1]; |
dva = vpage[1]; |
setpte4m((vm_offset_t) sva, spte); |
*vpage_pte[0] = spte; |
setpte4m((vm_offset_t) dva, dpte); |
*vpage_pte[1] = dpte; |
qcopy(sva, dva, NBPG); /* loads cache, so we must ... */ |
qcopy(sva, dva, NBPG); /* loads cache, so we must ... */ |
cache_flush_page((int)sva); |
cache_flush_page((int)sva); |
setpte4m((vm_offset_t) sva, SRMMU_TEINVALID); |
*vpage_pte[0] = SRMMU_TEINVALID; |
setpte4m((vm_offset_t) dva, SRMMU_TEINVALID); |
*vpage_pte[1] = SRMMU_TEINVALID; |
setcontext4m(ctx); |
tlb_flush_page((int)sva); |
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tlb_flush_page((int)dva); |
} |
} |
#endif /* Sun4M */ |
#endif /* Sun4M */ |
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pmap_redzone() |
pmap_redzone() |
{ |
{ |
pmap_remove(pmap_kernel(), KERNBASE, KERNBASE+NBPG); |
pmap_remove(pmap_kernel(), KERNBASE, KERNBASE+NBPG); |
return; |
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#if defined(SUN4M) |
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if (CPU_ISSUN4M) { |
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setpte4m(KERNBASE, 0); |
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return; |
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} |
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#endif |
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#if defined(SUN4) || defined(SUN4C) |
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if (CPU_ISSUN4OR4C) { |
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setpte4(KERNBASE, 0); |
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return; |
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} |
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#endif |
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} |
} |
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#ifdef DEBUG |
#ifdef DEBUG |