version 1.307.26.1, 2007/02/27 16:53:12 |
version 1.307.26.2, 2007/03/12 05:50:44 |
Line 397 int ncontext; /* sizeof ctx_freelist * |
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Line 397 int ncontext; /* sizeof ctx_freelist * |
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void ctx_alloc(struct pmap *); |
void ctx_alloc(struct pmap *); |
void ctx_free(struct pmap *); |
void ctx_free(struct pmap *); |
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caddr_t vmmap; /* one reserved MI vpage for /dev/mem */ |
void * vmmap; /* one reserved MI vpage for /dev/mem */ |
/*caddr_t vdumppages; -* 32KB worth of reserved dump pages */ |
/*void * vdumppages; -* 32KB worth of reserved dump pages */ |
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smeg_t tregion; /* [4/3mmu] Region for temporary mappings */ |
smeg_t tregion; /* [4/3mmu] Region for temporary mappings */ |
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Line 767 smp_tlb_flush_all(void) |
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Line 767 smp_tlb_flush_all(void) |
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#define tlb_flush_all() sp_tlb_flush_all() |
#define tlb_flush_all() sp_tlb_flush_all() |
#endif /* MULTIPROCESSOR */ |
#endif /* MULTIPROCESSOR */ |
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static u_int VA2PA(caddr_t); |
static u_int VA2PA(void *); |
static u_long srmmu_bypass_read(u_long); |
static u_long srmmu_bypass_read(u_long); |
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/* |
/* |
Line 780 static u_long srmmu_bypass_read(u_long); |
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Line 780 static u_long srmmu_bypass_read(u_long); |
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* during bootup to interact with the ROM's initial L1 mapping of the kernel. |
* during bootup to interact with the ROM's initial L1 mapping of the kernel. |
*/ |
*/ |
static u_int |
static u_int |
VA2PA(caddr_t addr) |
VA2PA(void *addr) |
{ |
{ |
u_int pte; |
u_int pte; |
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Line 993 pgt_page_free(struct pool *pp, void *v) |
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Line 993 pgt_page_free(struct pool *pp, void *v) |
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} while (0) |
} while (0) |
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static void get_phys_mem(caddr_t *); |
static void get_phys_mem(void **); |
void kvm_iocache(caddr_t, int); |
#if 0 /* not used */ |
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void kvm_iocache(char *, int); |
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#endif |
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#ifdef DEBUG |
#ifdef DEBUG |
void pm_check(char *, struct pmap *); |
void pm_check(char *, struct pmap *); |
Line 1021 static u_long va2pa_offset; |
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Line 1023 static u_long va2pa_offset; |
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* While here, compute `physmem'. |
* While here, compute `physmem'. |
*/ |
*/ |
void |
void |
get_phys_mem(caddr_t *top) |
get_phys_mem(void **top) |
{ |
{ |
struct memarr *mp; |
struct memarr *mp; |
caddr_t p; |
char *p; |
int i; |
int i; |
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/* Load the memory descriptor array at the current kernel top */ |
/* Load the memory descriptor array at the current kernel top */ |
p = (caddr_t)ALIGN(*top); |
p = (void *)ALIGN(*top); |
pmemarr = (struct memarr *)p; |
pmemarr = (struct memarr *)p; |
npmemarr = prom_makememarr(pmemarr, 1000, MEMARR_AVAILPHYS); |
npmemarr = prom_makememarr(pmemarr, 1000, MEMARR_AVAILPHYS); |
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Line 1273 mmu_reservemon4_4c(int *nrp, int *nsp) |
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Line 1275 mmu_reservemon4_4c(int *nrp, int *nsp) |
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* rather than segments, amongst the contexts. |
* rather than segments, amongst the contexts. |
*/ |
*/ |
for (i = ncontext; --i > 0;) |
for (i = ncontext; --i > 0;) |
prom_setcontext(i, (caddr_t)va, mmureg); |
prom_setcontext(i, (void *)va, mmureg); |
} |
} |
#endif |
#endif |
mmuseg = getsegmap(va); |
mmuseg = getsegmap(va); |
Line 1282 mmu_reservemon4_4c(int *nrp, int *nsp) |
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Line 1284 mmu_reservemon4_4c(int *nrp, int *nsp) |
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if (!HASSUN4_MMU3L) |
if (!HASSUN4_MMU3L) |
for (i = ncontext; --i > 0;) |
for (i = ncontext; --i > 0;) |
prom_setcontext(i, (caddr_t)va, mmuseg); |
prom_setcontext(i, (void *)va, mmuseg); |
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if (mmuseg == seginval) { |
if (mmuseg == seginval) { |
va += NBPSG; |
va += NBPSG; |
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#endif |
#endif |
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#if defined(SUN4M) || defined(SUN4D) |
#if defined(SUN4M) || defined(SUN4D) |
static void pmap_bootstrap4m(caddr_t); |
static void pmap_bootstrap4m(void *); |
#endif |
#endif |
#if defined(SUN4) || defined(SUN4C) |
#if defined(SUN4) || defined(SUN4C) |
static void pmap_bootstrap4_4c(caddr_t, int, int, int); |
static void pmap_bootstrap4_4c(void *, int, int, int); |
#endif |
#endif |
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/* |
/* |
Line 3037 static void pmap_bootstrap4_4c(caddr_t, |
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Line 3039 static void pmap_bootstrap4_4c(caddr_t, |
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void |
void |
pmap_bootstrap(int nctx, int nregion, int nsegment) |
pmap_bootstrap(int nctx, int nregion, int nsegment) |
{ |
{ |
caddr_t p; |
void *p; |
extern char etext[], kernel_data_start[]; |
extern char etext[], kernel_data_start[]; |
extern char *kernel_top; |
extern char *kernel_top; |
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Line 3087 pmap_bootstrap(int nctx, int nregion, in |
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Line 3089 pmap_bootstrap(int nctx, int nregion, in |
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#if defined(SUN4) || defined(SUN4C) |
#if defined(SUN4) || defined(SUN4C) |
void |
void |
pmap_bootstrap4_4c(caddr_t top, int nctx, int nregion, int nsegment) |
pmap_bootstrap4_4c(void *top, int nctx, int nregion, int nsegment) |
{ |
{ |
union ctxinfo *ci; |
union ctxinfo *ci; |
struct mmuentry *mmuseg; |
struct mmuentry *mmuseg; |
Line 3267 pmap_bootstrap4_4c(caddr_t top, int nctx |
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Line 3269 pmap_bootstrap4_4c(caddr_t top, int nctx |
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avail_start = PMAP_BOOTSTRAP_VA2PA(p); |
avail_start = PMAP_BOOTSTRAP_VA2PA(p); |
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i = p; |
i = p; |
cpuinfo.vpage[0] = (caddr_t)p, p += NBPG; |
cpuinfo.vpage[0] = (void *)p, p += NBPG; |
cpuinfo.vpage[1] = (caddr_t)p, p += NBPG; |
cpuinfo.vpage[1] = (void *)p, p += NBPG; |
vmmap = (caddr_t)p, p += NBPG; |
vmmap = (void *)p, p += NBPG; |
p = (vaddr_t)reserve_dumppages((caddr_t)p); |
p = (vaddr_t)reserve_dumppages((void *)p); |
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virtual_avail = p; |
virtual_avail = p; |
virtual_end = VM_MAX_KERNEL_ADDRESS; |
virtual_end = VM_MAX_KERNEL_ADDRESS; |
Line 3349 pmap_bootstrap4_4c(caddr_t top, int nctx |
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Line 3351 pmap_bootstrap4_4c(caddr_t top, int nctx |
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#if defined(SUN4_MMU3L) |
#if defined(SUN4_MMU3L) |
if (HASSUN4_MMU3L) { |
if (HASSUN4_MMU3L) { |
for (i = 1; i < nctx; i++) |
for (i = 1; i < nctx; i++) |
prom_setcontext(i, (caddr_t)p, rcookie); |
prom_setcontext(i, (void *)p, rcookie); |
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MMUQ_INSERT_TAIL(®ion_locked, |
MMUQ_INSERT_TAIL(®ion_locked, |
mmureg, me_list); |
mmureg, me_list); |
Line 3372 pmap_bootstrap4_4c(caddr_t top, int nctx |
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Line 3374 pmap_bootstrap4_4c(caddr_t top, int nctx |
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if (!HASSUN4_MMU3L) |
if (!HASSUN4_MMU3L) |
#endif |
#endif |
for (i = 1; i < nctx; i++) |
for (i = 1; i < nctx; i++) |
prom_setcontext(i, (caddr_t)p, scookie); |
prom_setcontext(i, (void *)p, scookie); |
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/* set up the mmu entry */ |
/* set up the mmu entry */ |
MMUQ_INSERT_TAIL(&segm_locked, mmuseg, me_list); |
MMUQ_INSERT_TAIL(&segm_locked, mmuseg, me_list); |
Line 3536 pmap_bootstrap4_4c(caddr_t top, int nctx |
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Line 3538 pmap_bootstrap4_4c(caddr_t top, int nctx |
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* Switches from ROM to kernel page tables, and sets up initial mappings. |
* Switches from ROM to kernel page tables, and sets up initial mappings. |
*/ |
*/ |
static void |
static void |
pmap_bootstrap4m(caddr_t top) |
pmap_bootstrap4m(void *top) |
{ |
{ |
int i, j; |
int i, j; |
vaddr_t p, q; |
vaddr_t p, q; |
Line 3692 pmap_bootstrap4m(caddr_t top) |
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Line 3694 pmap_bootstrap4m(caddr_t top) |
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for (reg = 0; reg < NKREG; reg++) { |
for (reg = 0; reg < NKREG; reg++) { |
struct regmap *rp; |
struct regmap *rp; |
caddr_t kphyssegtbl; |
void *kphyssegtbl; |
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/* |
/* |
* Entering new region; install & build segtbl |
* Entering new region; install & build segtbl |
Line 3700 pmap_bootstrap4m(caddr_t top) |
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Line 3702 pmap_bootstrap4m(caddr_t top) |
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rp = &pmap_kernel()->pm_regmap[reg + VA_VREG(KERNBASE)]; |
rp = &pmap_kernel()->pm_regmap[reg + VA_VREG(KERNBASE)]; |
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kphyssegtbl = (caddr_t) |
kphyssegtbl = (void *) |
&kernel_segtable_store[reg * SRMMU_L2SIZE]; |
&kernel_segtable_store[reg * SRMMU_L2SIZE]; |
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setpgt4m(&pmap_kernel()->pm_reg_ptps[0][reg + VA_VREG(KERNBASE)], |
setpgt4m(&pmap_kernel()->pm_reg_ptps[0][reg + VA_VREG(KERNBASE)], |
Line 3711 pmap_bootstrap4m(caddr_t top) |
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Line 3713 pmap_bootstrap4m(caddr_t top) |
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for (seg = 0; seg < NSEGRG; seg++) { |
for (seg = 0; seg < NSEGRG; seg++) { |
struct segmap *sp; |
struct segmap *sp; |
caddr_t kphyspagtbl; |
void *kphyspagtbl; |
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rp->rg_nsegmap++; |
rp->rg_nsegmap++; |
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sp = &rp->rg_segmap[seg]; |
sp = &rp->rg_segmap[seg]; |
kphyspagtbl = (caddr_t) |
kphyspagtbl = (void *) |
&kernel_pagtable_store |
&kernel_pagtable_store |
[((reg * NSEGRG) + seg) * SRMMU_L3SIZE]; |
[((reg * NSEGRG) + seg) * SRMMU_L3SIZE]; |
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Line 3739 pmap_bootstrap4m(caddr_t top) |
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Line 3741 pmap_bootstrap4m(caddr_t top) |
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* for /dev/mem, and some more for dumpsys(). |
* for /dev/mem, and some more for dumpsys(). |
*/ |
*/ |
q = p; |
q = p; |
cpuinfo.vpage[0] = (caddr_t)p, p += NBPG; |
cpuinfo.vpage[0] = (void *)p, p += NBPG; |
cpuinfo.vpage[1] = (caddr_t)p, p += NBPG; |
cpuinfo.vpage[1] = (void *)p, p += NBPG; |
vmmap = (caddr_t)p, p += NBPG; |
vmmap = (void *)p, p += NBPG; |
p = (vaddr_t)reserve_dumppages((caddr_t)p); |
p = (vaddr_t)reserve_dumppages((void *)p); |
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/* Find PTE locations of vpage[] to optimize zero_fill() et.al. */ |
/* Find PTE locations of vpage[] to optimize zero_fill() et.al. */ |
for (i = 0; i < 2; i++) { |
for (i = 0; i < 2; i++) { |
Line 4025 pmap_alloc_cpu(struct cpu_info *sc) |
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Line 4027 pmap_alloc_cpu(struct cpu_info *sc) |
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setpgt4m(&segtable[vs], |
setpgt4m(&segtable[vs], |
((u_long)pagtable_pa >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD); |
((u_long)pagtable_pa >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD); |
setpgt4m(&pagtable[vpg], |
setpgt4m(&pagtable[vpg], |
(VA2PA((caddr_t)sc) >> SRMMU_PPNPASHIFT) | |
(VA2PA((void *)sc) >> SRMMU_PPNPASHIFT) | |
(SRMMU_TEPTE | PPROT_N_RWX | SRMMU_PG_C)); |
(SRMMU_TEPTE | PPROT_N_RWX | SRMMU_PG_C)); |
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/* Install this CPU's context table */ |
/* Install this CPU's context table */ |
Line 4229 pmap_pmap_pool_ctor(void *arg, void *obj |
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Line 4231 pmap_pmap_pool_ctor(void *arg, void *obj |
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addr += sparc_ncpus * sizeof(int *); |
addr += sparc_ncpus * sizeof(int *); |
pm->pm_reg_ptps_pa = (int *)addr; |
pm->pm_reg_ptps_pa = (int *)addr; |
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qzero((caddr_t)pm->pm_regmap, NUREG * sizeof(struct regmap)); |
qzero((void *)pm->pm_regmap, NUREG * sizeof(struct regmap)); |
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/* pm->pm_ctx = NULL; // already done */ |
/* pm->pm_ctx = NULL; // already done */ |
simple_lock_init(&pm->pm_lock); |
simple_lock_init(&pm->pm_lock); |
Line 5732 pmap_enu4_4c(struct pmap *pm, vaddr_t va |
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Line 5734 pmap_enu4_4c(struct pmap *pm, vaddr_t va |
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if (rp->rg_segmap != NULL) |
if (rp->rg_segmap != NULL) |
panic("pmap_enter: segment filled during sleep"); |
panic("pmap_enter: segment filled during sleep"); |
#endif |
#endif |
qzero((caddr_t)sp, NSEGRG * sizeof (struct segmap)); |
qzero((void *)sp, NSEGRG * sizeof (struct segmap)); |
rp->rg_segmap = sp; |
rp->rg_segmap = sp; |
rp->rg_nsegmap = 0; |
rp->rg_nsegmap = 0; |
for (i = NSEGRG; --i >= 0;) |
for (i = NSEGRG; --i >= 0;) |
Line 5762 pmap_enu4_4c(struct pmap *pm, vaddr_t va |
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Line 5764 pmap_enu4_4c(struct pmap *pm, vaddr_t va |
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if (sp->sg_pmeg != seginval) |
if (sp->sg_pmeg != seginval) |
panic("pmap_enter: new ptes, but not seginval"); |
panic("pmap_enter: new ptes, but not seginval"); |
#endif |
#endif |
qzero((caddr_t)ptep, size); |
qzero((void *)ptep, size); |
sp->sg_pte = ptep; |
sp->sg_pte = ptep; |
sp->sg_npte = 1; |
sp->sg_npte = 1; |
rp->rg_nsegmap++; |
rp->rg_nsegmap++; |
Line 6306 pmap_enu4m(struct pmap *pm, vaddr_t va, |
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Line 6308 pmap_enu4m(struct pmap *pm, vaddr_t va, |
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if (rp->rg_segmap != NULL) |
if (rp->rg_segmap != NULL) |
panic("pmap_enu4m: segment filled during sleep"); |
panic("pmap_enu4m: segment filled during sleep"); |
#endif |
#endif |
qzero((caddr_t)sp, NSEGRG * sizeof (struct segmap)); |
qzero((void *)sp, NSEGRG * sizeof (struct segmap)); |
rp->rg_segmap = sp; |
rp->rg_segmap = sp; |
rp->rg_nsegmap = 0; |
rp->rg_nsegmap = 0; |
rp->rg_seg_ptps = NULL; |
rp->rg_seg_ptps = NULL; |
Line 6339 pmap_enu4m(struct pmap *pm, vaddr_t va, |
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Line 6341 pmap_enu4m(struct pmap *pm, vaddr_t va, |
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#endif |
#endif |
{ |
{ |
setpgt4m(&pm->pm_reg_ptps[i][vr], |
setpgt4m(&pm->pm_reg_ptps[i][vr], |
(VA2PA((caddr_t)ptd) >> SRMMU_PPNPASHIFT) | |
(VA2PA((void *)ptd) >> SRMMU_PPNPASHIFT) | |
SRMMU_TEPTD); |
SRMMU_TEPTD); |
} |
} |
} |
} |
Line 6367 pmap_enu4m(struct pmap *pm, vaddr_t va, |
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Line 6369 pmap_enu4m(struct pmap *pm, vaddr_t va, |
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for (i = 0; i < SRMMU_L3SIZE; i++) |
for (i = 0; i < SRMMU_L3SIZE; i++) |
setpgt4m(&pte[i], SRMMU_TEINVALID); |
setpgt4m(&pte[i], SRMMU_TEINVALID); |
setpgt4m(&rp->rg_seg_ptps[vs], |
setpgt4m(&rp->rg_seg_ptps[vs], |
(VA2PA((caddr_t)pte) >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD); |
(VA2PA((void *)pte) >> SRMMU_PPNPASHIFT) | SRMMU_TEPTD); |
} else { |
} else { |
#ifdef DIAGNOSTIC |
#ifdef DIAGNOSTIC |
if (sp->sg_npte <= 0) |
if (sp->sg_npte <= 0) |
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pmap_zero_page4_4c(paddr_t pa) |
pmap_zero_page4_4c(paddr_t pa) |
{ |
{ |
struct vm_page *pg; |
struct vm_page *pg; |
caddr_t va; |
void *va; |
int pte; |
int pte; |
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if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { |
if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { |
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pmap_copy_page4_4c(paddr_t src, paddr_t dst) |
pmap_copy_page4_4c(paddr_t src, paddr_t dst) |
{ |
{ |
struct vm_page *pg; |
struct vm_page *pg; |
caddr_t sva, dva; |
char *sva, *dva; |
int spte, dpte; |
int spte, dpte; |
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if ((pg = PHYS_TO_VM_PAGE(src)) != NULL) { |
if ((pg = PHYS_TO_VM_PAGE(src)) != NULL) { |
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pmap_zero_page4m(paddr_t pa) |
pmap_zero_page4m(paddr_t pa) |
{ |
{ |
struct vm_page *pg; |
struct vm_page *pg; |
caddr_t va; |
void *va; |
int pte; |
int pte; |
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if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { |
if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { |
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pmap_zero_page_hypersparc(paddr_t pa) |
pmap_zero_page_hypersparc(paddr_t pa) |
{ |
{ |
struct vm_page *pg; |
struct vm_page *pg; |
caddr_t va; |
void *va; |
int pte; |
int pte; |
int offset; |
int offset; |
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Line 7131 pmap_zero_page_hypersparc(paddr_t pa) |
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Line 7133 pmap_zero_page_hypersparc(paddr_t pa) |
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va = cpuinfo.vpage[0]; |
va = cpuinfo.vpage[0]; |
setpgt4m(cpuinfo.vpage_pte[0], pte); |
setpgt4m(cpuinfo.vpage_pte[0], pte); |
for (offset = 0; offset < NBPG; offset += 32) { |
for (offset = 0; offset < NBPG; offset += 32) { |
sta(va + offset, ASI_BLOCKFILL, 0); |
sta((char *)va + offset, ASI_BLOCKFILL, 0); |
} |
} |
/* Remove temporary mapping */ |
/* Remove temporary mapping */ |
sp_tlb_flush((int)va, 0, ASI_SRMMUFP_L3); |
sp_tlb_flush((int)va, 0, ASI_SRMMUFP_L3); |
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pmap_copy_page4m(paddr_t src, paddr_t dst) |
pmap_copy_page4m(paddr_t src, paddr_t dst) |
{ |
{ |
struct vm_page *pg; |
struct vm_page *pg; |
caddr_t sva, dva; |
void *sva, *dva; |
int spte, dpte; |
int spte, dpte; |
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if ((pg = PHYS_TO_VM_PAGE(src)) != NULL) { |
if ((pg = PHYS_TO_VM_PAGE(src)) != NULL) { |
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pmap_copy_page_hypersparc(paddr_t src, paddr_t dst) |
pmap_copy_page_hypersparc(paddr_t src, paddr_t dst) |
{ |
{ |
struct vm_page *pg; |
struct vm_page *pg; |
caddr_t sva, dva; |
void *sva, *dva; |
int spte, dpte; |
int spte, dpte; |
int offset; |
int offset; |
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Line 7249 pmap_copy_page_hypersparc(paddr_t src, p |
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Line 7251 pmap_copy_page_hypersparc(paddr_t src, p |
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setpgt4m(cpuinfo.vpage_pte[1], dpte); |
setpgt4m(cpuinfo.vpage_pte[1], dpte); |
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for (offset = 0; offset < NBPG; offset += 32) { |
for (offset = 0; offset < NBPG; offset += 32) { |
sta(dva + offset, ASI_BLOCKCOPY, sva + offset); |
sta((char *)dva + offset, ASI_BLOCKCOPY, (char *)sva + offset); |
} |
} |
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sp_tlb_flush((int)sva, 0, ASI_SRMMUFP_L3); |
sp_tlb_flush((int)sva, 0, ASI_SRMMUFP_L3); |
Line 7278 pmap_phys_address(int x) |
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Line 7280 pmap_phys_address(int x) |
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* in locked kernel space. A cache flush is also done. |
* in locked kernel space. A cache flush is also done. |
*/ |
*/ |
void |
void |
kvm_uncache(caddr_t va, int npages) |
kvm_uncache(char *va, int npages) |
{ |
{ |
struct vm_page *pg; |
struct vm_page *pg; |
int pte; |
int pte; |
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if (CPU_HAS_SRMMU) { |
if (CPU_HAS_SRMMU) { |
#if defined(SUN4M) || defined(SUN4D) |
#if defined(SUN4M) || defined(SUN4D) |
for (; --npages >= 0; va += NBPG) { |
for (; --npages >= 0; va = (char *)va + NBPG) { |
pte = getpte4m((vaddr_t) va); |
pte = getpte4m((vaddr_t) va); |
if ((pte & SRMMU_TETYPE) != SRMMU_TEPTE) |
if ((pte & SRMMU_TETYPE) != SRMMU_TEPTE) |
panic("kvm_uncache: table entry not pte"); |
panic("kvm_uncache: table entry not pte"); |
Line 7323 kvm_uncache(caddr_t va, int npages) |
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Line 7325 kvm_uncache(caddr_t va, int npages) |
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} |
} |
} |
} |
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#if 0 /* not used */ |
/* |
/* |
* Turn on IO cache for a given (va, number of pages). |
* Turn on IO cache for a given (va, number of pages). |
* |
* |
Line 7330 kvm_uncache(caddr_t va, int npages) |
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Line 7333 kvm_uncache(caddr_t va, int npages) |
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* in locked kernel space. A cache flush is also done. |
* in locked kernel space. A cache flush is also done. |
*/ |
*/ |
void |
void |
kvm_iocache(caddr_t va, int npages) |
kvm_iocache(char *va, int npages) |
{ |
{ |
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#if defined(SUN4M) |
#if defined(SUN4M) |
Line 7351 kvm_iocache(caddr_t va, int npages) |
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Line 7354 kvm_iocache(caddr_t va, int npages) |
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} |
} |
#endif |
#endif |
} |
} |
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#endif |
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/* |
/* |
* Find first virtual address >= *va that is |
* Find first virtual address >= *va that is |
Line 7471 pm_check_u(char *s, struct pmap *pm) |
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Line 7475 pm_check_u(char *s, struct pmap *pm) |
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#if defined(SUN4M) || defined(SUN4D) |
#if defined(SUN4M) || defined(SUN4D) |
if (CPU_HAS_SRMMU && |
if (CPU_HAS_SRMMU && |
(pm->pm_reg_ptps[cpu] == NULL || |
(pm->pm_reg_ptps[cpu] == NULL || |
pm->pm_reg_ptps_pa[cpu] != VA2PA((caddr_t)pm->pm_reg_ptps[cpu]))) |
pm->pm_reg_ptps_pa[cpu] != VA2PA((void *)pm->pm_reg_ptps[cpu]))) |
panic("%s: CPU %d: CHK(pmap %p): no SRMMU region table or bad pa: " |
panic("%s: CPU %d: CHK(pmap %p): no SRMMU region table or bad pa: " |
"tblva=%p, tblpa=0x%x", |
"tblva=%p, tblpa=0x%x", |
s, cpu, pm, pm->pm_reg_ptps[cpu], pm->pm_reg_ptps_pa[cpu]); |
s, cpu, pm, pm->pm_reg_ptps[cpu], pm->pm_reg_ptps_pa[cpu]); |
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if (CPU_HAS_SRMMU && pm->pm_ctx != NULL && |
if (CPU_HAS_SRMMU && pm->pm_ctx != NULL && |
(cpuinfo.ctx_tbl[pm->pm_ctxnum] != ((VA2PA((caddr_t)pm->pm_reg_ptps[cpu]) |
(cpuinfo.ctx_tbl[pm->pm_ctxnum] != ((VA2PA((void *)pm->pm_reg_ptps[cpu]) |
>> SRMMU_PPNPASHIFT) | |
>> SRMMU_PPNPASHIFT) | |
SRMMU_TEPTD))) |
SRMMU_TEPTD))) |
panic("%s: CPU %d: CHK(pmap %p): SRMMU region table at 0x%x not installed " |
panic("%s: CPU %d: CHK(pmap %p): SRMMU region table at 0x%x not installed " |
Line 7496 pm_check_u(char *s, struct pmap *pm) |
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Line 7500 pm_check_u(char *s, struct pmap *pm) |
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panic("%s: CPU %d: CHK(vr %d): nsegmap=%d; no SRMMU segment table", |
panic("%s: CPU %d: CHK(vr %d): nsegmap=%d; no SRMMU segment table", |
s, cpu, vr, rp->rg_nsegmap); |
s, cpu, vr, rp->rg_nsegmap); |
if (CPU_HAS_SRMMU && |
if (CPU_HAS_SRMMU && |
pm->pm_reg_ptps[cpu][vr] != ((VA2PA((caddr_t)rp->rg_seg_ptps) >> |
pm->pm_reg_ptps[cpu][vr] != ((VA2PA((void *)rp->rg_seg_ptps) >> |
SRMMU_PPNPASHIFT) | SRMMU_TEPTD)) |
SRMMU_PPNPASHIFT) | SRMMU_TEPTD)) |
panic("%s: CPU %d: CHK(vr %d): SRMMU segtbl not installed", |
panic("%s: CPU %d: CHK(vr %d): SRMMU segtbl not installed", |
s, cpu, vr); |
s, cpu, vr); |
Line 7516 pm_check_u(char *s, struct pmap *pm) |
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Line 7520 pm_check_u(char *s, struct pmap *pm) |
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#if defined(SUN4M) || defined(SUN4D) |
#if defined(SUN4M) || defined(SUN4D) |
if (CPU_HAS_SRMMU && |
if (CPU_HAS_SRMMU && |
rp->rg_seg_ptps[vs] != |
rp->rg_seg_ptps[vs] != |
((VA2PA((caddr_t)sp->sg_pte) |
((VA2PA((void *)sp->sg_pte) |
>> SRMMU_PPNPASHIFT) | |
>> SRMMU_PPNPASHIFT) | |
SRMMU_TEPTD)) |
SRMMU_TEPTD)) |
panic("%s: CPU %d: CHK(vr %d, vs %d): SRMMU page " |
panic("%s: CPU %d: CHK(vr %d, vs %d): SRMMU page " |
Line 7559 pm_check_k(char *s, struct pmap *pm) |
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Line 7563 pm_check_k(char *s, struct pmap *pm) |
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#if defined(SUN4M) || defined(SUN4D) |
#if defined(SUN4M) || defined(SUN4D) |
if (CPU_HAS_SRMMU && |
if (CPU_HAS_SRMMU && |
(pm->pm_reg_ptps[cpu] == NULL || |
(pm->pm_reg_ptps[cpu] == NULL || |
pm->pm_reg_ptps_pa[cpu] != VA2PA((caddr_t)pm->pm_reg_ptps[cpu]))) |
pm->pm_reg_ptps_pa[cpu] != VA2PA((void *)pm->pm_reg_ptps[cpu]))) |
panic("%s: CPU %d: CHK(pmap %p): no SRMMU region table or bad pa: tblva=%p, tblpa=0x%x", |
panic("%s: CPU %d: CHK(pmap %p): no SRMMU region table or bad pa: tblva=%p, tblpa=0x%x", |
s, cpu, pm, pm->pm_reg_ptps[cpu], pm->pm_reg_ptps_pa[cpu]); |
s, cpu, pm, pm->pm_reg_ptps[cpu], pm->pm_reg_ptps_pa[cpu]); |
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if (CPU_HAS_SRMMU && |
if (CPU_HAS_SRMMU && |
(cpuinfo.ctx_tbl[0] != ((VA2PA((caddr_t)pm->pm_reg_ptps[cpu]) >> |
(cpuinfo.ctx_tbl[0] != ((VA2PA((void *)pm->pm_reg_ptps[cpu]) >> |
SRMMU_PPNPASHIFT) | SRMMU_TEPTD))) |
SRMMU_PPNPASHIFT) | SRMMU_TEPTD))) |
panic("%s: CPU %d: CHK(pmap %p): SRMMU region table at 0x%x not installed " |
panic("%s: CPU %d: CHK(pmap %p): SRMMU region table at 0x%x not installed " |
"for context %d", s, cpu, pm, pm->pm_reg_ptps_pa[cpu], 0); |
"for context %d", s, cpu, pm, pm->pm_reg_ptps_pa[cpu], 0); |
Line 7582 pm_check_k(char *s, struct pmap *pm) |
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Line 7586 pm_check_k(char *s, struct pmap *pm) |
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s, cpu, vr, rp->rg_nsegmap); |
s, cpu, vr, rp->rg_nsegmap); |
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if (CPU_HAS_SRMMU && vr != NUREG /* 1st kseg is per CPU */ && |
if (CPU_HAS_SRMMU && vr != NUREG /* 1st kseg is per CPU */ && |
pm->pm_reg_ptps[cpu][vr] != ((VA2PA((caddr_t)rp->rg_seg_ptps) >> |
pm->pm_reg_ptps[cpu][vr] != ((VA2PA((void *)rp->rg_seg_ptps) >> |
SRMMU_PPNPASHIFT) | SRMMU_TEPTD)) |
SRMMU_PPNPASHIFT) | SRMMU_TEPTD)) |
panic("%s: CPU %d: CHK(vr %d): SRMMU segtbl not installed", |
panic("%s: CPU %d: CHK(vr %d): SRMMU segtbl not installed", |
s, cpu, vr); |
s, cpu, vr); |
Line 7634 pmap_dumpsize(void) |
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Line 7638 pmap_dumpsize(void) |
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* the MMU pmegs on sun4/sun4c |
* the MMU pmegs on sun4/sun4c |
*/ |
*/ |
int |
int |
pmap_dumpmmu(int (*dump)(dev_t, daddr_t, caddr_t, size_t), |
pmap_dumpmmu(int (*dump)(dev_t, daddr_t, void *, size_t), |
daddr_t blkno) |
daddr_t blkno) |
{ |
{ |
kcore_seg_t *ksegp; |
kcore_seg_t *ksegp; |
Line 7655 pmap_dumpmmu(int (*dump)(dev_t, daddr_t, |
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Line 7659 pmap_dumpmmu(int (*dump)(dev_t, daddr_t, |
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*bp++ = *sp++; \ |
*bp++ = *sp++; \ |
if (bp >= ep) { \ |
if (bp >= ep) { \ |
error = (*dump)(dumpdev, blkno, \ |
error = (*dump)(dumpdev, blkno, \ |
(caddr_t)buffer, dbtob(1)); \ |
(void *)buffer, dbtob(1)); \ |
if (error != 0) \ |
if (error != 0) \ |
return (error); \ |
return (error); \ |
++blkno; \ |
++blkno; \ |
Line 7742 pmap_dumpmmu(int (*dump)(dev_t, daddr_t, |
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Line 7746 pmap_dumpmmu(int (*dump)(dev_t, daddr_t, |
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out: |
out: |
if (bp != buffer) |
if (bp != buffer) |
error = (*dump)(dumpdev, blkno++, (caddr_t)buffer, dbtob(1)); |
error = (*dump)(dumpdev, blkno++, (void *)buffer, dbtob(1)); |
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return (error); |
return (error); |
} |
} |
Line 7850 debug_pagetables(void) |
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Line 7854 debug_pagetables(void) |
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} |
} |
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static u_int |
static u_int |
VA2PAsw(int ctx, caddr_t addr, int *pte) |
VA2PAsw(int ctx, void *addr, int *pte) |
{ |
{ |
int *curtbl; |
int *curtbl; |
int curpte; |
int curpte; |
Line 7937 test_region(int reg, int start, int stop |
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Line 7941 test_region(int reg, int start, int stop |
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cnt = 0; |
cnt = 0; |
} |
} |
*/ |
*/ |
if (VA2PA((caddr_t)addr) != VA2PAsw(0, (caddr_t)addr, &ptesw)) { |
if (VA2PA((void *)addr) != VA2PAsw(0, (void *)addr, &ptesw)) { |
printf("Mismatch at address 0x%x.\n", addr); |
printf("Mismatch at address 0x%x.\n", addr); |
if (cngetc() == 'q') |
if (cngetc() == 'q') |
break; |
break; |