CVS log for src/sys/arch/sparc/sparc/locore.s

Up to [cvs.NetBSD.org] / src / sys / arch / sparc / sparc

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

s/indicies/indices/ in comments.

Pull up following revision(s) (requested by riastradh in ticket #1859):

	sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
	sys/arch/aarch64/aarch64/locore.S: revision 1.91
	sys/arch/mips/include/asm.h: revision 1.74
	sys/arch/hppa/include/cpu.h: revision 1.13
	sys/arch/arm/arm/armv6_start.S: revision 1.38
	 (applied also to sys/arch/arm/cortex/a9_mpsubr.S,
	 sys/arch/arm/cortex/a9_mpsubr.S,
	 sys/arch/arm/cortex/cortex_init.S)
	sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
	sys/arch/mips/mips/locore.S: revision 1.229
	sys/arch/alpha/include/asm.h: revision 1.45
	 (applied to sys/arch/alpha/alpha/multiproc.s)
	sys/arch/sparc64/sparc64/locore.s: revision 1.432
	sys/arch/vax/vax/subr.S: revision 1.42
	sys/arch/mips/mips/locore_mips3.S: revision 1.116
	sys/arch/ia64/ia64/machdep.c: revision 1.44
	sys/arch/arm/arm32/cpuswitch.S: revision 1.106
	sys/arch/sparc/sparc/locore.s: revision 1.284
	(all via patch)

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.

Pull up following revision(s) (requested by riastradh in ticket #1676):

	sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
	sys/arch/aarch64/aarch64/locore.S: revision 1.91
	sys/arch/mips/include/asm.h: revision 1.74
	sys/arch/hppa/include/cpu.h: revision 1.13
	sys/arch/arm/arm/armv6_start.S: revision 1.38
	sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
	sys/arch/mips/mips/locore.S: revision 1.229
	sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
	sys/arch/alpha/include/asm.h: revision 1.45
	sys/arch/sparc64/sparc64/locore.s: revision 1.432
	sys/arch/vax/vax/subr.S: revision 1.42
	sys/arch/mips/mips/locore_mips3.S: revision 1.116
	sys/arch/ia64/ia64/machdep.c: revision 1.44
	sys/arch/arm/arm32/cpuswitch.S: revision 1.106
	sys/arch/sparc/sparc/locore.s: revision 1.284
	(all via patch)

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.

Pull up following revision(s) (requested by riastradh in ticket #264):

	sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
	sys/arch/aarch64/aarch64/locore.S: revision 1.91
	sys/arch/mips/include/asm.h: revision 1.74
	sys/arch/hppa/include/cpu.h: revision 1.13
	sys/arch/arm/arm/armv6_start.S: revision 1.38
	sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
	sys/arch/mips/mips/locore.S: revision 1.229
	sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
	sys/arch/alpha/include/asm.h: revision 1.45
	sys/arch/sparc64/sparc64/locore.s: revision 1.432
	sys/arch/vax/vax/subr.S: revision 1.42
	sys/arch/mips/mips/locore_mips3.S: revision 1.116
	sys/arch/riscv/riscv/cpu_switch.S: revision 1.3
	sys/arch/ia64/ia64/machdep.c: revision 1.44
	sys/arch/arm/arm32/cpuswitch.S: revision 1.106
	sys/arch/sparc/sparc/locore.s: revision 1.284

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

riscv: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.

sparc: Add missing barriers in cpu_switchto.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10

remove unused Lpanic_savefpstate.

fix various typos in comments and log messages.

s/aligment/alignment/ + one more typo fix in comments.

Sync with HEAD.

fix a comment to match the code.

Sync with HEAD.

avoid using 'extern <func|data>;' inside a .c file, but instead
use header files and ensure definitions are not duplicated or
are technically (if not in codegen) wrong.

Make copystr() a MI C function, part of libkern and shared on all
architectures.

Notes:

 - On alpha and ia64 the function is kept but gets renamed locally to avoid
   symbol collision. This is because on these two arches, I am not sure
   whether the ASM callers do not rely on fixed registers, so I prefer to
   keep the ASM body for now.
 - On Vax, only the symbol is removed, because the body is used from other
   functions.
 - On RISC-V, this change fixes a bug: copystr() was just a wrapper around
   strlcpy(), but strlcpy() makes the operation less safe (strlen on the
   source beyond its size).
 - The kASan, kCSan and kMSan wrappers are removed, because now that
   copystr() is in C, the compiler transformations are applied to it,
   without the need for manual wrappers.

Could test on amd64 only, but should be fine.

Merge changes from current as of 20200406

Sync with head.

Fix some more places in this file it's assumed cpu_info is smaller than 1kB.

oldlwp is always non-NULL in cpu_switchto so remove the test for NULL.

PR port-sparc/54789: Sparc boot fails with "Trap 0x21 while interrupts disabled"

Remove assumption that cpu_info is smaller than 1kB.

Sync with HEAD

remove code to directly check for NULL savefpstate() calls.
it has not triggered for years now, and if it comes back,
you still get a normal kernel fault.

Overhaul the API used to fetch and store individual memory cells in
userspace.  The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms.  The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.

Sync with HEAD, resolve a few conflicts

Remove compat_svr4 and compat_svr4_32, as discussed on tech-kern@ recently,
but also as discussed several times in the past.

Sync with HEAD

convert Lfp_null_fpstate (which is invoked if savefpstate() is called
with NULL) into a panic for DIAGNOSTIC kernels.

Synch with HEAD, resolve conflicts

remove obsolete ovbcopy().  it may be the very slightly bit
faster for larger copies, but slower for smaller ones.
i don't see any major benefit in keeping this code.

this is the final ovbcopy() reference in src.  you're welcome :-)

Pull up following revision(s) (requested by maya in ticket #1513):
	sys/arch/sparc/sparc/locore.s: 1.269
Avoid an instruction requiring a higher alignment than we are guaranteed
Fixes PR port-sparc/52721: ddb errors on ps command
Thanks to mlelstv.

Pull up following revision(s) (requested by maya in ticket #1530):
	sys/arch/sparc/sparc/locore.s: revision 1.269
Avoid an instruction requiring a higher alignment than we are guaranteed
Fixes PR port-sparc/52721: ddb errors on ps command
Thanks to mlelstv.

Pull up following revision(s) (requested by maya in ticket #1530):
	sys/arch/sparc/sparc/locore.s: revision 1.269
Avoid an instruction requiring a higher alignment than we are guaranteed
Fixes PR port-sparc/52721: ddb errors on ps command
Thanks to mlelstv.

Pull up following revision(s) (requested by maya in ticket #1530):
	sys/arch/sparc/sparc/locore.s: revision 1.269
Avoid an instruction requiring a higher alignment than we are guaranteed
Fixes PR port-sparc/52721: ddb errors on ps command
Thanks to mlelstv.

update from HEAD

Pull up following revision(s) (requested by maya in ticket #392):
	sys/arch/sparc/sparc/locore.s: revision 1.269
Avoid an instruction requiring a higher alignment than we are guaranteed
Fixes PR port-sparc/52721: ddb errors on ps command
Thanks to mlelstv.

Avoid an instruction requiring a higher alignment than we are guaranteed

Fixes PR port-sparc/52721: ddb errors on ps command
Thanks to mlelstv.

sync with (a bit old) head

Resync to 2012-11-19 00:00:00 UTC

in cpu_switchto(), remove the MP-unsafe code to mark a pmap active on a CPU,
pmap_activate() already does this.  add MP locking to pmap_activate()
and pmap_deactivate().  move flushing of user windows and virtual caches
from pamp_activate() to pmap_deactivate().

Add RAS support for sparc.

sync with head

sync to -current.

Remove COMPAT_SA / KERN_SA.  Welcome to 6.99.3!
Approved by core@.

re-introduce the NULL savefpstate IPI checks and evcnts.  something
is Wrong with GCC 4.5.3 and these trigger.  i haven't seen anything
else particularly wrong so for now this will allow sparc to switch
to GCC 4.5, which otherwise seems to be working very well for me.

sigh.  i'm going to file a PR to research what is really wrong here.

Sync with HEAD.

Apply patches (requested by mrg in ticket #1564):
	sys/arch/sparc/dev/zs.c:		patch
	sys/arch/sparc/include/cpu.h:		patch
	sys/arch/sparc/include/z8530var.h:	patch
	sys/arch/sparc/sparc/cpu.c:		patch
	sys/arch/sparc/sparc/cpuvar.h:		patch
	sys/arch/sparc/sparc/db_interface.c:	patch
	sys/arch/sparc/sparc/genassym.cf:	patch
	sys/arch/sparc/sparc/intr.c:		patch
	sys/arch/sparc/sparc/locore.s:		patch
	sys/arch/sparc/sparc/machdep.c:		patch
	sys/arch/sparc/sparc/timer.c:		patch
	sys/arch/sparc/sparc/timer_sun4m.c:	patch
	sys/arch/sparc/sparc/timervar.h:	patch
	sys/arch/sparc/sparc/trap.c:		patch
	sys/arch/sparc/sparc/vm_machdep.c:	patch

- fix a panic in savefpstate.  idea, and code suggestions from uwe
- convert xpmsg_lock to IPL_SCHED.  the old spl/simple_lock code ran at
  splsched(), and this significantly helps with stability under load when
  running with multiple active CPUs
- in strayintr() don't print about stray zs inters in MP case
- fix a deadlock in xcall()
- consolidate the interrupt evcnt(9) into a full set of per-IPL per-CPU
  soft/hard counters
- fix xcall() failure messages in some cases
- addd new ddb command "mach xcall"
- use schedintr() (not schedintr_4m()) on MP or single CPU configurations
- call hardclock() the same way on cpu0 in MP and !MP cases
- request the appropriate stack space for nmi_sun4m, in particular,
  make sure we have space for %g2...%g5.  now entering ddb via eg,
  serial break no longer causes cpu1 to fault.
- give memfault_sun*() some entry points that both gdb and ddb will find.
from tsutsui:
- fix panic in interrupt handlers in zs

sync with head

Sync with HEAD

remove an unused "1:" label left over from previous commit.

remove the evcnt for NULL struct fpstate * ipi, and switch over to an
explicit panic() if we get one.

i'm pretty sure that converting xmpsg_lock from IPL_VM to IPL_SCHED
fixed this problem properly.  i have not seen the evcnt trigger since
that change, nor have several others queried.

Sync with HEAD

give memfault_sun*() some entry points that both gdb and ddb will find.

- move nmi_sun4m intr counting into nmi_soft/nmi_hard.
- request the appropriate stack space for nmi_sun4m, in particular,
  make sure we have space for %g2...%g5.  now entering ddb via eg,
  serial break no longer causes cpu1 to fault.

Sync with HEAD

Pull up following revision(s) (requested by mrg in ticket #1532):
	sys/arch/sparc/sparc/cpu.c: revision 1.215 via patch
	sys/arch/sparc/sparc/cpuvar.h: revision 1.78 via patch
	sys/arch/sparc/sparc/genassym.cf: revision 1.57 via patch
	sys/arch/sparc/sparc/intr.c: revision 1.103-1.105 via patch
	sys/arch/sparc/sparc/locore.s: revision 1.247, 1.250 via patch
	sys/arch/sparc/sparc/pmap.c: revision 1.329 via patch

- print the cpu_number() when we get a strayintr().

- use _MAXNCPU instead of 4
- convert xpmsg_lock from a simplelock to a kmutex
- don't wait for sparc_noop IPI calls
- remove xmpsg_func's "retval" parameter and usage
- remove the IPI at high IPL message
- rework cpu_attach() a bunch, refactoring calls to getcpuinfo() and setting
 of cpi, and split most of the non-boot CPU handling into a new function
- make CPU_INFO_FOREACH() work whether modular or not
- move the MP cpu_info pages earlier
- move a few things in cpu.c around to colsolidate the MP code together
- remove useless if (cpus == NULL) tests -- cpus is an array now

with these changes, and an additional change to crazyintr() to not printf(),
i can get to single user shell on my SS20 again.  i can run a few commands
but some of them cause hangs.  "ps auxw" works, but "top -b" does not.

convert sparc "intrcnt" counters to evcnt(9) style.  XXX some of the names
could be better, but i just copied them from the old intrnames in locore.

i benchmarked this with a simple test of ircii ./configure && make, to see
if the additional load/store & arith would cause any noticeable degradation
as the change also converts 32 bit counters to 64 bits.  amusingly, the
only trend i saw in this was that for both portions, i see a consistent
(across at least 8 runs) benefit of about 0.8% improvement.  ie, the newer
larger code size / counter size code actually runs faster for some reason..
maybe there's a cacheline effect in the size of the code?

XXX the current implementation depends on a couple of things:
XXX   - ev_count member of evcnt{} is first and has offset 0
XXX   - that sizeof(struct evcnt) equals 32
XXX if these are not true, locore.s has #error's to catch it

- remove unused ft_want_ast()
- give nmi_sun* ENTRY() points so they show up in symbols properly
- add some disabled code to use this cpu's idlelwp area when hatching
 a cpu, but right now it makes this worse not better...

consolidate the interrupt evcnt(9) into a full set of per-IPL per-CPU
soft/hard counters.  beyond the extra info, it seems to help avoid some
of these counters getting corrupted due to unlocked multiple accesses.

adjust the xcallintr() from xcall() hack so that we don't count these
events as interrupts.  align the existing evcnt name to count this.

Pull up following revision(s) (requested by mrg in ticket #1527):
	sys/arch/sparc/sparc/pmap.c: revision 1.327, 1.328
	sys/arch/sparc/sparc/cpuvar.h: revision 1.77
	sys/arch/sparc/sparc/locore.s: revision 1.245
	sys/arch/sparc/sparc/cpu.c: revision 1.214
	sys/arch/sparc/sparc/db_interface.c: revision 1.84
- retire union cpu_info_pg
- allocate space for each cpu_info{} in pmap_bootstrap
- remap cpu0's space into the PA currently in CPUINFO_VA
- cpus[] becomes an array of pointers to cpu_info{}, easy to traverse
- only call kernel lock for IPL_VM interrupts (?  as implemented on
  x86 and sparc64)
- revert a minor part of locore.s:1.241
- in cpu_hatch(), set %sp to near the middle of the interrupt stack.
  we only need a %sp until we get to run an MI thread (own idlelwp or
  real code)
we still waste one page of space, but this gets SMP much closer to
actually working again.
fix a LOCKDEBUG problem from the previous: need to call pmap_kremove()
on a pre-existing mapping, before installing a new one.

introduce a hack to workaround the savefpstate IPI get's NULL
struct fpstate *.

add a new entry point ipi_savefpstate() that is used for this IPI
instead of the plain ipi_savefpstate().  check for %o0 being NULL,
and if so, just return.

add event counters for the savefpstate IPI, and another one for
when it detects the NULL problem.

make the cpu_info struct xmpsg be aligned to a single cache line.

with this change applied (and another minor change in testing) my
SS20 with dual SM75's has survived for 17 hours on build.sh -j5,
and has reported 7 NULL savefps.  (the minor change seems to have
a significant effect at reducing this number, but more testing is
needed for it.)


XXX:  this is horrible and we really need to find the real problem
XXX:  but this should let people use sparc smp again, and fixes
XXX:  for the real problem can be tested by seeing if any of the
XXX:  savefp IPI null counter becomes non-zero.

Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits.  Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

Sync with HEAD.

sync with head.

update a comment.

Sync with HEAD.

sync to netbsd-5

sync with head

gas has supported SPARC ".empty" for a long while; get rid of an
ancient workaround.

in savefpstate(), make sure we fill in the _first_ read of %fsr into
the fpstate structure, not the last one.  avoids fs->fs_fsr lacking the
traptype field later when fpu_cleanup() is processing it, which leads
to a panic() occuring.

idea, and code suggestions from uwe.

Pull up following revision(s) (requested by mrg in ticket #1223):
	sys/arch/sparc/include/cpu.h: revision 1.86
	sys/arch/sparc/sparc/locore.s: revision 1.246
	sys/arch/sparc/sparc/vm_machdep.c: revision 1.100
fix up cpu_setfunc() as noted by uwe:
- don't call lwp_startup for cpu_setfunc() users
- introduce lwp_setfunc_trampoline instead
- no need to set the "new" lwp for setfunc

use the idle lwp's uarea for stack, not the interrupt stack.  this works
now, and it fixes up idle vs interrupt time measurement for cpu>0.

reinsert part of the code accidentally deleted by the previous change.

add two new members to struct intrhand: ih_realfun and ih_realarg, and
use them to take the kernel lock around non-IPL_VM interrupts, using
a intr_biglock_wrapper() function ike x86 does.

use genassym generated names for struct intrhand elements and avoid magic.

- remove unused ft_want_ast()
- give nmi_sun* ENTRY() points so they show up in symbols properly
- add some disabled code to use this cpu's idlelwp area when hatching
  a cpu, but right now it makes this worse not better...

Rename L_ADDR to L_PCB and amend some comments accordingly.

Kill proc0paddr.  Use lwp0.l_addr instead.

sync with head

convert sparc "intrcnt" counters to evcnt(9) style.  XXX some of the names
could be better, but i just copied them from the old intrnames in locore.

i benchmarked this with a simple test of ircii ./configure && make, to see
if the additional load/store & arith would cause any noticeable degradation
as the change also converts 32 bit counters to 64 bits.  amusingly, the
only trend i saw in this was that for both portions, i see a consistent
(across at least 8 runs) benefit of about 0.8% improvement.  ie, the newer
larger code size / counter size code actually runs faster for some reason..
maybe there's a cacheline effect in the size of the code?


XXX the current implementation depends on a couple of things:
XXX   - ev_count member of evcnt{} is first and has offset 0
XXX   - that sizeof(struct evcnt) equals 32
XXX if these are not true, locore.s has #error's to catch it

fix up cpu_setfunc() as noted by uwe:

- don't call lwp_startup for cpu_setfunc() users
- introduce lwp_setfunc_trampoline instead
- no need to set the "new" lwp for setfunc

- retire union cpu_info_pg
- allocate space for each cpu_info{} in pmap_bootstrap
- remap cpu0's space into the PA currently in CPUINFO_VA
- cpus[] becomes an array of pointers to cpu_info{}, easy to traverse
- only call kernel lock for IPL_VM interrupts (?  as implemented on
  x86 and sparc64)
- revert a minor part of locore.s:1.241
- in cpu_hatch(), set %sp to near the middle of the interrupt stack.
  we only need a %sp until we get to run an MI thread (own idlelwp or
  real code)

we still waste one page of space, but this gets SMP much closer to
actually working again.

sync with head.

Sync w/ -current. 34 merge conflicts to follow.

sync with head

Sync with HEAD.

enable profiling of assembly functions.

sync with HEAD

Sync with HEAD.

sync with head

Sync with HEAD

sync with HEAD

cpu_intr_p() for sparc, from Andrew Doran.

Sync with HEAD.

Sync with head.

Sync with HEAD.

catch up with the adses: IPL_CLOCK -> IPL_VM in a couple of places
that are #ifdef MULTIPROCESSOR.

MP sparc kernel faults inside proc0_init() yet.

Sync with HEAD.

sync with head

Sync with HEAD.

Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

sync with head.

Sync with head.

Sync with HEAD.

Sync with head.

Remove MUNGE(NOP_ON_4M_15), that label no longer exists.

cpu_switchto(): if oldlwp is NULL, don't bother saving it.

Update to HEAD.

Fix cpu_idle() for machines that have a idlespin function - use a
sibling call to invoke it (cpu_idle pretends to be a leaf function).
Pointed out by uwe.

fix typo in cpu_idle - the function we want to call is in %01 not %o3

Make lwp_trampoline comment explain how things are set up in more details.
While here, fix gimplish in the inline comment too (hi, phone!)

fix the two problems i introduced with yamt-idlelwp:

- in lwp_trampoline, oldlwp is already in %o0.  don't save or the wrongly
  saved copy from cpu_lwp_fork().  as repeatedly pointed out my uwe.

- in cpu_idle use retl not ret.  as pointed out by martin.


thanks to uwe/martin/tnn for all the real debugging work.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

sync with head.

port yamt-idlelwp to sparc.  this does not work yet, but others have
asked that i commit this work-in-progress.

currently kernel threads end up running with PSR_S missing from %psr
and end up failing to dump a user corefile.

Don't need to save lwp for use in lwp_exit2().

Sync with HEAD.

Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

G/c NOP_ON_4_4C_1 that used to be part of microtime.
Keep for reference but ifdef out the code to munge 4/4c nops
as there are none left.

- sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.

sync with head.

- don't call lwp_exit2().  ad@ says it isn't required anymore.
- load uvm.page_idle_zero with "ldub" instead of "ld", avoiding an
  unaligned access panic introduced since the int->bool changes.

now a -current kernel (both UP and MP) boot on my SS20 as long as
i have "options LOCKDEBUG" as well.

Merge newlock2 to head.

For now always call sched_unlock_idle/sched_lock_idle. They will be
removed by yamt's cpu_switchto() changes.

Checkpoint work in progress.

sync with head.

sync with head

sync with head

Merge from HEAD.

Align the size and alignment of label_t (kernel jmp_buf equivalent)
with the use in setjmp/longjmp. Duh!
This makes DDB work again on sparc kernels compiled with gcc4.

sync with head.

sync with head.

Sync with head.

convert to timecounters (from branch simonb-timecounters)

Sync with head.

convert to timecounters

Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.

sync with head.

Fix some comments.

Sync with head.

sync with head.

Drop trailing whitespace.

Protect all places that refer to _redzone with
#if defined(DEBUG) && !defined(MULTIPROCESSOR)
Makes MULTIPROCESSOR + KGDB compilable.

Sync with HEAD. Here we go again...

sync with head

sigcode is needed only for COMPAT_16.

Shave off one instruction in _syscall.

fix borked MicroSPARC IIep microtime() from previous version.

add a function pointer to struct cpu_info:
void idlespin(struct cpu_info *)
which is called whenever the CPU is idle and uvm_pageidlezero() has nothing to
do

Run the MicroSPARC IIep PCI bus without endianness translation.
This allows us to run X without any additional code changes.

Hanlde NMI on microSPARC-IIep.

We don't do much useful except reporting, but that's better than to
stupidly use sun4m handler and wedge the machine.  May need to revisit
what's fatal.

Prodding by macallan@

- add syscall_{plain,fancy}
- make it use mi_userret

Pull up revision 1.215 (requested by pk in ticket #1154):
sun4/sun4c sw interrupt entry: check interrupt register to determine to
see whether there is a pending software interrupt at the given level.
If not, it must be a device interrupt sharing that level.

sync with -current

sync with head.

Sync with HEAD.

sun4/sun4c sw interrupt entry: check interrupt register to determine to
see whether there is a pending software interrupt at the given level.
If not, it must be a device interrupt sharing that level.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

cpu_simple_lock: on spin out, check whether we've already panicked. If so,
just take the lock on the assumption that in panic mode, we run on a single
CPU anyway.

Fix typo in CHECK_SP_REDZONE() which has been there since the beginning of time.

10+ entries in the kernel sources can't be wrong ... no, wait, they can:
it really is "panicking" instead of "panicing", so revert rev 1.211

thanks to Klaus for holding the spelling bee

typo in comment: panicking -> panicing

`uvmexp.swtch++' is already done in exit1().

The cpu_exit() detour is no longer necessary.

Fast trap handler for Illegal Instruction traps for (user space) FLUSH
instructions (these occur only on Cypress CPUs).

Pull up revisions 1.199-1.207 (requested by pk in ticket #179)

Many fixes for issues with sparc multi-processor support (includes
fixes to make HyperSPARC MP work).

Always provide the __cpu_simple_lock() entry point (for LKMs).

Provide a fast trap path for AST IPIs.

CMP_PTE_USER_READ4M: drop instruction that's effectively a no-op.

Various ft_srmmu_vcache_*() functions: use `branch on greater (unsigned)'
instead of `branch on positive'.

Make inlining __cpu_simple_lock() optional. Add a version with a built-in
spin out counter that panics with a diagnostic.

Update fast xcall interrupt event counter.
ft_srmmu_vcache_flush_range: adjust length for address alignment

When acknowledging a sun4m soft interrupt, read back the pending interrupts
hw register to make sure it gets through on Ross CPUs.

The macro CMP_PTE_USER_READ4M now needs to consider more PTE access
rights combinations, since the access rights table in pmap has changed.

Implement fast trap handlers for TLB and cache flushes.

Add openfirmware() entry point, since it's no longer defined as a macro
in openfirm.c.

Uppercase CPU, plural is CPUs.

Drop the old cpu_switch() code.

Construct arguments properly and update comment in previous bzero -> memset
changes.

Fix previous (bzero -> memset), it overlooked the delay slot.
Use set and clr pseudo instructions to simplify the code a bit.

use "mov 0, %o1" instead of kinda strange "sethi 0, %o1" in previous
pointed out by Matthew Green

use memset() instead of bzero()

cpu_switch: values in global registers are not preserved across function calls.

sun4m_access_fault: Treat text/data error traps as if they were text/data
exception traps, except that they're logged on the console.

sparc kernel support for SA_SIGINFO.

Make v8_*_len symbols local so that they don't get in the way in ddb.

Move all `ID prom' stuff into the prom library.

Allow the kernel to be loaded at its link address (aka KERNBASE) by the
boot program.

Merge the nathanw_sa branch.

Sync with HEAD.

Sync with HEAD.

cpu_switch:
* return `switched to same process' only if that process was actually
  already on a run queue when we entered.
* skip the switch to the idle stack if we can switch immediately
* .. and because of this, don't release the scheduler lock until after
  we've fully switched to the new process's stack.

Don't grab the kernel lock for system timer interrupts; this mostly prevents
stalls in system time processing.

XXX - deal with non-atomic global time variables updates later.

Sync with HEAD.

remove cpu_hatched, cpu_hatch_sc and cpu_hatchstack.  the first can use
the cpi->flags, the second is unused and the third is also cpi-idle_u.

Account softintr_common as uvmexp.softs, not uvmexp.intrs.

keep track of which cpu's have run a pmap and only broadcast tlb flushes to
cpu's who have done so.  implement pmap_deactivate() for MULTIPROCESSOR and
call it from cpu_switch() when we are about to switch proces and when we
enter idle().

with this change, i see significantly reduced tlb IPI traffic and fork/exec
bound processes -- such as "configure" -- run significantly faster, upto
15%.  i also obvserved a small (0-2%) benefit to CPU bound tasks as well.

Replace `want_resched' and `want_ast' globals by per-CPU variables.

Sync with HEAD.

Let all CPUs play..

Catch up to -current.

Remove the upcall trampoline, and invoke the upcall directly.  Also,
there is no need to fiddle with register windows here, nor to save the
arguments to the stack.

Reviewed by uwe.

Grab the kernel lock on interrupts at level IPL_CLOCK and lower.

new cpu_switch: SMP: even if we pick up the same process after idling, we
must reset its context as the process might have run on another cpu in
between and had its context changed, e.g. by exec(2).

Pass exit2 or lwp_exit2 to switchexit(), as is suggested in comments,
and eliminate switchlwpexit().

Apply SA changes to ALT_SWITCH_CODE.

Sync with HEAD.

XXX ALT_SWITCH_CODE is not yet LWP'ified.

SMP: lock kernel for soft interrupts < IPL_SCHED as well.

Slight optimisation in proc_trampoline().

New version of cpu_switch/switchexit, mostly to simplify SMP support. It's
currently conditional on ALT_SWITCH_CODE (defaults to `on' if MULTIPROCESSOR
is defined) until more testing rounds are completed.

nmi_sun4m: run handler at splhigh()

Rename cpu_preempt() to cpu_switchto(), and make the caller remove the
new process from its run queue before calling cpu_switchto().

While here, make a few cpu_switch() and cpu_switchto() implementations
get the outgoing LWP from the args, rather than looking at the curlwp
variable.

Sync with HEAD.

xcallintr() receive a `clockframe *' argument, not a `trapframe *'.
Setup a DDB context for paused CPUs by defining a soft trap (T_DBPAUSE)
which uses the generic trap handler code to get the trapframe constructed
and then calls on a debugger-defined `suspend' routine.

* cpu_hatch(): enable interrupts upon return from cpu_setup().
* interrupt trap: acquire the kernel lock only for interrupt levels <= PIL_SCHED

Sync with HEAD.

Soft interrupts use their own set of handlers lists.

cpu_switch(): avoid raising the interrupt level and enabling traps at the
same time as this may cause a spurious interrupt in some implementations.
Pointed out by uwe.

ienab_bi[cs] are never used in a context common to both sun4/4c and sun4m,
so there's no point in constructing common entry points for them in locore.s.

Pass the `device class interrupt level' on to intr_establish() and use to
raise the ipl in the interrupt handlers to the appropriate level. This avoids
interrupt handler interference if one of the devices actually interrupts at
a lower hardware level than the maximum level assined to a device class.

Based on code from Art Grabowski in openbsd.

Provide the V8 mul/div routines for SUN4D as well.

Move the installation of v8 specific .mul/.div functions into a separate
routine to be called when we're sure the CPU is actually sparc version 8.

Make upcalls work.  sa2 passes now.
sa3 seems to work but hangs after printing "About to exit."

Provide sparc v8 multiply/divide routines which are copied over the base
v7 versions on sun4m and sun4d machines. Based on Chris Torek's BSD/OS
code.

sync kqueue branch with HEAD

catch up with -current.

Catch up to -current.

Add missing slash to /* notyet *

Fix botch in previous.  #ifdef DIAGNOSTIC was one instructions too early
in sparc_interrupt4m, thus breaking soft interrupts for normal 4m's.

Should fix port-sparc/17891 (thanks, Martin).

Catch up to -current.

In DIAGNOSTIC kernels detect situation that on sun4m neither hardware
nor software interrupt pending bit is set for the current ipl.  Report
this as a "bogus" interrupt (better name anyone?).  This is a symptom
of a bug in interrupt handling in one of device drivers interrupting
at this ipl.  Reviewed by pk.

Catch up to -current.

catch up with -current.

Add sun4d cases for early bootstrap.  This is good enough to
get as far as printing the copyright on an SPARCserver 1000.

Print out a meaningful message on the sun4d if the kernel does
not support the sun4d, like we do with sun4c and sun4m.

catch up with -current.

Curproc->curlwp renaming.

Change uses of "curproc->l_proc" back to "curproc", which is more like the
original use. Bare uses of "curproc" are now "curlwp".

"curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL)
so that it is always safe to reference curproc (*de*referencing curproc
is another story, but that's always been true).

catch up with -current on kqueue branch

Catch up to -current.

Pull up revisions 1.154-1.157 (requested by pk in ticket #298):
  revision 1.157
    Fix typo in nmi_sun{4,4c}, use correct register.
  revision 1.156
    Fill delay slot in previous to match normal microtime.
  revision 1.155
    Do not use "std" in ms-IIep micortime, the argument is not guaranteed
    to be double-word aligned and it is not when we are called from bpf.
    Remove "should be able to std here" comment in generic microtime.
    While here, simplify some asm mnemonics and fix a typo in comment.
  revision 1.154
    Use C-style comments in a few places where ' appears in the comment,
    so that this works with GCC 2.95.3's ISO C preprocessor.

Fix typo in nmi_sun{4,4c}, use correct register.

Fill delay slot in previous to match normal microtime.

Do not use "std" in ms-IIep micortime, the argument is not guaranteed
to be double-word aligned and it is not when we are called from bpf.
Remove "should be able to std here" comment in generic microtime.
While here, simplify some asm mnemonics and fix a typo in comment.

Use C-style comments in a few places where ' appears in the comment,
so that this works with GCC 2.95.3's ISO C preprocessor.

Provide storage for proc0.

Catch up to -current.

Sync w/ -current.

Rename `esym' to `kernel_top' and always initialize it in locore from
the information provided by the loader if possible (defaulting to `end').
If the DDB symbols aren't needed, `kernel_top' is adjusted in
autoconf:bootstrap() before calling pmap_bootstrap(). It will also
preserve the bootinfo data (if passed by the loader) for non-DDB kernels.

Eliminate `cputyp' test from cpu_switch().

More catchup.

Sync kqueue branch with -current.

In the idle loop add a comment to wrpsr in the annulled delay slot of
an ifdefed branch instruction to make it obvious where it belongs to.
The ifdef makes it very confusing visually.

Catch up to -current.

Change interface between cpu_fork() and proc_trampoline() so that `tf_pc'
(instead of `tf_npc') contains the user-space return address. This ensures
entering the signal trampoline code correctly in case we take handled
signal during child_return().

Implement microSPARC-IIep versions of sparc_interrupt4m, raise and microtime.

Eliminate the loading and testing of `cputyp' in cpu_switch().

`l_stat' is an `int' now in stead of an `u_char'... Bloody confustication!

More work on lwpswitchexit(), cpu_preempt() and cpu_switch().
Fortunately, it seems we can share a fair deal of code among these.

Convert to SA framework.
Compilable, but some core functionality stubbed out still.

Catch up with -current.

file locore.s was added on branch nathanw_sa on 2001-11-20 16:31:55 +0000

Some sun4c machine (e.g. an IPC) can also have just 7 register windows,
so check for a possible context switch optimization #if SUN4C too.

The SAVE macro used in the context switch code wound up being defined
only if MULTIPROCESSOR in rev 1.142, causing spurious register window
corruption on some machines.

Merge Aug 24 -current into the kqueue branch.

g/c _remque()/_insque(); use the C version in libkern

- replace CPUFLG_STARTUP with new CPUFLG_READY scheme, used after startup has
occured.  cpus now spin waiting for new `go_smp_cpus' variable to go non-zero.
- new xpmsg_lock that must held around all cross call activity.  new macros:
LOCK_XPMSG() and UNLOCK_XPMSG().
- delete delay(1)/cache_flush gone from raise_ipi_wait_and_unlock(), it incurred
a stupid performance penalty.

Catch up to -current.

Be prepared to get OpenFirmware client entry in either %o3 (PROM way)
or %o0 (our boot code passes romp in %o0 even for OF machines).
Discussed with pk.

oops; non-primary cpus should still spin, not jump to idle.

more SMP work: finish up ipi's, SMP DDB support, cpu startup issues, and
idle() u area issues:

in nmi_sun4m(), if this is a soft NMI and DDB is configured, setup a trapframe
and pass it to nmi_soft().  in cpu_hatch(), spin until our cpu's flags no longer
have CPUFLG_STARTUP set.  then, setup registers and jump to
idle_enter_no_schedlock.  in idle(), if MULTIPROCESSOR, always switch to this
cpus idle u.  a minor optimisation to cpu_switch().

split {sunos,svr4}_sigcode out for LKMs

Pull in "opt_kgdb.h"; see PR#13036.

Pull up revision 1.139 (via patch, requested by pk):
  In proc_trampoline() make the new process run at base interrupt
  priority level.  Especially important for kernel threads, which
  would otherwise keep running at splclock().

  Eliminates system clock instability.

Sync with HEAD

proc_trampoline(): mave the new process run at base interrupt priority level.
This is especially important for in-kernel processes started from here,
which would otherwise keep running at splclock().

Catch up with -current.

Sync with HEAD.

in mem_access_fault*(), when invoking the pcb_onfault mechanism, pass the
return value of uvm_fault() to the onfault routine via %o0.  users of
pcb_onfault now return this value to their callers rather than always
returning EFAULT. this allows i/o errors in VOP_GETPAGES() to be returned
back to read(), etc.

lock the kernel around calling interrupt stubs.

Sync with HEAD.

* proc_trampoline: call `proc_trampoline_mp()' #if MULTIPROCESSOR;
  currently necessary to acquire the `running in kernel mode' lock;
  pointed out by Bill Sommerfeld/Simon Gerraty.

* remove reference to `cpu_set_kpc()' from comments, as we don't have it.

bootstrap area: remove dead code + some trivial reformatting

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Scheduler lock update.

Pull up revision 1.132 from trunk.

Fix delay slot error in the SUN4_MMU3L startup code.

Fix delay slot error in the SUN4_MMU3L startup code.

Sync w/ netbsd-1-5-base.

Fix a couple of typos.

- In the MULTIPROCESSOR case, initialize p_cpu before a process is
  marked SONPROC.
- Fix a bug where all cpu_info structures except for the boot CPUs
  would exist at both a CPU-local VA (CPUINFO_VA) and a gloal VA;
  The boot CPU's existed only a CPUINFO_VA.
- Add a self-reference pointer to the cpu_info that references the
  global address in the MULTIPROCESSOR case.  Just allow it to reference
  the `local' VA in the single-processor case, as CPUINFO_VA is global
  enough when there's only one processor to care about.  Change curcpu()
  to return the global address.

First sweep at scheduler state cleanup.  Collect MI scheduler
state into global and per-CPU scheduler state:

	- Global state: sched_qs (run queues), sched_whichqs (bitmap
	  of non-empty run queues), sched_slpque (sleep queues).
	  NOTE: These may collectively move into a struct schedstate
	  at some point in the future.

	- Per-CPU state, struct schedstate_percpu: spc_runtime
	  (time process on this CPU started running), spc_flags
	  (replaces struct proc's p_schedflags), and
	  spc_curpriority (usrpri of processes on this CPU).

	- Every platform must now supply a struct cpu_info and
	  a curcpu() macro.  Simplify existing cpu_info declarations
	  where appropriate.

	- All references to per-CPU scheduler state now made through
	  curcpu().  NOTE: this will likely be adjusted in the future
	  after further changes to struct proc are made.

Tested on i386 and Alpha.  Changes are mostly mechanical, but apologies
in advance if it doesn't compile on a particular platform.

Introduce a new process state distinct from SRUN called SONPROC
which indicates that the process is actually running on a
processor.  Test against SONPROC as appropriate rather than
combinations of SRUN and curproc.  Update all context switch code
to properly set SONPROC when the process becomes the current
process on the CPU.

Arrange to call uvm_pageidlezero() from idle loop.

Missing _C_LABEL().

Pull up to last week's -current.

Sync with -current

pull up rev 1.126 from trunk (requested by chs):
  Fix several panics in copy{in,out,}str().

several fixes to copy{in,out,}str() from charles and myself:
don't panic if maxlen == 0, just return ENAMETOLONG.
treat maxlen as unsigned like the manpage indicates.
avoid crashing if the userspace address is >= KERNBASE.
make sure *done is 0 when no bytes are copied.

file locore.s was added on branch comdex-fall-1999 on 1999-11-05 04:49:27 +0000

several fixes to copy{in,out,}str() from charles and myself:
don't panic if maxlen == 0, just return ENAMETOLONG.
treat maxlen as unsigned like the manpage indicates.
avoid crashing if the userspace address is >= KERNBASE.
make sure *done is 0 when no bytes are copied.

Since a context table is now pointing at the correct per-CPU region table
at all times, we can dispense with the hackery that patches the magic entry
at context-switch time.

Centralize the declaration and clearing of `cold'.

Sync w/ -current.

Declare `bootinfo' also if !DDB.

Argh, removed last ELF induced problem. We used to have syscall: in locore.s
and _C_LABEL(syscall) in trap.c. In ELF they are the same. Change the label
in locore.s to be _C_LABEL(_syscall).
While I am there, move the register save and restoral code used in the
*sigcode trampolines into two macros and use them instead of copying 100
lines of assembly each time.
Now everything ELF works.

Fix panic and panicstr to use _C_LABEL.
Statuc: ELF kernel loads symbols properly, hangs in syscall while running init.

Gain one instruction..

s/\<0x4000\>/PROM_LOADADDR
remove unused cputypvallen, and _msgbufaddr

* Add missing label.
* Avoid harmful delay-slot instruction, if we did not get a `bootinfo' thing.
* Compute correct location of `esym' for all three methods of debug
  symbol loading we support.

pullup 1.114->1.116 (christos)

Add bootinfo support for loading symbol tables.

Revert previous bootinfo premature commit, and commit the sunos_sigcode
stuff instead.

Add sunos_sigcode and sunos_esigcode for COMPAT_SUNOS

The MMU_3L option became SUN4_MMU3L long ago.

completely remove Mach VM support.  all that is left is the all the
header files as UVM still uses (most of) these.

Apply C_LABEL() to `esym' too.

Use macros from <machine/asm.h> to construct C labels.

romcall() => prom_halt()

Check OBP magic: if no match then assume an Openfirmware PROM.

Minor changes; indentation for delay slots and NOTREACHED comments.

Clean up kcopy() some more:
* Return EFAULT, not -1.
* Rearrange some instructions for better parallelism.

kcopy() must restore pcb_onfault handler. Pointed out by Charles Hannum.

Duh.. condition codes are not preserved when writing directly into %psr.
Also, we need to deal with bus latency when turning off bits in the
interrupt status register.

Maintain a current process (`curproc') a per CPU.

Drop cpuinfo's `L1_ptps'; instead keep a per CPU segment (level 2) page
table descriptor that is used to patch up a region (level 1) page table
associated with a user pmap at context switch time.

Let all CPUs spin at spl0.

EINTSTACK => EINTSTACKP

Oops, USPACE does not in 13 bits.. repair and save one instruction
in a non-SMP kernel.

In switchexit(), switch to the current CPU's idle u.area.

Make `_cpcb' (pointer to current user area) a per-CPU variable.
This cpuinfo field is initialized here in locore before calling bootstrap(),
since it must be valid before entering the window overflow/underflow handlers.

Fix miscalculation in the MULTIPROCESSOR version of INTR_SETUP().

Allocate a private PCB, kernel stack and interrupt stack for each processor.
As a result, the stack setup code in locore.s changes slightly in
the MULTIPROCESSOR case. Also, make the stack redzone barrier (for
debugging only) a per-CPU entity.

Use per-CPU interrupt status register.

We no longer need to access memerr() through a function pointer.
GC `cpumod' and `mmumod'.

Dedicate a pair of entry points to handling sun4m level 15 (NMI) interrupts.
Hardware NMIs are generated on various fault conditions that take place
asynchronously to the instruction stream. Software NMIs are going to be used
for inter-processor communications.

Get synchronous fault information separately from asynchronous fault
information. Do the former right after taking a memory fault trap and
store the values in temporary locations within the cpuinfo structure (XXX),
so we can unconditionally clear the sync fault status register after
MMU probe operations. This all is to work around a Hypersparc feature
which could lead to loss of fault information because of the fault
status register getting locked.

sigh.. put back non-garbage collectible `que' functions.

Pull in <sys/syscall.h> directly into locore.s

A few slight optimizations.

Nuke `insqeu' and `remque'

Add hatching code for other CPUs.