CVS log for src/sys/arch/sgimips/sgimips/bus.c

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Default branch: MAIN

Remove unnecessary <sys/malloc.h>.

update from HEAD

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

Sync with HEAD

reenable mips1-specific dmamem_sync method
clean up a bit while there

Sync with HEAD

Wrap long line

Fix compile

Sync with HEAD

switch sgimips to common bus_dma and bus_space in arch/mips/
Tested on O2 and Indy.
Things that are compile-tested only for lack of hardware:
- GIO ethernet cards with PCI bridges
- IP2x hardware not found on Indy
- IP1x

Resync to 2012-11-19 00:00:00 UTC

sync with head

move common/bus_dma/ -> dev/bus_dma/

sync with head

merge to -current.

Change old-style function defintions to C89 prototypes.

Approved by releng.

Switch MIPS and MIPS-ish architectures to new-style <sys/bus.h>.  This
involves moving some inline bus_space(9) implementation into .c files.

Sync with HEAD.

sync with head

Sync with HEAD

Merge forward matt-nb5-mips64
Adapt to new interrupt/spl framework
Deal with arcbios calls being O32 and kernels being N32/N64.
Need to save/restore T8 across arcbios calls.

Sync with HEAD

PMAP_NOCACHE -> PGC_NOCACHE where appropriate

Sync with HEAD.

sync with head.

Turn PMAP_NOCACHE into MI flag.
Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR.
Update pmap(9) manpage.

hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag
mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE.

x86: Implement new MI flags using Page-Attribute Tables.
x86: Implement BUS_SPACE_MAP_PREFETCHABLE.

Patch presented on tech-kern@:
http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html

No comments on this last version.

sync with head

Adjust things to the new world order.

Deal with various changes with avail_end and avail_start, etc.

make this compile again by sprinkling PRIxWHATEVER

Merge from matt-nb5-mips64
Merge mips-specific arch files.

mips3_ld/mips3_sd need to be passed a volatile uint64_t *

sync with head

Add preliminary LP64 support for sgimips

Use bus_dmamem_common.

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

sync with head.

Sync with HEAD.

Enable Personal IRIS 4D/20 and 4D/25 support:
  - Adapt int(4) to handle the INT1 chip
  - Move generic rtc clocks out of hpc/ and into dev/
  - Handle the very strangely wired eeprom and other bits in arcemu
  - Sprinkle MACH_SGI_IP6 as necessary
  - Enable IP6/IP10 devices in GENERIC32_IP12. Yes, the naming is poor but
    there's no winning with kernel/hw compatibility on sgimips...

Tested on my 4D/25. Doesn't (appear to) break macallan@'s IP22.

Pull up following revision(s) (requested by tsutsui in ticket #1221):
	sys/arch/sgimips/conf/files.sgimips: revision 1.44
	sys/arch/sgimips/sgimips/bus.c: revision 1.50
make the delay()s and spl*()s in bus_space*() functions optional
( enable with options MACE_NEEDS_DELAYS )
mec apparently was the only device that really needed them and that's no
longer the case, at least on my O2.

Sync w/ -current. 34 merge conflicts to follow.

sync with head.

Sync with HEAD.

Also fix build.

vm_page: put TAILQ_ENTRY into a union with LIST_ENTRY, so we can use both.

Sync with HEAD.

sync with head.

sync with head.

Remove clause 3 and 4 from TNF licenses

sync with HEAD

sync with head.

Sync with HEAD.

add bus_space_mmap()

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Sync with HEAD

sync with head.

Sync with HEAD.

use 64bit paddr_t and bus_addr_t so we can mmap DMA buffers uncached

make the delay()s and spl*()s in bus_space*() functions optional
( enable with options MACE_NEEDS_DELAYS )
mec apparently was the only device that really needed them and that's no
longer the case, at least on my O2.

Sync with head.

Sync with head.

sync with head.

Flush the write buffer as appropriate in the MACE case as we do in the
non-MACE cases. From sekiya@

Sync with HEAD.

Use (char *) to appease -Wpointer-arith.

Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

sync with head

sync with head.

sync with head.

Sync with head.

Implement bus_space_*_stream_* methods for sgimips - so that we can use the
atheros wlan driver. Thanks to Izumi Tsutsui for lots of input. All errors,
as usualy, are mine though.

Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.

sync with head.

Sync with head.

sync with head - hopefully this will work

Mising -> Mixing

Fix function names in panic messages.

_ds_vaddr member in struct sgimips_bus_dma_segment is a virtual address,
so it should be vaddr_t rather than bus_addr_t.

merge yamt-uio_vmspace branch.

- use vmspace rather than proc or lwp where appropriate.
  the latter is more natural to specify an address space.
  (and less likely to be abused for random purposes.)
- fix a swdmover race.

keep vmspace rather than proc in sgimips_bus_dmamap.

adapt the rest of MD code.

merge ktrace-lwp.

Sync with head.

sync with head.

bus_dmamem_map: honour BUS_DMA_NOWAIT.  noted by Manuel Bouyer.
bus_space_map: always do NOWAIT allocation as it used to be before yamt-km.

we have too many copies!

sync with -current

Sync with HEAD.

merge yamt-km branch.
- don't use managed mappings/backing objects for wired memory allocations.
  save some resources like pv_entry.  also fix (most of) PR/27030.
- simplify kernel memory management API.
- simplify pmap bootstrap of some ports.
- some related cleanups.

sync with head.  xen and whitespace.  xen part is not finished.

Adapt to new dm_maxsegsz semantics.

Don't deref a NULL struct lwp *. This shouldn't happen, but...

use new apis.

Sync with HEAD.

Nuke MIPS64; we'll use MIPS3 to indicate the presence of MIPS3 instructions
and _LP64 to indicate that 64-bit is desired.

Pointed out by simonb@

Remove gratuitous use of MIPS1/MIPS3.

bus_dmamap_load_mbuf(): Skip zero-length mbufs.
kern/24811

Sync with HEAD

Use the mips3 bus functions on IP30.  Recognize the IP30 as a supported* SGI
platform.

* For extremely small values of "supported".  arch/mips/* needs a lot of work
  yet for MIPS64.

s,#ifdef MIPS3,#if defined(MIPS3) || defined(MIPS64),g

Use ANSI function declarations.

Fix the sync with head I botched.

Sync with HEAD.

Correct a few comment typos that have propagated through the
tree.

Sync with HEAD

Back out portions of previous commit -- the mips/bus_dma.c code is less
correct than the sgimips-specific code.

Merge fixes from arch/mips/mips/bus_dma.c -- a curproc->lwp fix, and streamline
the cache magic for BUS_DMASYNC_PREREAD in _bus_dmamap_sync_mips3().

(Note to self: investigate feasibility of replacing MD bus.c with MI bus_dma.c)

Sprinkle some #ifdef MIPS3 to be able to compile the port without
including MIPS3 code.

for upcoming IP12

Following the example of the hpc/, gio/, and ioc/ directories, move the
mace devices to their own mace/ directory.  Alter conf/files.sgimips to
reflect this change in a sane manner (i.e., pull in dev/files.dev and
mace/files.mace when appropriate).

At the same time, allow crime_intr_establish() to fall through to
mace_intr_establish().  mace devices now call cpu_intr_establish().

Large rototill of the lowlevel code:

* move all device-specific bitbanging to the device drivers in question --
  i.e., the ip32 init code doesn't access the CRIME registers directly but
  instead trusts the CRIME driver to DTRT.  machdep.c is cleaner thereby.
* introduce int.c, which handles the interrupt-controller goo formerly
  in ip2x.c.
* unify the CPU interrupt handler, with CRIME, INT2, and the various timer
  handlers hooked in via pointers in the platform struct.
* eliminate ip2x.c and ip32.c.  After the interrupt handler cleanup, the
  actual platform-dependent code was so minimal (rev identification, mask level
  initialization) that it made sense to move it into machdep.c
* "#ifdef DEBUG printf("foo"); #endif" becomes aprint_debug.

Tested on my ip22 and ip32.  Discussed with pooka@, rafal@.

Implement bus routines for MIPS1 processors.  Originally from Steve Rumble,
massaged by pooka@.

mips3_* functions aren't available when MIPS3 is not defined, so provide
MIPS1 workalikes (which, for the _8 routines, discard the top 32 bits).

CRIME revision 1.1 has a bug that affects PIO operations to/from the MACE.
The recommended workaround is a 5-10ms delay before and after accesses.
Therefore, move the affected bus_space_* operations from bus.h to bus.c
and special-case MACE accesses.

CRIME accesses are not affected, so introduce SGIMIPS_BUS_SPACE_CRIME and
use it as the CRIME tag.

My ip32 seems a little bit happier with this change, and my ip22 didn't
notice the change.

Use proper mips_dcache_{wb,inv,wbinv}_range() ops in dmamap sync function
if possible. Tested on my O2 (with r5ksc patch).

XXX should we apply similar changes to mips/bus_dma.c and use it?

Use proper macros.

__KERNEL_RCSID()

Apply the aborted ktrace-lwp changes to a specific branch.  This is just for
others to review, I'm concerned that patch fuziness may have resulted in some
errant code being generated but I'll look at that later by comparing the diff
from the base to the branch with the file I attempt to apply to it.  This will,
at the very least, put the changes in a better context for others to review
them and attempt to tinker with removing passing of 'struct lwp' through
the kernel.

Back out the lwp/ktrace changes. They contained a lot of colateral damage,
and need to be examined and discussed more.

Pass lwp pointers throughtout the kernel, as required, so that the lwpid can
be inserted into ktrace records.  The general change has been to replace
"struct proc *" with "struct lwp *" in various function prototypes, pass
the lwp through and use l_proc to get the process pointer when needed.

Bump the kernel rev up to 1.6V

Use PAGE_SIZE rather than NBPG.

Sync with HEAD.

add bus_space_vaddr()

from rafal

Catch up to -current.

Memory and I/O space accesses to MACE PCI address ranges are passed through
in the correct byte order, so there's no reason to byteswap them.

catch up with -current.

catch up with -current on kqueue branch

Catch up to -current.

move initialization of the "struct pglist" returned by uvm_pglistalloc()
from the calling code into uvm_pglistalloc() itself for consistency
and easier error handling

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

Catch up with -current.

Replace lots of 8x<space> with <tabs> and other miscellaneous indentation
fixes.
Wrap a couple of long lines.
Use <return-type>\n<function name> as per KNF in a few places.

Catch up to -current.

In _bus_dmamap_sync, only invalidate as much data as there is in the current
segment rather than invalidating the total map length for each segment.

Sync kqueue branch with -current.

file bus.c was added on branch nathanw_sa on 2002-02-28 04:11:36 +0000

Merge the thorpej-mips-cache branch onto the trunk.  This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

compilation fix.
s/mips3_HitFlushDCache/mips_dcache_wbinv_range/

Catch up with -current.

Update the kqueue branch to HEAD.

Update pmap_update to now take the updated pmap as an argument.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.

Currently this is a no-op on most platforms, so they should see no difference.

Reviewed by Jason.

bcopy -> memcpy, bzero -> memset

Catch up to -current.

replace vm_page_t with struct vm_page *.

Use hit-flush ops in bus_dmamap_sync().  From Rafal K. Boni.

Sprinkle pmap_update() calls after calls to:
- pmap_enter()
- pmap_remove()
- pmap_protect()
- pmap_kenter_pa()
- pmap_kremove()
as described in pmap(9).

These calls are relatively conservative.  It may be possible to
optimize these a little more.

Catch up with -current.

Sync with HEAD.

s/vm_page_alloc_memory/uvm_pglistalloc/ in panic message.

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Pull up mmap paddr_t/off_t changes from trunk.

file bus.c was added on branch thorpej_scsipi on 2000-11-20 20:23:48 +0000

remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>

remove/move more mach vm header files:

	<vm/pglist.h> -> <uvm/uvm_pglist.h>
	<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
	<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
	<vm/vm_object.h> -> nothing
	<vm/vm_pager.h> -> into <uvm/uvm_pager.h>

also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.

Change the kernel mmap interface so that the offset to map is an
"off_t" and the return value is a "paddr_t" to allow mappings
at offsets past 2^31 bytes.  Somewhat inspired by FreeBSD, which
only changed the offset to a "vm_offset_t".

Includes updates for the i386, pc532 and sh3 mmmmap from Jason Thorpe.

Sync w/ netbsd-1-5-base.

file bus.c was added on branch minoura-xpg4dl on 2000-06-22 17:03:39 +0000

Initial commit. Needs work.