CVS log for src/sys/arch/sgimips/hpc/hpcdma.c

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Keyword substitution: kv
Default branch: MAIN

Add (intptr_t) casts to fix "cast to pointer from integer of different size",
mainly for GENERIC64_32_* configs.
Also change segp->ds_len format specifier to %lld, which fixes DMA_DEBUG build.

#include <sys/bus.h> instead of <machine/bus.h>.

Sync with HEAD.

sync with head

Sync with HEAD

Some KNF and cosmetics.

u_intNN_t -> uintNN_t

Small bus_dma(9) tweaks:
- call bus_dmamap_create(9) after bus_dmamem_alloc(9) and bus_dmamem_map(9)
  return successfully
- no need to use PAGE_SIZE for size of descriptor dmamap
- use bus_addr_t to store DMA address
- BUS_DMASYNC_PREWRITE is enough for host-to-device only descriptors

Tested on R5000 Indy.

sync with head

Merge from matt-nb5-mips64
Merge mips-specific arch files.

Add preliminary LP64 support for sgimips

Sync w/ -current. 34 merge conflicts to follow.

Backout previous: the license sweep touched these files in error, so
restore the old license.

Remove clause 3 and 4 from TNF licenses

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Sync with HEAD

sync with head.

Sync with HEAD.

Sync with HEAD.

Sync with HEAD.

After move to 64-bit paddr_t, cast via vaddr_t before casting to void*.
OK'ed by macallan@.

Sync with HEAD.

Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

merge ktrace-lwp.

Sync with HEAD.

Prepend HPC3 macros universally with "HPC3_" to distinctly recognise
the corresponding revision and maintain consistency with HPC1.

No functional change intended.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Fixes to HPC abstraction layer from Steve Rumble:

        - hpc1_hdd_{ctl,bufptr} and hpc3_hdd_{ctl,bufptr} are
          established in hpcreg.h. All references to these fields
          are updated with the exception of if_sq: (haltwo,
          hpcdma). This makes reading the code and spotting bugs
          easier.
        - hpcdma.c was applying EOCHAIN to the wrong descriptor
          word for the hpc1 case.
        - I added scsi_max_xfer to the abstraction layer, and it
          allows some crusty #defines in wdsc.c to be removed.
          hpc1 now doesn't waste descriptors as it once did.
        - hpcreg.h was updated to reflect the lack of XMITDONE
          bit in hpc1. HPC1_REV15 added for a test in hpc.c
        - hpc.c now verifies HPC1 revisions (1.0 vs 1.5) and
          prints the output a little prettier ;)
        - power interrupts shouldn't establish on non-IP22
          platforms.

Introduce abstraction layer for HPC registers and values, which addresses the
divergence between HPC revision 1.5 and revision 3.

The wdsc driver has been updated to reflect this layer (and may now work on
IP20).  The sq driver needs a bit more work before it can be committed.

__KERNEL_RCSID()

Use PAGE_SIZE rather than NBPG.

Catch up to -current

Avoid a strict-aliasing warning from GCC 3.3.

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

Catch up with -current.

Replace lots of 8x<space> with <tabs> and other miscellaneous indentation
fixes.
Wrap a couple of long lines.
Use <return-type>\n<function name> as per KNF in a few places.

Sync kqueue branch with -current.

Catch up to -current.

* Clean up HPC autoconfiguration a little.  Pass device register and
  DMA register offsets, as well as IRQ, to children.  Use direct
  config.  Use machine type/subtype to determine which devices are
  present.
* Add support for the second SCSI controller on the Indigo2.

* Add a callback to the front-end for the 33c93 driver to reset
  the controller/SCSI bus.
* Implement controller/SCSI bus reset on SGI HPC3 SCSI using the
  "channel reset" bit in the SCSI DMA channel control register.

Merge Aug 24 -current into the kqueue branch.

file hpcdma.c was added on branch nathanw_sa on 2002-01-08 00:27:27 +0000

file hpcdma.c was added on branch kqueue on 2001-08-25 06:15:49 +0000

Initial implementation of WD33C9x SCSI driver for SGI IP22 platforms.

Based on mvme68k and Atari drivers for the same chipset with the
addition of bus_space support.  Attempts have been made to seperate out the
machine dependent dma components and more work is required in this area.

Tested on SGI R4K Indy, but has little testing on other platforms.